src/i965_encoder_common.h

   1 /*
   2  * Copyright @ 2017 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the
   6  * "Software"), to deal in the Software without restriction, including
   7  * without limitation the rights to use, copy, modify, merge, publish,
   8  * distribute, sub license, and/or sell copies of the Software, and to
   9  * permit persons to whom the Software is furnished to do so, subject to
  10  * the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the
  13  * next paragraph) shall be included in all copies or substantial portions
  14  * of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  17  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  18  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  19  * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
  20  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  21  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  22  * SOFTWAR OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors:
  25  *     Pengfei Qu <Pengfei.Qu@intel.com>
  26  *
  27  */
  28
  29 #ifndef _I965_COMMON_ENCODER_H
  30 #define _I965_COMMON_ENCODER_H
  31
  32 #include <drm.h>
  33 #include <i915_drm.h>
  34 #include <intel_bufmgr.h>
  35
  36 #include <va/va.h>
  37 #include "i965_encoder.h"
  38 #include "i965_gpe_utils.h"
  39
  40 struct encode_state;
  41 struct intel_encoder_context;
  42
  43 /*
  44    this file define the common structure for encoder, such as H264/H265/VP8/VP9
  45 */
  46 #define INTEL_BRC_NONE   0x00000001
  47 #define INTEL_BRC_CBR    0x00000002
  48 #define INTEL_BRC_VBR    0x00000004
  49 #define INTEL_BRC_CQP    0x00000010
  50 #define INTEL_BRC_AVBR   0x00000040
  51
  52 #define INTEL_BRC_INIT_FLAG_CBR                        0x0010,
  53 #define INTEL_BRC_INIT_FLAG_VBR                        0x0020,
  54 #define INTEL_BRC_INIT_FLAG_AVBR                       0x0040,
  55 #define INTEL_BRC_INIT_FLAG_CQL                        0x0080,
  56 #define INTEL_BRC_INIT_FLAG_FIELD_PIC                  0x0100,
  57 #define INTEL_BRC_INIT_FLAG_ICQ                        0x0200,
  58 #define INTEL_BRC_INIT_FLAG_VCM                        0x0400,
  59 #define INTEL_BRC_INIT_FLAG_IGNORE_PICTURE_HEADER_SIZE 0x2000,
  60 #define INTEL_BRC_INIT_FLAG_QVBR                       0x4000,
  61 #define INTEL_BRC_INIT_FLAG_DISABLE_MBBRC              0x8000
  62
  63
  64 #define INTEL_BRC_UPDATE_FLAG_FIELD                  0x01,
  65 #define INTEL_BRC_UPDATE_FLAG_MBAFF                  (0x01 << 1),
  66 #define INTEL_BRC_UPDATE_FLAG_BOTTOM_FIELD           (0x01 << 2),
  67 #define INTEL_BRC_UPDATE_FLAG_ACTUALQP               (0x01 << 6),
  68 #define INTEL_BRC_UPDATE_FLAG_REFERENCE              (0x01 << 7)
  69
  70 #define INTEL_VME_MIN_ALLOWED_WIDTH_HEIGHT           48
  71
  72 #define INTEL_ROI_NUM                    4
  73
  74 extern const unsigned int table_enc_search_path[2][8][16];
  75
  76 // BRC Flag in BRC Init Kernel
  77 typedef enum _INTEL_ENCODE_BRCINIT_FLAG {
  78     INTEL_ENCODE_BRCINIT_ISCBR                       = 0x0010,
  79     INTEL_ENCODE_BRCINIT_ISVBR                       = 0x0020,
  80     INTEL_ENCODE_BRCINIT_ISAVBR                      = 0x0040,
  81     INTEL_ENCODE_BRCINIT_ISCQL                       = 0x0080,
  82     INTEL_ENCODE_BRCINIT_FIELD_PIC                   = 0x0100,
  83     INTEL_ENCODE_BRCINIT_ISICQ                       = 0x0200,
  84     INTEL_ENCODE_BRCINIT_ISVCM                       = 0x0400,
  85     INTEL_ENCODE_BRCINIT_IGNORE_PICTURE_HEADER_SIZE  = 0x2000,
  86     INTEL_ENCODE_BRCINIT_ISQVBR                      = 0x4000,
  87     INTEL_ENCODE_BRCINIT_DISABLE_MBBRC               = 0x8000
  88 } INTEL_ENCODE_BRCINIT_FLAG;
  89
  90 // BRC Flag in BRC Update Kernel
  91 typedef enum _INTEL_ENCODE_BRCUPDATE_FLAG {
  92     INTEL_ENCODE_BRCUPDATE_IS_FIELD                  = 0x01,
  93     INTEL_ENCODE_BRCUPDATE_IS_MBAFF                  = (0x01 << 1),
  94     INTEL_ENCODE_BRCUPDATE_IS_BOTTOM_FIELD           = (0x01 << 2),
  95     INTEL_ENCODE_BRCUPDATE_IS_ACTUALQP               = (0x01 << 6),
  96     INTEL_ENCODE_BRCUPDATE_IS_REFERENCE              = (0x01 << 7)
  97 } INTEL_ENCODE_BRCUPDATE_FLAG;
  98
  99 /*
 100 kernel operation related defines
 101 */
 102 typedef enum _INTEL_GENERIC_ENC_OPERATION {
 103     INTEL_GENERIC_ENC_SCALING4X = 0,
 104     INTEL_GENERIC_ENC_SCALING2X,
 105     INTEL_GENERIC_ENC_ME,
 106     INTEL_GENERIC_ENC_BRC,
 107     INTEL_GENERIC_ENC_MBENC,
 108     INTEL_GENERIC_ENC_MBENC_WIDI,
 109     INTEL_GENERIC_ENC_WP,
 110     INTEL_GENERIC_ENC_SFD,                   // Static frame detection
 111     INTEL_GENERIC_ENC_DYS
 112 } INTEL_GENERIC_ENC_OPERATION;
 113
 114 typedef enum _INTEL_MEDIA_STATE_TYPE {
 115     INTEL_MEDIA_STATE_OLP                                = 0,
 116     INTEL_MEDIA_STATE_ENC_NORMAL                         = 1,
 117     INTEL_MEDIA_STATE_ENC_PERFORMANCE                    = 2,
 118     INTEL_MEDIA_STATE_ENC_QUALITY                        = 3,
 119     INTEL_MEDIA_STATE_ENC_I_FRAME_DIST                   = 4,
 120     INTEL_MEDIA_STATE_32X_SCALING                        = 5,
 121     INTEL_MEDIA_STATE_16X_SCALING                        = 6,
 122     INTEL_MEDIA_STATE_4X_SCALING                         = 7,
 123     INTEL_MEDIA_STATE_32X_ME                             = 8,
 124     INTEL_MEDIA_STATE_16X_ME                             = 9,
 125     INTEL_MEDIA_STATE_4X_ME                              = 10,
 126     INTEL_MEDIA_STATE_BRC_INIT_RESET                     = 11,
 127     INTEL_MEDIA_STATE_BRC_UPDATE                         = 12,
 128     INTEL_MEDIA_STATE_BRC_BLOCK_COPY                     = 13,
 129     INTEL_MEDIA_STATE_PA_COPY                            = 20,
 130     INTEL_MEDIA_STATE_PL2_COPY                           = 21,
 131     INTEL_MEDIA_STATE_ENC_WIDI                           = 22,
 132     INTEL_MEDIA_STATE_2X_SCALING                         = 23,
 133     INTEL_MEDIA_STATE_32x32_PU_MODE_DECISION             = 24,
 134     INTEL_MEDIA_STATE_16x16_PU_SAD                       = 25,
 135     INTEL_MEDIA_STATE_16x16_PU_MODE_DECISION             = 26,
 136     INTEL_MEDIA_STATE_8x8_PU                             = 27,
 137     INTEL_MEDIA_STATE_8x8_PU_FMODE                       = 28,
 138     INTEL_MEDIA_STATE_32x32_B_INTRA_CHECK                = 29,
 139     INTEL_MEDIA_STATE_HEVC_B_MBENC                       = 30,
 140     INTEL_MEDIA_STATE_HEVC_B_PAK                         = 32,
 141     INTEL_MEDIA_STATE_HEVC_BRC_LCU_UPDATE                = 33,
 142     INTEL_MEDIA_STATE_VP9_ENC_I_32x32                    = 35,
 143     INTEL_MEDIA_STATE_VP9_ENC_I_16x16                    = 36,
 144     INTEL_MEDIA_STATE_VP9_ENC_P                          = 37,
 145     INTEL_MEDIA_STATE_VP9_ENC_TX                         = 38,
 146     INTEL_MEDIA_STATE_VP9_DYS                            = 39,
 147     INTEL_MEDIA_STATE_PREPROC                            = 51,
 148     INTEL_MEDIA_STATE_ENC_WP                             = 52,
 149     INTEL_MEDIA_STATE_HEVC_I_MBENC                       = 53,
 150     INTEL_MEDIA_STATE_CSC_DS_COPY                        = 54,
 151     INTEL_MEDIA_STATE_2X_4X_SCALING                      = 55,
 152     INTEL_MEDIA_STATE_HEVC_LCU64_B_MBENC                 = 56,
 153     INTEL_MEDIA_STATE_MB_BRC_UPDATE                      = 57,
 154     INTEL_MEDIA_STATE_STATIC_FRAME_DETECTION             = 58,
 155     INTEL_MEDIA_STATE_HEVC_ROI                           = 59,
 156     INTEL_MEDIA_STATE_SW_SCOREBOARD_INIT                 = 60,
 157     INTEL_NUM_MEDIA_STATES                               = 61
 158 } INTEL_MEDIA_STATE_TYPE;
 159
 160 typedef enum {
 161     INTEL_ROLLING_I_DISABLED  = 0,
 162     INTEL_ROLLING_I_COLUMN    = 1,
 163     INTEL_ROLLING_I_ROW       = 2,
 164     INTEL_ROLLING_I_SQUARE    = 3
 165 } INTEL_ROLLING_I_SETTING;
 166
 167 struct encoder_kernel_parameter {
 168     unsigned int curbe_size;
 169     unsigned int inline_data_size;
 170     unsigned int sampler_size;
 171 };
 172
 173 struct encoder_scoreboard_parameter {
 174     unsigned int mask;
 175     unsigned int type;
 176     unsigned int enable;
 177     unsigned int walkpat_flag;
 178 };
 179
 180
 181 /*
 182 ME related defines
 183 */
 184 #define INTEL_ENC_HME_4x    0
 185 #define INTEL_ENC_HME_16x   1
 186 #define INTEL_ENC_HME_32x   2
 187
 188 /*
 189    the definition for rate control
 190 */
 191 #define GENERIC_BRC_SEQ         0x01
 192 #define GENERIC_BRC_HRD         0x02
 193 #define GENERIC_BRC_RC          0x04
 194 #define GENERIC_BRC_FR          0x08
 195 #define GENERIC_BRC_FAILURE     (1 << 31)
 196
 197 enum INTEL_ENC_KERNAL_MODE {
 198     INTEL_ENC_KERNEL_QUALITY      = 0,
 199     INTEL_ENC_KERNEL_NORMAL,
 200     INTEL_ENC_KERNEL_PERFORMANCE
 201 };
 202
 203 enum INTEL_ENC_PRESET_MODE {
 204     INTEL_PRESET_UNKNOWN         = 0,
 205     INTEL_PRESET_BEST_QUALITY    = 1,
 206     INTEL_PRESET_HI_QUALITY      = 2,
 207     INTEL_PRESET_OPT_QUALITY     = 3,
 208     INTEL_PRESET_OK_QUALITY      = 5,
 209     INTEL_PRESET_NO_SPEED        = 1,
 210     INTEL_PRESET_OPT_SPEED       = 3,
 211     INTEL_PRESET_RT_SPEED        = 4,
 212     INTEL_PRESET_HI_SPEED        = 6,
 213     INTEL_PRESET_BEST_SPEED      = 7,
 214     INTEL_PRESET_LOW_LATENCY     = 0x10,
 215     INTEL_PRESET_MULTIPASS       = 0x20
 216 };
 217
 218 /*
 219    the definition for encoder VME/PAK context
 220 */
 221
 222
 223 struct generic_encoder_context {
 224     // kernel pointer
 225     void * enc_kernel_ptr;
 226     uint32_t enc_kernel_size;
 227     //scoreboard
 228     uint32_t use_hw_scoreboard;
 229     uint32_t use_hw_non_stalling_scoreboard;
 230     //input surface
 231     struct i965_gpe_resource res_uncompressed_input_surface;
 232     //reconstructed surface
 233     struct i965_gpe_resource res_reconstructed_surface;
 234     //output bitstream
 235     struct {
 236         struct i965_gpe_resource res;
 237         uint32_t start_offset;
 238         uint32_t end_offset;
 239     } compressed_bitstream;
 240
 241     bool (*get_kernel_header_and_size)(
 242         void *pvbinary,
 243         int binary_size,
 244         INTEL_GENERIC_ENC_OPERATION operation,
 245         int krnstate_idx,
 246         struct i965_kernel *ret_kernel);
 247
 248     //curbe set function pointer
 249     void (*pfn_set_curbe_scaling2x)(
 250         VADriverContextP ctx,
 251         struct encode_state *encode_state,
 252         struct i965_gpe_context *gpe_context,
 253         struct intel_encoder_context *encoder_context,
 254         void *param);
 255
 256     void (*pfn_set_curbe_scaling4x)(
 257         VADriverContextP ctx,
 258         struct encode_state *encode_state,
 259         struct i965_gpe_context *gpe_context,
 260         struct intel_encoder_context *encoder_context,
 261         void *param);
 262
 263     void (*pfn_set_curbe_me)(
 264         VADriverContextP ctx,
 265         struct encode_state *encode_state,
 266         struct i965_gpe_context *gpe_context,
 267         struct intel_encoder_context *encoder_context,
 268         void *param);
 269
 270     void (*pfn_set_curbe_mbenc)(
 271         VADriverContextP ctx,
 272         struct encode_state *encode_state,
 273         struct i965_gpe_context *gpe_context,
 274         struct intel_encoder_context *encoder_context,
 275         void *param);
 276
 277     void (*pfn_set_curbe_brc_init_reset)(
 278         VADriverContextP ctx,
 279         struct encode_state *encode_state,
 280         struct i965_gpe_context *gpe_context,
 281         struct intel_encoder_context *encoder_context,
 282         void *param);
 283
 284     void (*pfn_set_curbe_brc_frame_update)(
 285         VADriverContextP ctx,
 286         struct encode_state *encode_state,
 287         struct i965_gpe_context *gpe_context,
 288         struct intel_encoder_context *encoder_context,
 289         void *param);
 290
 291     void (*pfn_set_curbe_brc_mb_update)(
 292         VADriverContextP ctx,
 293         struct encode_state *encode_state,
 294         struct i965_gpe_context *gpe_context,
 295         struct intel_encoder_context *encoder_context,
 296         void *param);
 297
 298     void (*pfn_set_curbe_sfd)(
 299         VADriverContextP ctx,
 300         struct encode_state *encode_state,
 301         struct i965_gpe_context *gpe_context,
 302         struct intel_encoder_context *encoder_context,
 303         void *param);
 304
 305     void (*pfn_set_curbe_wp)(
 306         VADriverContextP ctx,
 307         struct encode_state *encode_state,
 308         struct i965_gpe_context *gpe_context,
 309         struct intel_encoder_context *encoder_context,
 310         void *param);
 311
 312     //surface set function pointer
 313     void (*pfn_send_scaling_surface)(
 314         VADriverContextP ctx,
 315         struct encode_state *encode_state,
 316         struct i965_gpe_context *gpe_context,
 317         struct intel_encoder_context *encoder_context,
 318         void *param);
 319
 320     void (*pfn_send_me_surface)(
 321         VADriverContextP ctx,
 322         struct encode_state *encode_state,
 323         struct i965_gpe_context *gpe_context,
 324         struct intel_encoder_context *encoder_context,
 325         void *param);
 326
 327     void (*pfn_send_mbenc_surface)(
 328         VADriverContextP ctx,
 329         struct encode_state *encode_state,
 330         struct i965_gpe_context *gpe_context,
 331         struct intel_encoder_context *encoder_context,
 332         void *param);
 333
 334     void (*pfn_send_brc_init_reset_surface)(
 335         VADriverContextP ctx,
 336         struct encode_state *encode_state,
 337         struct i965_gpe_context *gpe_context,
 338         struct intel_encoder_context *encoder_context,
 339         void *param);
 340
 341     void (*pfn_send_brc_frame_update_surface)(
 342         VADriverContextP ctx,
 343         struct encode_state *encode_state,
 344         struct i965_gpe_context *gpe_context,
 345         struct intel_encoder_context *encoder_context,
 346         void *param);
 347
 348     void (*pfn_send_brc_mb_update_surface)(
 349         VADriverContextP ctx,
 350         struct encode_state *encode_state,
 351         struct i965_gpe_context *gpe_context,
 352         struct intel_encoder_context *encoder_context,
 353         void *param);
 354
 355     void (*pfn_send_sfd_surface)(
 356         VADriverContextP ctx,
 357         struct encode_state *encode_state,
 358         struct i965_gpe_context *gpe_context,
 359         struct intel_encoder_context *encoder_context,
 360         void *param);
 361
 362     void (*pfn_send_wp_surface)(
 363         VADriverContextP ctx,
 364         struct encode_state *encode_state,
 365         struct i965_gpe_context *gpe_context,
 366         struct intel_encoder_context *encoder_context,
 367         void *param);
 368 };
 369 /*
 370    the definition for encoder codec state
 371 */
 372
 373 struct generic_enc_codec_state {
 374
 375     //generic related
 376     int32_t  kernel_mode;
 377     int32_t  preset;
 378     int32_t  seq_frame_number;
 379     int32_t  total_frame_number;
 380     int32_t  herder_bytes_inserted;
 381     uint8_t  frame_type;
 382     bool     first_frame;
 383
 384     // original width/height
 385     uint32_t frame_width_in_pixel;
 386     uint32_t frame_height_in_pixel;
 387     uint32_t frame_width_in_mbs;
 388     uint32_t frame_height_in_mbs;
 389
 390     //scaling related
 391     uint32_t frame_width_2x;
 392     uint32_t frame_height_2x;
 393     uint32_t downscaled_width_2x_in_mb;
 394     uint32_t downscaled_height_2x_in_mb;
 395     uint32_t frame_width_4x;
 396     uint32_t frame_height_4x;
 397     uint32_t frame_width_16x;
 398     uint32_t frame_height_16x;
 399     uint32_t frame_width_32x;
 400     uint32_t frame_height_32x;
 401     uint32_t downscaled_width_4x_in_mb;
 402     uint32_t downscaled_height_4x_in_mb;
 403     uint32_t downscaled_width_16x_in_mb;
 404     uint32_t downscaled_height_16x_in_mb;
 405     uint32_t downscaled_width_32x_in_mb;
 406     uint32_t downscaled_height_32x_in_mb;
 407
 408     // ME related
 409     uint32_t hme_supported: 1;
 410     uint32_t b16xme_supported: 1;
 411     uint32_t b32xme_supported: 1;
 412     uint32_t hme_enabled: 1;
 413     uint32_t b16xme_enabled: 1;
 414     uint32_t b32xme_enabled: 1;
 415     uint32_t brc_distortion_buffer_supported: 1;
 416     uint32_t brc_constant_buffer_supported: 1;
 417     uint32_t hme_reserved: 24;
 418
 419     //BRC related
 420     uint32_t frame_rate;
 421     uint32_t internal_rate_mode;
 422
 423     uint32_t brc_allocated: 1;
 424     uint32_t brc_inited: 1;
 425     uint32_t brc_need_reset: 1;
 426     uint32_t is_low_delay: 1;
 427     uint32_t brc_enabled: 1;
 428     uint32_t curr_pak_pass: 4;
 429     uint32_t num_pak_passes: 4;
 430     uint32_t is_first_pass: 1;
 431     uint32_t is_last_pass: 1;
 432     uint32_t mb_brc_enabled: 1;
 433     uint32_t brc_roi_enable: 1;
 434     uint32_t brc_dirty_roi_enable: 1;
 435     uint32_t skip_frame_enbale: 1;
 436     uint32_t brc_reserved: 13;
 437
 438     uint32_t target_bit_rate;
 439     uint32_t max_bit_rate;
 440     uint32_t min_bit_rate;
 441     uint64_t init_vbv_buffer_fullness_in_bit;
 442     uint64_t vbv_buffer_size_in_bit;
 443     uint32_t frames_per_100s;
 444     uint32_t gop_size;
 445     uint32_t gop_ref_distance;
 446     uint32_t brc_target_size;
 447     uint32_t brc_mode;
 448     double   brc_init_current_target_buf_full_in_bits;
 449     double   brc_init_reset_input_bits_per_frame;
 450     uint32_t brc_init_reset_buf_size_in_bits;
 451     uint32_t brc_init_previous_target_buf_full_in_bits;
 452     int32_t  frames_per_window_size;
 453     int32_t  target_percentage;
 454     uint16_t avbr_curracy;
 455     uint16_t avbr_convergence;
 456
 457     //skip frame enbale
 458     uint32_t num_skip_frames;
 459     uint32_t size_skip_frames;
 460
 461     // ROI related
 462     uint32_t dirty_num_roi;
 463     uint32_t num_roi;
 464     uint32_t max_delta_qp;
 465     uint32_t min_delta_qp;
 466     struct intel_roi roi[INTEL_ROI_NUM];
 467
 468 };
 469
 470 /*
 471  by now VME and PAK use the same context. it will bind the ctx according to the codec and platform, also vdenc and non-vdenc
 472 */
 473 struct encoder_vme_mfc_context {
 474     int32_t codec_id;
 475     void * generic_enc_ctx;
 476     void * private_enc_ctx; //pointer to the specific enc_ctx
 477     void * generic_enc_state;
 478     void * private_enc_state; //pointer to the specific enc_state
 479 };
 480
 481 #endif /* _I965_COMMON_ENCODER_H */