src/i965_encoder_common.h

   1 /*
   2  * Copyright @ 2017 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the
   6  * "Software"), to deal in the Software without restriction, including
   7  * without limitation the rights to use, copy, modify, merge, publish,
   8  * distribute, sub license, and/or sell copies of the Software, and to
   9  * permit persons to whom the Software is furnished to do so, subject to
  10  * the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the
  13  * next paragraph) shall be included in all copies or substantial portions
  14  * of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  17  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  18  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  19  * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
  20  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  21  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  22  * SOFTWAR OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors:
  25  *     Pengfei Qu <Pengfei.Qu@intel.com>
  26  *
  27  */
  28
  29 #ifndef _I965_COMMON_ENCODER_H
  30 #define _I965_COMMON_ENCODER_H
  31
  32 #include <drm.h>
  33 #include <i915_drm.h>
  34 #include <intel_bufmgr.h>
  35
  36 #include <va/va.h>
  37 #include "i965_encoder.h"
  38 #include "i965_gpe_utils.h"
  39
  40 struct encode_state;
  41 struct intel_encoder_context;
  42
  43 /*
  44    this file define the common structure for encoder, such as H264/H265/VP8/VP9
  45 */
  46 #define INTEL_BRC_NONE   0x00000001
  47 #define INTEL_BRC_CBR    0x00000002
  48 #define INTEL_BRC_VBR    0x00000004
  49 #define INTEL_BRC_CQP    0x00000010
  50 #define INTEL_BRC_AVBR   0x00000040
  51
  52 #define INTEL_BRC_INIT_FLAG_CBR                        0x0010,
  53 #define INTEL_BRC_INIT_FLAG_VBR                        0x0020,
  54 #define INTEL_BRC_INIT_FLAG_AVBR                       0x0040,
  55 #define INTEL_BRC_INIT_FLAG_CQL                        0x0080,
  56 #define INTEL_BRC_INIT_FLAG_FIELD_PIC                  0x0100,
  57 #define INTEL_BRC_INIT_FLAG_ICQ                        0x0200,
  58 #define INTEL_BRC_INIT_FLAG_VCM                        0x0400,
  59 #define INTEL_BRC_INIT_FLAG_IGNORE_PICTURE_HEADER_SIZE 0x2000,
  60 #define INTEL_BRC_INIT_FLAG_QVBR                       0x4000,
  61 #define INTEL_BRC_INIT_FLAG_DISABLE_MBBRC              0x8000
  62
  63
  64 #define INTEL_BRC_UPDATE_FLAG_FIELD                  0x01,
  65 #define INTEL_BRC_UPDATE_FLAG_MBAFF                  (0x01 << 1),
  66 #define INTEL_BRC_UPDATE_FLAG_BOTTOM_FIELD           (0x01 << 2),
  67 #define INTEL_BRC_UPDATE_FLAG_ACTUALQP               (0x01 << 6),
  68 #define INTEL_BRC_UPDATE_FLAG_REFERENCE              (0x01 << 7)
  69
  70 #define INTEL_VME_MIN_ALLOWED_WIDTH_HEIGHT           48
  71
  72 #define INTEL_ROI_NUM                                4
  73
  74 extern const unsigned int table_enc_search_path[2][8][16];
  75
  76 // BRC Flag in BRC Init Kernel
  77 typedef enum _INTEL_ENCODE_BRCINIT_FLAG
  78 {
  79     INTEL_ENCODE_BRCINIT_ISCBR                       = 0x0010,
  80     INTEL_ENCODE_BRCINIT_ISVBR                       = 0x0020,
  81     INTEL_ENCODE_BRCINIT_ISAVBR                      = 0x0040,
  82     INTEL_ENCODE_BRCINIT_ISCQL                       = 0x0080,
  83     INTEL_ENCODE_BRCINIT_FIELD_PIC                   = 0x0100,
  84     INTEL_ENCODE_BRCINIT_ISICQ                       = 0x0200,
  85     INTEL_ENCODE_BRCINIT_ISVCM                       = 0x0400,
  86     INTEL_ENCODE_BRCINIT_IGNORE_PICTURE_HEADER_SIZE  = 0x2000,
  87     INTEL_ENCODE_BRCINIT_ISQVBR                      = 0x4000,
  88     INTEL_ENCODE_BRCINIT_DISABLE_MBBRC               = 0x8000
  89 } INTEL_ENCODE_BRCINIT_FLAG;
  90
  91 // BRC Flag in BRC Update Kernel
  92 typedef enum _INTEL_ENCODE_BRCUPDATE_FLAG
  93 {
  94     INTEL_ENCODE_BRCUPDATE_IS_FIELD                  = 0x01,
  95     INTEL_ENCODE_BRCUPDATE_IS_MBAFF                  = (0x01 << 1),
  96     INTEL_ENCODE_BRCUPDATE_IS_BOTTOM_FIELD           = (0x01 << 2),
  97     INTEL_ENCODE_BRCUPDATE_IS_ACTUALQP               = (0x01 << 6),
  98     INTEL_ENCODE_BRCUPDATE_IS_REFERENCE              = (0x01 << 7)
  99 } INTEL_ENCODE_BRCUPDATE_FLAG;
 100
 101 /*
 102 kernel operation related defines
 103 */
 104 typedef enum _INTEL_GENERIC_ENC_OPERATION
 105 {
 106     INTEL_GENERIC_ENC_SCALING4X = 0,
 107     INTEL_GENERIC_ENC_SCALING2X,
 108     INTEL_GENERIC_ENC_ME,
 109     INTEL_GENERIC_ENC_BRC,
 110     INTEL_GENERIC_ENC_MBENC,
 111     INTEL_GENERIC_ENC_MBENC_WIDI,
 112     INTEL_GENERIC_ENC_WP,
 113     INTEL_GENERIC_ENC_SFD,                   // Static frame detection
 114     INTEL_GENERIC_ENC_DYS
 115 } INTEL_GENERIC_ENC_OPERATION;
 116
 117 typedef enum _INTEL_MEDIA_STATE_TYPE
 118 {
 119     INTEL_MEDIA_STATE_OLP                                = 0,
 120     INTEL_MEDIA_STATE_ENC_NORMAL                         = 1,
 121     INTEL_MEDIA_STATE_ENC_PERFORMANCE                    = 2,
 122     INTEL_MEDIA_STATE_ENC_QUALITY                        = 3,
 123     INTEL_MEDIA_STATE_ENC_I_FRAME_DIST                   = 4,
 124     INTEL_MEDIA_STATE_32X_SCALING                        = 5,
 125     INTEL_MEDIA_STATE_16X_SCALING                        = 6,
 126     INTEL_MEDIA_STATE_4X_SCALING                         = 7,
 127     INTEL_MEDIA_STATE_32X_ME                             = 8,
 128     INTEL_MEDIA_STATE_16X_ME                             = 9,
 129     INTEL_MEDIA_STATE_4X_ME                              = 10,
 130     INTEL_MEDIA_STATE_BRC_INIT_RESET                     = 11,
 131     INTEL_MEDIA_STATE_BRC_UPDATE                         = 12,
 132     INTEL_MEDIA_STATE_BRC_BLOCK_COPY                     = 13,
 133     INTEL_MEDIA_STATE_PA_COPY                            = 20,
 134     INTEL_MEDIA_STATE_PL2_COPY                           = 21,
 135     INTEL_MEDIA_STATE_ENC_WIDI                           = 22,
 136     INTEL_MEDIA_STATE_2X_SCALING                         = 23,
 137     INTEL_MEDIA_STATE_32x32_PU_MODE_DECISION             = 24,
 138     INTEL_MEDIA_STATE_16x16_PU_SAD                       = 25,
 139     INTEL_MEDIA_STATE_16x16_PU_MODE_DECISION             = 26,
 140     INTEL_MEDIA_STATE_8x8_PU                             = 27,
 141     INTEL_MEDIA_STATE_8x8_PU_FMODE                       = 28,
 142     INTEL_MEDIA_STATE_32x32_B_INTRA_CHECK                = 29,
 143     INTEL_MEDIA_STATE_HEVC_B_MBENC                       = 30,
 144     INTEL_MEDIA_STATE_HEVC_B_PAK                         = 32,
 145     INTEL_MEDIA_STATE_HEVC_BRC_LCU_UPDATE                = 33,
 146     INTEL_MEDIA_STATE_VP9_ENC_I_32x32                    = 35,
 147     INTEL_MEDIA_STATE_VP9_ENC_I_16x16                    = 36,
 148     INTEL_MEDIA_STATE_VP9_ENC_P                          = 37,
 149     INTEL_MEDIA_STATE_VP9_ENC_TX                         = 38,
 150     INTEL_MEDIA_STATE_VP9_DYS                            = 39,
 151     INTEL_MEDIA_STATE_PREPROC                            = 51,
 152     INTEL_MEDIA_STATE_ENC_WP                             = 52,
 153     INTEL_MEDIA_STATE_HEVC_I_MBENC                       = 53,
 154     INTEL_MEDIA_STATE_CSC_DS_COPY                        = 54,
 155     INTEL_MEDIA_STATE_2X_4X_SCALING                      = 55,
 156     INTEL_MEDIA_STATE_HEVC_LCU64_B_MBENC                 = 56,
 157     INTEL_MEDIA_STATE_MB_BRC_UPDATE                      = 57,
 158     INTEL_MEDIA_STATE_STATIC_FRAME_DETECTION             = 58,
 159     INTEL_MEDIA_STATE_HEVC_ROI                           = 59,
 160     INTEL_MEDIA_STATE_SW_SCOREBOARD_INIT                 = 60,
 161     INTEL_NUM_MEDIA_STATES                               = 61
 162 } INTEL_MEDIA_STATE_TYPE;
 163
 164 typedef enum
 165 {
 166     INTEL_ROLLING_I_DISABLED  = 0,
 167     INTEL_ROLLING_I_COLUMN    = 1,
 168     INTEL_ROLLING_I_ROW       = 2,
 169     INTEL_ROLLING_I_SQUARE    = 3
 170 } INTEL_ROLLING_I_SETTING;
 171
 172 struct encoder_kernel_parameter
 173 {
 174     unsigned int curbe_size;
 175     unsigned int inline_data_size;
 176     unsigned int sampler_size;
 177 };
 178
 179 struct encoder_scoreboard_parameter
 180 {
 181     unsigned int mask;
 182     unsigned int type;
 183     unsigned int enable;
 184     unsigned int walkpat_flag;
 185 };
 186
 187
 188 /*
 189 ME related defines
 190 */
 191 #define INTEL_ENC_HME_4x    0
 192 #define INTEL_ENC_HME_16x   1
 193 #define INTEL_ENC_HME_32x   2
 194
 195 /*
 196    the definition for rate control
 197 */
 198 #define GENERIC_BRC_SEQ         0x01
 199 #define GENERIC_BRC_HRD         0x02
 200 #define GENERIC_BRC_RC          0x04
 201 #define GENERIC_BRC_FR          0x08
 202 #define GENERIC_BRC_FAILURE     (1 << 31)
 203
 204 enum INTEL_ENC_KERNAL_MODE
 205 {
 206     INTEL_ENC_KERNEL_QUALITY      = 0,
 207     INTEL_ENC_KERNEL_NORMAL,
 208     INTEL_ENC_KERNEL_PERFORMANCE
 209 };
 210
 211 enum INTEL_ENC_PRESET_MODE
 212 {
 213     INTEL_PRESET_UNKNOWN         = 0,
 214     INTEL_PRESET_BEST_QUALITY    = 1,
 215     INTEL_PRESET_HI_QUALITY      = 2,
 216     INTEL_PRESET_OPT_QUALITY     = 3,
 217     INTEL_PRESET_OK_QUALITY      = 5,
 218     INTEL_PRESET_NO_SPEED        = 1,
 219     INTEL_PRESET_OPT_SPEED       = 3,
 220     INTEL_PRESET_RT_SPEED        = 4,
 221     INTEL_PRESET_HI_SPEED        = 6,
 222     INTEL_PRESET_BEST_SPEED      = 7,
 223     INTEL_PRESET_LOW_LATENCY     = 0x10,
 224     INTEL_PRESET_MULTIPASS       = 0x20
 225 };
 226
 227 /*
 228    the definition for encoder VME/PAK context
 229 */
 230
 231
 232 struct generic_encoder_context
 233 {
 234     // kernel pointer
 235     void * enc_kernel_ptr;
 236     uint32_t enc_kernel_size;
 237     //scoreboard
 238     uint32_t use_hw_scoreboard;
 239     uint32_t use_hw_non_stalling_scoreboard;
 240     //input surface
 241     struct i965_gpe_resource res_uncompressed_input_surface;
 242     //reconstructed surface
 243     struct i965_gpe_resource res_reconstructed_surface;
 244     //output bitstream
 245     struct {
 246         struct i965_gpe_resource res;
 247         uint32_t start_offset;
 248         uint32_t end_offset;
 249     } compressed_bitstream;
 250
 251     //curbe set function pointer
 252     void (*pfn_set_curbe_scaling2x)(
 253         VADriverContextP ctx,
 254         struct encode_state *encode_state,
 255         struct i965_gpe_context *gpe_context,
 256         struct intel_encoder_context *encoder_context,
 257         void *param);
 258
 259     void (*pfn_set_curbe_scaling4x)(
 260         VADriverContextP ctx,
 261         struct encode_state *encode_state,
 262         struct i965_gpe_context *gpe_context,
 263         struct intel_encoder_context *encoder_context,
 264         void *param);
 265
 266     void (*pfn_set_curbe_me)(
 267         VADriverContextP ctx,
 268         struct encode_state *encode_state,
 269         struct i965_gpe_context *gpe_context,
 270         struct intel_encoder_context *encoder_context,
 271         void *param);
 272
 273     void (*pfn_set_curbe_mbenc)(
 274         VADriverContextP ctx,
 275         struct encode_state *encode_state,
 276         struct i965_gpe_context *gpe_context,
 277         struct intel_encoder_context *encoder_context,
 278         void *param);
 279
 280     void (*pfn_set_curbe_brc_init_reset)(
 281         VADriverContextP ctx,
 282         struct encode_state *encode_state,
 283         struct i965_gpe_context *gpe_context,
 284         struct intel_encoder_context *encoder_context,
 285         void *param);
 286
 287     void (*pfn_set_curbe_brc_frame_update)(
 288         VADriverContextP ctx,
 289         struct encode_state *encode_state,
 290         struct i965_gpe_context *gpe_context,
 291         struct intel_encoder_context *encoder_context,
 292         void *param);
 293
 294     void (*pfn_set_curbe_brc_mb_update)(
 295         VADriverContextP ctx,
 296         struct encode_state *encode_state,
 297         struct i965_gpe_context *gpe_context,
 298         struct intel_encoder_context *encoder_context,
 299         void *param);
 300
 301     void (*pfn_set_curbe_sfd)(
 302         VADriverContextP ctx,
 303         struct encode_state *encode_state,
 304         struct i965_gpe_context *gpe_context,
 305         struct intel_encoder_context *encoder_context,
 306         void *param);
 307
 308     void (*pfn_set_curbe_wp)(
 309         VADriverContextP ctx,
 310         struct encode_state *encode_state,
 311         struct i965_gpe_context *gpe_context,
 312         struct intel_encoder_context *encoder_context,
 313         void *param);
 314
 315     //surface set function pointer
 316     void (*pfn_send_scaling_surface)(
 317         VADriverContextP ctx,
 318         struct encode_state *encode_state,
 319         struct i965_gpe_context *gpe_context,
 320         struct intel_encoder_context *encoder_context,
 321         void *param);
 322
 323     void (*pfn_send_me_surface)(
 324         VADriverContextP ctx,
 325         struct encode_state *encode_state,
 326         struct i965_gpe_context *gpe_context,
 327         struct intel_encoder_context *encoder_context,
 328         void *param);
 329
 330     void (*pfn_send_mbenc_surface)(
 331         VADriverContextP ctx,
 332         struct encode_state *encode_state,
 333         struct i965_gpe_context *gpe_context,
 334         struct intel_encoder_context *encoder_context,
 335         void *param);
 336
 337     void (*pfn_send_brc_init_reset_surface)(
 338         VADriverContextP ctx,
 339         struct encode_state *encode_state,
 340         struct i965_gpe_context *gpe_context,
 341         struct intel_encoder_context *encoder_context,
 342         void *param);
 343
 344     void (*pfn_send_brc_frame_update_surface)(
 345         VADriverContextP ctx,
 346         struct encode_state *encode_state,
 347         struct i965_gpe_context *gpe_context,
 348         struct intel_encoder_context *encoder_context,
 349         void *param);
 350
 351     void (*pfn_send_brc_mb_update_surface)(
 352         VADriverContextP ctx,
 353         struct encode_state *encode_state,
 354         struct i965_gpe_context *gpe_context,
 355         struct intel_encoder_context *encoder_context,
 356         void *param);
 357
 358     void (*pfn_send_sfd_surface)(
 359         VADriverContextP ctx,
 360         struct encode_state *encode_state,
 361         struct i965_gpe_context *gpe_context,
 362         struct intel_encoder_context *encoder_context,
 363         void *param);
 364
 365     void (*pfn_send_wp_surface)(
 366         VADriverContextP ctx,
 367         struct encode_state *encode_state,
 368         struct i965_gpe_context *gpe_context,
 369         struct intel_encoder_context *encoder_context,
 370         void *param);
 371 };
 372 /*
 373    the definition for encoder codec state
 374 */
 375
 376 struct generic_enc_codec_state {
 377
 378     //generic related
 379     int32_t  kernel_mode;
 380     int32_t  preset;
 381     int32_t  seq_frame_number;
 382     int32_t  total_frame_number;
 383     int32_t  herder_bytes_inserted;
 384     uint8_t  frame_type;
 385     bool     first_frame;
 386
 387     // original width/height
 388     uint32_t frame_width_in_pixel;
 389     uint32_t frame_height_in_pixel;
 390     uint32_t frame_width_in_mbs;
 391     uint32_t frame_height_in_mbs;
 392
 393     //scaling related
 394     uint32_t frame_width_2x;
 395     uint32_t frame_height_2x;
 396     uint32_t downscaled_width_2x_in_mb;
 397     uint32_t downscaled_height_2x_in_mb;
 398     uint32_t frame_width_4x;
 399     uint32_t frame_height_4x;
 400     uint32_t frame_width_16x;
 401     uint32_t frame_height_16x;
 402     uint32_t frame_width_32x;
 403     uint32_t frame_height_32x;
 404     uint32_t downscaled_width_4x_in_mb;
 405     uint32_t downscaled_height_4x_in_mb;
 406     uint32_t downscaled_width_16x_in_mb;
 407     uint32_t downscaled_height_16x_in_mb;
 408     uint32_t downscaled_width_32x_in_mb;
 409     uint32_t downscaled_height_32x_in_mb;
 410
 411     // ME related
 412     uint32_t hme_supported:1;
 413     uint32_t b16xme_supported:1;
 414     uint32_t b32xme_supported:1;
 415     uint32_t hme_enabled:1;
 416     uint32_t b16xme_enabled:1;
 417     uint32_t b32xme_enabled:1;
 418     uint32_t brc_distortion_buffer_supported:1;
 419     uint32_t brc_constant_buffer_supported:1;
 420     uint32_t hme_reserved:24;
 421
 422     //BRC related
 423     uint32_t frame_rate;
 424     uint32_t internal_rate_mode;
 425
 426     uint32_t brc_allocated:1;
 427     uint32_t brc_inited:1;
 428     uint32_t brc_need_reset:1;
 429     uint32_t is_low_delay:1;
 430     uint32_t brc_enabled:1;
 431     uint32_t curr_pak_pass:4;
 432     uint32_t num_pak_passes:4;
 433     uint32_t is_first_pass:1;
 434     uint32_t is_last_pass:1;
 435     uint32_t mb_brc_enabled:1;
 436     uint32_t brc_roi_enable:1;
 437     uint32_t brc_dirty_roi_enable:1;
 438     uint32_t skip_frame_enbale:1;
 439     uint32_t brc_reserved:13;
 440
 441     uint32_t target_bit_rate;
 442     uint32_t max_bit_rate;
 443     uint32_t min_bit_rate;
 444     uint64_t init_vbv_buffer_fullness_in_bit;
 445     uint64_t vbv_buffer_size_in_bit;
 446     uint32_t frames_per_100s;
 447     uint32_t gop_size;
 448     uint32_t gop_ref_distance;
 449     uint32_t brc_target_size;
 450     uint32_t brc_mode;
 451     double   brc_init_current_target_buf_full_in_bits;
 452     double   brc_init_reset_input_bits_per_frame;
 453     uint32_t brc_init_reset_buf_size_in_bits;
 454     uint32_t brc_init_previous_target_buf_full_in_bits;
 455     int32_t  frames_per_window_size;
 456     int32_t  target_percentage;
 457     uint16_t avbr_curracy;
 458     uint16_t avbr_convergence;
 459
 460     //skip frame enbale
 461     uint32_t num_skip_frames;
 462     uint32_t size_skip_frames;
 463
 464     // ROI related
 465     uint32_t dirty_num_roi;
 466     uint32_t num_roi;
 467     uint32_t max_delta_qp;
 468     uint32_t min_delta_qp;
 469     struct intel_roi roi[INTEL_ROI_NUM];
 470
 471 };
 472
 473 /*
 474  by now VME and PAK use the same context. it will bind the ctx according to the codec and platform, also vdenc and non-vdenc
 475 */
 476 struct encoder_vme_mfc_context {
 477     int32_t codec_id;
 478     void * generic_enc_ctx;
 479     void * private_enc_ctx; //pointer to the specific enc_ctx
 480     void * generic_enc_state;
 481     void * private_enc_state; //pointer to the specific enc_state
 482 };
 483
 484 #endif /* _I965_COMMON_ENCODER_H */