src/i965_encoder_common.h

   1 /*
   2  * Copyright @ 2017 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the
   6  * "Software"), to deal in the Software without restriction, including
   7  * without limitation the rights to use, copy, modify, merge, publish,
   8  * distribute, sub license, and/or sell copies of the Software, and to
   9  * permit persons to whom the Software is furnished to do so, subject to
  10  * the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the
  13  * next paragraph) shall be included in all copies or substantial portions
  14  * of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  17  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  18  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  19  * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
  20  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  21  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  22  * SOFTWAR OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors:
  25  *     Pengfei Qu <Pengfei.Qu@intel.com>
  26  *
  27  */
  28
  29 #ifndef _I965_COMMON_ENCODER_H
  30 #define _I965_COMMON_ENCODER_H
  31
  32 #include <drm.h>
  33 #include <i915_drm.h>
  34 #include <intel_bufmgr.h>
  35
  36 #include <va/va.h>
  37 #include "i965_encoder.h"
  38 #include "i965_gpe_utils.h"
  39
  40 struct encode_state;
  41 struct intel_encoder_context;
  42
  43 /*
  44    this file define the common structure for encoder, such as H264/H265/VP8/VP9
  45 */
  46 #define INTEL_BRC_NONE   0x00000001
  47 #define INTEL_BRC_CBR    0x00000002
  48 #define INTEL_BRC_VBR    0x00000004
  49 #define INTEL_BRC_CQP    0x00000010
  50 #define INTEL_BRC_AVBR   0x00000040
  51
  52 #define INTEL_BRC_INIT_FLAG_CBR                        0x0010,
  53 #define INTEL_BRC_INIT_FLAG_VBR                        0x0020,
  54 #define INTEL_BRC_INIT_FLAG_AVBR                       0x0040,
  55 #define INTEL_BRC_INIT_FLAG_CQL                        0x0080,
  56 #define INTEL_BRC_INIT_FLAG_FIELD_PIC                  0x0100,
  57 #define INTEL_BRC_INIT_FLAG_ICQ                        0x0200,
  58 #define INTEL_BRC_INIT_FLAG_VCM                        0x0400,
  59 #define INTEL_BRC_INIT_FLAG_IGNORE_PICTURE_HEADER_SIZE 0x2000,
  60 #define INTEL_BRC_INIT_FLAG_QVBR                       0x4000,
  61 #define INTEL_BRC_INIT_FLAG_DISABLE_MBBRC              0x8000
  62
  63
  64 #define INTEL_BRC_UPDATE_FLAG_FIELD                  0x01,
  65 #define INTEL_BRC_UPDATE_FLAG_MBAFF                  (0x01 << 1),
  66 #define INTEL_BRC_UPDATE_FLAG_BOTTOM_FIELD           (0x01 << 2),
  67 #define INTEL_BRC_UPDATE_FLAG_ACTUALQP               (0x01 << 6),
  68 #define INTEL_BRC_UPDATE_FLAG_REFERENCE              (0x01 << 7)
  69
  70 #define INTEL_VME_MIN_ALLOWED_WIDTH_HEIGHT           48
  71
  72 #define INTEL_ROI_NUM                    4
  73
  74 extern const unsigned int table_enc_search_path[2][8][16];
  75
  76 // BRC Flag in BRC Init Kernel
  77 typedef enum _INTEL_ENCODE_BRCINIT_FLAG {
  78     INTEL_ENCODE_BRCINIT_ISCBR                       = 0x0010,
  79     INTEL_ENCODE_BRCINIT_ISVBR                       = 0x0020,
  80     INTEL_ENCODE_BRCINIT_ISAVBR                      = 0x0040,
  81     INTEL_ENCODE_BRCINIT_ISCQL                       = 0x0080,
  82     INTEL_ENCODE_BRCINIT_FIELD_PIC                   = 0x0100,
  83     INTEL_ENCODE_BRCINIT_ISICQ                       = 0x0200,
  84     INTEL_ENCODE_BRCINIT_ISVCM                       = 0x0400,
  85     INTEL_ENCODE_BRCINIT_IGNORE_PICTURE_HEADER_SIZE  = 0x2000,
  86     INTEL_ENCODE_BRCINIT_ISQVBR                      = 0x4000,
  87     INTEL_ENCODE_BRCINIT_DISABLE_MBBRC               = 0x8000
  88 } INTEL_ENCODE_BRCINIT_FLAG;
  89
  90 // BRC Flag in BRC Update Kernel
  91 typedef enum _INTEL_ENCODE_BRCUPDATE_FLAG {
  92     INTEL_ENCODE_BRCUPDATE_IS_FIELD                  = 0x01,
  93     INTEL_ENCODE_BRCUPDATE_IS_MBAFF                  = (0x01 << 1),
  94     INTEL_ENCODE_BRCUPDATE_IS_BOTTOM_FIELD           = (0x01 << 2),
  95     INTEL_ENCODE_BRCUPDATE_IS_ACTUALQP               = (0x01 << 6),
  96     INTEL_ENCODE_BRCUPDATE_IS_REFERENCE              = (0x01 << 7)
  97 } INTEL_ENCODE_BRCUPDATE_FLAG;
  98
  99 /*
 100 kernel operation related defines
 101 */
 102 typedef enum _INTEL_GENERIC_ENC_OPERATION {
 103     INTEL_GENERIC_ENC_SCALING4X = 0,
 104     INTEL_GENERIC_ENC_SCALING2X,
 105     INTEL_GENERIC_ENC_ME,
 106     INTEL_GENERIC_ENC_BRC,
 107     INTEL_GENERIC_ENC_MBENC,
 108     INTEL_GENERIC_ENC_MBENC_WIDI,
 109     INTEL_GENERIC_ENC_WP,
 110     INTEL_GENERIC_ENC_SFD,                   // Static frame detection
 111     INTEL_GENERIC_ENC_DYS,
 112     INTEL_GENERIC_ENC_PREPROC
 113 } INTEL_GENERIC_ENC_OPERATION;
 114
 115 typedef enum _INTEL_MEDIA_STATE_TYPE {
 116     INTEL_MEDIA_STATE_OLP                                = 0,
 117     INTEL_MEDIA_STATE_ENC_NORMAL                         = 1,
 118     INTEL_MEDIA_STATE_ENC_PERFORMANCE                    = 2,
 119     INTEL_MEDIA_STATE_ENC_QUALITY                        = 3,
 120     INTEL_MEDIA_STATE_ENC_I_FRAME_DIST                   = 4,
 121     INTEL_MEDIA_STATE_32X_SCALING                        = 5,
 122     INTEL_MEDIA_STATE_16X_SCALING                        = 6,
 123     INTEL_MEDIA_STATE_4X_SCALING                         = 7,
 124     INTEL_MEDIA_STATE_32X_ME                             = 8,
 125     INTEL_MEDIA_STATE_16X_ME                             = 9,
 126     INTEL_MEDIA_STATE_4X_ME                              = 10,
 127     INTEL_MEDIA_STATE_BRC_INIT_RESET                     = 11,
 128     INTEL_MEDIA_STATE_BRC_UPDATE                         = 12,
 129     INTEL_MEDIA_STATE_BRC_BLOCK_COPY                     = 13,
 130     INTEL_MEDIA_STATE_PA_COPY                            = 20,
 131     INTEL_MEDIA_STATE_PL2_COPY                           = 21,
 132     INTEL_MEDIA_STATE_ENC_WIDI                           = 22,
 133     INTEL_MEDIA_STATE_2X_SCALING                         = 23,
 134     INTEL_MEDIA_STATE_32x32_PU_MODE_DECISION             = 24,
 135     INTEL_MEDIA_STATE_16x16_PU_SAD                       = 25,
 136     INTEL_MEDIA_STATE_16x16_PU_MODE_DECISION             = 26,
 137     INTEL_MEDIA_STATE_8x8_PU                             = 27,
 138     INTEL_MEDIA_STATE_8x8_PU_FMODE                       = 28,
 139     INTEL_MEDIA_STATE_32x32_B_INTRA_CHECK                = 29,
 140     INTEL_MEDIA_STATE_HEVC_B_MBENC                       = 30,
 141     INTEL_MEDIA_STATE_HEVC_B_PAK                         = 32,
 142     INTEL_MEDIA_STATE_HEVC_BRC_LCU_UPDATE                = 33,
 143     INTEL_MEDIA_STATE_VP9_ENC_I_32x32                    = 35,
 144     INTEL_MEDIA_STATE_VP9_ENC_I_16x16                    = 36,
 145     INTEL_MEDIA_STATE_VP9_ENC_P                          = 37,
 146     INTEL_MEDIA_STATE_VP9_ENC_TX                         = 38,
 147     INTEL_MEDIA_STATE_VP9_DYS                            = 39,
 148     INTEL_MEDIA_STATE_PREPROC                            = 51,
 149     INTEL_MEDIA_STATE_ENC_WP                             = 52,
 150     INTEL_MEDIA_STATE_HEVC_I_MBENC                       = 53,
 151     INTEL_MEDIA_STATE_CSC_DS_COPY                        = 54,
 152     INTEL_MEDIA_STATE_2X_4X_SCALING                      = 55,
 153     INTEL_MEDIA_STATE_HEVC_LCU64_B_MBENC                 = 56,
 154     INTEL_MEDIA_STATE_MB_BRC_UPDATE                      = 57,
 155     INTEL_MEDIA_STATE_STATIC_FRAME_DETECTION             = 58,
 156     INTEL_MEDIA_STATE_HEVC_ROI                           = 59,
 157     INTEL_MEDIA_STATE_SW_SCOREBOARD_INIT                 = 60,
 158     INTEL_NUM_MEDIA_STATES                               = 61
 159 } INTEL_MEDIA_STATE_TYPE;
 160
 161 typedef enum {
 162     INTEL_ROLLING_I_DISABLED  = 0,
 163     INTEL_ROLLING_I_COLUMN    = 1,
 164     INTEL_ROLLING_I_ROW       = 2,
 165     INTEL_ROLLING_I_SQUARE    = 3
 166 } INTEL_ROLLING_I_SETTING;
 167
 168 struct encoder_kernel_parameter {
 169     unsigned int curbe_size;
 170     unsigned int inline_data_size;
 171     unsigned int sampler_size;
 172 };
 173
 174 struct encoder_scoreboard_parameter {
 175     unsigned int mask;
 176     unsigned int type;
 177     unsigned int enable;
 178     unsigned int walkpat_flag;
 179 };
 180
 181
 182 /*
 183 ME related defines
 184 */
 185 #define INTEL_ENC_HME_4x    0
 186 #define INTEL_ENC_HME_16x   1
 187 #define INTEL_ENC_HME_32x   2
 188
 189 /*
 190    the definition for rate control
 191 */
 192 #define GENERIC_BRC_SEQ         0x01
 193 #define GENERIC_BRC_HRD         0x02
 194 #define GENERIC_BRC_RC          0x04
 195 #define GENERIC_BRC_FR          0x08
 196 #define GENERIC_BRC_FAILURE     (1 << 31)
 197
 198 enum INTEL_ENC_KERNAL_MODE {
 199     INTEL_ENC_KERNEL_QUALITY      = 0,
 200     INTEL_ENC_KERNEL_NORMAL,
 201     INTEL_ENC_KERNEL_PERFORMANCE
 202 };
 203
 204 enum INTEL_ENC_PRESET_MODE {
 205     INTEL_PRESET_UNKNOWN         = 0,
 206     INTEL_PRESET_BEST_QUALITY    = 1,
 207     INTEL_PRESET_HI_QUALITY      = 2,
 208     INTEL_PRESET_OPT_QUALITY     = 3,
 209     INTEL_PRESET_OK_QUALITY      = 5,
 210     INTEL_PRESET_NO_SPEED        = 1,
 211     INTEL_PRESET_OPT_SPEED       = 3,
 212     INTEL_PRESET_RT_SPEED        = 4,
 213     INTEL_PRESET_HI_SPEED        = 6,
 214     INTEL_PRESET_BEST_SPEED      = 7,
 215     INTEL_PRESET_LOW_LATENCY     = 0x10,
 216     INTEL_PRESET_MULTIPASS       = 0x20
 217 };
 218
 219 /*
 220    the definition for encoder VME/PAK context
 221 */
 222
 223
 224 struct generic_encoder_context {
 225     // kernel pointer
 226     void * enc_kernel_ptr;
 227     uint32_t enc_kernel_size;
 228     //scoreboard
 229     uint32_t use_hw_scoreboard;
 230     uint32_t use_hw_non_stalling_scoreboard;
 231     //input surface
 232     struct i965_gpe_resource res_uncompressed_input_surface;
 233     //reconstructed surface
 234     struct i965_gpe_resource res_reconstructed_surface;
 235     //output bitstream
 236     struct {
 237         struct i965_gpe_resource res;
 238         uint32_t start_offset;
 239         uint32_t end_offset;
 240     } compressed_bitstream;
 241
 242     bool (*get_kernel_header_and_size)(
 243         void *pvbinary,
 244         int binary_size,
 245         INTEL_GENERIC_ENC_OPERATION operation,
 246         int krnstate_idx,
 247         struct i965_kernel *ret_kernel);
 248
 249     //curbe set function pointer
 250     void (*pfn_set_curbe_scaling2x)(
 251         VADriverContextP ctx,
 252         struct encode_state *encode_state,
 253         struct i965_gpe_context *gpe_context,
 254         struct intel_encoder_context *encoder_context,
 255         void *param);
 256
 257     void (*pfn_set_curbe_scaling4x)(
 258         VADriverContextP ctx,
 259         struct encode_state *encode_state,
 260         struct i965_gpe_context *gpe_context,
 261         struct intel_encoder_context *encoder_context,
 262         void *param);
 263
 264     void (*pfn_set_curbe_me)(
 265         VADriverContextP ctx,
 266         struct encode_state *encode_state,
 267         struct i965_gpe_context *gpe_context,
 268         struct intel_encoder_context *encoder_context,
 269         void *param);
 270
 271     void (*pfn_set_curbe_mbenc)(
 272         VADriverContextP ctx,
 273         struct encode_state *encode_state,
 274         struct i965_gpe_context *gpe_context,
 275         struct intel_encoder_context *encoder_context,
 276         void *param);
 277
 278     void (*pfn_set_curbe_brc_init_reset)(
 279         VADriverContextP ctx,
 280         struct encode_state *encode_state,
 281         struct i965_gpe_context *gpe_context,
 282         struct intel_encoder_context *encoder_context,
 283         void *param);
 284
 285     void (*pfn_set_curbe_brc_frame_update)(
 286         VADriverContextP ctx,
 287         struct encode_state *encode_state,
 288         struct i965_gpe_context *gpe_context,
 289         struct intel_encoder_context *encoder_context,
 290         void *param);
 291
 292     void (*pfn_set_curbe_brc_mb_update)(
 293         VADriverContextP ctx,
 294         struct encode_state *encode_state,
 295         struct i965_gpe_context *gpe_context,
 296         struct intel_encoder_context *encoder_context,
 297         void *param);
 298
 299     void (*pfn_set_curbe_sfd)(
 300         VADriverContextP ctx,
 301         struct encode_state *encode_state,
 302         struct i965_gpe_context *gpe_context,
 303         struct intel_encoder_context *encoder_context,
 304         void *param);
 305
 306     void (*pfn_set_curbe_wp)(
 307         VADriverContextP ctx,
 308         struct encode_state *encode_state,
 309         struct i965_gpe_context *gpe_context,
 310         struct intel_encoder_context *encoder_context,
 311         void *param);
 312
 313     void (*pfn_set_curbe_preproc)(
 314         VADriverContextP ctx,
 315         struct encode_state *encode_state,
 316         struct i965_gpe_context *gpe_context,
 317         struct intel_encoder_context *encoder_context,
 318         void *param);
 319
 320     //surface set function pointer
 321     void (*pfn_send_scaling_surface)(
 322         VADriverContextP ctx,
 323         struct encode_state *encode_state,
 324         struct i965_gpe_context *gpe_context,
 325         struct intel_encoder_context *encoder_context,
 326         void *param);
 327
 328     void (*pfn_send_me_surface)(
 329         VADriverContextP ctx,
 330         struct encode_state *encode_state,
 331         struct i965_gpe_context *gpe_context,
 332         struct intel_encoder_context *encoder_context,
 333         void *param);
 334
 335     void (*pfn_send_mbenc_surface)(
 336         VADriverContextP ctx,
 337         struct encode_state *encode_state,
 338         struct i965_gpe_context *gpe_context,
 339         struct intel_encoder_context *encoder_context,
 340         void *param);
 341
 342     void (*pfn_send_brc_init_reset_surface)(
 343         VADriverContextP ctx,
 344         struct encode_state *encode_state,
 345         struct i965_gpe_context *gpe_context,
 346         struct intel_encoder_context *encoder_context,
 347         void *param);
 348
 349     void (*pfn_send_brc_frame_update_surface)(
 350         VADriverContextP ctx,
 351         struct encode_state *encode_state,
 352         struct i965_gpe_context *gpe_context,
 353         struct intel_encoder_context *encoder_context,
 354         void *param);
 355
 356     void (*pfn_send_brc_mb_update_surface)(
 357         VADriverContextP ctx,
 358         struct encode_state *encode_state,
 359         struct i965_gpe_context *gpe_context,
 360         struct intel_encoder_context *encoder_context,
 361         void *param);
 362
 363     void (*pfn_send_sfd_surface)(
 364         VADriverContextP ctx,
 365         struct encode_state *encode_state,
 366         struct i965_gpe_context *gpe_context,
 367         struct intel_encoder_context *encoder_context,
 368         void *param);
 369
 370     void (*pfn_send_wp_surface)(
 371         VADriverContextP ctx,
 372         struct encode_state *encode_state,
 373         struct i965_gpe_context *gpe_context,
 374         struct intel_encoder_context *encoder_context,
 375         void *param);
 376
 377     void (*pfn_send_preproc_surface)(
 378         VADriverContextP ctx,
 379         struct encode_state *encode_state,
 380         struct i965_gpe_context *gpe_context,
 381         struct intel_encoder_context *encoder_context,
 382         void *param);
 383 };
 384 /*
 385    the definition for encoder codec state
 386 */
 387
 388 struct generic_enc_codec_state {
 389
 390     //generic related
 391     int32_t  kernel_mode;
 392     int32_t  preset;
 393     int32_t  seq_frame_number;
 394     int32_t  total_frame_number;
 395     int32_t  herder_bytes_inserted;
 396     uint8_t  frame_type;
 397     bool     first_frame;
 398
 399     // original width/height
 400     uint32_t frame_width_in_pixel;
 401     uint32_t frame_height_in_pixel;
 402     uint32_t frame_width_in_mbs;
 403     uint32_t frame_height_in_mbs;
 404
 405     //scaling related
 406     uint32_t frame_width_2x;
 407     uint32_t frame_height_2x;
 408     uint32_t downscaled_width_2x_in_mb;
 409     uint32_t downscaled_height_2x_in_mb;
 410     uint32_t frame_width_4x;
 411     uint32_t frame_height_4x;
 412     uint32_t frame_width_16x;
 413     uint32_t frame_height_16x;
 414     uint32_t frame_width_32x;
 415     uint32_t frame_height_32x;
 416     uint32_t downscaled_width_4x_in_mb;
 417     uint32_t downscaled_height_4x_in_mb;
 418     uint32_t downscaled_width_16x_in_mb;
 419     uint32_t downscaled_height_16x_in_mb;
 420     uint32_t downscaled_width_32x_in_mb;
 421     uint32_t downscaled_height_32x_in_mb;
 422
 423     // ME related
 424     uint32_t hme_supported: 1;
 425     uint32_t b16xme_supported: 1;
 426     uint32_t b32xme_supported: 1;
 427     uint32_t hme_enabled: 1;
 428     uint32_t b16xme_enabled: 1;
 429     uint32_t b32xme_enabled: 1;
 430     uint32_t brc_distortion_buffer_supported: 1;
 431     uint32_t brc_constant_buffer_supported: 1;
 432     uint32_t hme_reserved: 24;
 433
 434     //BRC related
 435     uint32_t frame_rate;
 436     uint32_t internal_rate_mode;
 437
 438     uint32_t brc_allocated: 1;
 439     uint32_t brc_inited: 1;
 440     uint32_t brc_need_reset: 1;
 441     uint32_t is_low_delay: 1;
 442     uint32_t brc_enabled: 1;
 443     uint32_t curr_pak_pass: 4;
 444     uint32_t num_pak_passes: 4;
 445     uint32_t is_first_pass: 1;
 446     uint32_t is_last_pass: 1;
 447     uint32_t mb_brc_enabled: 1;
 448     uint32_t brc_roi_enable: 1;
 449     uint32_t brc_dirty_roi_enable: 1;
 450     uint32_t skip_frame_enbale: 1;
 451     uint32_t brc_reserved: 13;
 452
 453     uint32_t target_bit_rate;
 454     uint32_t max_bit_rate;
 455     uint32_t min_bit_rate;
 456     uint64_t init_vbv_buffer_fullness_in_bit;
 457     uint64_t vbv_buffer_size_in_bit;
 458     uint32_t frames_per_100s;
 459     uint32_t gop_size;
 460     uint32_t gop_ref_distance;
 461     uint32_t brc_target_size;
 462     uint32_t brc_mode;
 463     double   brc_init_current_target_buf_full_in_bits;
 464     double   brc_init_reset_input_bits_per_frame;
 465     uint32_t brc_init_reset_buf_size_in_bits;
 466     uint32_t brc_init_previous_target_buf_full_in_bits;
 467     int32_t  frames_per_window_size;
 468     int32_t  target_percentage;
 469     uint16_t avbr_curracy;
 470     uint16_t avbr_convergence;
 471
 472     //skip frame enbale
 473     uint32_t num_skip_frames;
 474     uint32_t size_skip_frames;
 475
 476     // ROI related
 477     uint32_t dirty_num_roi;
 478     uint32_t num_roi;
 479     uint32_t max_delta_qp;
 480     uint32_t min_delta_qp;
 481     struct intel_roi roi[INTEL_ROI_NUM];
 482
 483 };
 484
 485 /*
 486  by now VME and PAK use the same context. it will bind the ctx according to the codec and platform, also vdenc and non-vdenc
 487 */
 488 struct encoder_vme_mfc_context {
 489     int32_t codec_id;
 490     void * generic_enc_ctx;
 491     void * private_enc_ctx; //pointer to the specific enc_ctx
 492     void * generic_enc_state;
 493     void * private_enc_state; //pointer to the specific enc_state
 494 };
 495
 496 #endif /* _I965_COMMON_ENCODER_H */