src/i965_encoder_common.h

   1 /*
   2  * Copyright ? 2016 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the
   6  * "Software"), to deal in the Software without restriction, including
   7  * without limitation the rights to use, copy, modify, merge, publish,
   8  * distribute, sub license, and/or sell copies of the Software, and to
   9  * permit persons to whom the Software is furnished to do so, subject to
  10  * the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the
  13  * next paragraph) shall be included in all copies or substantial portions
  14  * of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  17  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  18  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  19  * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
  20  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  21  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  22  * SOFTWAR
  23  *
  24  * Authors:
  25  *     Pengfei Qu <Pengfei.Qu@intel.com>
  26  *
  27  */
  28
  29 #ifndef _I965_COMMON_ENCODER_H
  30 #define _I965_COMMON_ENCODER_H
  31
  32 #include <drm.h>
  33 #include <i915_drm.h>
  34 #include <intel_bufmgr.h>
  35
  36 #include <va/va.h>
  37 #include "i965_encoder.h"
  38 #include "i965_gpe_utils.h"
  39 //#include "gen9_avc_encoder.h"
  40
  41 struct encode_state;
  42 struct intel_encoder_context;
  43
  44 /*
  45    this file define the common structure for encoder, such as H264/H265/VP8/VP9
  46 */
  47
  48 #define INTEL_BRC_NONE   0
  49 #define INTEL_BRC_CBR    1
  50 #define INTEL_BRC_VBR    2
  51 #define INTEL_BRC_CQP    3
  52 #define INTEL_BRC_AVBR   4
  53
  54 #define INTEL_BRC_INIT_FLAG_CBR                        0x0010,
  55 #define INTEL_BRC_INIT_FLAG_VBR                        0x0020,
  56 #define INTEL_BRC_INIT_FLAG_AVBR                       0x0040,
  57 #define INTEL_BRC_INIT_FLAG_CQL                        0x0080,
  58 #define INTEL_BRC_INIT_FLAG_FIELD_PIC                  0x0100,
  59 #define INTEL_BRC_INIT_FLAG_ICQ                        0x0200,
  60 #define INTEL_BRC_INIT_FLAG_VCM                        0x0400,
  61 #define INTEL_BRC_INIT_FLAG_IGNORE_PICTURE_HEADER_SIZE 0x2000,
  62 #define INTEL_BRC_INIT_FLAG_QVBR                       0x4000,
  63 #define INTEL_BRC_INIT_FLAG_DISABLE_MBBRC              0x8000
  64
  65
  66 #define INTEL_BRC_UPDATE_FLAG_FIELD                  0x01,
  67 #define INTEL_BRC_UPDATE_FLAG_MBAFF                  (0x01 << 1),
  68 #define INTEL_BRC_UPDATE_FLAG_BOTTOM_FIELD           (0x01 << 2),
  69 #define INTEL_BRC_UPDATE_FLAG_ACTUALQP               (0x01 << 6),
  70 #define INTEL_BRC_UPDATE_FLAG_REFERENCE              (0x01 << 7)
  71
  72 #define INTEL_VME_MIN_ALLOWED_WIDTH_HEIGHT           48
  73
  74 extern const unsigned int table_enc_search_path[2][8][16];
  75
  76 // BRC Flag in BRC Init Kernel
  77 typedef enum _INTEL_ENCODE_BRCINIT_FLAG
  78 {
  79     INTEL_ENCODE_BRCINIT_ISCBR                       = 0x0010,
  80     INTEL_ENCODE_BRCINIT_ISVBR                       = 0x0020,
  81     INTEL_ENCODE_BRCINIT_ISAVBR                      = 0x0040,
  82     INTEL_ENCODE_BRCINIT_ISCQL                       = 0x0080,
  83     INTEL_ENCODE_BRCINIT_FIELD_PIC                   = 0x0100,
  84     INTEL_ENCODE_BRCINIT_ISICQ                       = 0x0200,
  85     INTEL_ENCODE_BRCINIT_ISVCM                       = 0x0400,
  86     INTEL_ENCODE_BRCINIT_IGNORE_PICTURE_HEADER_SIZE  = 0x2000,
  87     INTEL_ENCODE_BRCINIT_ISQVBR                      = 0x4000,
  88     INTEL_ENCODE_BRCINIT_DISABLE_MBBRC               = 0x8000
  89 } INTEL_ENCODE_BRCINIT_FLAG;
  90
  91 // BRC Flag in BRC Update Kernel
  92 typedef enum _INTEL_ENCODE_BRCUPDATE_FLAG
  93 {
  94     INTEL_ENCODE_BRCUPDATE_IS_FIELD                  = 0x01,
  95     INTEL_ENCODE_BRCUPDATE_IS_MBAFF                  = (0x01 << 1),
  96     INTEL_ENCODE_BRCUPDATE_IS_BOTTOM_FIELD           = (0x01 << 2),
  97     INTEL_ENCODE_BRCUPDATE_IS_ACTUALQP               = (0x01 << 6),
  98     INTEL_ENCODE_BRCUPDATE_IS_REFERENCE              = (0x01 << 7)
  99 } INTEL_ENCODE_BRCUPDATE_FLAG;
 100
 101 /*
 102 kernel operation related defines
 103 */
 104 typedef enum _INTEL_GENERIC_ENC_OPERATION
 105 {
 106     INTEL_GENERIC_ENC_SCALING4X = 0,
 107     INTEL_GENERIC_ENC_SCALING2X,
 108     INTEL_GENERIC_ENC_ME,
 109     INTEL_GENERIC_ENC_BRC,
 110     INTEL_GENERIC_ENC_MBENC,
 111     INTEL_GENERIC_ENC_MBENC_WIDI,
 112     INTEL_GENERIC_ENC_RESETVLINESTRIDE,
 113     INTEL_GENERIC_ENC_MC,
 114     INTEL_GENERIC_ENC_MBPAK,
 115     INTEL_GENERIC_ENC_DEBLOCK,
 116     INTEL_GENERIC_ENC_PREPROC,
 117     INTEL_GENERIC_VDENC_ME,
 118     INTEL_GENERIC_ENC_WP,
 119     INTEL_GENERIC_ENC_SFD,                   // Static frame detection
 120     INTEL_GENERIC_ENC_DYS
 121 } INTEL_GENERIC_ENC_OPERATION;
 122
 123 typedef enum _INTEL_MEDIA_STATE_TYPE
 124 {
 125     INTEL_MEDIA_STATE_OLP                                = 0,
 126     INTEL_MEDIA_STATE_ENC_NORMAL                         = 1,
 127     INTEL_MEDIA_STATE_ENC_PERFORMANCE                    = 2,
 128     INTEL_MEDIA_STATE_ENC_QUALITY                        = 3,
 129     INTEL_MEDIA_STATE_ENC_I_FRAME_DIST                   = 4,
 130     INTEL_MEDIA_STATE_32X_SCALING                        = 5,
 131     INTEL_MEDIA_STATE_16X_SCALING                        = 6,
 132     INTEL_MEDIA_STATE_4X_SCALING                         = 7,
 133     INTEL_MEDIA_STATE_32X_ME                             = 8,
 134     INTEL_MEDIA_STATE_16X_ME                             = 9,
 135     INTEL_MEDIA_STATE_4X_ME                              = 10,
 136     INTEL_MEDIA_STATE_BRC_INIT_RESET                     = 11,
 137     INTEL_MEDIA_STATE_BRC_UPDATE                         = 12,
 138     INTEL_MEDIA_STATE_BRC_BLOCK_COPY                     = 13,
 139     INTEL_MEDIA_STATE_HYBRID_PAK_P1                      = 14,
 140     INTEL_MEDIA_STATE_HYBRID_PAK_P2                      = 15,
 141     INTEL_MEDIA_STATE_ENC_I_FRAME_CHROMA                 = 16,
 142     INTEL_MEDIA_STATE_ENC_I_FRAME_LUMA                   = 17,
 143     INTEL_MEDIA_STATE_MPU_FHB                            = 18,
 144     INTEL_MEDIA_STATE_TPU_FHB                            = 19,
 145     INTEL_MEDIA_STATE_PA_COPY                            = 20,
 146     INTEL_MEDIA_STATE_PL2_COPY                           = 21,
 147     INTEL_MEDIA_STATE_ENC_WIDI                           = 22,
 148     INTEL_MEDIA_STATE_2X_SCALING                         = 23,
 149     INTEL_MEDIA_STATE_32x32_PU_MODE_DECISION             = 24,
 150     INTEL_MEDIA_STATE_16x16_PU_SAD                       = 25,
 151     INTEL_MEDIA_STATE_16x16_PU_MODE_DECISION             = 26,
 152     INTEL_MEDIA_STATE_8x8_PU                             = 27,
 153     INTEL_MEDIA_STATE_8x8_PU_FMODE                       = 28,
 154     INTEL_MEDIA_STATE_32x32_B_INTRA_CHECK                = 29,
 155     INTEL_MEDIA_STATE_HEVC_B_MBENC                       = 30,
 156     INTEL_MEDIA_STATE_RESET_VLINE_STRIDE                 = 31,
 157     INTEL_MEDIA_STATE_HEVC_B_PAK                         = 32,
 158     INTEL_MEDIA_STATE_HEVC_BRC_LCU_UPDATE                = 33,
 159     INTEL_MEDIA_STATE_ME_VDENC_STREAMIN                  = 34,
 160     INTEL_MEDIA_STATE_VP9_ENC_I_32x32                    = 35,
 161     INTEL_MEDIA_STATE_VP9_ENC_I_16x16                    = 36,
 162     INTEL_MEDIA_STATE_VP9_ENC_P                          = 37,
 163     INTEL_MEDIA_STATE_VP9_ENC_TX                         = 38,
 164     INTEL_MEDIA_STATE_VP9_DYS                            = 39,
 165     INTEL_MEDIA_STATE_VP9_PAK_LUMA_RECON                 = 40,
 166     INTEL_MEDIA_STATE_VP9_PAK_CHROMA_RECON               = 41,
 167     INTEL_MEDIA_STATE_VP9_PAK_DEBLOCK_MASK               = 42,
 168     INTEL_MEDIA_STATE_VP9_PAK_LUMA_DEBLOCK               = 43,
 169     INTEL_MEDIA_STATE_VP9_PAK_CHROMA_DEBLOCK             = 44,
 170     INTEL_MEDIA_STATE_VP9_PAK_MC_PRED                    = 45,
 171     INTEL_MEDIA_STATE_VP9_PAK_P_FRAME_LUMA_RECON         = 46,
 172     INTEL_MEDIA_STATE_VP9_PAK_P_FRAME_LUMA_RECON_32x32   = 47,
 173     INTEL_MEDIA_STATE_VP9_PAK_P_FRAME_CHROMA_RECON       = 48,
 174     INTEL_MEDIA_STATE_VP9_PAK_P_FRAME_INTRA_LUMA_RECON   = 49,
 175     INTEL_MEDIA_STATE_VP9_PAK_P_FRAME_INTRA_CHROMA_RECON = 50,
 176     INTEL_MEDIA_STATE_PREPROC                            = 51,
 177     INTEL_MEDIA_STATE_ENC_WP                             = 52,
 178     INTEL_MEDIA_STATE_HEVC_I_MBENC                       = 53,
 179     INTEL_MEDIA_STATE_CSC_DS_COPY                        = 54,
 180     INTEL_MEDIA_STATE_2X_4X_SCALING                      = 55,
 181     INTEL_MEDIA_STATE_HEVC_LCU64_B_MBENC                 = 56,
 182     INTEL_MEDIA_STATE_MB_BRC_UPDATE                      = 57,
 183     INTEL_MEDIA_STATE_STATIC_FRAME_DETECTION             = 58,
 184     INTEL_MEDIA_STATE_HEVC_ROI                           = 59,
 185     INTEL_MEDIA_STATE_SW_SCOREBOARD_INIT                 = 60,
 186     INTEL_NUM_MEDIA_STATES                               = 61
 187 } INTEL_MEDIA_STATE_TYPE;
 188
 189 struct encoder_kernel_parameter
 190 {
 191     unsigned int curbe_size;
 192     unsigned int inline_data_size;
 193     unsigned int sampler_size;
 194 };
 195
 196 struct encoder_scoreboard_parameter
 197 {
 198     unsigned int mask;
 199     unsigned int type;
 200     unsigned int enable;
 201     unsigned int walkpat_flag;
 202 };
 203
 204
 205 /*
 206 ME related defines
 207 */
 208 #define INTEL_ENC_HME_4x    0
 209 #define INTEL_ENC_HME_16x   1
 210 #define INTEL_ENC_HME_32x   2
 211
 212 /*
 213    the definition for rate control
 214 */
 215 #define GENERIC_BRC_SEQ         0x01
 216 #define GENERIC_BRC_HRD         0x02
 217 #define GENERIC_BRC_RC          0x04
 218 #define GENERIC_BRC_FR          0x08
 219 #define GENERIC_BRC_FAILURE     (1 << 31)
 220
 221 enum INTEL_ENC_KERNAL_MODE
 222 {
 223     INTEL_ENC_KERNEL_QUALITY      = 0,
 224     INTEL_ENC_KERNEL_NORMAL,
 225     INTEL_ENC_KERNEL_PERFORMANCE
 226 };
 227
 228 enum INTEL_ENC_PRESET_MODE
 229 {
 230     INTEL_PRESET_UNKNOWN         = 0,
 231     INTEL_PRESET_BEST_QUALITY    = 1,
 232     INTEL_PRESET_HI_QUALITY      = 2,
 233     INTEL_PRESET_OPT_QUALITY     = 3,
 234     INTEL_PRESET_OK_QUALITY      = 5,
 235     INTEL_PRESET_NO_SPEED        = 1,
 236     INTEL_PRESET_OPT_SPEED       = 3,
 237     INTEL_PRESET_RT_SPEED        = 4,
 238     INTEL_PRESET_HI_SPEED        = 6,
 239     INTEL_PRESET_BEST_SPEED      = 7,
 240     INTEL_PRESET_LOW_LATENCY     = 0x10,
 241     INTEL_PRESET_MULTIPASS       = 0x20
 242 };
 243 /*
 244    the definition for encoder status
 245 */
 246 struct encoder_status
 247 {
 248     uint32_t bs_byte_count;
 249     uint32_t image_status_ctrl;
 250     uint32_t media_index;
 251 };
 252
 253 struct encoder_status_buffer_internal
 254 {
 255     uint32_t bs_byte_count_offset;
 256     uint32_t reserved[15];
 257
 258     uint32_t image_status_ctrl_offset;
 259
 260     uint32_t bs_frame_reg_offset;
 261     uint32_t image_status_ctrl_reg_offset;
 262     dri_bo *bo;
 263     uint32_t status_buffer_size;
 264     uint32_t base_offset;
 265
 266     uint32_t media_index_offset;
 267 };
 268
 269 struct {
 270     struct i965_gpe_resource res;
 271     uint32_t base_offset;
 272     uint32_t size;
 273     uint32_t bytes_per_frame_offset;
 274 } status_bffuer;
 275
 276 /*
 277    the definition for encoder VME/PAK context
 278 */
 279
 280
 281 struct generic_encoder_context
 282 {
 283     //scoreboard
 284     uint32_t use_hw_scoreboard;
 285     uint32_t use_hw_non_stalling_scoreboard;
 286     //input surface
 287     struct i965_gpe_resource res_uncompressed_input_surface;
 288     //reconstructed surface
 289     struct i965_gpe_resource res_reconstructed_surface;
 290     //output bitstream
 291     struct {
 292         struct i965_gpe_resource res;
 293         uint32_t start_offset;
 294         uint32_t end_offset;
 295     } compressed_bitstream;
 296
 297     //curbe set function pointer
 298     void (*pfn_set_curbe_scaling2x)(
 299         VADriverContextP ctx,
 300         struct encode_state *encode_state,
 301         struct i965_gpe_context *gpe_context,
 302         struct intel_encoder_context *encoder_context,
 303         void *param);
 304
 305     void (*pfn_set_curbe_scaling4x)(
 306         VADriverContextP ctx,
 307         struct encode_state *encode_state,
 308         struct i965_gpe_context *gpe_context,
 309         struct intel_encoder_context *encoder_context,
 310         void *param);
 311
 312     void (*pfn_set_curbe_me)(
 313         VADriverContextP ctx,
 314         struct encode_state *encode_state,
 315         struct i965_gpe_context *gpe_context,
 316         struct intel_encoder_context *encoder_context,
 317         void *param);
 318
 319     void (*pfn_set_curbe_mbenc)(
 320         VADriverContextP ctx,
 321         struct encode_state *encode_state,
 322         struct i965_gpe_context *gpe_context,
 323         struct intel_encoder_context *encoder_context,
 324         void *param);
 325
 326     void (*pfn_set_curbe_brc_init_reset)(
 327         VADriverContextP ctx,
 328         struct encode_state *encode_state,
 329         struct i965_gpe_context *gpe_context,
 330         struct intel_encoder_context *encoder_context,
 331         void *param);
 332
 333     void (*pfn_set_curbe_brc_frame_update)(
 334         VADriverContextP ctx,
 335         struct encode_state *encode_state,
 336         struct i965_gpe_context *gpe_context,
 337         struct intel_encoder_context *encoder_context,
 338         void *param);
 339
 340     void (*pfn_set_curbe_brc_mb_update)(
 341         VADriverContextP ctx,
 342         struct encode_state *encode_state,
 343         struct i965_gpe_context *gpe_context,
 344         struct intel_encoder_context *encoder_context,
 345         void *param);
 346
 347     void (*pfn_set_curbe_sfd)(
 348         VADriverContextP ctx,
 349         struct encode_state *encode_state,
 350         struct i965_gpe_context *gpe_context,
 351         struct intel_encoder_context *encoder_context,
 352         void *param);
 353
 354     void (*pfn_set_curbe_wp)(
 355         VADriverContextP ctx,
 356         struct encode_state *encode_state,
 357         struct i965_gpe_context *gpe_context,
 358         struct intel_encoder_context *encoder_context,
 359         void *param);
 360
 361     //surface set function pointer
 362     void (*pfn_send_scaling_surface)(
 363         VADriverContextP ctx,
 364         struct encode_state *encode_state,
 365         struct i965_gpe_context *gpe_context,
 366         struct intel_encoder_context *encoder_context,
 367         void *param);
 368
 369     void (*pfn_send_me_surface)(
 370         VADriverContextP ctx,
 371         struct encode_state *encode_state,
 372         struct i965_gpe_context *gpe_context,
 373         struct intel_encoder_context *encoder_context,
 374         void *param);
 375
 376     void (*pfn_send_mbenc_surface)(
 377         VADriverContextP ctx,
 378         struct encode_state *encode_state,
 379         struct i965_gpe_context *gpe_context,
 380         struct intel_encoder_context *encoder_context,
 381         void *param);
 382
 383     void (*pfn_send_brc_init_reset_surface)(
 384         VADriverContextP ctx,
 385         struct encode_state *encode_state,
 386         struct i965_gpe_context *gpe_context,
 387         struct intel_encoder_context *encoder_context,
 388         void *param);
 389
 390     void (*pfn_send_brc_frame_update_surface)(
 391         VADriverContextP ctx,
 392         struct encode_state *encode_state,
 393         struct i965_gpe_context *gpe_context,
 394         struct intel_encoder_context *encoder_context,
 395         void *param);
 396
 397     void (*pfn_send_brc_mb_update_surface)(
 398         VADriverContextP ctx,
 399         struct encode_state *encode_state,
 400         struct i965_gpe_context *gpe_context,
 401         struct intel_encoder_context *encoder_context,
 402         void *param);
 403
 404     void (*pfn_send_sfd_surface)(
 405         VADriverContextP ctx,
 406         struct encode_state *encode_state,
 407         struct i965_gpe_context *gpe_context,
 408         struct intel_encoder_context *encoder_context,
 409         void *param);
 410
 411     void (*pfn_send_wp_surface)(
 412         VADriverContextP ctx,
 413         struct encode_state *encode_state,
 414         struct i965_gpe_context *gpe_context,
 415         struct intel_encoder_context *encoder_context,
 416         void *param);
 417
 418
 419
 420 };
 421 /*
 422    the definition for encoder codec state
 423 */
 424
 425 struct generic_enc_codec_state {
 426
 427     //generic related
 428     int32_t  kernel_mode;
 429     int32_t  preset;
 430     int32_t  seq_frame_number;
 431     int32_t  total_frame_number;
 432     int32_t  herder_bytes_inserted;
 433     uint8_t  frame_type;
 434     bool     first_frame;
 435
 436     // original width/height
 437     uint32_t frame_width_in_pixel;
 438     uint32_t frame_height_in_pixel;
 439     uint32_t frame_width_in_mbs;
 440     uint32_t frame_height_in_mbs;
 441
 442     //scaling related
 443     uint32_t frame_width_2x;
 444     uint32_t frame_height_2x;
 445     uint32_t downscaled_width_2x_in_mb;
 446     uint32_t downscaled_height_2x_in_mb;
 447     uint32_t frame_width_4x;
 448     uint32_t frame_height_4x;
 449     uint32_t frame_width_16x;
 450     uint32_t frame_height_16x;
 451     uint32_t frame_width_32x;
 452     uint32_t frame_height_32x;
 453     uint32_t downscaled_width_4x_in_mb;
 454     uint32_t downscaled_height_4x_in_mb;
 455     uint32_t downscaled_width_16x_in_mb;
 456     uint32_t downscaled_height_16x_in_mb;
 457     uint32_t downscaled_width_32x_in_mb;
 458     uint32_t downscaled_height_32x_in_mb;
 459
 460     // ME related
 461     uint32_t hme_supported:1;
 462     uint32_t b16xme_supported:1;
 463     uint32_t b32xme_supported:1;
 464     uint32_t hme_enabled:1;
 465     uint32_t b16xme_enabled:1;
 466     uint32_t b32xme_enabled:1;
 467     uint32_t brc_distortion_buffer_supported:1;
 468     uint32_t brc_constant_buffer_supported:1;
 469     uint32_t hme_reserved:24;
 470
 471     //BRC related
 472     uint32_t frame_rate;
 473
 474     uint32_t brc_allocated:1;
 475     uint32_t brc_inited:1;
 476     uint32_t brc_need_reset:1;
 477     uint32_t is_low_delay:1;
 478     uint32_t brc_enabled:1;
 479     uint32_t internal_rate_mode:4;
 480     uint32_t curr_pak_pass:4;
 481     uint32_t num_pak_passes:4;
 482     uint32_t is_first_pass:1;
 483     uint32_t is_last_pass:1;
 484     uint32_t mb_brc_enabled:1;
 485     uint32_t brc_roi_enable:1;
 486     uint32_t brc_dirty_roi_enable:1;
 487     uint32_t skip_frame_enbale:1;
 488     uint32_t brc_reserved:9;
 489
 490     uint32_t target_bit_rate;
 491     uint32_t max_bit_rate;
 492     uint32_t min_bit_rate;
 493     uint64_t init_vbv_buffer_fullness_in_bit;
 494     uint64_t vbv_buffer_size_in_bit;
 495     uint32_t frames_per_100s;
 496     uint32_t gop_size;
 497     uint32_t gop_ref_distance;
 498     uint32_t brc_target_size;
 499     uint32_t brc_mode;
 500     double   brc_init_current_target_buf_full_in_bits;
 501     double   brc_init_reset_input_bits_per_frame;
 502     uint32_t brc_init_reset_buf_size_in_bits;
 503     uint32_t brc_init_previous_target_buf_full_in_bits;
 504     int32_t  window_size;
 505     int32_t  target_percentage;
 506     uint16_t avbr_curracy;
 507     uint16_t avbr_convergence;
 508
 509     //skip frame enbale
 510     uint32_t num_skip_frames;
 511     uint32_t size_skip_frames;
 512
 513     // ROI related
 514     uint32_t dirty_num_roi;
 515     uint32_t num_roi;
 516     uint32_t max_delta_qp;
 517     uint32_t min_delta_qp;
 518     struct intel_roi roi[3];
 519
 520 };
 521
 522 /*
 523  by now VME and PAK use the same context. it will bind the ctx according to the codec and platform, also vdenc and non-vdenc
 524 */
 525 struct encoder_vme_mfc_context {
 526     int32_t codec_id;
 527     void * generic_enc_ctx;
 528     void * private_enc_ctx; //pointer to the specific enc_ctx
 529     void * generic_enc_state;
 530     void * private_enc_state; //pointer to the specific enc_state
 531 };
 532
 533 #endif /* _I965_COMMON_ENCODER_H */