src/i965_encoder_vp8.c

   1 /*
   2  * Copyright © 2017 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the
   6  * "Software"), to deal in the Software without restriction, including
   7  * without limitation the rights to use, copy, modify, merge, publish,
   8  * distribute, sub license, and/or sell copies of the Software, and to
   9  * permit persons to whom the Software is furnished to do so, subject to
  10  * the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the
  13  * next paragraph) shall be included in all copies or substantial portions
  14  * of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  17  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  18  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  19  * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
  20  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  21  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  22  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors:
  25  *    Xiang, Haihao <haihao.xiang@intel.com>
  26  *
  27  */
  28
  29 #include <stdio.h>
  30 #include <stdlib.h>
  31 #include <stdbool.h>
  32 #include <string.h>
  33 #include <math.h>
  34 #include <time.h>
  35 #include <assert.h>
  36
  37 #include "intel_batchbuffer.h"
  38 #include "intel_driver.h"
  39
  40 #include "i965_defines.h"
  41 #include "i965_drv_video.h"
  42 #include "i965_encoder.h"
  43 #include "i965_encoder_vp8.h"
  44 #include "vp8_probs.h"
  45 #include "vpx_quant.h"
  46
  47 #define SCALE_FACTOR_4X                 4
  48 #define SCALE_FACTOR_16X                16
  49
  50 #define MAX_VP8_ENCODER_SURFACES        128
  51
  52 #define MAX_URB_SIZE                    2048 /* In register */
  53 #define NUM_KERNELS_PER_GPE_CONTEXT     1
  54
  55 #define VP8_BRC_KBPS                    1000
  56
  57 #define BRC_KERNEL_CBR                  0x0010
  58 #define BRC_KERNEL_VBR                  0x0020
  59
  60 struct i965_kernel vp8_kernels_brc_init_reset[NUM_VP8_BRC_RESET] = {
  61     {
  62         "VP8 BRC Init",
  63         VP8_BRC_INIT,
  64         NULL,
  65         0,
  66         NULL
  67     },
  68
  69     {
  70         "VP8 BRC Reset",
  71         VP8_BRC_RESET,
  72         NULL,
  73         0,
  74         NULL
  75     },
  76 };
  77
  78 struct i965_kernel vp8_kernels_scaling[NUM_VP8_SCALING] = {
  79     {
  80         "VP8 SCALE 4X",
  81         VP8_SCALING_4X,
  82         NULL,
  83         0,
  84         NULL
  85     },
  86
  87     {
  88         "VP8 SCALE 16",
  89         VP8_SCALING_16X,
  90         NULL,
  91         0,
  92         NULL
  93     },
  94 };
  95
  96 struct i965_kernel vp8_kernels_me[NUM_VP8_ME] = {
  97     {
  98         "VP8 ME 4X",
  99         VP8_ME_4X,
 100         NULL,
 101         0,
 102         NULL
 103     },
 104
 105     {
 106         "VP8 ME 16",
 107         VP8_ME_16X,
 108         NULL,
 109         0,
 110         NULL
 111     },
 112 };
 113
 114 struct i965_kernel vp8_kernels_mbenc[NUM_VP8_MBENC] = {
 115     {
 116         "VP8 MBEnc I Frame Dist",
 117         VP8_MBENC_I_FRAME_DIST,
 118         NULL,
 119         0,
 120         NULL
 121     },
 122
 123     {
 124         "VP8 MBEnc I Frame Luma",
 125         VP8_MBENC_I_FRAME_LUMA,
 126         NULL,
 127         0,
 128         NULL
 129     },
 130
 131     {
 132         "VP8 MBEnc I Frame Chroma",
 133         VP8_MBENC_I_FRAME_CHROMA,
 134         NULL,
 135         0,
 136         NULL
 137     },
 138
 139     {
 140         "VP8 MBEnc P Frame",
 141         VP8_MBENC_P_FRAME,
 142         NULL,
 143         0,
 144         NULL
 145     },
 146 };
 147
 148 struct i965_kernel vp8_kernels_mpu[NUM_VP8_MPU] = {
 149     {
 150         "VP8 MPU",
 151         VP8_MPU,
 152         NULL,
 153         0,
 154         NULL
 155     },
 156 };
 157
 158 struct i965_kernel vp8_kernels_tpu[NUM_VP8_TPU] = {
 159     {
 160         "VP8 TPU",
 161         VP8_TPU,
 162         NULL,
 163         0,
 164         NULL
 165     },
 166 };
 167
 168 struct i965_kernel vp8_kernels_brc_update[NUM_VP8_BRC_UPDATE] = {
 169     {
 170         "VP8 BRC Update",
 171         VP8_BRC_UPDATE,
 172         NULL,
 173         0,
 174         NULL
 175     },
 176 };
 177
 178 static const unsigned char
 179 vp8_num_refs[8] = {
 180     0, 1, 1, 2, 1, 2, 2, 3
 181 };
 182
 183 static const unsigned int
 184 vp8_search_path[8][16] = {
 185     // MEMethod: 0
 186     {
 187         0x120FF10F, 0x1E22E20D, 0x20E2FF10, 0x2EDD06FC, 0x11D33FF1, 0xEB1FF33D, 0x4EF1F1F1, 0xF1F21211,
 188         0x0DFFFFE0, 0x11201F1F, 0x1105F1CF, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000
 189     },
 190     // MEMethod: 1
 191     {
 192         0x120FF10F, 0x1E22E20D, 0x20E2FF10, 0x2EDD06FC, 0x11D33FF1, 0xEB1FF33D, 0x4EF1F1F1, 0xF1F21211,
 193         0x0DFFFFE0, 0x11201F1F, 0x1105F1CF, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000
 194     },
 195     // MEMethod: 2
 196     {
 197         0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
 198         0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000
 199     },
 200     // MEMethod: 3
 201     {
 202         0x01010101, 0x11010101, 0x01010101, 0x11010101, 0x01010101, 0x11010101, 0x01010101, 0x11010101,
 203         0x01010101, 0x11010101, 0x01010101, 0x00010101, 0x00000000, 0x00000000, 0x00000000, 0x00000000
 204     },
 205     // MEMethod: 4
 206     {
 207         0x0101F00F, 0x0F0F1010, 0xF0F0F00F, 0x01010101, 0x10101010, 0x0F0F0F0F, 0xF0F0F00F, 0x0101F0F0,
 208         0x01010101, 0x10101010, 0x0F0F1010, 0x0F0F0F0F, 0xF0F0F00F, 0xF0F0F0F0, 0x00000000, 0x00000000
 209     },
 210     // MEMethod: 5
 211     {
 212         0x0101F00F, 0x0F0F1010, 0xF0F0F00F, 0x01010101, 0x10101010, 0x0F0F0F0F, 0xF0F0F00F, 0x0101F0F0,
 213         0x01010101, 0x10101010, 0x0F0F1010, 0x0F0F0F0F, 0xF0F0F00F, 0xF0F0F0F0, 0x00000000, 0x00000000
 214     },
 215     // MEMethod: 6
 216     {
 217         0x120FF10F, 0x1E22E20D, 0x20E2FF10, 0x2EDD06FC, 0x11D33FF1, 0xEB1FF33D, 0x4EF1F1F1, 0xF1F21211,
 218         0x0DFFFFE0, 0x11201F1F, 0x1105F1CF, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000
 219     },
 220     // MEMethod: 7
 221     {
 222         0x1F11F10F, 0x2E22E2FE, 0x20E220DF, 0x2EDD06FC, 0x11D33FF1, 0xEB1FF33D, 0x02F1F1F1, 0x1F201111,
 223         0xF1EFFF0C, 0xF01104F1, 0x10FF0A50, 0x000FF1C0, 0x00000000, 0x00000000, 0x00000000, 0x00000000
 224     }
 225 };
 226
 227 static const unsigned char
 228 i_frame_vme_costs_vp8[NUM_QP_VP8][4] = {
 229     {0x05, 0x1f, 0x02, 0x09},
 230     {0x05, 0x1f, 0x02, 0x09},
 231     {0x08, 0x2b, 0x03, 0x0e},
 232     {0x08, 0x2b, 0x03, 0x0e},
 233     {0x0a, 0x2f, 0x04, 0x12},
 234     {0x0a, 0x2f, 0x04, 0x12},
 235     {0x0d, 0x39, 0x05, 0x17},
 236     {0x0d, 0x39, 0x05, 0x17},
 237     {0x0d, 0x39, 0x05, 0x17},
 238     {0x0f, 0x3b, 0x06, 0x1b},
 239     {0x0f, 0x3b, 0x06, 0x1b},
 240     {0x19, 0x3d, 0x07, 0x20},
 241     {0x19, 0x3d, 0x07, 0x20},
 242     {0x1a, 0x3f, 0x08, 0x24},
 243     {0x1a, 0x3f, 0x08, 0x24},
 244     {0x1a, 0x3f, 0x08, 0x24},
 245     {0x1b, 0x48, 0x09, 0x29},
 246     {0x1b, 0x48, 0x09, 0x29},
 247     {0x1d, 0x49, 0x09, 0x2d},
 248     {0x1d, 0x49, 0x09, 0x2d},
 249     {0x1d, 0x49, 0x09, 0x2d},
 250     {0x1d, 0x49, 0x09, 0x2d},
 251     {0x1e, 0x4a, 0x0a, 0x32},
 252     {0x1e, 0x4a, 0x0a, 0x32},
 253     {0x1e, 0x4a, 0x0a, 0x32},
 254     {0x1e, 0x4a, 0x0a, 0x32},
 255     {0x1f, 0x4b, 0x0b, 0x36},
 256     {0x1f, 0x4b, 0x0b, 0x36},
 257     {0x1f, 0x4b, 0x0b, 0x36},
 258     {0x28, 0x4c, 0x0c, 0x3b},
 259     {0x28, 0x4c, 0x0c, 0x3b},
 260     {0x29, 0x4d, 0x0d, 0x3f},
 261     {0x29, 0x4d, 0x0d, 0x3f},
 262     {0x29, 0x4e, 0x0e, 0x44},
 263     {0x29, 0x4e, 0x0e, 0x44},
 264     {0x2a, 0x4f, 0x0f, 0x48},
 265     {0x2a, 0x4f, 0x0f, 0x48},
 266     {0x2b, 0x58, 0x10, 0x4d},
 267     {0x2b, 0x58, 0x10, 0x4d},
 268     {0x2b, 0x58, 0x11, 0x51},
 269     {0x2b, 0x58, 0x11, 0x51},
 270     {0x2b, 0x58, 0x11, 0x51},
 271     {0x2c, 0x58, 0x12, 0x56},
 272     {0x2c, 0x58, 0x12, 0x56},
 273     {0x2c, 0x59, 0x13, 0x5a},
 274     {0x2c, 0x59, 0x13, 0x5a},
 275     {0x2d, 0x59, 0x14, 0x5f},
 276     {0x2d, 0x59, 0x14, 0x5f},
 277     {0x2e, 0x5a, 0x15, 0x63},
 278     {0x2e, 0x5a, 0x15, 0x63},
 279     {0x2e, 0x5a, 0x16, 0x68},
 280     {0x2e, 0x5a, 0x16, 0x68},
 281     {0x2e, 0x5a, 0x16, 0x68},
 282     {0x2f, 0x5b, 0x17, 0x6c},
 283     {0x2f, 0x5b, 0x17, 0x6c},
 284     {0x38, 0x5b, 0x18, 0x71},
 285     {0x38, 0x5b, 0x18, 0x71},
 286     {0x38, 0x5c, 0x19, 0x76},
 287     {0x38, 0x5c, 0x19, 0x76},
 288     {0x38, 0x5c, 0x1a, 0x7a},
 289     {0x38, 0x5c, 0x1a, 0x7a},
 290     {0x39, 0x5d, 0x1a, 0x7f},
 291     {0x39, 0x5d, 0x1a, 0x7f},
 292     {0x39, 0x5d, 0x1b, 0x83},
 293     {0x39, 0x5d, 0x1b, 0x83},
 294     {0x39, 0x5e, 0x1c, 0x88},
 295     {0x39, 0x5e, 0x1c, 0x88},
 296     {0x3a, 0x5e, 0x1d, 0x8c},
 297     {0x3a, 0x5e, 0x1d, 0x8c},
 298     {0x3a, 0x5f, 0x1e, 0x91},
 299     {0x3a, 0x5f, 0x1e, 0x91},
 300     {0x3a, 0x5f, 0x1f, 0x95},
 301     {0x3a, 0x5f, 0x1f, 0x95},
 302     {0x3a, 0x68, 0x20, 0x9a},
 303     {0x3a, 0x68, 0x20, 0x9a},
 304     {0x3b, 0x68, 0x21, 0x9e},
 305     {0x3b, 0x68, 0x21, 0x9e},
 306     {0x3b, 0x68, 0x22, 0xa3},
 307     {0x3b, 0x68, 0x22, 0xa3},
 308     {0x3b, 0x68, 0x23, 0xa7},
 309     {0x3b, 0x68, 0x23, 0xa7},
 310     {0x3c, 0x68, 0x24, 0xac},
 311     {0x3c, 0x68, 0x24, 0xac},
 312     {0x3c, 0x68, 0x24, 0xac},
 313     {0x3c, 0x69, 0x25, 0xb0},
 314     {0x3c, 0x69, 0x25, 0xb0},
 315     {0x3c, 0x69, 0x26, 0xb5},
 316     {0x3c, 0x69, 0x26, 0xb5},
 317     {0x3d, 0x69, 0x27, 0xb9},
 318     {0x3d, 0x69, 0x27, 0xb9},
 319     {0x3d, 0x69, 0x28, 0xbe},
 320     {0x3d, 0x69, 0x28, 0xbe},
 321     {0x3d, 0x6a, 0x29, 0xc2},
 322     {0x3d, 0x6a, 0x29, 0xc2},
 323     {0x3e, 0x6a, 0x2a, 0xc7},
 324     {0x3e, 0x6a, 0x2a, 0xc7},
 325     {0x3e, 0x6a, 0x2b, 0xcb},
 326     {0x3e, 0x6a, 0x2b, 0xd0},
 327     {0x3f, 0x6b, 0x2c, 0xd4},
 328     {0x3f, 0x6b, 0x2d, 0xd9},
 329     {0x3f, 0x6b, 0x2e, 0xdd},
 330     {0x48, 0x6b, 0x2f, 0xe2},
 331     {0x48, 0x6b, 0x2f, 0xe2},
 332     {0x48, 0x6c, 0x30, 0xe6},
 333     {0x48, 0x6c, 0x31, 0xeb},
 334     {0x48, 0x6c, 0x32, 0xf0},
 335     {0x48, 0x6c, 0x33, 0xf4},
 336     {0x48, 0x6c, 0x34, 0xf9},
 337     {0x49, 0x6d, 0x35, 0xfd},
 338     {0x49, 0x6d, 0x36, 0xff},
 339     {0x49, 0x6d, 0x37, 0xff},
 340     {0x49, 0x6d, 0x38, 0xff},
 341     {0x49, 0x6e, 0x3a, 0xff},
 342     {0x49, 0x6e, 0x3b, 0xff},
 343     {0x4a, 0x6e, 0x3c, 0xff},
 344     {0x4a, 0x6f, 0x3d, 0xff},
 345     {0x4a, 0x6f, 0x3d, 0xff},
 346     {0x4a, 0x6f, 0x3e, 0xff},
 347     {0x4a, 0x6f, 0x3f, 0xff},
 348     {0x4a, 0x6f, 0x40, 0xff},
 349     {0x4b, 0x78, 0x41, 0xff},
 350     {0x4b, 0x78, 0x42, 0xff},
 351     {0x4b, 0x78, 0x43, 0xff},
 352     {0x4b, 0x78, 0x44, 0xff},
 353     {0x4b, 0x78, 0x46, 0xff},
 354     {0x4c, 0x78, 0x47, 0xff},
 355     {0x4c, 0x79, 0x49, 0xff},
 356     {0x4c, 0x79, 0x4a, 0xff}
 357 };
 358
 359 static const unsigned char
 360 mainref_table_vp8[8] = {
 361     0, 1, 2, 9, 3, 13, 14, 57
 362 };
 363
 364 static const unsigned int
 365 cost_table_vp8[NUM_QP_VP8][7] = {
 366     {0x398f0500, 0x6f6f6f6f, 0x0000006f, 0x06040402, 0x1a0c0907, 0x08, 0x0e},
 367     {0x3b8f0600, 0x6f6f6f6f, 0x0000006f, 0x06040402, 0x1a0c0907, 0x0a, 0x11},
 368     {0x3e8f0700, 0x6f6f6f6f, 0x0000006f, 0x06040402, 0x1a0c0907, 0x0c, 0x14},
 369     {0x488f0800, 0x6f6f6f6f, 0x0000006f, 0x06040402, 0x1a0c0907, 0x0f, 0x18},
 370     {0x498f0a00, 0x6f6f6f6f, 0x0000006f, 0x0d080805, 0x291b190e, 0x11, 0x1b},
 371     {0x4a8f0b00, 0x6f6f6f6f, 0x0000006f, 0x0d080805, 0x291b190e, 0x13, 0x1e},
 372     {0x4b8f0c00, 0x6f6f6f6f, 0x0000006f, 0x0d080805, 0x291b190e, 0x15, 0x22},
 373     {0x4b8f0c00, 0x6f6f6f6f, 0x0000006f, 0x0d080805, 0x291b190e, 0x15, 0x22},
 374     {0x4d8f0d00, 0x6f6f6f6f, 0x0000006f, 0x0d080805, 0x291b190e, 0x17, 0x25},
 375     {0x4e8f0e00, 0x6f6f6f6f, 0x0000006f, 0x190b0c07, 0x2e281e1a, 0x19, 0x29},
 376     {0x4f8f0f00, 0x6f6f6f6f, 0x0000006f, 0x190b0c07, 0x2e281e1a, 0x1b, 0x2c},
 377     {0x588f1800, 0x6f6f6f6f, 0x0000006f, 0x190b0c07, 0x2e281e1a, 0x1d, 0x2f},
 378     {0x588f1900, 0x6f6f6f6f, 0x0000006f, 0x190b0c07, 0x2e281e1a, 0x1f, 0x33},
 379     {0x598f1900, 0x6f6f6f6f, 0x0000006f, 0x1c0f0f0a, 0x392b291e, 0x21, 0x36},
 380     {0x5a8f1a00, 0x6f6f6f6f, 0x0000006f, 0x1c0f0f0a, 0x392b291e, 0x23, 0x3a},
 381     {0x5a8f1a00, 0x6f6f6f6f, 0x0000006f, 0x1c0f0f0a, 0x392b291e, 0x23, 0x3a},
 382     {0x5a8f1a00, 0x6f6f6f6f, 0x0000006f, 0x1c0f0f0a, 0x392b291e, 0x25, 0x3d},
 383     {0x5b8f1b00, 0x6f6f6f6f, 0x0000006f, 0x1c0f0f0a, 0x392b291e, 0x27, 0x40},
 384     {0x5b8f1c00, 0x6f6f6f6f, 0x0000006f, 0x2819190c, 0x3c2e2b29, 0x2a, 0x44},
 385     {0x5b8f1c00, 0x6f6f6f6f, 0x0000006f, 0x2819190c, 0x3c2e2b29, 0x2a, 0x44},
 386     {0x5c8f1c00, 0x6f6f6f6f, 0x0000006f, 0x2819190c, 0x3c2e2b29, 0x2c, 0x47},
 387     {0x5c8f1c00, 0x6f6f6f6f, 0x0000006f, 0x2819190c, 0x3c2e2b29, 0x2c, 0x47},
 388     {0x5d8f1d00, 0x6f6f6f6f, 0x0000006f, 0x2819190c, 0x3c2e2b29, 0x2e, 0x4a},
 389     {0x5d8f1d00, 0x6f6f6f6f, 0x0000006f, 0x2819190c, 0x3c2e2b29, 0x2e, 0x4a},
 390     {0x5d8f1d00, 0x6f6f6f6f, 0x0000006f, 0x2819190c, 0x3c2e2b29, 0x30, 0x4e},
 391     {0x5d8f1d00, 0x6f6f6f6f, 0x0000006f, 0x2819190c, 0x3c2e2b29, 0x30, 0x4e},
 392     {0x5e8f1e00, 0x6f6f6f6f, 0x0000006f, 0x291b1b0f, 0x3e382e2a, 0x32, 0x51},
 393     {0x5e8f1f00, 0x6f6f6f6f, 0x0000006f, 0x291b1b0f, 0x3e382e2a, 0x34, 0x55},
 394     {0x5e8f1f00, 0x6f6f6f6f, 0x0000006f, 0x291b1b0f, 0x3e382e2a, 0x34, 0x55},
 395     {0x5f8f1f00, 0x6f6f6f6f, 0x0000006f, 0x291b1b0f, 0x3e382e2a, 0x36, 0x58},
 396     {0x688f2800, 0x6f6f6f6f, 0x0000006f, 0x291b1b0f, 0x3e382e2a, 0x38, 0x5b},
 397     {0x688f2800, 0x6f6f6f6f, 0x0000006f, 0x2b1d1d18, 0x483a382c, 0x3a, 0x5f},
 398     {0x688f2800, 0x6f6f6f6f, 0x0000006f, 0x2b1d1d18, 0x483a382c, 0x3c, 0x62},
 399     {0x688f2900, 0x6f6f6f6f, 0x0000006f, 0x2b1d1d18, 0x483a382c, 0x3e, 0x65},
 400     {0x698f2900, 0x6f6f6f6f, 0x0000006f, 0x2b1d1d18, 0x483a382c, 0x40, 0x69},
 401     {0x698f2900, 0x6f6f6f6f, 0x0000006f, 0x2c1f1f19, 0x493b392e, 0x43, 0x6c},
 402     {0x698f2900, 0x6f6f6f6f, 0x0000006f, 0x2c1f1f19, 0x493b392e, 0x45, 0x70},
 403     {0x6a8f2a00, 0x6f6f6f6f, 0x0000006f, 0x2c1f1f19, 0x493b392e, 0x47, 0x73},
 404     {0x6a8f2a00, 0x6f6f6f6f, 0x0000006f, 0x2c1f1f19, 0x493b392e, 0x49, 0x76},
 405     {0x6a8f2a00, 0x6f6f6f6f, 0x0000006f, 0x2e28281b, 0x4b3d3a38, 0x4b, 0x7a},
 406     {0x6b8f2b00, 0x6f6f6f6f, 0x0000006f, 0x2e28281b, 0x4b3d3a38, 0x4d, 0x7d},
 407     {0x6b8f2b00, 0x6f6f6f6f, 0x0000006f, 0x2e28281b, 0x4b3d3a38, 0x4d, 0x7d},
 408     {0x6b8f2b00, 0x6f6f6f6f, 0x0000006f, 0x2e28281b, 0x4b3d3a38, 0x4f, 0x81},
 409     {0x6b8f2b00, 0x6f6f6f6f, 0x0000006f, 0x2e28281b, 0x4b3d3a38, 0x51, 0x84},
 410     {0x6b8f2c00, 0x6f6f6f6f, 0x0000006f, 0x2f29291c, 0x4c3e3b38, 0x53, 0x87},
 411     {0x6c8f2c00, 0x6f6f6f6f, 0x0000006f, 0x2f29291c, 0x4c3e3b38, 0x55, 0x8b},
 412     {0x6c8f2c00, 0x6f6f6f6f, 0x0000006f, 0x2f29291c, 0x4c3e3b38, 0x57, 0x8e},
 413     {0x6c8f2c00, 0x6f6f6f6f, 0x0000006f, 0x2f29291c, 0x4c3e3b38, 0x59, 0x91},
 414     {0x6d8f2d00, 0x6f6f6f6f, 0x0000006f, 0x382a2a1d, 0x4d483c39, 0x5b, 0x95},
 415     {0x6d8f2d00, 0x6f6f6f6f, 0x0000006f, 0x382a2a1d, 0x4d483c39, 0x5e, 0x98},
 416     {0x6d8f2d00, 0x6f6f6f6f, 0x0000006f, 0x382a2a1d, 0x4d483c39, 0x60, 0x9c},
 417     {0x6d8f2d00, 0x6f6f6f6f, 0x0000006f, 0x382a2a1d, 0x4d483c39, 0x60, 0x9c},
 418     {0x6d8f2e00, 0x6f6f6f6f, 0x0000006f, 0x382a2a1d, 0x4d483c39, 0x62, 0x9f},
 419     {0x6e8f2e00, 0x6f6f6f6f, 0x0000006f, 0x392b2b1e, 0x4e483e3a, 0x64, 0xa2},
 420     {0x6e8f2e00, 0x6f6f6f6f, 0x0000006f, 0x392b2b1e, 0x4e483e3a, 0x66, 0xa6},
 421     {0x6e8f2e00, 0x6f6f6f6f, 0x0000006f, 0x392b2b1e, 0x4e483e3a, 0x68, 0xa9},
 422     {0x6f8f2f00, 0x6f6f6f6f, 0x0000006f, 0x392b2b1e, 0x4e483e3a, 0x6a, 0xad},
 423     {0x6f8f2f00, 0x6f6f6f6f, 0x0000006f, 0x3a2c2c1f, 0x4f493f3b, 0x6c, 0xb0},
 424     {0x6f8f2f00, 0x6f6f6f6f, 0x0000006f, 0x3a2c2c1f, 0x4f493f3b, 0x6e, 0xb3},
 425     {0x788f3800, 0x6f6f6f6f, 0x0000006f, 0x3a2c2c1f, 0x4f493f3b, 0x70, 0xb7},
 426     {0x788f3800, 0x6f6f6f6f, 0x0000006f, 0x3a2c2c1f, 0x4f493f3b, 0x72, 0xba},
 427     {0x788f3800, 0x6f6f6f6f, 0x0000006f, 0x3b2d2d28, 0x584a483c, 0x74, 0xbd},
 428     {0x788f3800, 0x6f6f6f6f, 0x0000006f, 0x3b2d2d28, 0x584a483c, 0x76, 0xc1},
 429     {0x788f3800, 0x6f6f6f6f, 0x0000006f, 0x3b2d2d28, 0x584a483c, 0x79, 0xc4},
 430     {0x788f3800, 0x6f6f6f6f, 0x0000006f, 0x3b2d2d28, 0x584a483c, 0x7b, 0xc8},
 431     {0x788f3800, 0x6f6f6f6f, 0x0000006f, 0x3b2e2e29, 0x594b483d, 0x7d, 0xcb},
 432     {0x798f3900, 0x6f6f6f6f, 0x0000006f, 0x3b2e2e29, 0x594b483d, 0x7f, 0xce},
 433     {0x798f3900, 0x6f6f6f6f, 0x0000006f, 0x3b2e2e29, 0x594b483d, 0x81, 0xd2},
 434     {0x798f3900, 0x6f6f6f6f, 0x0000006f, 0x3b2e2e29, 0x594b483d, 0x83, 0xd5},
 435     {0x798f3900, 0x6f6f6f6f, 0x0000006f, 0x3c2f2f29, 0x594b493e, 0x85, 0xd9},
 436     {0x798f3900, 0x6f6f6f6f, 0x0000006f, 0x3c2f2f29, 0x594b493e, 0x87, 0xdc},
 437     {0x798f3900, 0x6f6f6f6f, 0x0000006f, 0x3c2f2f29, 0x594b493e, 0x89, 0xdf},
 438     {0x798f3a00, 0x6f6f6f6f, 0x0000006f, 0x3c2f2f29, 0x594b493e, 0x8b, 0xe3},
 439     {0x7a8f3a00, 0x6f6f6f6f, 0x0000006f, 0x3d38382a, 0x5a4c493f, 0x8d, 0xe6},
 440     {0x7a8f3a00, 0x6f6f6f6f, 0x0000006f, 0x3d38382a, 0x5a4c493f, 0x8f, 0xe9},
 441     {0x7a8f3a00, 0x6f6f6f6f, 0x0000006f, 0x3d38382a, 0x5a4c493f, 0x91, 0xed},
 442     {0x7a8f3a00, 0x6f6f6f6f, 0x0000006f, 0x3d38382a, 0x5a4c493f, 0x94, 0xf0},
 443     {0x7a8f3a00, 0x6f6f6f6f, 0x0000006f, 0x3e38382b, 0x5b4d4a48, 0x96, 0xf4},
 444     {0x7a8f3a00, 0x6f6f6f6f, 0x0000006f, 0x3e38382b, 0x5b4d4a48, 0x98, 0xf7},
 445     {0x7b8f3b00, 0x6f6f6f6f, 0x0000006f, 0x3e38382b, 0x5b4d4a48, 0x9a, 0xfa},
 446     {0x7b8f3b00, 0x6f6f6f6f, 0x0000006f, 0x3e38382b, 0x5b4d4a48, 0x9c, 0xfe},
 447     {0x7b8f3b00, 0x6f6f6f6f, 0x0000006f, 0x3f38392b, 0x5b4d4b48, 0x9e, 0xff},
 448     {0x7b8f3b00, 0x6f6f6f6f, 0x0000006f, 0x3f38392b, 0x5b4d4b48, 0x9e, 0xff},
 449     {0x7b8f3b00, 0x6f6f6f6f, 0x0000006f, 0x3f38392b, 0x5b4d4b48, 0xa0, 0xff},
 450     {0x7b8f3b00, 0x6f6f6f6f, 0x0000006f, 0x3f38392b, 0x5b4d4b48, 0xa2, 0xff},
 451     {0x7b8f3b00, 0x6f6f6f6f, 0x0000006f, 0x3f38392b, 0x5b4d4b48, 0xa4, 0xff},
 452     {0x7b8f3b00, 0x6f6f6f6f, 0x0000006f, 0x3f39392c, 0x5c4e4b48, 0xa6, 0xff},
 453     {0x7c8f3c00, 0x6f6f6f6f, 0x0000006f, 0x3f39392c, 0x5c4e4b48, 0xa8, 0xff},
 454     {0x7c8f3c00, 0x6f6f6f6f, 0x0000006f, 0x3f39392c, 0x5c4e4b48, 0xaa, 0xff},
 455     {0x7c8f3c00, 0x6f6f6f6f, 0x0000006f, 0x3f39392c, 0x5c4e4b48, 0xac, 0xff},
 456     {0x7c8f3c00, 0x6f6f6f6f, 0x0000006f, 0x48393a2c, 0x5c4f4c49, 0xaf, 0xff},
 457     {0x7c8f3c00, 0x6f6f6f6f, 0x0000006f, 0x48393a2c, 0x5c4f4c49, 0xb1, 0xff},
 458     {0x7c8f3c00, 0x6f6f6f6f, 0x0000006f, 0x48393a2c, 0x5c4f4c49, 0xb3, 0xff},
 459     {0x7c8f3c00, 0x6f6f6f6f, 0x0000006f, 0x48393a2c, 0x5c4f4c49, 0xb5, 0xff},
 460     {0x7d8f3d00, 0x6f6f6f6f, 0x0000006f, 0x483a3a2d, 0x5d584c49, 0xb7, 0xff},
 461     {0x7d8f3d00, 0x6f6f6f6f, 0x0000006f, 0x483a3a2d, 0x5d584c49, 0xb9, 0xff},
 462     {0x7d8f3d00, 0x6f6f6f6f, 0x0000006f, 0x483a3a2d, 0x5d584c49, 0xbd, 0xff},
 463     {0x7d8f3d00, 0x6f6f6f6f, 0x0000006f, 0x493a3b2e, 0x5e584d4a, 0xc1, 0xff},
 464     {0x7e8f3e00, 0x6f6f6f6f, 0x0000006f, 0x493a3b2e, 0x5e584d4a, 0xc5, 0xff},
 465     {0x7e8f3e00, 0x6f6f6f6f, 0x0000006f, 0x493b3b2e, 0x5e584e4a, 0xc8, 0xff},
 466     {0x7e8f3e00, 0x6f6f6f6f, 0x0000006f, 0x493b3b2e, 0x5e584e4a, 0xcc, 0xff},
 467     {0x7e8f3e00, 0x6f6f6f6f, 0x0000006f, 0x493b3c2f, 0x5f594e4b, 0xd0, 0xff},
 468     {0x7f8f3f00, 0x6f6f6f6f, 0x0000006f, 0x493b3c2f, 0x5f594e4b, 0xd2, 0xff},
 469     {0x7f8f3f00, 0x6f6f6f6f, 0x0000006f, 0x493b3c2f, 0x5f594e4b, 0xd4, 0xff},
 470     {0x7f8f3f00, 0x6f6f6f6f, 0x0000006f, 0x4a3c3c2f, 0x5f594f4b, 0xd8, 0xff},
 471     {0x7f8f3f00, 0x6f6f6f6f, 0x0000006f, 0x4a3c3c2f, 0x5f594f4b, 0xdc, 0xff},
 472     {0x888f4800, 0x6f6f6f6f, 0x0000006f, 0x4a3c3d38, 0x68594f4c, 0xe0, 0xff},
 473     {0x888f4800, 0x6f6f6f6f, 0x0000006f, 0x4a3c3d38, 0x68594f4c, 0xe5, 0xff},
 474     {0x888f4800, 0x6f6f6f6f, 0x0000006f, 0x4b3d3d38, 0x685a584c, 0xe9, 0xff},
 475     {0x888f4800, 0x6f6f6f6f, 0x0000006f, 0x4b3d3d38, 0x685a584c, 0xed, 0xff},
 476     {0x888f4800, 0x6f6f6f6f, 0x0000006f, 0x4b3d3e38, 0x685a584c, 0xf1, 0xff},
 477     {0x888f4800, 0x6f6f6f6f, 0x0000006f, 0x4b3d3e38, 0x685a584c, 0xf5, 0xff},
 478     {0x898f4900, 0x6f6f6f6f, 0x0000006f, 0x4b3e3e39, 0x695b584d, 0xfe, 0xff},
 479     {0x898f4900, 0x6f6f6f6f, 0x0000006f, 0x4c3e3e39, 0x695b594d, 0xff, 0xff},
 480     {0x898f4900, 0x6f6f6f6f, 0x0000006f, 0x4c3e3e39, 0x695b594d, 0xff, 0xff},
 481     {0x898f4900, 0x6f6f6f6f, 0x0000006f, 0x4c3f3f39, 0x695b594e, 0xff, 0xff},
 482     {0x898f4900, 0x6f6f6f6f, 0x0000006f, 0x4c3f3f39, 0x695b594e, 0xff, 0xff},
 483     {0x898f4900, 0x6f6f6f6f, 0x0000006f, 0x4d3f3f3a, 0x6a5c594e, 0xff, 0xff},
 484     {0x898f4900, 0x6f6f6f6f, 0x0000006f, 0x4d3f3f3a, 0x6a5c594e, 0xff, 0xff},
 485     {0x8a8f4a00, 0x6f6f6f6f, 0x0000006f, 0x4d48483a, 0x6a5c594f, 0xff, 0xff},
 486     {0x8a8f4a00, 0x6f6f6f6f, 0x0000006f, 0x4d48483a, 0x6a5c594f, 0xff, 0xff},
 487     {0x8a8f4a00, 0x6f6f6f6f, 0x0000006f, 0x4d48483a, 0x6a5c5a4f, 0xff, 0xff},
 488     {0x8a8f4a00, 0x6f6f6f6f, 0x0000006f, 0x4d48483a, 0x6a5c5a4f, 0xff, 0xff},
 489     {0x8a8f4a00, 0x6f6f6f6f, 0x0000006f, 0x4e48483a, 0x6a5d5a58, 0xff, 0xff},
 490     {0x8b8f4b00, 0x6f6f6f6f, 0x0000006f, 0x4e48483b, 0x6b5d5a58, 0xff, 0xff},
 491     {0x8b8f4b00, 0x6f6f6f6f, 0x0000006f, 0x4e48483b, 0x6b5d5a58, 0xff, 0xff},
 492     {0x8b8f4b00, 0x6f6f6f6f, 0x0000006f, 0x4f48493b, 0x6b5d5b58, 0xff, 0xff},
 493     {0x8b8f4b00, 0x6f6f6f6f, 0x0000006f, 0x4f49493b, 0x6b5e5b58, 0xff, 0xff}
 494 };
 495
 496 static const unsigned int single_su_vp8[56] = {
 497     0x00000000, 0x00000000, 0x00000000, 0x00000000,
 498     0x00000000, 0x00000000, 0x00000000, 0x00000000,
 499     0x00000000, 0x00000000, 0x00000000, 0x00000000,
 500     0x00000000, 0x00000000
 501 };
 502
 503 static const unsigned char full_spiral_48x40_vp8[56] = {
 504     // L -> U -> R -> D
 505     0x0F,
 506     0xF0,
 507     0x01, 0x01,
 508     0x10, 0x10,
 509     0x0F, 0x0F, 0x0F,
 510     0xF0, 0xF0, 0xF0,
 511     0x01, 0x01, 0x01, 0x01,
 512     0x10, 0x10, 0x10, 0x10,
 513     0x0F, 0x0F, 0x0F, 0x0F, 0x0F,
 514     0xF0, 0xF0, 0xF0, 0xF0, 0xF0,
 515     0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
 516     0x10, 0x10, 0x10, 0x10, 0x10, 0x10,       // The last 0x10 steps outside the search window.
 517     0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, // These are outside the search window.
 518     0xF0, 0xF0, 0xF0, 0xF0, 0xF0, 0xF0, 0xF0
 519 };
 520
 521 static const unsigned char raster_scan_48x40_vp8[56] = {
 522     0x11, 0x01, 0x01, 0x01,
 523     0x11, 0x01, 0x01, 0x01,
 524     0x11, 0x01, 0x01, 0x01,
 525     0x11, 0x01, 0x01, 0x01,
 526     0x11, 0x01, 0x01, 0x01,
 527     0x01, 0x01, 0x01, 0x01,
 528     0x00, 0x00, 0x00, 0x00,
 529     0x00, 0x00, 0x00, 0x00,
 530     0x00, 0x00, 0x00, 0x00,
 531     0x00, 0x00, 0x00, 0x00,
 532     0x00, 0x00, 0x00, 0x00,
 533     0x00, 0x00, 0x00, 0x00,
 534     0x00, 0x00, 0x00, 0x00,
 535     0x00, 0x00, 0x00, 0x00
 536 };
 537
 538 static const unsigned char diamond_vp8[56] = {
 539     0x0F, 0xF1, 0x0F, 0x12,//5
 540     0x0D, 0xE2, 0x22, 0x1E,//9
 541     0x10, 0xFF, 0xE2, 0x20,//13
 542     0xFC, 0x06, 0xDD,//16
 543     0x2E, 0xF1, 0x3F, 0xD3, 0x11, 0x3D, 0xF3, 0x1F,//24
 544     0xEB, 0xF1, 0xF1, 0xF1,//28
 545     0x4E, 0x11, 0x12, 0xF2, 0xF1,//33
 546     0xE0, 0xFF, 0xFF, 0x0D, 0x1F, 0x1F,//39
 547     0x20, 0x11, 0xCF, 0xF1, 0x05, 0x11,//45
 548     0x00, 0x00, 0x00, 0x00, 0x00, 0x00,//51
 549     0x00, 0x00, 0x00, 0x00, 0x00, 0x00
 550 };
 551
 552 static const unsigned short
 553 mv_ref_cost_context_vp8[6][4][2] = {
 554     {{1328, 10},
 555      {2047, 1},
 556      {2047, 1},
 557      {214, 304},
 558     },
 559     {{1072, 21},
 560      {979, 27},
 561      {1072, 21},
 562      {321, 201},
 563     },
 564     {{235, 278},
 565      {511, 107},
 566      {553, 93},
 567      {488, 115},
 568     },
 569     {{534, 99},
 570      {560, 92},
 571      {255, 257},
 572      {505, 109},
 573     },
 574     {{174, 361},
 575      {238, 275},
 576      {255, 257},
 577      {744, 53},
 578     },
 579     {{32, 922},
 580      {113, 494},
 581      {255, 257},
 582      {816, 43},
 583     },
 584 };
 585
 586 static const unsigned int
 587 new_mv_skip_threshold_vp8[NUM_QP_VP8] = {
 588     111, 120, 129, 137, 146, 155, 163, 172, 180, 189, 198, 206, 215, 224, 232, 241,
 589     249, 258, 267, 275, 284, 293, 301, 310, 318, 327, 336, 344, 353, 362, 370, 379,
 590     387, 396, 405, 413, 422, 431, 439, 448, 456, 465, 474, 482, 491, 500, 508, 517,
 591     525, 534, 543, 551, 560, 569, 577, 586, 594, 603, 612, 620, 629, 638, 646, 655,
 592     663, 672, 681, 689, 698, 707, 715, 724, 733, 741, 750, 758, 767, 776, 784, 793,
 593     802, 810, 819, 827, 836, 845, 853, 862, 871, 879, 888, 896, 905, 914, 922, 931,
 594     940, 948, 957, 965, 974, 983, 991, 1000, 1009, 1017, 1026, 1034, 1043, 1052, 1060, 1069,
 595     1078, 1086, 1095, 1103, 1112, 1121, 1129, 1138, 1147, 1155, 1164, 1172, 1181, 1190, 1198, 1208
 596 };
 597
 598 static const unsigned short
 599 mb_mode_cost_luma_vp8[10] = {
 600     657,    869,    915,    917,    208,    0,      0,      0,      0,      0
 601 };
 602
 603
 604 static const unsigned short
 605 block_mode_cost_vp8[10][10][10] = {
 606     {
 607         {37,  1725,  1868,  1151,  1622,  2096,  2011,  1770,  2218,  2128  },
 608         {139,  759,  1683,  911,  1455,  1846,  1570,  1295,  1792,  1648   },
 609         {560,  1383,  408,  639,  1612,  1174,  1562,  1736,  847,  991     },
 610         {191,  1293,  1299,  466,  1774,  1840,  1784,  1691,  1698,  1505  },
 611         {211,  1624,  1294,  779,  714,  1622,  2222,  1554,  1706,  903    },
 612         {297,  1259,  1098,  1062,  1583,  618,  1053,  1889,  851,  1127   },
 613         {275,  703,  1356,  1111,  1597,  1075,  656,  1529,  1531,  1275   },
 614         {150,  1046,  1760,  1039,  1353,  1981,  2174,  728,  1730,  1379  },
 615         {516,  1414,  741,  1045,  1495,  738,  1288,  1619,  442,  1200    },
 616         {424,  1365,  706,  825,  1197,  1453,  1191,  1462,  1186,  519    },
 617     },
 618     {
 619         {393,  515,  1491,  549,  1598,  1524,  964,  1126,  1651,  2172    },
 620         {693,  237,  1954,  641,  1525,  2073,  1183,  971,  1973,  2235    },
 621         {560,  739,  855,  836,  1224,  1115,  966,  839,  1076,  767       },
 622         {657,  368,  1406,  425,  1672,  1853,  1210,  1125,  1969,  1542   },
 623         {321,  1056,  1776,  774,  803,  3311,  1265,  1177,  1366,  636    },
 624         {693,  510,  949,  877,  1049,  658,  882,  1178,  1515,  1111      },
 625         {744,  377,  1278,  958,  1576,  1168,  477,  1146,  1838,  1501    },
 626         {488,  477,  1767,  973,  1107,  1511,  1773,  486,  1527,  1449    },
 627         {744,  1004,  695,  1012,  1326,  834,  1215,  774,  724,  704      },
 628         {522,  567,  1036,  1082,  1039,  1333,  873,  1135,  1189,  677    },
 629     },
 630     {
 631         {103,  1441,  1000,  864,  1513,  1928,  1832,  1916,  1663,  1567  },
 632         {304,  872,  1100,  515,  1416,  1417,  3463,  1051,  1305,  1227   },
 633         {684,  2176,  242,  729,  1867,  1496,  2056,  1544,  1038,  930    },
 634         {534,  1198,  669,  300,  1805,  1377,  2165,  1894,  1249,  1153   },
 635         {346,  1602,  1178,  612,  997,  3381,  1335,  1328,  997,  646     },
 636         {393,  1027,  649,  813,  1276,  945,  1545,  1278,  875,  1031     },
 637         {528,  996,  930,  617,  1086,  1190,  621,  2760,  787,  1347      },
 638         {216,  873,  1595,  738,  1339,  3896,  3898,  743,  1343,  1605    },
 639         {675,  1580,  543,  749,  1859,  1245,  1589,  2377,  384,  1075    },
 640         {594,  1163,  415,  684,  1474,  1080,  1491,  1478,  1077,  801    },
 641     },
 642     {
 643         {238,  1131,  1483,  398,  1510,  1651,  1495,  1545,  1970,  2090  },
 644         {499,  456,  1499,  449,  1558,  1691,  1272,  969,  2114,  2116    },
 645         {675,  1386,  318,  645,  1449,  1588,  1666,  1925,  979,  859     },
 646         {467,  957,  1223,  238,  1825,  1704,  1608,  1560,  1665,  1376   },
 647         {331,  1460,  1238,  627,  787,  1882,  3928,  1544,  1897,  579    },
 648         {457,  1038,  903,  784,  1158,  725,  955,  1517,  842,  1016      },
 649         {505,  497,  1131,  812,  1508,  1206,  703,  1072,  1254,  1256    },
 650         {397,  741,  1336,  642,  1506,  1852,  1340,  599,  1854,  1000    },
 651         {625,  1212,  597,  750,  1291,  1057,  1401,  1401,  527,  954     },
 652         {499,  1041,  654,  752,  1299,  1217,  1605,  1424,  1377,  505    },
 653     },
 654     {
 655         {263,  1094,  1218,  602,  938,  1487,  1231,  1016,  1724,  1448   },
 656         {452,  535,  1728,  562,  1008,  1471,  1473,  873,  3182,  1136    },
 657         {553,  1570,  935,  1093,  826,  1339,  879,  1007,  1006,  476     },
 658         {365,  900,  1050,  582,  866,  1398,  1236,  1123,  1608,  1039    },
 659         {294,  2044,  1790,  1143,  430,  1642,  3688,  1549,  2080,  704   },
 660         {703,  1210,  958,  815,  1211,  960,  623,  2455,  815,  559       },
 661         {675,  574,  862,  1261,  866,  864,  761,  1267,  1014,  936       },
 662         {342,  1254,  1857,  989,  612,  1856,  1858,  553,  1840,  1037    },
 663         {553,  1316,  811,  1072,  1068,  728,  1328,  1317,  1064,  475    },
 664         {288,  1303,  1167,  1167,  823,  1634,  1636,  2497,  1294,  491   },
 665     },
 666     {
 667         {227,  1059,  1369,  1066,  1505,  740,  970,  1511,  972,  1775    },
 668         {516,  587,  1033,  646,  1188,  748,  978,  1445,  1294,  1450     },
 669         {684,  1048,  663,  747,  1126,  826,  1386,  1128,  635,  924      },
 670         {494,  814,  933,  510,  1606,  951,  878,  1344,  1031,  1347      },
 671         {553,  1071,  1327,  726,  809,  3376,  1330,  1324,  1062,  407    },
 672         {625,  1120,  988,  1121,  1197,  347,  1064,  1308,  862,  1206    },
 673         {633,  853,  1657,  1073,  1662,  634,  460,  1405,  811,  1155     },
 674         {505,  621,  1394,  876,  1394,  876,  878,  795,  878,  1399       },
 675         {684,  1302,  968,  1704,  1280,  561,  972,  1713,  387,  1104     },
 676         {397,  1447,  1060,  867,  957,  1058,  749,  1475,  1210,  660     },
 677     },
 678     {
 679         {331,  933,  1647,  761,  1647,  998,  513,  1402,  1461,  2219     },
 680         {573,  485,  1968,  641,  1570,  1198,  588,  1086,  1382,  1982    },
 681         {790,  942,  570,  790,  1607,  1005,  938,  1193,  714,  751       },
 682         {511,  745,  1152,  492,  1878,  1206,  596,  1867,  1617,  1157    },
 683         {452,  1308,  896,  896,  451,  1308,  3354,  1301,  1306,  794     },
 684         {693,  670,  1072,  1020,  1687,  566,  488,  1432,  1096,  3142    },
 685         {778,  566,  1993,  1283,  3139,  1251,  227,  1378,  1784,  1447   },
 686         {393,  937,  1091,  934,  939,  1348,  1092,  579,  1351,  1095     },
 687         {560,  1013,  1007,  1014,  1011,  644,  1165,  1155,  605,  1016   },
 688         {567,  627,  997,  793,  2562,  998,  849,  1260,  922,  748        },
 689     },
 690     {
 691         {338,  762,  1868,  717,  1247,  1757,  1263,  535,  1751,  2162    },
 692         {488,  442,  3235,  756,  1658,  1814,  1264,  528,  1857,  2119    },
 693         {522,  1087,  840,  1103,  843,  1354,  1098,  888,  946,  588      },
 694         {483,  688,  1502,  651,  1213,  1446,  1397,  491,  1908,  1253    },
 695         {452,  1386,  1910,  1175,  298,  1507,  3553,  930,  1904,  905    },
 696         {713,  839,  716,  715,  932,  719,  931,  848,  3088,  1042        },
 697         {516,  495,  1331,  1340,  1331,  1069,  665,  702,  1593,  1337    },
 698         {401,  977,  2167,  1537,  1069,  1764,  3810,  259,  3624,  1578   },
 699         {560,  1104,  601,  1371,  965,  658,  2704,  779,  967,  969       },
 700         {547,  1057,  801,  1141,  1133,  1397,  937,  605,  1252,  631     },
 701     },
 702     {
 703         {163,  1240,  925,  983,  1653,  1321,  1353,  1566,  946,  1601    },
 704         {401,  726,  758,  836,  1241,  926,  1656,  795,  1394,  1396      },
 705         {905,  1073,  366,  876,  1436,  1576,  1732,  2432,  459,  1019    },
 706         {594,  922,  835,  417,  1387,  1124,  1098,  2042,  843,  1023     },
 707         {415,  1262,  860,  1274,  758,  1272,  3318,  1010,  1276,  503    },
 708         {641,  1018,  1020,  1095,  1619,  667,  1371,  2348,  397,  849    },
 709         {560,  817,  903,  1014,  1420,  695,  756,  904,  821,  1421       },
 710         {406,  596,  1001,  993,  1257,  1258,  1260,  746,  1002,  1264    },
 711         {979,  1371,  780,  1188,  1693,  1024,  1286,  1699,  183,  1405   },
 712         {733,  1292,  458,  884,  1554,  889,  1151,  1286,  738,  740      },
 713     },
 714     {
 715         {109,  1377,  1177,  933,  1140,  1928,  1639,  1705,  1861,  1292  },
 716         {342,  570,  1081,  638,  1154,  1231,  1339,  1342,  1750,  1494   },
 717         {560,  1203,  345,  767,  1325,  1681,  1425,  1905,  1205,  786    },
 718         {406,  1027,  1011,  410,  1306,  1901,  1389,  1636,  1493,  776   },
 719         {206,  1329,  1337,  1037,  802,  1600,  3646,  1451,  1603,  693   },
 720         {472,  1167,  758,  911,  1424,  703,  2749,  1428,  703,  764      },
 721         {342,  780,  1139,  889,  1290,  1139,  781,  1544,  957,  1042     },
 722         {227,  888,  1039,  929,  988,  3753,  1707,  818,  1710,  1306     },
 723         {767,  1055,  627,  725,  1312,  980,  1065,  1324,  599,  811      },
 724         {304,  1372,  888,  1173,  979,  1578,  1580,  1974,  1318,  482    },
 725     }
 726 };
 727
 728 static const unsigned char
 729 brc_qpadjustment_distthreshold_maxframethreshold_distqpadjustment_ipb_vp8[576] = {
 730     0x01, 0x03, 0x05, 0x07, 0x09, 0x01, 0x02, 0x03, 0x05, 0x07, 0x00, 0x00, 0x01, 0x02, 0x04, 0x00,
 731     0x00, 0x00, 0x01, 0x02, 0xff, 0x00, 0x00, 0x00, 0x01, 0xfd, 0xfe, 0xff, 0x00, 0x00, 0xfb, 0xfc,
 732     0xfe, 0xff, 0x00, 0xf9, 0xfa, 0xfc, 0xfe, 0xff, 0xf7, 0xf9, 0xfb, 0xfe, 0xff, 0x00, 0x04, 0x1e,
 733     0x3c, 0x50, 0x78, 0x8c, 0xc8, 0xff, 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x00, 0x00, 0x00, 0x00, 0x00,
 734     0x01, 0x02, 0x05, 0x08, 0x0a, 0x01, 0x02, 0x04, 0x06, 0x08, 0x00, 0x01, 0x02, 0x04, 0x06, 0x00,
 735     0x00, 0x00, 0x01, 0x02, 0xff, 0x00, 0x00, 0x00, 0x01, 0xfe, 0xff, 0xff, 0x00, 0x00, 0xfd, 0xfe,
 736     0xff, 0xff, 0x00, 0xfb, 0xfd, 0xfe, 0xff, 0x00, 0xf9, 0xfa, 0xfc, 0xfe, 0xff, 0x00, 0x04, 0x1e,
 737     0x3c, 0x50, 0x78, 0x8c, 0xc8, 0xff, 0x04, 0x05, 0x06, 0x06, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00,
 738     0x01, 0x02, 0x05, 0x08, 0x0a, 0x01, 0x02, 0x04, 0x06, 0x08, 0x00, 0x01, 0x02, 0x04, 0x06, 0x00,
 739     0x00, 0x00, 0x01, 0x02, 0xff, 0x00, 0x00, 0x00, 0x01, 0xfe, 0xff, 0xff, 0x00, 0x00, 0xfd, 0xfe,
 740     0xff, 0xff, 0x00, 0xfb, 0xfd, 0xfe, 0xff, 0x00, 0xf9, 0xfa, 0xfc, 0xfe, 0xff, 0x00, 0x02, 0x14,
 741     0x28, 0x46, 0x82, 0xa0, 0xc8, 0xff, 0x04, 0x05, 0x06, 0x06, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00,
 742     0x00, 0x00, 0x00, 0x00, 0x00, 0x04, 0x06, 0x08, 0x0a, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x05,
 743     0x07, 0x09, 0xff, 0x00, 0x00, 0x00, 0x00, 0x03, 0x04, 0x06, 0x07, 0xfe, 0xff, 0x00, 0x00, 0x00,
 744     0x01, 0x02, 0x03, 0x05, 0xfd, 0xfe, 0xff, 0x00, 0x00, 0x00, 0x01, 0x03, 0x05, 0xfc, 0xfe, 0xff,
 745     0x00, 0x00, 0x00, 0x01, 0x03, 0x05, 0xfb, 0xfd, 0xfe, 0xff, 0x00, 0x00, 0x01, 0x03, 0x05, 0xfa,
 746     0xfc, 0xfe, 0xff, 0x00, 0x00, 0x01, 0x03, 0x05, 0xfa, 0xfc, 0xfe, 0xff, 0x00, 0x00, 0x01, 0x03,
 747     0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 748     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 749     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 750     0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x05, 0x07, 0x09, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x05,
 751     0x06, 0x08, 0xff, 0x00, 0x00, 0x00, 0x00, 0x03, 0x05, 0x07, 0x08, 0xfe, 0xff, 0x00, 0x00, 0x00,
 752     0x02, 0x04, 0x05, 0x06, 0xfd, 0xfe, 0xff, 0x00, 0x00, 0x00, 0x01, 0x04, 0x05, 0xfc, 0xfe, 0xff,
 753     0x00, 0x00, 0x00, 0x01, 0x04, 0x05, 0xfc, 0xfe, 0xff, 0xff, 0x00, 0x00, 0x00, 0x04, 0x05, 0xfc,
 754     0xfd, 0xfe, 0xff, 0x00, 0x00, 0x00, 0x01, 0x05, 0xfb, 0xfc, 0xfe, 0xff, 0x00, 0x00, 0x00, 0x01,
 755     0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 756     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 757     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 758     0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x05, 0x07, 0x09, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x05,
 759     0x06, 0x08, 0xff, 0x00, 0x00, 0x00, 0x00, 0x03, 0x05, 0x07, 0x08, 0xfe, 0xff, 0x00, 0x00, 0x00,
 760     0x02, 0x04, 0x05, 0x06, 0xfd, 0xfe, 0xff, 0x00, 0x00, 0x00, 0x01, 0x04, 0x05, 0xfc, 0xfe, 0xff,
 761     0x00, 0x00, 0x00, 0x01, 0x04, 0x05, 0xfc, 0xfe, 0xff, 0xff, 0x00, 0x00, 0x00, 0x04, 0x05, 0xfc,
 762     0xfd, 0xfe, 0xff, 0x00, 0x00, 0x00, 0x01, 0x05, 0xfb, 0xfc, 0xfe, 0xff, 0x00, 0x00, 0x00, 0x01,
 763     0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 764     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 765     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 766 };
 767
 768 static const unsigned char
 769 brc_iframe_cost_vp8[128][4] = {
 770     { 0x5, 0x5, 0x8, 0x8 },
 771     { 0xa, 0xa, 0xd, 0xd },
 772     { 0xd, 0xf, 0xf, 0x19 },
 773     { 0x19, 0x1a, 0x1a, 0x1a },
 774     { 0x1b, 0x1b, 0x1d, 0x1d },
 775     { 0x1d, 0x1d, 0x1e, 0x1e },
 776     { 0x1e, 0x1e, 0x1f, 0x1f },
 777     { 0x1f, 0x28, 0x28, 0x29 },
 778     { 0x29, 0x29, 0x29, 0x2a },
 779     { 0x2a, 0x2b, 0x2b, 0x2b },
 780     { 0x2b, 0x2b, 0x2c, 0x2c },
 781     { 0x2c, 0x2c, 0x2d, 0x2d },
 782     { 0x2e, 0x2e, 0x2e, 0x2e },
 783     { 0x2e, 0x2f, 0x2f, 0x38 },
 784     { 0x38, 0x38, 0x38, 0x38 },
 785     { 0x38, 0x39, 0x39, 0x39 },
 786     { 0x39, 0x39, 0x39, 0x3a },
 787     { 0x3a, 0x3a, 0x3a, 0x3a },
 788     { 0x3a, 0x3a, 0x3a, 0x3b },
 789     { 0x3b, 0x3b, 0x3b, 0x3b },
 790     { 0x3b, 0x3c, 0x3c, 0x3c },
 791     { 0x3c, 0x3c, 0x3c, 0x3c },
 792     { 0x3d, 0x3d, 0x3d, 0x3d },
 793     { 0x3d, 0x3d, 0x3e, 0x3e },
 794     { 0x3e, 0x3e, 0x3f, 0x3f },
 795     { 0x3f, 0x48, 0x48, 0x48 },
 796     { 0x48, 0x48, 0x48, 0x48 },
 797     { 0x49, 0x49, 0x49, 0x49 },
 798     { 0x49, 0x49, 0x4a, 0x4a },
 799     { 0x4a, 0x4a, 0x4a, 0x4a },
 800     { 0x4b, 0x4b, 0x4b, 0x4b },
 801     { 0x4b, 0x4c, 0x4c, 0x4c },
 802     { 0x1f, 0x1f, 0x2b, 0x2b },
 803     { 0x2f, 0x2f, 0x39, 0x39 },
 804     { 0x39, 0x3b, 0x3b, 0x3d },
 805     { 0x3d, 0x3f, 0x3f, 0x3f },
 806     { 0x48, 0x48, 0x49, 0x49 },
 807     { 0x49, 0x49, 0x4a, 0x4a },
 808     { 0x4a, 0x4a, 0x4b, 0x4b },
 809     { 0x4b, 0x4c, 0x4c, 0x4d },
 810     { 0x4d, 0x4e, 0x4e, 0x4f },
 811     { 0x4f, 0x58, 0x58, 0x58 },
 812     { 0x58, 0x58, 0x58, 0x58 },
 813     { 0x59, 0x59, 0x59, 0x59 },
 814     { 0x5a, 0x5a, 0x5a, 0x5a },
 815     { 0x5a, 0x5b, 0x5b, 0x5b },
 816     { 0x5b, 0x5c, 0x5c, 0x5c },
 817     { 0x5c, 0x5d, 0x5d, 0x5d },
 818     { 0x5d, 0x5e, 0x5e, 0x5e },
 819     { 0x5e, 0x5f, 0x5f, 0x5f },
 820     { 0x5f, 0x68, 0x68, 0x68 },
 821     { 0x68, 0x68, 0x68, 0x68 },
 822     { 0x68, 0x68, 0x68, 0x68 },
 823     { 0x69, 0x69, 0x69, 0x69 },
 824     { 0x69, 0x69, 0x69, 0x69 },
 825     { 0x6a, 0x6a, 0x6a, 0x6a },
 826     { 0x6a, 0x6a, 0x6b, 0x6b },
 827     { 0x6b, 0x6b, 0x6b, 0x6c },
 828     { 0x6c, 0x6c, 0x6c, 0x6c },
 829     { 0x6d, 0x6d, 0x6d, 0x6d },
 830     { 0x6e, 0x6e, 0x6e, 0x6f },
 831     { 0x6f, 0x6f, 0x6f, 0x6f },
 832     { 0x78, 0x78, 0x78, 0x78 },
 833     { 0x78, 0x78, 0x79, 0x79 },
 834     { 0x2, 0x2, 0x3, 0x3 },
 835     { 0x4, 0x4, 0x5, 0x5 },
 836     { 0x5, 0x6, 0x6, 0x7 },
 837     { 0x7, 0x8, 0x8, 0x8 },
 838     { 0x9, 0x9, 0x9, 0x9 },
 839     { 0x9, 0x9, 0xa, 0xa },
 840     { 0xa, 0xa, 0xb, 0xb },
 841     { 0xb, 0xc, 0xc, 0xd },
 842     { 0xd, 0xe, 0xe, 0xf },
 843     { 0xf, 0x10, 0x10, 0x11 },
 844     { 0x11, 0x11, 0x12, 0x12 },
 845     { 0x13, 0x13, 0x14, 0x14 },
 846     { 0x15, 0x15, 0x16, 0x16 },
 847     { 0x16, 0x17, 0x17, 0x18 },
 848     { 0x18, 0x19, 0x19, 0x1a },
 849     { 0x1a, 0x1a, 0x1a, 0x1b },
 850     { 0x1b, 0x1c, 0x1c, 0x1d },
 851     { 0x1d, 0x1e, 0x1e, 0x1f },
 852     { 0x1f, 0x20, 0x20, 0x21 },
 853     { 0x21, 0x22, 0x22, 0x23 },
 854     { 0x23, 0x24, 0x24, 0x24 },
 855     { 0x25, 0x25, 0x26, 0x26 },
 856     { 0x27, 0x27, 0x28, 0x28 },
 857     { 0x29, 0x29, 0x2a, 0x2a },
 858     { 0x2b, 0x2b, 0x2c, 0x2d },
 859     { 0x2e, 0x2f, 0x2f, 0x30 },
 860     { 0x31, 0x32, 0x33, 0x34 },
 861     { 0x35, 0x36, 0x37, 0x38 },
 862     { 0x3a, 0x3b, 0x3c, 0x3d },
 863     { 0x3d, 0x3e, 0x3f, 0x40 },
 864     { 0x41, 0x42, 0x43, 0x44 },
 865     { 0x46, 0x47, 0x49, 0x4a },
 866     { 0x9, 0x9, 0xe, 0xe },
 867     { 0x12, 0x12, 0x17, 0x17 },
 868     { 0x17, 0x1b, 0x1b, 0x20 },
 869     { 0x20, 0x24, 0x24, 0x24 },
 870     { 0x29, 0x29, 0x2d, 0x2d },
 871     { 0x2d, 0x2d, 0x32, 0x32 },
 872     { 0x32, 0x32, 0x36, 0x36 },
 873     { 0x36, 0x3b, 0x3b, 0x3f },
 874     { 0x3f, 0x44, 0x44, 0x48 },
 875     { 0x48, 0x4d, 0x4d, 0x51 },
 876     { 0x51, 0x51, 0x56, 0x56 },
 877     { 0x5a, 0x5a, 0x5f, 0x5f },
 878     { 0x63, 0x63, 0x68, 0x68 },
 879     { 0x68, 0x6c, 0x6c, 0x71 },
 880     { 0x71, 0x76, 0x76, 0x7a },
 881     { 0x7a, 0x7f, 0x7f, 0x83 },
 882     { 0x83, 0x88, 0x88, 0x8c },
 883     { 0x8c, 0x91, 0x91, 0x95 },
 884     { 0x95, 0x9a, 0x9a, 0x9e },
 885     { 0x9e, 0xa3, 0xa3, 0xa7 },
 886     { 0xa7, 0xac, 0xac, 0xac },
 887     { 0xb0, 0xb0, 0xb5, 0xb5 },
 888     { 0xb9, 0xb9, 0xbe, 0xbe },
 889     { 0xc2, 0xc2, 0xc7, 0xc7 },
 890     { 0xcb, 0xd0, 0xd4, 0xd9 },
 891     { 0xdd, 0xe2, 0xe2, 0xe6 },
 892     { 0xeb, 0xf0, 0xf4, 0xf9 },
 893     { 0xfd, 0xff, 0xff, 0xff },
 894     { 0xff, 0xff, 0xff, 0xff },
 895     { 0xff, 0xff, 0xff, 0xff },
 896     { 0xff, 0xff, 0xff, 0xff },
 897     { 0xff, 0xff, 0xff, 0xff },
 898 };
 899
 900 static const unsigned int
 901 brc_pframe_cost_vp8[256] = {
 902     0x06040402,
 903     0x06040402,
 904     0x06040402,
 905     0x06040402,
 906     0x0d080805,
 907     0x0d080805,
 908     0x0d080805,
 909     0x0d080805,
 910     0x0d080805,
 911     0x190b0c07,
 912     0x190b0c07,
 913     0x190b0c07,
 914     0x190b0c07,
 915     0x1c0f0f0a,
 916     0x1c0f0f0a,
 917     0x1c0f0f0a,
 918     0x1c0f0f0a,
 919     0x1c0f0f0a,
 920     0x2819190c,
 921     0x2819190c,
 922     0x2819190c,
 923     0x2819190c,
 924     0x2819190c,
 925     0x2819190c,
 926     0x2819190c,
 927     0x2819190c,
 928     0x291b1b0f,
 929     0x291b1b0f,
 930     0x291b1b0f,
 931     0x291b1b0f,
 932     0x291b1b0f,
 933     0x2b1d1d18,
 934     0x2b1d1d18,
 935     0x2b1d1d18,
 936     0x2b1d1d18,
 937     0x2c1f1f19,
 938     0x2c1f1f19,
 939     0x2c1f1f19,
 940     0x2c1f1f19,
 941     0x2e28281b,
 942     0x2e28281b,
 943     0x2e28281b,
 944     0x2e28281b,
 945     0x2e28281b,
 946     0x2f29291c,
 947     0x2f29291c,
 948     0x2f29291c,
 949     0x2f29291c,
 950     0x382a2a1d,
 951     0x382a2a1d,
 952     0x382a2a1d,
 953     0x382a2a1d,
 954     0x382a2a1d,
 955     0x392b2b1e,
 956     0x392b2b1e,
 957     0x392b2b1e,
 958     0x392b2b1e,
 959     0x3a2c2c1f,
 960     0x3a2c2c1f,
 961     0x3a2c2c1f,
 962     0x3a2c2c1f,
 963     0x3b2d2d28,
 964     0x3b2d2d28,
 965     0x3b2d2d28,
 966     0x3b2d2d28,
 967     0x3b2e2e29,
 968     0x3b2e2e29,
 969     0x3b2e2e29,
 970     0x3b2e2e29,
 971     0x3c2f2f29,
 972     0x3c2f2f29,
 973     0x3c2f2f29,
 974     0x3c2f2f29,
 975     0x3d38382a,
 976     0x3d38382a,
 977     0x3d38382a,
 978     0x3d38382a,
 979     0x3e38382b,
 980     0x3e38382b,
 981     0x3e38382b,
 982     0x3e38382b,
 983     0x3f38392b,
 984     0x3f38392b,
 985     0x3f38392b,
 986     0x3f38392b,
 987     0x3f38392b,
 988     0x3f39392c,
 989     0x3f39392c,
 990     0x3f39392c,
 991     0x3f39392c,
 992     0x48393a2c,
 993     0x48393a2c,
 994     0x48393a2c,
 995     0x48393a2c,
 996     0x483a3a2d,
 997     0x483a3a2d,
 998     0x483a3a2d,
 999     0x493a3b2e,
1000     0x493a3b2e,
1001     0x493b3b2e,
1002     0x493b3b2e,
1003     0x493b3c2f,
1004     0x493b3c2f,
1005     0x493b3c2f,
1006     0x4a3c3c2f,
1007     0x4a3c3c2f,
1008     0x4a3c3d38,
1009     0x4a3c3d38,
1010     0x4b3d3d38,
1011     0x4b3d3d38,
1012     0x4b3d3e38,
1013     0x4b3d3e38,
1014     0x4b3e3e39,
1015     0x4c3e3e39,
1016     0x4c3e3e39,
1017     0x4c3f3f39,
1018     0x4c3f3f39,
1019     0x4d3f3f3a,
1020     0x4d3f3f3a,
1021     0x4d48483a,
1022     0x4d48483a,
1023     0x4d48483a,
1024     0x4d48483a,
1025     0x4e48483a,
1026     0x4e48483b,
1027     0x4e48483b,
1028     0x4f48493b,
1029     0x4f49493b,
1030     0x1a0c0907,
1031     0x1a0c0907,
1032     0x1a0c0907,
1033     0x1a0c0907,
1034     0x291b190e,
1035     0x291b190e,
1036     0x291b190e,
1037     0x291b190e,
1038     0x291b190e,
1039     0x2e281e1a,
1040     0x2e281e1a,
1041     0x2e281e1a,
1042     0x2e281e1a,
1043     0x392b291e,
1044     0x392b291e,
1045     0x392b291e,
1046     0x392b291e,
1047     0x392b291e,
1048     0x3c2e2b29,
1049     0x3c2e2b29,
1050     0x3c2e2b29,
1051     0x3c2e2b29,
1052     0x3c2e2b29,
1053     0x3c2e2b29,
1054     0x3c2e2b29,
1055     0x3c2e2b29,
1056     0x3e382e2a,
1057     0x3e382e2a,
1058     0x3e382e2a,
1059     0x3e382e2a,
1060     0x3e382e2a,
1061     0x483a382c,
1062     0x483a382c,
1063     0x483a382c,
1064     0x483a382c,
1065     0x493b392e,
1066     0x493b392e,
1067     0x493b392e,
1068     0x493b392e,
1069     0x4b3d3a38,
1070     0x4b3d3a38,
1071     0x4b3d3a38,
1072     0x4b3d3a38,
1073     0x4b3d3a38,
1074     0x4c3e3b38,
1075     0x4c3e3b38,
1076     0x4c3e3b38,
1077     0x4c3e3b38,
1078     0x4d483c39,
1079     0x4d483c39,
1080     0x4d483c39,
1081     0x4d483c39,
1082     0x4d483c39,
1083     0x4e483e3a,
1084     0x4e483e3a,
1085     0x4e483e3a,
1086     0x4e483e3a,
1087     0x4f493f3b,
1088     0x4f493f3b,
1089     0x4f493f3b,
1090     0x4f493f3b,
1091     0x584a483c,
1092     0x584a483c,
1093     0x584a483c,
1094     0x584a483c,
1095     0x594b483d,
1096     0x594b483d,
1097     0x594b483d,
1098     0x594b483d,
1099     0x594b493e,
1100     0x594b493e,
1101     0x594b493e,
1102     0x594b493e,
1103     0x5a4c493f,
1104     0x5a4c493f,
1105     0x5a4c493f,
1106     0x5a4c493f,
1107     0x5b4d4a48,
1108     0x5b4d4a48,
1109     0x5b4d4a48,
1110     0x5b4d4a48,
1111     0x5b4d4b48,
1112     0x5b4d4b48,
1113     0x5b4d4b48,
1114     0x5b4d4b48,
1115     0x5b4d4b48,
1116     0x5c4e4b48,
1117     0x5c4e4b48,
1118     0x5c4e4b48,
1119     0x5c4e4b48,
1120     0x5c4f4c49,
1121     0x5c4f4c49,
1122     0x5c4f4c49,
1123     0x5c4f4c49,
1124     0x5d584c49,
1125     0x5d584c49,
1126     0x5d584c49,
1127     0x5e584d4a,
1128     0x5e584d4a,
1129     0x5e584e4a,
1130     0x5e584e4a,
1131     0x5f594e4b,
1132     0x5f594e4b,
1133     0x5f594e4b,
1134     0x5f594f4b,
1135     0x5f594f4b,
1136     0x68594f4c,
1137     0x68594f4c,
1138     0x685a584c,
1139     0x685a584c,
1140     0x685a584c,
1141     0x685a584c,
1142     0x695b584d,
1143     0x695b594d,
1144     0x695b594d,
1145     0x695b594e,
1146     0x695b594e,
1147     0x6a5c594e,
1148     0x6a5c594e,
1149     0x6a5c594f,
1150     0x6a5c594f,
1151     0x6a5c5a4f,
1152     0x6a5c5a4f,
1153     0x6a5d5a58,
1154     0x6b5d5a58,
1155     0x6b5d5a58,
1156     0x6b5d5b58,
1157     0x6b5e5b58,
1158 };
1159
1160 static const unsigned short
1161 brc_skip_mv_threshold_vp8[256] = {
1162     111,  120,  129,  137,  146,  155,  163,  172,  180,  189,  198,  206,  215,  224,  232,  241,
1163     249,  258,  267,  275,  284,  293,  301,  310,  318,  327,  336,  344,  353,  362,  370,  379,
1164     387,  396,  405,  413,  422,  431,  439,  448,  456,  465,  474,  482,  491,  500,  508,  517,
1165     525,  534,  543,  551,  560,  569,  577,  586,  594,  603,  612,  620,  629,  638,  646,  655,
1166     663,  672,  681,  689,  698,  707,  715,  724,  733,  741,  750,  758,  767,  776,  784,  793,
1167     802,  810,  819,  827,  836,  845,  853,  862,  871,  879,  888,  896,  905,  914,  922,  931,
1168     940,  948,  957,  965,  974,  983,  991, 1000, 1009, 1017, 1026, 1034, 1043, 1052, 1060, 1069,
1169     1078,1086, 1095, 1103, 1112, 1121, 1129, 1138, 1147, 1155, 1164, 1172, 1181, 1190, 1198, 1208
1170 };
1171
1172 void
1173 i965_encoder_vp8_check_motion_estimation(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
1174 {
1175     struct i965_encoder_vp8_context *vp8_context = encoder_context->vme_context;
1176
1177     if (vp8_context->down_scaled_width_4x < vp8_context->min_scaled_dimension  ||
1178         vp8_context->down_scaled_width_in_mb4x < vp8_context->min_scaled_dimension_in_mbs ||
1179         vp8_context->down_scaled_height_4x < vp8_context->min_scaled_dimension ||
1180         vp8_context->down_scaled_height_in_mb4x < vp8_context->min_scaled_dimension_in_mbs) {
1181
1182         vp8_context->hme_16x_supported = 0;
1183
1184         if (vp8_context->down_scaled_width_4x < vp8_context->min_scaled_dimension  ||
1185             vp8_context->down_scaled_width_in_mb4x < vp8_context->min_scaled_dimension_in_mbs) {
1186
1187             vp8_context->down_scaled_width_4x = vp8_context->min_scaled_dimension;
1188             vp8_context->down_scaled_width_in_mb4x = vp8_context->min_scaled_dimension_in_mbs;
1189         }
1190
1191         if (vp8_context->down_scaled_height_4x < vp8_context->min_scaled_dimension ||
1192             vp8_context->down_scaled_height_in_mb4x < vp8_context->min_scaled_dimension_in_mbs) {
1193
1194             vp8_context->down_scaled_height_4x = vp8_context->min_scaled_dimension;
1195             vp8_context->down_scaled_height_in_mb4x = vp8_context->min_scaled_dimension_in_mbs;
1196         }
1197     } else if (vp8_context->down_scaled_width_16x < vp8_context->min_scaled_dimension ||
1198                vp8_context->down_scaled_width_in_mb16x < vp8_context->min_scaled_dimension_in_mbs ||
1199                vp8_context->down_scaled_height_16x < vp8_context->min_scaled_dimension ||
1200                vp8_context->down_scaled_height_in_mb16x < vp8_context->min_scaled_dimension_in_mbs) {
1201
1202         if (vp8_context->down_scaled_width_16x < vp8_context->min_scaled_dimension ||
1203             vp8_context->down_scaled_width_in_mb16x < vp8_context->min_scaled_dimension_in_mbs) {
1204
1205             vp8_context->down_scaled_width_16x = vp8_context->min_scaled_dimension;
1206             vp8_context->down_scaled_width_in_mb16x = vp8_context->min_scaled_dimension_in_mbs;
1207         }
1208
1209         if (vp8_context->down_scaled_height_16x < vp8_context->min_scaled_dimension ||
1210             vp8_context->down_scaled_height_in_mb16x < vp8_context->min_scaled_dimension_in_mbs) {
1211
1212             vp8_context->down_scaled_height_16x = vp8_context->min_scaled_dimension;
1213             vp8_context->down_scaled_height_in_mb16x = vp8_context->min_scaled_dimension_in_mbs;
1214         }
1215     }
1216 }
1217
1218 static void
1219 i965_encoder_vp8_free_surfaces(void **data)
1220 {
1221     struct i965_encoder_vp8_surface *vp8_surface;
1222
1223     if (!data || !(*data))
1224         return;
1225
1226     vp8_surface = *data;
1227
1228     if (vp8_surface->scaled_4x_surface_obj) {
1229         i965_DestroySurfaces(vp8_surface->ctx, &vp8_surface->scaled_4x_surface_id, 1);
1230         vp8_surface->scaled_4x_surface_id = VA_INVALID_SURFACE;
1231         vp8_surface->scaled_4x_surface_obj = NULL;
1232     }
1233
1234     if (vp8_surface->scaled_16x_surface_obj) {
1235         i965_DestroySurfaces(vp8_surface->ctx, &vp8_surface->scaled_16x_surface_id, 1);
1236         vp8_surface->scaled_16x_surface_id = VA_INVALID_SURFACE;
1237         vp8_surface->scaled_16x_surface_obj = NULL;
1238     }
1239 }
1240
1241 static void
1242 i965_encoder_vp8_allocate_surfaces(VADriverContextP ctx,
1243                                    struct intel_encoder_context *encoder_context,
1244                                    struct object_surface *obj_surface,
1245                                    int forced_free)
1246 {
1247     struct i965_driver_data *i965 = i965_driver_data(ctx);
1248     struct i965_encoder_vp8_context *vp8_context = encoder_context->vme_context;
1249     struct i965_encoder_vp8_surface *vp8_surface;
1250     int down_scaled_width_4x, down_scaled_height_4x;
1251     int down_scaled_width_16x, down_scaled_height_16x;
1252
1253     if (!obj_surface)
1254         return;
1255
1256     if (obj_surface->private_data && obj_surface->free_private_data) {
1257         if (forced_free && obj_surface->free_private_data != i965_encoder_vp8_free_surfaces)
1258             obj_surface->free_private_data(obj_surface->private_data);
1259         else
1260             return;
1261     }
1262
1263     vp8_surface = calloc(1, sizeof(struct i965_encoder_vp8_surface));
1264
1265     if (!vp8_surface) {
1266         obj_surface->private_data = NULL;
1267         obj_surface->free_private_data = NULL;
1268
1269         return;
1270     }
1271
1272     vp8_surface->ctx = ctx;
1273
1274     down_scaled_width_4x = vp8_context->down_scaled_width_4x;
1275     down_scaled_height_4x = vp8_context->down_scaled_height_4x;
1276     i965_CreateSurfaces(ctx,
1277                         down_scaled_width_4x,
1278                         down_scaled_height_4x,
1279                         VA_RT_FORMAT_YUV420,
1280                         1,
1281                         &vp8_surface->scaled_4x_surface_id);
1282     vp8_surface->scaled_4x_surface_obj = SURFACE(vp8_surface->scaled_4x_surface_id);
1283
1284     if (vp8_surface->scaled_4x_surface_obj)
1285         i965_check_alloc_surface_bo(ctx, vp8_surface->scaled_4x_surface_obj, 1,
1286                                     VA_FOURCC('N', 'V', '1', '2'), SUBSAMPLE_YUV420);
1287
1288     down_scaled_width_16x = vp8_context->down_scaled_width_16x;
1289     down_scaled_height_16x = vp8_context->down_scaled_height_16x;
1290     i965_CreateSurfaces(ctx,
1291                         down_scaled_width_16x,
1292                         down_scaled_height_16x,
1293                         VA_RT_FORMAT_YUV420,
1294                         1,
1295                         &vp8_surface->scaled_16x_surface_id);
1296     vp8_surface->scaled_16x_surface_obj = SURFACE(vp8_surface->scaled_16x_surface_id);
1297
1298     if (vp8_surface->scaled_16x_surface_obj)
1299         i965_check_alloc_surface_bo(ctx, vp8_surface->scaled_16x_surface_obj, 1,
1300                                     VA_FOURCC('N', 'V', '1', '2'), SUBSAMPLE_YUV420);
1301
1302     obj_surface->private_data = vp8_surface;
1303     obj_surface->free_private_data = i965_encoder_vp8_free_surfaces;
1304 }
1305
1306 static void
1307 i965_encoder_vp8_read_encode_status(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
1308 {
1309     struct intel_batchbuffer *batch = encoder_context->base.batch;
1310     struct i965_encoder_vp8_context *vp8_context = encoder_context->mfc_context;
1311     struct i965_encoder_vp8_encode_status_buffer *encode_status_buffer = &vp8_context->encode_status_buffer;
1312     struct i965_gpe_table *gpe = vp8_context->gpe_table;
1313     struct gpe_mi_store_register_mem_parameter mi_store_register_mem_param;
1314     struct gpe_mi_flush_dw_parameter mi_flush_dw_param;
1315     unsigned int base_offset;
1316
1317     base_offset = encode_status_buffer->base_offset;
1318
1319     memset(&mi_flush_dw_param, 0, sizeof(mi_flush_dw_param));
1320     gpe->mi_flush_dw(ctx, batch, &mi_flush_dw_param);
1321
1322     memset(&mi_store_register_mem_param, 0, sizeof(mi_store_register_mem_param));
1323     mi_store_register_mem_param.bo = encode_status_buffer->bo;
1324     mi_store_register_mem_param.offset = base_offset + encode_status_buffer->bitstream_byte_count_offset;
1325     mi_store_register_mem_param.mmio_offset = vp8_context->vdbox_mmio_base + VP8_MFC_BITSTREAM_BYTECOUNT_FRAME_REG_OFFSET;
1326     gpe->mi_store_register_mem(ctx, batch, &mi_store_register_mem_param);
1327
1328     mi_store_register_mem_param.offset = base_offset + encode_status_buffer->image_status_mask_offset;
1329     mi_store_register_mem_param.mmio_offset = vp8_context->vdbox_mmio_base + VP8_MFC_IMAGE_STATUS_MASK_REG_OFFSET;
1330     gpe->mi_store_register_mem(ctx, batch, &mi_store_register_mem_param);
1331
1332     mi_store_register_mem_param.offset = base_offset + encode_status_buffer->image_status_ctrl_offset;
1333     mi_store_register_mem_param.mmio_offset = vp8_context->vdbox_mmio_base + VP8_MFC_IMAGE_STATUS_CTRL_REG_OFFSET;
1334     gpe->mi_store_register_mem(ctx, batch, &mi_store_register_mem_param);
1335
1336     memset(&mi_flush_dw_param, 0, sizeof(mi_flush_dw_param));
1337     gpe->mi_flush_dw(ctx, batch, &mi_flush_dw_param);
1338 }
1339
1340 static void
1341 i965_encoder_vp8_read_pak_statistics(VADriverContextP ctx,
1342                                      struct intel_encoder_context *encoder_context,
1343                                      int ipass)
1344 {
1345     struct intel_batchbuffer *batch = encoder_context->base.batch;
1346     struct i965_encoder_vp8_context *vp8_context = encoder_context->mfc_context;
1347     struct i965_gpe_table *gpe = vp8_context->gpe_table;
1348     struct gpe_mi_store_data_imm_parameter mi_store_data_imm_param;
1349     struct gpe_mi_store_register_mem_parameter mi_store_register_mem_param;
1350     struct gpe_mi_flush_dw_parameter mi_flush_dw_param;
1351
1352     memset(&mi_flush_dw_param, 0, sizeof(mi_flush_dw_param));
1353     gpe->mi_flush_dw(ctx, batch, &mi_flush_dw_param);
1354
1355     if (ipass < vp8_context->num_brc_pak_passes) {
1356         memset(&mi_store_data_imm_param, 0, sizeof(mi_store_data_imm_param));
1357         mi_store_data_imm_param.bo = vp8_context->brc_pak_statistics_buffer.bo;
1358         mi_store_data_imm_param.offset = sizeof(unsigned int) * 2;
1359         mi_store_data_imm_param.dw0 = (ipass + 1) << 8;
1360         gpe->mi_store_data_imm(ctx, batch, &mi_store_data_imm_param);
1361     }
1362
1363     memset(&mi_store_register_mem_param, 0, sizeof(mi_store_register_mem_param));
1364     mi_store_register_mem_param.bo = vp8_context->brc_pak_statistics_buffer.bo;
1365     mi_store_register_mem_param.offset = 0;
1366     mi_store_register_mem_param.mmio_offset = vp8_context->vdbox_mmio_base + VP8_MFC_BITSTREAM_BYTECOUNT_FRAME_REG_OFFSET;
1367     gpe->mi_store_register_mem(ctx, batch, &mi_store_register_mem_param);
1368
1369     if (ipass == 0) {
1370         mi_store_register_mem_param.offset = sizeof(unsigned int) * 4;
1371         mi_store_register_mem_param.mmio_offset = vp8_context->vdbox_mmio_base + VP8_MFX_BRC_CUMULATIVE_DQ_INDEX01_REG_OFFSET;
1372         gpe->mi_store_register_mem(ctx, batch, &mi_store_register_mem_param);
1373     }
1374
1375     mi_store_register_mem_param.offset = sizeof(unsigned int) * 5;
1376     mi_store_register_mem_param.mmio_offset = vp8_context->vdbox_mmio_base + VP8_MFX_BRC_DQ_INDEX_REG_OFFSET;
1377     gpe->mi_store_register_mem(ctx, batch, &mi_store_register_mem_param);
1378
1379     mi_store_register_mem_param.offset = sizeof(unsigned int) * 6;
1380     mi_store_register_mem_param.mmio_offset = vp8_context->vdbox_mmio_base + VP8_MFX_BRC_D_LOOP_FILTER_REG_OFFSET;
1381     gpe->mi_store_register_mem(ctx, batch, &mi_store_register_mem_param);
1382
1383     mi_store_register_mem_param.offset = sizeof(unsigned int) * 9;
1384     mi_store_register_mem_param.mmio_offset = vp8_context->vdbox_mmio_base + VP8_MFX_BRC_CUMULATIVE_DQ_INDEX01_REG_OFFSET;
1385     gpe->mi_store_register_mem(ctx, batch, &mi_store_register_mem_param);
1386
1387     mi_store_register_mem_param.offset = sizeof(unsigned int) * 10;
1388     mi_store_register_mem_param.mmio_offset = vp8_context->vdbox_mmio_base + VP8_MFX_BRC_CUMULATIVE_DQ_INDEX23_REG_OFFSET;
1389     gpe->mi_store_register_mem(ctx, batch, &mi_store_register_mem_param);
1390
1391     mi_store_register_mem_param.offset = sizeof(unsigned int) * 11;
1392     mi_store_register_mem_param.mmio_offset = vp8_context->vdbox_mmio_base + VP8_MFX_BRC_CUMULATIVE_D_LOOP_FILTER01_REG_OFFSET;
1393     gpe->mi_store_register_mem(ctx, batch, &mi_store_register_mem_param);
1394
1395     mi_store_register_mem_param.offset = sizeof(unsigned int) * 12;
1396     mi_store_register_mem_param.mmio_offset = vp8_context->vdbox_mmio_base + VP8_MFX_BRC_CUMULATIVE_D_LOOP_FILTER23_REG_OFFSET;
1397     gpe->mi_store_register_mem(ctx, batch, &mi_store_register_mem_param);
1398
1399     mi_store_register_mem_param.offset = sizeof(unsigned int) * 13;
1400     mi_store_register_mem_param.mmio_offset = vp8_context->vdbox_mmio_base + VP8_MFX_BRC_CONVERGENCE_STATUS_REG_OFFSET;
1401     gpe->mi_store_register_mem(ctx, batch, &mi_store_register_mem_param);
1402 }
1403
1404 static void
1405 i965_encoder_vp8_gpe_context_init_once(VADriverContextP ctx,
1406                                        struct i965_gpe_context *gpe_context,
1407                                        struct vp8_encoder_kernel_parameters *kernel_params,
1408                                        unsigned int idrt_entry_size)
1409 {
1410     struct i965_driver_data *i965 = i965_driver_data(ctx);
1411
1412     gpe_context->curbe.length = kernel_params->curbe_size; // in bytes
1413
1414     gpe_context->sampler.entry_size = 0;
1415     gpe_context->sampler.max_entries = 0;
1416
1417     gpe_context->idrt.entry_size = idrt_entry_size;
1418     gpe_context->idrt.max_entries = NUM_KERNELS_PER_GPE_CONTEXT;
1419
1420     gpe_context->surface_state_binding_table.max_entries = MAX_VP8_ENCODER_SURFACES;
1421     gpe_context->surface_state_binding_table.binding_table_offset = 0;
1422     gpe_context->surface_state_binding_table.surface_state_offset = gpe_context->surface_state_binding_table.binding_table_offset +
1423         ALIGN(MAX_VP8_ENCODER_SURFACES * 4, 64);
1424     gpe_context->surface_state_binding_table.length = ALIGN(MAX_VP8_ENCODER_SURFACES * 4, 64) + ALIGN(MAX_VP8_ENCODER_SURFACES * SURFACE_STATE_PADDED_SIZE_GEN8, 64);
1425
1426     if (i965->intel.eu_total > 0)
1427         gpe_context->vfe_state.max_num_threads = 6 * i965->intel.eu_total;
1428     else
1429         gpe_context->vfe_state.max_num_threads = 112;
1430
1431     gpe_context->vfe_state.curbe_allocation_size = ALIGN(gpe_context->curbe.length, 32) >> 5; // in registers
1432     gpe_context->vfe_state.urb_entry_size = MAX(1, (ALIGN(kernel_params->inline_data_size, 32) +
1433                                                     ALIGN(kernel_params->external_data_size, 32)) >> 5); // in registers
1434     gpe_context->vfe_state.num_urb_entries = (MAX_URB_SIZE -
1435                                               gpe_context->vfe_state.curbe_allocation_size -
1436                                               ((gpe_context->idrt.entry_size >> 5) *
1437                                                gpe_context->idrt.max_entries)) / gpe_context->vfe_state.urb_entry_size;
1438     gpe_context->vfe_state.num_urb_entries = CLAMP(gpe_context->vfe_state.num_urb_entries, 1, 64);
1439     gpe_context->vfe_state.gpgpu_mode = 0;
1440 }
1441
1442 static void
1443 i965_encoder_vp8_gpe_context_vfe_scoreboard_init(struct i965_gpe_context *gpe_context, struct vp8_encoder_scoreboard_parameters *scoreboard_params)
1444 {
1445     gpe_context->vfe_desc5.scoreboard0.mask = scoreboard_params->mask;
1446     gpe_context->vfe_desc5.scoreboard0.type = scoreboard_params->type;
1447     gpe_context->vfe_desc5.scoreboard0.enable = scoreboard_params->enable;
1448
1449     // Scoreboard 0
1450     gpe_context->vfe_desc6.scoreboard1.delta_x0 = 0xF;
1451     gpe_context->vfe_desc6.scoreboard1.delta_y0 = 0x0;
1452
1453     // Scoreboard 1
1454     gpe_context->vfe_desc6.scoreboard1.delta_x1 = 0x0;
1455     gpe_context->vfe_desc6.scoreboard1.delta_y1 = 0xF;
1456
1457     // Scoreboard 2
1458     gpe_context->vfe_desc6.scoreboard1.delta_x2 = 0x1;
1459     gpe_context->vfe_desc6.scoreboard1.delta_y2 = 0xF;
1460
1461     // Scoreboard 3
1462     gpe_context->vfe_desc6.scoreboard1.delta_x3 = 0xF;
1463     gpe_context->vfe_desc6.scoreboard1.delta_y3 = 0xF;
1464
1465     // Scoreboard 4
1466     gpe_context->vfe_desc7.scoreboard2.delta_x4 = 0xF;
1467     gpe_context->vfe_desc7.scoreboard2.delta_y4 = 0x1;
1468
1469     // Scoreboard 5
1470     gpe_context->vfe_desc7.scoreboard2.delta_x5 = 0x0;
1471     gpe_context->vfe_desc7.scoreboard2.delta_y5 = 0xE;
1472     // Scoreboard 6
1473     gpe_context->vfe_desc7.scoreboard2.delta_x6 = 0x1;
1474     gpe_context->vfe_desc7.scoreboard2.delta_y6 = 0xE;
1475     // Scoreboard 7
1476     gpe_context->vfe_desc7.scoreboard2.delta_x6 = 0xF;
1477     gpe_context->vfe_desc7.scoreboard2.delta_y6 = 0xE;
1478 }
1479
1480 static void
1481 i965_add_2d_gpe_surface(VADriverContextP ctx,
1482                         struct intel_encoder_context *encoder_context,
1483                         struct i965_gpe_context *gpe_context,
1484                         struct object_surface *obj_surface,
1485                         int is_uv_surface,
1486                         int is_media_block_rw,
1487                         unsigned int format,
1488                         int index)
1489 {
1490     struct i965_encoder_vp8_context *vp8_context = encoder_context->vme_context;
1491     struct i965_gpe_table *gpe = vp8_context->gpe_table;
1492     struct i965_gpe_resource gpe_resource;
1493     struct i965_gpe_surface gpe_surface;
1494
1495     memset(&gpe_surface, 0, sizeof(gpe_surface));
1496
1497     i965_object_surface_to_2d_gpe_resource(&gpe_resource, obj_surface);
1498     gpe_surface.gpe_resource = &gpe_resource;
1499     gpe_surface.is_2d_surface = 1;
1500     gpe_surface.is_uv_surface = !!is_uv_surface;
1501     gpe_surface.is_media_block_rw = !!is_media_block_rw;
1502
1503     gpe_surface.cacheability_control = vp8_context->mocs;
1504     gpe_surface.format = format;
1505
1506     gpe->context_add_surface(gpe_context, &gpe_surface, index);
1507     i965_free_gpe_resource(&gpe_resource);
1508 }
1509
1510 static void
1511 i965_add_adv_gpe_surface(VADriverContextP ctx,
1512                          struct intel_encoder_context *encoder_context,
1513                          struct i965_gpe_context *gpe_context,
1514                          struct object_surface *obj_surface,
1515                          int index)
1516 {
1517     struct i965_encoder_vp8_context *vp8_context = encoder_context->vme_context;
1518     struct i965_gpe_table *gpe = vp8_context->gpe_table;
1519     struct i965_gpe_resource gpe_resource;
1520     struct i965_gpe_surface gpe_surface;
1521
1522     memset(&gpe_surface, 0, sizeof(gpe_surface));
1523
1524     i965_object_surface_to_2d_gpe_resource(&gpe_resource, obj_surface);
1525     gpe_surface.gpe_resource = &gpe_resource;
1526     gpe_surface.is_adv_surface = 1;
1527     gpe_surface.cacheability_control = vp8_context->mocs;
1528     gpe_surface.v_direction = I965_VDIRECTION_FULL_FRAME;
1529
1530     gpe->context_add_surface(gpe_context, &gpe_surface, index);
1531     i965_free_gpe_resource(&gpe_resource);
1532 }
1533
1534 static void
1535 i965_add_buffer_gpe_surface(VADriverContextP ctx,
1536                             struct intel_encoder_context *encoder_context,
1537                             struct i965_gpe_context *gpe_context,
1538                             struct i965_gpe_resource *gpe_buffer,
1539                             int is_raw_buffer,
1540                             unsigned int size,
1541                             unsigned int offset,
1542                             int index)
1543 {
1544     struct i965_encoder_vp8_context *vp8_context = encoder_context->vme_context;
1545     struct i965_gpe_table *gpe = vp8_context->gpe_table;
1546     struct i965_gpe_surface gpe_surface;
1547
1548     memset(&gpe_surface, 0, sizeof(gpe_surface));
1549
1550     gpe_surface.gpe_resource = gpe_buffer;
1551     gpe_surface.is_buffer = 1;
1552     gpe_surface.is_raw_buffer = !!is_raw_buffer;
1553     gpe_surface.cacheability_control = vp8_context->mocs;
1554     gpe_surface.size = size;
1555     gpe_surface.offset = offset;
1556
1557     gpe->context_add_surface(gpe_context, &gpe_surface, index);
1558 }
1559
1560 static void
1561 i965_add_buffer_2d_gpe_surface(VADriverContextP ctx,
1562                                struct intel_encoder_context *encoder_context,
1563                                struct i965_gpe_context *gpe_context,
1564                                struct i965_gpe_resource *gpe_buffer,
1565                                int is_media_block_rw,
1566                                unsigned int format,
1567                                int index)
1568 {
1569     struct i965_encoder_vp8_context *vp8_context = encoder_context->vme_context;
1570     struct i965_gpe_table *gpe = vp8_context->gpe_table;
1571     struct i965_gpe_surface gpe_surface;
1572
1573     memset(&gpe_surface, 0, sizeof(gpe_surface));
1574
1575     gpe_surface.gpe_resource = gpe_buffer;
1576     gpe_surface.is_2d_surface = 1;
1577     gpe_surface.is_media_block_rw = !!is_media_block_rw;
1578     gpe_surface.cacheability_control = vp8_context->mocs;
1579     gpe_surface.format = format;
1580
1581     gpe->context_add_surface(gpe_context, &gpe_surface, index);
1582 }
1583
1584 static void
1585 i965_add_dri_buffer_gpe_surface(VADriverContextP ctx,
1586                                 struct intel_encoder_context *encoder_context,
1587                                 struct i965_gpe_context *gpe_context,
1588                                 dri_bo *bo,
1589                                 int is_raw_buffer,
1590                                 unsigned int size,
1591                                 unsigned int offset,
1592                                 int index)
1593 {
1594     struct i965_gpe_resource gpe_resource;
1595
1596     i965_dri_object_to_buffer_gpe_resource(&gpe_resource, bo);
1597     i965_add_buffer_gpe_surface(ctx,
1598                                 encoder_context,
1599                                 gpe_context,
1600                                 &gpe_resource,
1601                                 is_raw_buffer,
1602                                 size,
1603                                 offset,
1604                                 index);
1605
1606     i965_free_gpe_resource(&gpe_resource);
1607 }
1608
1609 static void
1610 i965_add_dri_buffer_2d_gpe_surface(VADriverContextP ctx,
1611                                    struct intel_encoder_context *encoder_context,
1612                                    struct i965_gpe_context *gpe_context,
1613                                    dri_bo *bo,
1614                                    unsigned int width,
1615                                    unsigned int height,
1616                                    unsigned int pitch,
1617                                    int is_media_block_rw,
1618                                    unsigned int format,
1619                                    int index)
1620 {
1621     struct i965_gpe_resource gpe_resource;
1622
1623     i965_dri_object_to_2d_gpe_resource(&gpe_resource, bo, width, height, pitch);
1624     i965_add_buffer_2d_gpe_surface(ctx,
1625                                    encoder_context,
1626                                    gpe_context,
1627                                    &gpe_resource,
1628                                    is_media_block_rw,
1629                                    format,
1630                                    index);
1631
1632     i965_free_gpe_resource(&gpe_resource);
1633 }
1634
1635 static void
1636 i965_run_kernel_media_object(VADriverContextP ctx,
1637                              struct intel_encoder_context *encoder_context,
1638                              struct i965_gpe_context *gpe_context,
1639                              int media_function,
1640                              struct gpe_media_object_parameter *param)
1641 {
1642     struct i965_encoder_vp8_context *vp8_context = encoder_context->vme_context;
1643     struct i965_gpe_table *gpe = vp8_context->gpe_table;
1644     struct intel_batchbuffer *batch = encoder_context->base.batch;
1645
1646     intel_batchbuffer_start_atomic(batch, 0x1000);
1647
1648     intel_batchbuffer_emit_mi_flush(batch);
1649     gpe->pipeline_setup(ctx, gpe_context, batch);
1650     gpe->media_object(ctx, gpe_context, batch, param);
1651     gpe->media_state_flush(ctx, gpe_context, batch);
1652     gpe->pipeline_end(ctx, gpe_context, batch);
1653
1654     intel_batchbuffer_end_atomic(batch);
1655
1656     intel_batchbuffer_flush(batch);
1657 }
1658
1659 static void
1660 i965_init_media_object_walker_parameters(struct intel_encoder_context *encoder_context,
1661                                          struct vp8_encoder_kernel_walker_parameter *kernel_walker_param,
1662                                          struct gpe_media_object_walker_parameter *walker_param)
1663 {
1664     memset(walker_param, 0, sizeof(*walker_param));
1665
1666     walker_param->use_scoreboard = kernel_walker_param->use_scoreboard;
1667
1668     walker_param->block_resolution.x = kernel_walker_param->resolution_x;
1669     walker_param->block_resolution.y = kernel_walker_param->resolution_y;
1670
1671     walker_param->global_resolution.x = kernel_walker_param->resolution_x;
1672     walker_param->global_resolution.y = kernel_walker_param->resolution_y;
1673
1674     walker_param->global_outer_loop_stride.x = kernel_walker_param->resolution_x;
1675     walker_param->global_outer_loop_stride.y = 0;
1676
1677     walker_param->global_inner_loop_unit.x = 0;
1678     walker_param->global_inner_loop_unit.y = kernel_walker_param->resolution_y;
1679
1680     walker_param->local_loop_exec_count = 0xFFFF;  //MAX VALUE
1681     walker_param->global_loop_exec_count = 0xFFFF;  //MAX VALUE
1682
1683     if (kernel_walker_param->no_dependency) {
1684         walker_param->scoreboard_mask = 0;
1685
1686         // Raster scan walking pattern
1687         walker_param->local_outer_loop_stride.x = 0;
1688         walker_param->local_outer_loop_stride.y = 1;
1689         walker_param->local_inner_loop_unit.x = 1;
1690         walker_param->local_inner_loop_unit.y = 0;
1691         walker_param->local_end.x = kernel_walker_param->resolution_x - 1;
1692         walker_param->local_end.y = 0;
1693     } else {
1694         walker_param->local_end.x = 0;
1695         walker_param->local_end.y = 0;
1696
1697         if (kernel_walker_param->walker_degree == VP8_ENCODER_46_DEGREE) {
1698             // 46 degree
1699             walker_param->scoreboard_mask = kernel_walker_param->scoreboard_mask;
1700             walker_param->local_outer_loop_stride.x = 1;
1701             walker_param->local_outer_loop_stride.y = 0;
1702             walker_param->local_inner_loop_unit.x = -1;
1703             walker_param->local_inner_loop_unit.y = 1;
1704         } else if (kernel_walker_param->walker_degree == VP8_ENCODER_45Z_DEGREE) {
1705             // 45z degree
1706             walker_param->scoreboard_mask = 0x0F;
1707
1708             walker_param->global_loop_exec_count = 0x3FF;
1709             walker_param->local_loop_exec_count = 0x3FF;
1710
1711             walker_param->global_resolution.x = (unsigned int)(kernel_walker_param->resolution_x / 2.f) + 1;
1712             walker_param->global_resolution.y = 2 * kernel_walker_param->resolution_y;
1713
1714             walker_param->global_start.x = 0;
1715             walker_param->global_start.y = 0;
1716
1717             walker_param->global_outer_loop_stride.x = walker_param->global_resolution.x;
1718             walker_param->global_outer_loop_stride.y = 0;
1719
1720             walker_param->global_inner_loop_unit.x = 0;
1721             walker_param->global_inner_loop_unit.y = walker_param->global_resolution.y;
1722
1723             walker_param->block_resolution.x = walker_param->global_resolution.x;
1724             walker_param->block_resolution.y = walker_param->global_resolution.y;
1725
1726             walker_param->local_start.x = 0;
1727             walker_param->local_start.y = 0;
1728
1729             walker_param->local_outer_loop_stride.x = 1;
1730             walker_param->local_outer_loop_stride.y = 0;
1731
1732             walker_param->local_inner_loop_unit.x = -1;
1733             walker_param->local_inner_loop_unit.y = 4;
1734
1735             walker_param->middle_loop_extra_steps = 3;
1736             walker_param->mid_loop_unit_x = 0;
1737             walker_param->mid_loop_unit_y = 1;
1738         } else if (kernel_walker_param->walker_degree == VP8_ENCODER_45_DEGREE) {
1739             // 45 degree
1740             walker_param->scoreboard_mask = 0x03;
1741             walker_param->local_outer_loop_stride.x = 1;
1742             walker_param->local_outer_loop_stride.y = 0;
1743             walker_param->local_inner_loop_unit.x = -1;
1744             walker_param->local_inner_loop_unit.y = 1;
1745         } else {
1746             // 26 degree
1747             walker_param->scoreboard_mask = 0x0F;
1748             walker_param->local_outer_loop_stride.x = 1;
1749             walker_param->local_outer_loop_stride.y = 0;
1750             walker_param->local_inner_loop_unit.x = -2;
1751             walker_param->local_inner_loop_unit.y = 1;
1752         }
1753     }
1754 }
1755
1756 static void
1757 i965_run_kernel_media_object_walker(VADriverContextP ctx,
1758                                     struct intel_encoder_context *encoder_context,
1759                                     struct i965_gpe_context *gpe_context,
1760                                     int media_function,
1761                                     struct gpe_media_object_walker_parameter *param)
1762 {
1763     struct i965_encoder_vp8_context *vp8_context = encoder_context->vme_context;
1764     struct i965_gpe_table *gpe = vp8_context->gpe_table;
1765     struct intel_batchbuffer *batch = encoder_context->base.batch;
1766
1767     intel_batchbuffer_start_atomic(batch, 0x1000);
1768
1769     intel_batchbuffer_emit_mi_flush(batch);
1770     gpe->pipeline_setup(ctx, gpe_context, batch);
1771     gpe->media_object_walker(ctx, gpe_context, batch, param);
1772     gpe->media_state_flush(ctx, gpe_context, batch);
1773     gpe->pipeline_end(ctx, gpe_context, batch);
1774
1775     intel_batchbuffer_end_atomic(batch);
1776
1777     intel_batchbuffer_flush(batch);
1778 }
1779
1780 static void
1781 i965_encoder_vp8_vme_init_mpu_tpu_buffer(VADriverContextP ctx,
1782                                          struct intel_encoder_context *encoder_context,
1783                                          struct i965_encoder_vp8_context *vp8_context)
1784 {
1785     char *pbuffer = NULL;
1786
1787     i965_zero_gpe_resource(&vp8_context->pak_mpu_tpu_mode_probs_buffer);
1788     i965_zero_gpe_resource(&vp8_context->pak_mpu_tpu_ref_mode_probs_buffer);
1789
1790     pbuffer = i965_map_gpe_resource(&vp8_context->pak_mpu_tpu_ref_coeff_probs_buffer);
1791
1792     if (!pbuffer)
1793         return;
1794
1795     memcpy(pbuffer, vp8_default_coef_probs, sizeof(vp8_default_coef_probs));
1796     i965_unmap_gpe_resource(&vp8_context->pak_mpu_tpu_ref_coeff_probs_buffer);
1797
1798     pbuffer = i965_map_gpe_resource(&vp8_context->pak_mpu_tpu_entropy_cost_table_buffer);
1799
1800     if (!pbuffer)
1801         return;
1802
1803     memcpy(pbuffer, vp8_prob_cost, sizeof(vp8_prob_cost));
1804     i965_unmap_gpe_resource(&vp8_context->pak_mpu_tpu_entropy_cost_table_buffer);
1805
1806     pbuffer = i965_map_gpe_resource(&vp8_context->pak_mpu_tpu_pak_token_update_flags_buffer);
1807
1808     if (!pbuffer)
1809         return;
1810
1811     memcpy(pbuffer, vp8_probs_update_flag, sizeof(vp8_probs_update_flag));
1812     i965_unmap_gpe_resource(&vp8_context->pak_mpu_tpu_pak_token_update_flags_buffer);
1813
1814     pbuffer = i965_map_gpe_resource(&vp8_context->pak_mpu_tpu_default_token_probability_buffer);
1815
1816     if (!pbuffer)
1817         return;
1818
1819     memcpy(pbuffer, vp8_coef_update_probs, sizeof(vp8_coef_update_probs));
1820     i965_unmap_gpe_resource(&vp8_context->pak_mpu_tpu_default_token_probability_buffer);
1821
1822     pbuffer = i965_map_gpe_resource(&vp8_context->pak_mpu_tpu_key_frame_token_probability_buffer);
1823
1824     if (!pbuffer)
1825         return;
1826
1827     memcpy(pbuffer, vp8_default_coef_probs, sizeof(vp8_default_coef_probs));
1828     i965_unmap_gpe_resource(&vp8_context->pak_mpu_tpu_key_frame_token_probability_buffer);
1829
1830     pbuffer = i965_map_gpe_resource(&vp8_context->pak_mpu_tpu_updated_token_probability_buffer);
1831
1832     if (!pbuffer)
1833         return;
1834
1835     memcpy(pbuffer, vp8_default_coef_probs, sizeof(vp8_default_coef_probs));
1836     i965_unmap_gpe_resource(&vp8_context->pak_mpu_tpu_updated_token_probability_buffer);
1837 }
1838
1839 #define ALLOC_VP8_RESOURCE_BUFFER(buffer, bufsize, des) {       \
1840         vp8_context->buffer.type = I965_GPE_RESOURCE_BUFFER;    \
1841         vp8_context->buffer.width = (bufsize);                  \
1842         vp8_context->buffer.height = 1;                         \
1843         vp8_context->buffer.pitch = vp8_context->buffer.width;  \
1844         vp8_context->buffer.size = vp8_context->buffer.pitch *  \
1845             vp8_context->buffer.height;                         \
1846         vp8_context->buffer.tiling = I915_TILING_NONE;          \
1847         i965_allocate_gpe_resource(i965->intel.bufmgr,          \
1848                                    &vp8_context->buffer,        \
1849                                    vp8_context->buffer.size,    \
1850                                    (des));                      \
1851     } while (0)
1852
1853 static void
1854 i965_encoder_vp8_vme_allocate_resources(VADriverContextP ctx,
1855                                         struct intel_encoder_context *encoder_context,
1856                                         struct i965_encoder_vp8_context *vp8_context)
1857 {
1858     struct i965_driver_data *i965 = i965_driver_data(ctx);
1859     unsigned int frame_size_in_mbs = vp8_context->frame_width_in_mbs *
1860         vp8_context->frame_height_in_mbs;
1861
1862     vp8_context->mv_offset = ALIGN((frame_size_in_mbs * 16 * 4), 4096);
1863     vp8_context->mb_coded_buffer_size = vp8_context->mv_offset + (frame_size_in_mbs * 16 * sizeof(unsigned int));
1864
1865     ALLOC_VP8_RESOURCE_BUFFER(reference_frame_mb_count_buffer, 32, "Reference frame mb count buffer");
1866
1867     vp8_context->mb_mode_cost_luma_buffer.type = I965_GPE_RESOURCE_2D;
1868     vp8_context->mb_mode_cost_luma_buffer.width = ALIGN((sizeof(short) * 10), 64);
1869     vp8_context->mb_mode_cost_luma_buffer.height = 1;
1870     vp8_context->mb_mode_cost_luma_buffer.pitch = vp8_context->mb_mode_cost_luma_buffer.width;
1871     vp8_context->mb_mode_cost_luma_buffer.size = vp8_context->mb_mode_cost_luma_buffer.pitch *
1872         vp8_context->mb_mode_cost_luma_buffer.height;
1873     vp8_context->mb_mode_cost_luma_buffer.tiling = I915_TILING_NONE;
1874     i965_allocate_gpe_resource(i965->intel.bufmgr,
1875                                &vp8_context->mb_mode_cost_luma_buffer,
1876                                vp8_context->mb_mode_cost_luma_buffer.size,
1877                                "MB mode cost luma buffer");
1878
1879     vp8_context->block_mode_cost_buffer.type = I965_GPE_RESOURCE_2D;
1880     vp8_context->block_mode_cost_buffer.width = ALIGN((sizeof(short) * 10 * 10 * 10), 64);
1881     vp8_context->block_mode_cost_buffer.height = 1;
1882     vp8_context->block_mode_cost_buffer.pitch = vp8_context->block_mode_cost_buffer.width;
1883     vp8_context->block_mode_cost_buffer.size = vp8_context->block_mode_cost_buffer.pitch *
1884         vp8_context->block_mode_cost_buffer.height;
1885     vp8_context->block_mode_cost_buffer.tiling = I915_TILING_NONE;
1886     i965_allocate_gpe_resource(i965->intel.bufmgr,
1887                                &vp8_context->block_mode_cost_buffer,
1888                                vp8_context->block_mode_cost_buffer.size,
1889                                "Block mode cost luma buffer");
1890
1891     ALLOC_VP8_RESOURCE_BUFFER(chroma_recon_buffer, frame_size_in_mbs * 64, "Chroma recon buffer");
1892
1893     vp8_context->per_mb_quant_data_buffer.type = I965_GPE_RESOURCE_2D;
1894     vp8_context->per_mb_quant_data_buffer.width = ALIGN((vp8_context->frame_width_in_mbs * 4), 64);
1895     vp8_context->per_mb_quant_data_buffer.height = vp8_context->frame_height_in_mbs;
1896     vp8_context->per_mb_quant_data_buffer.pitch = vp8_context->per_mb_quant_data_buffer.width;
1897     vp8_context->per_mb_quant_data_buffer.size = vp8_context->per_mb_quant_data_buffer.pitch *
1898         vp8_context->per_mb_quant_data_buffer.height;
1899     vp8_context->per_mb_quant_data_buffer.tiling = I915_TILING_NONE;
1900     i965_allocate_gpe_resource(i965->intel.bufmgr,
1901                                &vp8_context->per_mb_quant_data_buffer,
1902                                vp8_context->per_mb_quant_data_buffer.size,
1903                                "Per MB quant data buffer");
1904
1905     ALLOC_VP8_RESOURCE_BUFFER(pred_mv_data_buffer, frame_size_in_mbs * 4 * sizeof(unsigned int), "Pred mv data buffer");
1906     ALLOC_VP8_RESOURCE_BUFFER(mode_cost_update_buffer, 16 * sizeof(unsigned int), "Mode cost update buffer");
1907
1908     /*
1909      * BRC buffers
1910      */
1911     ALLOC_VP8_RESOURCE_BUFFER(brc_history_buffer, VP8_BRC_HISTORY_BUFFER_SIZE, "BRC history buffer");
1912     i965_zero_gpe_resource(&vp8_context->brc_history_buffer);
1913
1914     vp8_context->brc_segment_map_buffer.type = I965_GPE_RESOURCE_2D;
1915     vp8_context->brc_segment_map_buffer.width = vp8_context->frame_width_in_mbs;
1916     vp8_context->brc_segment_map_buffer.height = vp8_context->frame_height_in_mbs;
1917     vp8_context->brc_segment_map_buffer.pitch = vp8_context->brc_segment_map_buffer.width;
1918     vp8_context->brc_segment_map_buffer.size = vp8_context->brc_segment_map_buffer.pitch *
1919         vp8_context->brc_segment_map_buffer.height;
1920     vp8_context->brc_segment_map_buffer.tiling = I915_TILING_NONE;
1921     i965_allocate_gpe_resource(i965->intel.bufmgr,
1922                                &vp8_context->brc_segment_map_buffer,
1923                                vp8_context->brc_segment_map_buffer.size,
1924                                "BRC segment map buffer");
1925
1926     vp8_context->brc_distortion_buffer.type = I965_GPE_RESOURCE_2D;
1927     vp8_context->brc_distortion_buffer.width = ALIGN((vp8_context->down_scaled_width_in_mb4x * 8), 64);
1928     vp8_context->brc_distortion_buffer.height = 2 * ALIGN((vp8_context->down_scaled_height_in_mb4x * 4), 8);
1929     vp8_context->brc_distortion_buffer.pitch = vp8_context->brc_distortion_buffer.width;
1930     vp8_context->brc_distortion_buffer.size = vp8_context->brc_distortion_buffer.pitch *
1931         vp8_context->brc_distortion_buffer.height;
1932     vp8_context->brc_distortion_buffer.tiling = I915_TILING_NONE;
1933     i965_allocate_gpe_resource(i965->intel.bufmgr,
1934                                &vp8_context->brc_distortion_buffer,
1935                                vp8_context->brc_distortion_buffer.size,
1936                                "BRC distortion buffer");
1937     i965_zero_gpe_resource(&vp8_context->brc_distortion_buffer);
1938
1939     ALLOC_VP8_RESOURCE_BUFFER(brc_pak_statistics_buffer, sizeof(struct vp8_brc_pak_statistics), "BRC pak statistics buffer");
1940     i965_zero_gpe_resource(&vp8_context->brc_pak_statistics_buffer);
1941
1942     ALLOC_VP8_RESOURCE_BUFFER(brc_vp8_cfg_command_read_buffer, VP8_BRC_IMG_STATE_SIZE_PER_PASS * VP8_BRC_MAXIMUM_NUM_PASSES, "BRC VP8 configuration command read buffer");
1943     i965_zero_gpe_resource(&vp8_context->brc_vp8_cfg_command_read_buffer);
1944
1945     ALLOC_VP8_RESOURCE_BUFFER(brc_vp8_cfg_command_write_buffer, VP8_BRC_IMG_STATE_SIZE_PER_PASS * VP8_BRC_MAXIMUM_NUM_PASSES, "BRC VP8 configuration command write buffer");
1946     i965_zero_gpe_resource(&vp8_context->brc_vp8_cfg_command_write_buffer);
1947
1948     ALLOC_VP8_RESOURCE_BUFFER(brc_vp8_constant_data_buffer, VP8_BRC_CONSTANT_DATA_SIZE, "BRC VP8 constant data buffer");
1949     i965_zero_gpe_resource(&vp8_context->brc_vp8_constant_data_buffer);
1950
1951     ALLOC_VP8_RESOURCE_BUFFER(brc_pak_statistics_dump_buffer, vp8_context->num_brc_pak_passes * sizeof(unsigned int) * 12, "BRC pak statistics buffer");
1952     i965_zero_gpe_resource(&vp8_context->brc_pak_statistics_dump_buffer);
1953
1954     vp8_context->me_4x_mv_data_buffer.type = I965_GPE_RESOURCE_2D;
1955     vp8_context->me_4x_mv_data_buffer.width = vp8_context->down_scaled_width_in_mb4x * 32;
1956     vp8_context->me_4x_mv_data_buffer.height = vp8_context->down_scaled_height_in_mb4x * 4 * 4;
1957     vp8_context->me_4x_mv_data_buffer.pitch = ALIGN(vp8_context->me_4x_mv_data_buffer.width, 64);
1958     vp8_context->me_4x_mv_data_buffer.size = vp8_context->me_4x_mv_data_buffer.pitch *
1959         vp8_context->me_4x_mv_data_buffer.height;
1960     vp8_context->me_4x_mv_data_buffer.tiling = I915_TILING_NONE;
1961     i965_allocate_gpe_resource(i965->intel.bufmgr,
1962                                &vp8_context->me_4x_mv_data_buffer,
1963                                vp8_context->me_4x_mv_data_buffer.size,
1964                                "ME 4x MV Data buffer");
1965
1966     vp8_context->me_4x_distortion_buffer.type = I965_GPE_RESOURCE_2D;
1967     vp8_context->me_4x_distortion_buffer.width = vp8_context->down_scaled_width_in_mb4x * 8;
1968     vp8_context->me_4x_distortion_buffer.height = vp8_context->down_scaled_height_in_mb4x * 4 * 4;
1969     vp8_context->me_4x_distortion_buffer.pitch = ALIGN(vp8_context->me_4x_distortion_buffer.width, 64);
1970     vp8_context->me_4x_distortion_buffer.size = vp8_context->me_4x_distortion_buffer.pitch *
1971         vp8_context->me_4x_distortion_buffer.height;
1972     vp8_context->me_4x_distortion_buffer.tiling = I915_TILING_NONE;
1973     i965_allocate_gpe_resource(i965->intel.bufmgr,
1974                                &vp8_context->me_4x_distortion_buffer,
1975                                vp8_context->me_4x_distortion_buffer.size,
1976                                "ME 4x Distortion buffer");
1977
1978     vp8_context->me_16x_mv_data_buffer.type = I965_GPE_RESOURCE_2D;
1979     vp8_context->me_16x_mv_data_buffer.width = ALIGN((vp8_context->down_scaled_width_in_mb16x * 32), 64);
1980     vp8_context->me_16x_mv_data_buffer.height = vp8_context->down_scaled_height_in_mb16x * 4 * VP8_ME_MV_DATA_SIZE_MULTIPLIER;
1981     vp8_context->me_16x_mv_data_buffer.pitch = vp8_context->me_16x_mv_data_buffer.width;
1982     vp8_context->me_16x_mv_data_buffer.size = vp8_context->me_16x_mv_data_buffer.pitch *
1983         vp8_context->me_16x_mv_data_buffer.height;
1984     vp8_context->me_16x_mv_data_buffer.tiling = I915_TILING_NONE;
1985     i965_allocate_gpe_resource(i965->intel.bufmgr,
1986                                &vp8_context->me_16x_mv_data_buffer,
1987                                vp8_context->me_16x_mv_data_buffer.size,
1988                                "ME 16x MV Data buffer");
1989
1990     ALLOC_VP8_RESOURCE_BUFFER(histogram_buffer, VP8_HISTOGRAM_SIZE, "Histogram buffer");
1991     ALLOC_VP8_RESOURCE_BUFFER(pak_intra_row_store_scratch_buffer, vp8_context->frame_width_in_mbs * 64, "Intra row store scratch buffer");
1992     ALLOC_VP8_RESOURCE_BUFFER(pak_deblocking_filter_row_store_scratch_buffer, vp8_context->frame_width_in_mbs * 4 * 64, "Deblocking filter row store scratch buffer");
1993     ALLOC_VP8_RESOURCE_BUFFER(pak_mpc_row_store_scratch_buffer, vp8_context->frame_width_in_mbs * 2 * 64, "MPC row store scratch buffer");
1994     ALLOC_VP8_RESOURCE_BUFFER(pak_stream_out_buffer, frame_size_in_mbs * 16, "stream out buffer");
1995     ALLOC_VP8_RESOURCE_BUFFER(pak_frame_header_buffer, VP8_FRAME_HEADER_SIZE, "Frame header buffer");
1996     ALLOC_VP8_RESOURCE_BUFFER(pak_intermediate_buffer, frame_size_in_mbs * 256 * 2 + frame_size_in_mbs * 64 + VP8_INTERMEDIATE_PARTITION0_SIZE, "Intermediate buffer");
1997     ALLOC_VP8_RESOURCE_BUFFER(pak_mpu_tpu_mode_probs_buffer, VP8_MODE_PROPABILITIES_SIZE, "Mode probs buffer");
1998     ALLOC_VP8_RESOURCE_BUFFER(pak_mpu_tpu_ref_mode_probs_buffer, VP8_MODE_PROPABILITIES_SIZE, "Ref mode probs buffer");
1999     ALLOC_VP8_RESOURCE_BUFFER(pak_mpu_tpu_coeff_probs_buffer, VP8_COEFFS_PROPABILITIES_SIZE, "Coeff probs buffer");
2000     ALLOC_VP8_RESOURCE_BUFFER(pak_mpu_tpu_ref_coeff_probs_buffer, VP8_COEFFS_PROPABILITIES_SIZE, "Ref coeff probs buffer");
2001     ALLOC_VP8_RESOURCE_BUFFER(pak_mpu_tpu_token_bits_data_buffer, VP8_TOKEN_BITS_DATA_SIZE, "Token bits data buffer");
2002     i965_zero_gpe_resource(&vp8_context->pak_mpu_tpu_token_bits_data_buffer);
2003     ALLOC_VP8_RESOURCE_BUFFER(pak_mpu_tpu_picture_state_buffer, VP8_PICTURE_STATE_SIZE, "Picture state buffer");
2004     ALLOC_VP8_RESOURCE_BUFFER(pak_mpu_tpu_mpu_bitstream_buffer, VP8_MPU_BITSTREAM_SIZE, "Mpu bitstream buffer");
2005     ALLOC_VP8_RESOURCE_BUFFER(pak_mpu_tpu_tpu_bitstream_buffer, VP8_TPU_BITSTREAM_SIZE, "Tpu bitstream buffer");
2006     ALLOC_VP8_RESOURCE_BUFFER(pak_mpu_tpu_entropy_cost_table_buffer, VP8_ENTROPY_COST_TABLE_SIZE, "Entropy cost buffer");
2007     ALLOC_VP8_RESOURCE_BUFFER(pak_mpu_tpu_pak_token_statistics_buffer, VP8_TOKEN_STATISTICS_SIZE, "Pak token statistics buffer");
2008     ALLOC_VP8_RESOURCE_BUFFER(pak_mpu_tpu_pak_token_update_flags_buffer, VP8_COEFFS_PROPABILITIES_SIZE, "Pak token update flags buffer");
2009     ALLOC_VP8_RESOURCE_BUFFER(pak_mpu_tpu_default_token_probability_buffer, VP8_COEFFS_PROPABILITIES_SIZE, "Default token probability buffer");
2010     ALLOC_VP8_RESOURCE_BUFFER(pak_mpu_tpu_key_frame_token_probability_buffer, VP8_COEFFS_PROPABILITIES_SIZE, "Key frame token probability buffer");
2011     ALLOC_VP8_RESOURCE_BUFFER(pak_mpu_tpu_updated_token_probability_buffer, VP8_COEFFS_PROPABILITIES_SIZE, "Updated token probability buffer");
2012     ALLOC_VP8_RESOURCE_BUFFER(pak_mpu_tpu_hw_token_probability_pak_pass_2_buffer, VP8_COEFFS_PROPABILITIES_SIZE, "Hw token probability pak pass 2 buffer");
2013     ALLOC_VP8_RESOURCE_BUFFER(pak_mpu_tpu_repak_decision_buffer, VP8_REPAK_DECISION_BUF_SIZE, "Tpu repak decision buffer");
2014
2015     i965_encoder_vp8_vme_init_mpu_tpu_buffer(ctx, encoder_context, vp8_context);
2016
2017     ALLOC_VP8_RESOURCE_BUFFER(mb_coded_buffer, vp8_context->mb_coded_buffer_size, "MB coded buffer");
2018 }
2019
2020 #undef ALLOC_VP8_RESOURCE_BUFFER
2021
2022 static void
2023 i965_encoder_vp8_vme_free_resources(struct i965_encoder_vp8_context *vp8_context)
2024 {
2025     i965_free_gpe_resource(&vp8_context->reference_frame_mb_count_buffer);
2026     i965_free_gpe_resource(&vp8_context->mb_mode_cost_luma_buffer);
2027     i965_free_gpe_resource(&vp8_context->block_mode_cost_buffer);
2028     i965_free_gpe_resource(&vp8_context->chroma_recon_buffer);
2029     i965_free_gpe_resource(&vp8_context->per_mb_quant_data_buffer);
2030     i965_free_gpe_resource(&vp8_context->pred_mv_data_buffer);
2031     i965_free_gpe_resource(&vp8_context->mode_cost_update_buffer);
2032
2033     i965_free_gpe_resource(&vp8_context->brc_history_buffer);
2034     i965_free_gpe_resource(&vp8_context->brc_segment_map_buffer);
2035     i965_free_gpe_resource(&vp8_context->brc_distortion_buffer);
2036     i965_free_gpe_resource(&vp8_context->brc_pak_statistics_buffer);
2037     i965_free_gpe_resource(&vp8_context->brc_vp8_cfg_command_read_buffer);
2038     i965_free_gpe_resource(&vp8_context->brc_vp8_cfg_command_write_buffer);
2039     i965_free_gpe_resource(&vp8_context->brc_vp8_constant_data_buffer);
2040     i965_free_gpe_resource(&vp8_context->brc_pak_statistics_dump_buffer);
2041
2042     i965_free_gpe_resource(&vp8_context->me_4x_mv_data_buffer);
2043     i965_free_gpe_resource(&vp8_context->me_4x_distortion_buffer);
2044     i965_free_gpe_resource(&vp8_context->me_16x_mv_data_buffer);
2045
2046     i965_free_gpe_resource(&vp8_context->histogram_buffer);
2047
2048     i965_free_gpe_resource(&vp8_context->pak_intra_row_store_scratch_buffer);
2049     i965_free_gpe_resource(&vp8_context->pak_deblocking_filter_row_store_scratch_buffer);
2050     i965_free_gpe_resource(&vp8_context->pak_mpc_row_store_scratch_buffer);
2051     i965_free_gpe_resource(&vp8_context->pak_stream_out_buffer);
2052     i965_free_gpe_resource(&vp8_context->pak_frame_header_buffer);
2053     i965_free_gpe_resource(&vp8_context->pak_intermediate_buffer);
2054     i965_free_gpe_resource(&vp8_context->pak_mpu_tpu_mode_probs_buffer);
2055     i965_free_gpe_resource(&vp8_context->pak_mpu_tpu_ref_mode_probs_buffer);
2056     i965_free_gpe_resource(&vp8_context->pak_mpu_tpu_coeff_probs_buffer);
2057     i965_free_gpe_resource(&vp8_context->pak_mpu_tpu_ref_coeff_probs_buffer);
2058     i965_free_gpe_resource(&vp8_context->pak_mpu_tpu_token_bits_data_buffer);
2059     i965_free_gpe_resource(&vp8_context->pak_mpu_tpu_picture_state_buffer);
2060     i965_free_gpe_resource(&vp8_context->pak_mpu_tpu_mpu_bitstream_buffer);
2061     i965_free_gpe_resource(&vp8_context->pak_mpu_tpu_tpu_bitstream_buffer);
2062     i965_free_gpe_resource(&vp8_context->pak_mpu_tpu_entropy_cost_table_buffer);
2063     i965_free_gpe_resource(&vp8_context->pak_mpu_tpu_pak_token_statistics_buffer);
2064     i965_free_gpe_resource(&vp8_context->pak_mpu_tpu_pak_token_update_flags_buffer);
2065     i965_free_gpe_resource(&vp8_context->pak_mpu_tpu_default_token_probability_buffer);
2066     i965_free_gpe_resource(&vp8_context->pak_mpu_tpu_key_frame_token_probability_buffer);
2067     i965_free_gpe_resource(&vp8_context->pak_mpu_tpu_updated_token_probability_buffer);
2068     i965_free_gpe_resource(&vp8_context->pak_mpu_tpu_hw_token_probability_pak_pass_2_buffer);
2069     i965_free_gpe_resource(&vp8_context->pak_mpu_tpu_repak_decision_buffer);
2070
2071     i965_free_gpe_resource(&vp8_context->mb_coded_buffer);
2072 }
2073
2074 static void
2075 i965_encoder_vp8_update_internal_rc_mode(VADriverContextP ctx,
2076                                          struct encode_state *encode_state,
2077                                          struct intel_encoder_context *encoder_context)
2078 {
2079     struct i965_encoder_vp8_context *vp8_context = encoder_context->vme_context;
2080
2081     if (encoder_context->rate_control_mode & VA_RC_CBR)
2082         vp8_context->internal_rate_mode = I965_BRC_CBR;
2083     else if (encoder_context->rate_control_mode & VA_RC_VBR)
2084         vp8_context->internal_rate_mode = I965_BRC_VBR;
2085     else
2086         vp8_context->internal_rate_mode = I965_BRC_CQP;
2087 }
2088
2089 static void
2090 i965_encoder_vp8_get_sequence_parameter(VADriverContextP ctx,
2091                                         struct encode_state *encode_state,
2092                                         struct intel_encoder_context *encoder_context)
2093 {
2094     struct i965_encoder_vp8_context *vp8_context = encoder_context->vme_context;
2095
2096     /*
2097      * It is required to update frame width and height for each frame
2098      */
2099     if (encoder_context->frame_width_in_pixel != vp8_context->picture_width ||
2100         encoder_context->frame_height_in_pixel != vp8_context->picture_height) {
2101         vp8_context->picture_width = encoder_context->frame_width_in_pixel;
2102         vp8_context->picture_height = encoder_context->frame_height_in_pixel;
2103
2104         vp8_context->frame_width_in_mbs = WIDTH_IN_MACROBLOCKS(vp8_context->picture_width);
2105         vp8_context->frame_height_in_mbs = HEIGHT_IN_MACROBLOCKS(vp8_context->picture_height);
2106
2107         vp8_context->frame_width = vp8_context->frame_width_in_mbs * 16;
2108         vp8_context->frame_height = vp8_context->frame_height_in_mbs * 16;
2109
2110         vp8_context->down_scaled_width_in_mb4x = WIDTH_IN_MACROBLOCKS(vp8_context->frame_width / SCALE_FACTOR_4X);
2111         vp8_context->down_scaled_height_in_mb4x = HEIGHT_IN_MACROBLOCKS(vp8_context->frame_height / SCALE_FACTOR_4X);
2112         vp8_context->down_scaled_width_4x = vp8_context->down_scaled_width_in_mb4x * 16;
2113         vp8_context->down_scaled_height_4x = vp8_context->down_scaled_height_in_mb4x * 16;
2114
2115         vp8_context->down_scaled_width_in_mb16x = WIDTH_IN_MACROBLOCKS(vp8_context->frame_width / SCALE_FACTOR_16X);
2116         vp8_context->down_scaled_height_in_mb16x = HEIGHT_IN_MACROBLOCKS(vp8_context->frame_height / SCALE_FACTOR_16X);
2117         vp8_context->down_scaled_width_16x = vp8_context->down_scaled_width_in_mb16x * 16;
2118         vp8_context->down_scaled_height_16x = vp8_context->down_scaled_height_in_mb16x * 16;
2119
2120         i965_encoder_vp8_check_motion_estimation(ctx, encoder_context);
2121
2122         i965_encoder_vp8_vme_free_resources(vp8_context);
2123         i965_encoder_vp8_vme_allocate_resources(ctx, encoder_context, vp8_context);
2124     }
2125
2126     vp8_context->num_passes = 0;
2127     vp8_context->repak_pass_iter_val = 0;
2128     vp8_context->ref_ctrl_optimization_done = 0;
2129 }
2130
2131 static void
2132 i965_encoder_vp8_get_picture_parameter(VADriverContextP ctx,
2133                                        struct encode_state *encode_state,
2134                                        struct intel_encoder_context *encoder_context)
2135 {
2136     struct i965_driver_data *i965 = i965_driver_data(ctx);
2137     struct i965_encoder_vp8_context *vp8_context = encoder_context->vme_context;
2138     struct object_surface *obj_surface;
2139     VAEncPictureParameterBufferVP8 *pic_param = (VAEncPictureParameterBufferVP8 *)encode_state->pic_param_ext->buffer;
2140     VAQMatrixBufferVP8 *quant_params = (VAQMatrixBufferVP8 *)encode_state->q_matrix->buffer;
2141     int is_intra, i;
2142     unsigned int average_qp = 0;
2143     unsigned char brc_enabled = (vp8_context->internal_rate_mode == I965_BRC_CBR ||
2144                                  vp8_context->internal_rate_mode == I965_BRC_VBR);
2145
2146     vp8_context->frame_type = pic_param->pic_flags.bits.frame_type ? MPEG_P_PICTURE : MPEG_I_PICTURE;
2147     is_intra = (vp8_context->frame_type == MPEG_I_PICTURE);
2148
2149     if (is_intra) {
2150         vp8_context->ref_frame_ctrl = 0;
2151     } else {
2152         vp8_context->ref_frame_ctrl =
2153             ((!pic_param->ref_flags.bits.no_ref_last) |
2154              (!pic_param->ref_flags.bits.no_ref_gf << 1) |
2155              (!pic_param->ref_flags.bits.no_ref_arf << 2));
2156     }
2157
2158     vp8_context->hme_enabled = (vp8_context->hme_supported && !is_intra && vp8_context->ref_frame_ctrl != 0);
2159     vp8_context->hme_16x_enabled = (vp8_context->hme_16x_supported && !is_intra);
2160
2161     if (pic_param->ref_last_frame != VA_INVALID_SURFACE) {
2162         obj_surface = SURFACE(pic_param->ref_last_frame);
2163
2164         if (obj_surface && obj_surface->bo)
2165             vp8_context->ref_last_frame = obj_surface;
2166         else
2167             vp8_context->ref_last_frame = NULL;
2168     } else {
2169         vp8_context->ref_last_frame = NULL;
2170     }
2171
2172     if (pic_param->ref_gf_frame != VA_INVALID_SURFACE) {
2173         obj_surface = SURFACE(pic_param->ref_gf_frame);
2174
2175         if (obj_surface && obj_surface->bo)
2176             vp8_context->ref_gf_frame = obj_surface;
2177         else
2178             vp8_context->ref_gf_frame = NULL;
2179     } else {
2180         vp8_context->ref_gf_frame = NULL;
2181     }
2182
2183     if (pic_param->ref_arf_frame != VA_INVALID_SURFACE) {
2184         obj_surface = SURFACE(pic_param->ref_arf_frame);
2185
2186         if (obj_surface && obj_surface->bo)
2187             vp8_context->ref_arf_frame = obj_surface;
2188         else
2189             vp8_context->ref_arf_frame = NULL;
2190     } else {
2191         vp8_context->ref_arf_frame = NULL;
2192     }
2193
2194     vp8_context->brc_distortion_buffer_need_reset = 0;
2195
2196     if (brc_enabled) {
2197         if (is_intra) {
2198             vp8_context->brc_distortion_buffer_need_reset = 1;
2199         } else {
2200             if (vp8_context->frame_num % vp8_context->gop_size == 1) {
2201                 vp8_context->brc_distortion_buffer_need_reset = 1;
2202             }
2203         }
2204     }
2205
2206     if (pic_param->pic_flags.bits.segmentation_enabled) {
2207         for (i = 0; i < VP8_MAX_SEGMENTS; i++) {
2208             average_qp += quant_params->quantization_index[i] + quant_params->quantization_index_delta[i];
2209         }
2210
2211         average_qp = average_qp / VP8_MAX_SEGMENTS;
2212     } else {
2213         average_qp += quant_params->quantization_index[0] + quant_params->quantization_index_delta[0];
2214     }
2215
2216     if (is_intra) {
2217         vp8_context->average_i_frame_qp = average_qp;
2218     } else {
2219         vp8_context->average_p_frame_qp = average_qp;
2220     }
2221
2222     if (brc_enabled && vp8_context->multiple_pass_brc_supported)
2223         vp8_context->num_brc_pak_passes = VP8_BRC_MINIMUM_NUM_PASSES;
2224     else
2225         vp8_context->num_brc_pak_passes = VP8_BRC_SINGLE_PASS;
2226
2227     vp8_context->num_passes = 0;
2228     vp8_context->min_pak_passes = 1;
2229     vp8_context->repak_pass_iter_val = 0;
2230
2231     if (encoder_context->quality_level == ENCODER_DEFAULT_QUALITY) {
2232         vp8_context->num_passes = 1;
2233         vp8_context->min_pak_passes = 2;
2234     } else if (encoder_context->quality_level == ENCODER_LOW_QUALITY) {
2235         vp8_context->num_passes = 0;
2236         vp8_context->min_pak_passes = 1;
2237     } else {
2238         vp8_context->num_passes = 0;
2239         vp8_context->min_pak_passes = 1;
2240     }
2241
2242     if (!vp8_context->repak_supported) {
2243         vp8_context->num_passes = 0;
2244         vp8_context->min_pak_passes = 1;
2245     }
2246
2247     if (brc_enabled)
2248         vp8_context->num_passes += (vp8_context->num_brc_pak_passes - 1);
2249
2250     if (vp8_context->repak_supported && vp8_context->min_pak_passes > 1)
2251         vp8_context->repak_pass_iter_val = vp8_context->num_passes;
2252 }
2253
2254 static void
2255 i965_encoder_vp8_get_misc_parameters(VADriverContextP ctx,
2256                                      struct encode_state *encode_state,
2257                                      struct intel_encoder_context *encoder_context)
2258 {
2259     struct i965_encoder_vp8_context *vp8_context = encoder_context->vme_context;
2260
2261     if (vp8_context->internal_rate_mode == I965_BRC_CQP) {
2262         vp8_context->init_vbv_buffer_fullness_in_bit = 0;
2263         vp8_context->vbv_buffer_size_in_bit = 0;
2264         vp8_context->target_bit_rate = 0;
2265         vp8_context->max_bit_rate = 0;
2266         vp8_context->min_bit_rate = 0;
2267         vp8_context->brc_need_reset = 0;
2268     } else {
2269         vp8_context->gop_size = encoder_context->brc.gop_size;
2270
2271         if (encoder_context->brc.need_reset) {
2272             vp8_context->framerate = encoder_context->brc.framerate[0];
2273             vp8_context->vbv_buffer_size_in_bit = encoder_context->brc.hrd_buffer_size;
2274             vp8_context->init_vbv_buffer_fullness_in_bit = encoder_context->brc.hrd_initial_buffer_fullness;
2275             vp8_context->max_bit_rate = encoder_context->brc.bits_per_second[0]; // currently only one layer is supported
2276             vp8_context->brc_need_reset = (vp8_context->brc_initted && encoder_context->brc.need_reset);
2277
2278             if (vp8_context->internal_rate_mode == I965_BRC_CBR) {
2279                 vp8_context->min_bit_rate = vp8_context->max_bit_rate;
2280                 vp8_context->target_bit_rate = vp8_context->max_bit_rate;
2281             } else {
2282                 assert(vp8_context->internal_rate_mode == I965_BRC_VBR);
2283
2284                 if (encoder_context->brc.target_percentage[0] <= 50)
2285                     vp8_context->min_bit_rate = 0;
2286                 else
2287                     vp8_context->min_bit_rate = vp8_context->max_bit_rate * (2 * encoder_context->brc.target_percentage[0] - 100) / 100;
2288
2289                 vp8_context->target_bit_rate = vp8_context->max_bit_rate * encoder_context->brc.target_percentage[0] / 100;
2290             }
2291         }
2292     }
2293
2294     if (encoder_context->quality_level == ENCODER_LOW_QUALITY)
2295         vp8_context->hme_16x_supported = 0;
2296 }
2297
2298 static VAStatus
2299 i965_encoder_vp8_get_paramters(VADriverContextP ctx,
2300                                struct encode_state *encode_state,
2301                                struct intel_encoder_context *encoder_context)
2302 {
2303     VAQMatrixBufferVP8 *quant_params = (VAQMatrixBufferVP8 *)encode_state->q_matrix->buffer;
2304     struct i965_encoder_vp8_surface *vp8_surface;
2305
2306     i965_encoder_vp8_update_internal_rc_mode(ctx, encode_state, encoder_context);
2307     i965_encoder_vp8_get_sequence_parameter(ctx, encode_state, encoder_context);
2308     i965_encoder_vp8_get_misc_parameters(ctx, encode_state, encoder_context);
2309     i965_encoder_vp8_get_picture_parameter(ctx, encode_state, encoder_context);
2310
2311     i965_encoder_vp8_allocate_surfaces(ctx, encoder_context, encode_state->reconstructed_object, 1);
2312     vp8_surface = encode_state->reconstructed_object->private_data;
2313     vp8_surface->qp_index = quant_params->quantization_index[0];
2314
2315     return VA_STATUS_SUCCESS;
2316 }
2317
2318 static VAStatus
2319 i965_encoder_vp8_vme_gpe_kernel_init(VADriverContextP ctx,
2320                                      struct encode_state *encode_state,
2321                                      struct intel_encoder_context *encoder_context)
2322 {
2323     struct i965_driver_data *i965 = i965_driver_data(ctx);
2324     struct i965_encoder_vp8_context *vp8_context = encoder_context->vme_context;
2325     struct i965_gpe_table *gpe = vp8_context->gpe_table;
2326     struct i965_encoder_vp8_mbenc_context *mbenc_context = &vp8_context->mbenc_context;
2327     struct i965_encoder_vp8_mpu_context *mpu_context = &vp8_context->mpu_context;
2328     struct i965_encoder_vp8_tpu_context *tpu_context = &vp8_context->tpu_context;
2329     struct gpe_dynamic_state_parameter ds_param;
2330     int i;
2331
2332     /*
2333      * BRC will update MBEnc curbe data buffer, so initialize GPE context for
2334      * MBEnc first
2335      */
2336     for (i = 0; i < NUM_VP8_MBENC; i++) {
2337         gpe->context_init(ctx, &mbenc_context->gpe_contexts[i]);
2338     }
2339
2340     /*
2341      * VP8_MBENC_I_FRAME_LUMA and VP8_MBENC_I_FRAME_CHROMA will use the same
2342      * the dynamic state buffer,
2343      */
2344     ds_param.bo_size = ALIGN(MAX(sizeof(struct vp8_mbenc_i_frame_curbe_data), sizeof(struct vp8_mbenc_p_frame_curbe_data)), 64) +
2345         vp8_context->idrt_entry_size * 2;
2346     mbenc_context->luma_chroma_dynamic_buffer = dri_bo_alloc(i965->intel.bufmgr,
2347                                                              "IFrame Luma & CHROMA curbe buffer",
2348                                                              ds_param.bo_size,
2349                                                              0x1000);
2350
2351     /*
2352      * VP8_MBENC_I_FRAME_LUMA and VP8_MBENC_I_FRAME_CHROMA will share the same
2353      * the curbe data buffer
2354      */
2355     ds_param.bo = mbenc_context->luma_chroma_dynamic_buffer;
2356     ds_param.curbe_offset = 0;
2357     ds_param.idrt_offset = ALIGN(MAX(sizeof(struct vp8_mbenc_i_frame_curbe_data), sizeof(struct vp8_mbenc_p_frame_curbe_data)), 64);
2358     ds_param.sampler_offset = ds_param.bo_size;
2359     gpe->set_dynamic_buffer(ctx, &mbenc_context->gpe_contexts[VP8_MBENC_I_FRAME_LUMA], &ds_param);
2360
2361     ds_param.idrt_offset = ds_param.idrt_offset + vp8_context->idrt_entry_size;
2362     gpe->set_dynamic_buffer(ctx, &mbenc_context->gpe_contexts[VP8_MBENC_I_FRAME_CHROMA], &ds_param);
2363
2364     /*
2365      * BRC will update MPU curbe data buffer, so initialize GPE context for
2366      * MPU first
2367      */
2368     gpe->context_init(ctx, &mpu_context->gpe_contexts[0]);
2369     ds_param.bo_size = ALIGN(sizeof(struct vp8_mpu_curbe_data), 64) + vp8_context->idrt_entry_size;
2370     mpu_context->dynamic_buffer = dri_bo_alloc(i965->intel.bufmgr,
2371                                                "MPU dynamic buffer",
2372                                                ds_param.bo_size,
2373                                                0x1000);
2374
2375     ds_param.bo = mpu_context->dynamic_buffer;
2376     ds_param.curbe_offset = 0;
2377     ds_param.idrt_offset = ALIGN(sizeof(struct vp8_mpu_curbe_data), 64);
2378     ds_param.sampler_offset = ds_param.bo_size;
2379     gpe->set_dynamic_buffer(ctx, &mpu_context->gpe_contexts[0], &ds_param);
2380
2381     /*
2382      * BRC will update TPU curbe data buffer, so initialize GPE context for
2383      * TPU first
2384      */
2385     gpe->context_init(ctx, &tpu_context->gpe_contexts[0]);
2386     ds_param.bo_size = ALIGN(sizeof(struct vp8_tpu_curbe_data), 64) + vp8_context->idrt_entry_size;
2387     tpu_context->dynamic_buffer = dri_bo_alloc(i965->intel.bufmgr,
2388                                                "MPU dynamic buffer",
2389                                                ds_param.bo_size,
2390                                                0x1000);
2391
2392     ds_param.bo = tpu_context->dynamic_buffer;
2393     ds_param.curbe_offset = 0;
2394     ds_param.idrt_offset = ALIGN(sizeof(struct vp8_tpu_curbe_data), 64);
2395     ds_param.sampler_offset = ds_param.bo_size;
2396     gpe->set_dynamic_buffer(ctx, &tpu_context->gpe_contexts[0], &ds_param);
2397
2398     return VA_STATUS_SUCCESS;
2399 }
2400
2401 static void
2402 i965_encoder_vp8_vme_brc_init_reset_set_curbe(VADriverContextP ctx,
2403                                               struct encode_state *encode_state,
2404                                               struct intel_encoder_context *encoder_context,
2405                                               struct i965_gpe_context *gpe_context)
2406 {
2407     struct i965_encoder_vp8_context *vp8_context = encoder_context->vme_context;
2408     VAEncPictureParameterBufferVP8 *pic_param = (VAEncPictureParameterBufferVP8 *)encode_state->pic_param_ext->buffer;
2409     struct vp8_brc_init_reset_curbe_data *pcmd = i965_gpe_context_map_curbe(gpe_context);
2410     double input_bits_per_frame, bps_ratio;
2411
2412     if (!pcmd)
2413         return;
2414
2415     memset(pcmd, 0, sizeof(*pcmd));
2416
2417     pcmd->dw0.profile_level_max_frame = vp8_context->frame_width * vp8_context->frame_height;
2418     pcmd->dw1.init_buf_full_in_bits = vp8_context->init_vbv_buffer_fullness_in_bit;
2419     pcmd->dw2.buf_size_in_bits = vp8_context->vbv_buffer_size_in_bit;
2420     pcmd->dw3.average_bitrate = (vp8_context->target_bit_rate + VP8_BRC_KBPS - 1) / VP8_BRC_KBPS * VP8_BRC_KBPS;
2421     pcmd->dw4.max_bitrate = (vp8_context->max_bit_rate + VP8_BRC_KBPS - 1) / VP8_BRC_KBPS * VP8_BRC_KBPS;
2422     pcmd->dw6.frame_rate_m = vp8_context->framerate.num;
2423     pcmd->dw7.frame_rate_d = vp8_context->framerate.den;
2424     pcmd->dw8.brc_flag = 0;
2425     pcmd->dw8.gop_minus1 = vp8_context->gop_size - 1;
2426
2427     if (vp8_context->internal_rate_mode == I965_BRC_CBR) {
2428         pcmd->dw4.max_bitrate = pcmd->dw3.average_bitrate;
2429
2430         pcmd->dw8.brc_flag = pcmd->dw8.brc_flag | BRC_KERNEL_CBR;
2431     } else if (vp8_context->internal_rate_mode == I965_BRC_VBR) {
2432         if (pcmd->dw4.max_bitrate < pcmd->dw3.average_bitrate) {
2433             pcmd->dw4.max_bitrate = 2 * pcmd->dw3.average_bitrate;
2434         }
2435
2436         pcmd->dw8.brc_flag = pcmd->dw8.brc_flag | BRC_KERNEL_VBR;
2437     }
2438
2439     input_bits_per_frame =
2440         ((double)(pcmd->dw4.max_bitrate) * (double)(pcmd->dw7.frame_rate_d) /
2441          (double)(pcmd->dw6.frame_rate_m));
2442
2443     if (pcmd->dw2.buf_size_in_bits < (unsigned int)input_bits_per_frame * 4) {
2444         pcmd->dw2.buf_size_in_bits = (unsigned int)input_bits_per_frame * 4;
2445     }
2446
2447     if (pcmd->dw1.init_buf_full_in_bits == 0) {
2448         pcmd->dw1.init_buf_full_in_bits = 7 * pcmd->dw2.buf_size_in_bits / 8;
2449     }
2450
2451     if (pcmd->dw1.init_buf_full_in_bits < (unsigned int)(input_bits_per_frame * 2)) {
2452         pcmd->dw1.init_buf_full_in_bits = (unsigned int)(input_bits_per_frame * 2);
2453     }
2454
2455     if (pcmd->dw1.init_buf_full_in_bits > pcmd->dw2.buf_size_in_bits) {
2456         pcmd->dw1.init_buf_full_in_bits = pcmd->dw2.buf_size_in_bits;
2457     }
2458
2459     bps_ratio = input_bits_per_frame / ((double)(pcmd->dw2.buf_size_in_bits) / 30);
2460     bps_ratio = (bps_ratio < 0.1) ? 0.1 : (bps_ratio > 3.5) ? 3.5 : bps_ratio;
2461
2462     pcmd->dw9.frame_width_in_bytes = vp8_context->frame_width;
2463     pcmd->dw10.frame_height_in_bytes = vp8_context->frame_height;
2464     pcmd->dw10.avbr_accuracy = 30;
2465     pcmd->dw11.avbr_convergence = 150;
2466     pcmd->dw11.min_qp = pic_param->clamp_qindex_low;
2467     pcmd->dw12.max_qp = pic_param->clamp_qindex_high;
2468     pcmd->dw12.level_qp = 60;
2469
2470     // DW13 default 100
2471     pcmd->dw13.max_section_pct = 100;
2472     pcmd->dw13.under_shoot_cbr_pct = 115;
2473
2474     // DW14 default 100
2475     pcmd->dw14.min_section_pct = 100;
2476     pcmd->dw14.vbr_bias_pct = 100;
2477     pcmd->dw15.instant_rate_threshold_0_for_p = 30;
2478     pcmd->dw15.instant_rate_threshold_1_for_p = 50;
2479     pcmd->dw15.instant_rate_threshold_2_for_p = 70;
2480     pcmd->dw15.instant_rate_threshold_3_for_p = 120;
2481
2482     pcmd->dw17.instant_rate_threshold_0_for_i = 30;
2483     pcmd->dw17.instant_rate_threshold_1_for_i = 50;
2484     pcmd->dw17.instant_rate_threshold_2_for_i = 90;
2485     pcmd->dw17.instant_rate_threshold_3_for_i = 115;
2486     pcmd->dw18.deviation_threshold_0_for_p = (unsigned int)(-50 * pow(0.9, bps_ratio));
2487     pcmd->dw18.deviation_threshold_1_for_p = (unsigned int)(-50 * pow(0.66, bps_ratio));
2488     pcmd->dw18.deviation_threshold_2_for_p = (unsigned int)(-50 * pow(0.46, bps_ratio));
2489     pcmd->dw18.deviation_threshold_3_for_p = (unsigned int)(-50 * pow(0.3, bps_ratio));
2490     pcmd->dw19.deviation_threshold_4_for_p = (unsigned int)(50 * pow(0.3, bps_ratio));
2491     pcmd->dw19.deviation_threshold_5_for_p = (unsigned int)(50 * pow(0.46, bps_ratio));
2492     pcmd->dw19.deviation_threshold_6_for_p = (unsigned int)(50 * pow(0.7, bps_ratio));
2493     pcmd->dw19.deviation_threshold_7_for_p = (unsigned int)(50 * pow(0.9, bps_ratio));
2494     pcmd->dw20.deviation_threshold_0_for_vbr = (unsigned int)(-50 * pow(0.9, bps_ratio));
2495     pcmd->dw20.deviation_threshold_1_for_vbr = (unsigned int)(-50 * pow(0.7, bps_ratio));
2496     pcmd->dw20.deviation_threshold_2_for_vbr = (unsigned int)(-50 * pow(0.5, bps_ratio));
2497     pcmd->dw20.deviation_threshold_3_for_vbr = (unsigned int)(-50 * pow(0.3, bps_ratio));
2498     pcmd->dw21.deviation_threshold_4_for_vbr = (unsigned int)(100 * pow(0.4, bps_ratio));
2499     pcmd->dw21.deviation_threshold_5_for_vbr = (unsigned int)(100 * pow(0.5, bps_ratio));
2500     pcmd->dw21.deviation_threshold_6_for_vbr = (unsigned int)(100 * pow(0.75, bps_ratio));
2501     pcmd->dw21.deviation_threshold_7_for_vbr = (unsigned int)(100 * pow(0.9, bps_ratio));
2502     pcmd->dw22.deviation_threshold_0_for_i = (unsigned int)(-50 * pow(0.8, bps_ratio));
2503     pcmd->dw22.deviation_threshold_1_for_i = (unsigned int)(-50 * pow(0.6, bps_ratio));
2504     pcmd->dw22.deviation_threshold_2_for_i = (unsigned int)(-50 * pow(0.34, bps_ratio));
2505     pcmd->dw22.deviation_threshold_3_for_i = (unsigned int)(-50 * pow(0.2, bps_ratio));
2506     pcmd->dw23.deviation_threshold_4_for_i = (unsigned int)(50 * pow(0.2, bps_ratio));
2507     pcmd->dw23.deviation_threshold_5_for_i = (unsigned int)(50 * pow(0.4, bps_ratio));
2508     pcmd->dw23.deviation_threshold_6_for_i = (unsigned int)(50 * pow(0.66, bps_ratio));
2509     pcmd->dw23.deviation_threshold_7_for_i = (unsigned int)(50 * pow(0.9, bps_ratio));
2510
2511     // Default: 1
2512     pcmd->dw24.num_t_levels = 1;
2513
2514     if (!vp8_context->brc_initted) {
2515         vp8_context->brc_init_current_target_buf_full_in_bits = pcmd->dw1.init_buf_full_in_bits;
2516     }
2517
2518     vp8_context->brc_init_reset_buf_size_in_bits = pcmd->dw2.buf_size_in_bits;
2519     vp8_context->brc_init_reset_input_bits_per_frame = input_bits_per_frame;
2520
2521     pcmd->dw26.history_buffer_bti = VP8_BTI_BRC_INIT_RESET_HISTORY;
2522     pcmd->dw27.distortion_buffer_bti = VP8_BTI_BRC_INIT_RESET_DISTORTION;
2523
2524     i965_gpe_context_unmap_curbe(gpe_context);
2525 }
2526
2527 static void
2528 i965_encoder_vp8_vme_brc_init_reset_add_surfaces(VADriverContextP ctx,
2529                                                  struct encode_state *encode_state,
2530                                                  struct intel_encoder_context *encoder_context,
2531                                                  struct i965_gpe_context *gpe_context)
2532 {
2533     struct i965_encoder_vp8_context *vp8_context = encoder_context->vme_context;
2534
2535     i965_add_buffer_gpe_surface(ctx,
2536                                 encoder_context,
2537                                 gpe_context,
2538                                 &vp8_context->brc_history_buffer,
2539                                 0,
2540                                 vp8_context->brc_history_buffer.size,
2541                                 0,
2542                                 VP8_BTI_BRC_INIT_RESET_HISTORY);
2543
2544     i965_add_buffer_2d_gpe_surface(ctx,
2545                                    encoder_context,
2546                                    gpe_context,
2547                                    &vp8_context->brc_distortion_buffer,
2548                                    1,
2549                                    I965_SURFACEFORMAT_R8_UNORM,
2550                                    VP8_BTI_BRC_INIT_RESET_DISTORTION);
2551 }
2552
2553 static VAStatus
2554 i965_encoder_vp8_vme_brc_init_reset(VADriverContextP ctx,
2555                                     struct encode_state *encode_state,
2556                                     struct intel_encoder_context *encoder_context)
2557 {
2558     struct i965_encoder_vp8_context *vp8_context = encoder_context->vme_context;
2559     struct i965_encoder_vp8_brc_init_reset_context *init_reset_context = &vp8_context->brc_init_reset_context;
2560     struct i965_gpe_table *gpe = vp8_context->gpe_table;
2561     struct gpe_media_object_parameter media_object_param;
2562     struct i965_gpe_context *gpe_context;
2563     int gpe_index = VP8_BRC_INIT;
2564     int media_function = VP8_MEDIA_STATE_BRC_INIT_RESET;
2565
2566     if (vp8_context->brc_initted)
2567         gpe_index = VP8_BRC_RESET;
2568
2569     gpe_context = &init_reset_context->gpe_contexts[gpe_index];
2570
2571     gpe->context_init(ctx, gpe_context);
2572     gpe->reset_binding_table(ctx, gpe_context);
2573     i965_encoder_vp8_vme_brc_init_reset_set_curbe(ctx, encode_state, encoder_context, gpe_context);
2574     i965_encoder_vp8_vme_brc_init_reset_add_surfaces(ctx, encode_state, encoder_context, gpe_context);
2575     gpe->setup_interface_data(ctx, gpe_context);
2576
2577     memset(&media_object_param, 0, sizeof(media_object_param));
2578     i965_run_kernel_media_object(ctx, encoder_context, gpe_context, media_function, &media_object_param);
2579
2580     return VA_STATUS_SUCCESS;
2581 }
2582
2583 static void
2584 i965_encoder_vp8_vme_scaling_set_curbe(VADriverContextP ctx,
2585                                        struct encode_state *encode_state,
2586                                        struct intel_encoder_context *encoder_context,
2587                                        struct i965_gpe_context *gpe_context,
2588                                        struct scaling_curbe_parameters *params)
2589 {
2590     struct vp8_scaling_curbe_data *pcmd = i965_gpe_context_map_curbe(gpe_context);
2591
2592     if (!pcmd)
2593         return;
2594
2595     memset(pcmd, 0, sizeof(*pcmd));
2596
2597     pcmd->dw0.input_picture_width = params->input_picture_width;
2598     pcmd->dw0.input_picture_height = params->input_picture_height;
2599
2600     if (!params->is_field_picture) {
2601         pcmd->dw1.input_y_bti_frame = VP8_BTI_SCALING_FRAME_SRC_Y;
2602         pcmd->dw2.output_y_bti_frame = VP8_BTI_SCALING_FRAME_DST_Y;
2603     } else {
2604         pcmd->dw1.input_y_bti_top_field = VP8_BTI_SCALING_FIELD_TOP_SRC_Y;
2605         pcmd->dw2.output_y_bti_top_field = VP8_BTI_SCALING_FIELD_TOP_DST_Y;
2606         pcmd->dw3.input_y_bti_bottom_field = VP8_BTI_SCALING_FIELD_BOT_SRC_Y;
2607         pcmd->dw4.output_y_bti_bottom_field = VP8_BTI_SCALING_FIELD_BOT_DST_Y;
2608     }
2609
2610     if (params->flatness_check_enabled) {
2611         pcmd->dw5.flatness_threshold = 128;
2612         pcmd->dw6.enable_mb_flatness_check = 1;
2613
2614         if (!params->is_field_picture) {
2615             pcmd->dw8.flatness_output_bti_frame = VP8_BTI_SCALING_FRAME_FLATNESS_DST;
2616         } else {
2617             pcmd->dw8.flatness_output_bti_top_field = VP8_BTI_SCALING_FIELD_TOP_FLATNESS_DST;
2618             pcmd->dw9.flatness_output_bti_bottom_field = VP8_BTI_SCALING_FIELD_BOT_FLATNESS_DST;
2619         }
2620     } else {
2621         pcmd->dw6.enable_mb_flatness_check = 0;
2622     }
2623
2624     pcmd->dw6.enable_mb_variance_output = params->mb_variance_output_enabled;
2625     pcmd->dw6.enable_mb_pixel_average_output = params->mb_pixel_average_output_enabled;
2626
2627     if (params->mb_variance_output_enabled || params->mb_pixel_average_output_enabled) {
2628         if (!params->is_field_picture) {
2629             pcmd->dw10.mbv_proc_stats_bti_frame = VP8_BTI_SCALING_FRAME_MBVPROCSTATS_DST;
2630         } else {
2631             pcmd->dw10.mbv_proc_stats_bti_top_field = VP8_BTI_SCALING_FIELD_TOP_MBVPROCSTATS_DST;
2632             pcmd->dw11.mbv_proc_stats_bti_bottom_field = VP8_BTI_SCALING_FIELD_BOT_MBVPROCSTATS_DST;
2633         }
2634     }
2635
2636     i965_gpe_context_unmap_curbe(gpe_context);
2637 }
2638
2639 static void
2640 i965_encoder_vp8_vme_scaling_add_surfaces(VADriverContextP ctx,
2641                                           struct encode_state *encode_state,
2642                                           struct intel_encoder_context *encoder_context,
2643                                           struct i965_gpe_context *gpe_context,
2644                                           struct scaling_surface_parameters *params)
2645 {
2646     i965_add_2d_gpe_surface(ctx,
2647                             encoder_context,
2648                             gpe_context,
2649                             params->input_obj_surface,
2650                             0,
2651                             1,
2652                             I965_SURFACEFORMAT_R32_UNORM,
2653                             VP8_BTI_SCALING_FRAME_SRC_Y);
2654     i965_add_2d_gpe_surface(ctx,
2655                             encoder_context,
2656                             gpe_context,
2657                             params->output_obj_surface,
2658                             0,
2659                             1,
2660                             I965_SURFACEFORMAT_R32_UNORM,
2661                             VP8_BTI_SCALING_FRAME_DST_Y);
2662 }
2663
2664 static VAStatus
2665 i965_encoder_vp8_vme_scaling(VADriverContextP ctx,
2666                              struct encode_state *encode_state,
2667                              struct intel_encoder_context *encoder_context,
2668                              int scaling_16x_enabled)
2669 {
2670     struct i965_encoder_vp8_context *vp8_context = encoder_context->vme_context;
2671     struct i965_encoder_vp8_scaling_context *scaling_context = &vp8_context->scaling_context;
2672     struct i965_gpe_table *gpe = vp8_context->gpe_table;
2673     struct gpe_media_object_walker_parameter media_object_walker_param;
2674     struct i965_gpe_context *gpe_context;
2675     struct scaling_curbe_parameters scaling_curbe_params;
2676     struct scaling_surface_parameters scaling_surface_params;
2677     struct vp8_encoder_kernel_walker_parameter kernel_walker_param;
2678     struct object_surface *input_obj_surface, *output_obj_surface;
2679     struct i965_encoder_vp8_surface *vp8_surface;
2680     unsigned int input_frame_width, input_frame_height, output_frame_width, output_frame_height;
2681     unsigned int down_scaled_width_in_mbs, down_scaled_height_in_mbs;
2682     int gpe_index, media_function;
2683
2684     vp8_surface = encode_state->reconstructed_object->private_data;
2685
2686     if (scaling_16x_enabled) {
2687         gpe_index = VP8_SCALING_16X;
2688         media_function = VP8_MEDIA_STATE_16X_SCALING;
2689
2690         down_scaled_width_in_mbs = vp8_context->down_scaled_width_in_mb16x;
2691         down_scaled_height_in_mbs = vp8_context->down_scaled_height_in_mb16x;
2692
2693         input_obj_surface = vp8_surface->scaled_4x_surface_obj;
2694         input_frame_width = vp8_context->down_scaled_width_4x;
2695         input_frame_height = vp8_context->down_scaled_height_4x;
2696
2697         output_obj_surface = vp8_surface->scaled_16x_surface_obj;
2698         output_frame_width = vp8_context->down_scaled_width_16x;
2699         output_frame_height = vp8_context->down_scaled_height_16x;
2700     } else {
2701         gpe_index = VP8_SCALING_4X;
2702         media_function = VP8_MEDIA_STATE_4X_SCALING;
2703
2704         down_scaled_width_in_mbs = vp8_context->down_scaled_width_in_mb4x;
2705         down_scaled_height_in_mbs = vp8_context->down_scaled_height_in_mb4x;
2706
2707         input_obj_surface = encode_state->input_yuv_object;
2708         input_frame_width = vp8_context->picture_width;         /* the orignal width */
2709         input_frame_height = vp8_context->picture_height;       /* the orignal height */
2710
2711         output_obj_surface = vp8_surface->scaled_4x_surface_obj;
2712         output_frame_width = vp8_context->down_scaled_width_4x;
2713         output_frame_height = vp8_context->down_scaled_height_4x;
2714     }
2715
2716     gpe_context = &scaling_context->gpe_contexts[gpe_index];
2717
2718     gpe->context_init(ctx, gpe_context);
2719     gpe->reset_binding_table(ctx, gpe_context);
2720
2721     memset(&scaling_curbe_params, 0, sizeof(scaling_curbe_params));
2722     scaling_curbe_params.input_picture_width = input_frame_width;
2723     scaling_curbe_params.input_picture_height = input_frame_height;
2724     scaling_curbe_params.is_field_picture = 0;
2725     scaling_curbe_params.flatness_check_enabled = 0;
2726     scaling_curbe_params.mb_variance_output_enabled = 0;
2727     scaling_curbe_params.mb_pixel_average_output_enabled = 0;
2728     i965_encoder_vp8_vme_scaling_set_curbe(ctx, encode_state, encoder_context, gpe_context, &scaling_curbe_params);
2729
2730     scaling_surface_params.input_obj_surface = input_obj_surface;
2731     scaling_surface_params.input_width = input_frame_width;
2732     scaling_surface_params.input_height = input_frame_height;
2733     scaling_surface_params.output_obj_surface = output_obj_surface;
2734     scaling_surface_params.output_width = output_frame_width;
2735     scaling_surface_params.output_height = output_frame_height;
2736     i965_encoder_vp8_vme_scaling_add_surfaces(ctx, encode_state, encoder_context, gpe_context, &scaling_surface_params);
2737
2738     gpe->setup_interface_data(ctx, gpe_context);
2739
2740     memset(&kernel_walker_param, 0, sizeof(kernel_walker_param));
2741     kernel_walker_param.resolution_x = down_scaled_width_in_mbs * 2; /* 8x8 level */
2742     kernel_walker_param.resolution_y = down_scaled_height_in_mbs * 2;
2743     kernel_walker_param.no_dependency = 1;
2744     i965_init_media_object_walker_parameters(encoder_context, &kernel_walker_param, &media_object_walker_param);
2745
2746     i965_run_kernel_media_object_walker(ctx, encoder_context, gpe_context, media_function, &media_object_walker_param);
2747
2748     return VA_STATUS_SUCCESS;
2749 }
2750
2751 static void
2752 i965_encoder_vp8_vme_me_set_curbe(VADriverContextP ctx,
2753                                   struct encode_state *encode_state,
2754                                   struct intel_encoder_context *encoder_context,
2755                                   struct i965_gpe_context *gpe_context,
2756                                   struct me_curbe_parameters *params)
2757 {
2758     struct i965_encoder_vp8_context *vp8_context = encoder_context->vme_context;
2759     struct vp8_me_curbe_data *pcmd = i965_gpe_context_map_curbe(gpe_context);
2760     int me_mode, me_method;
2761
2762     if (!pcmd)
2763         return;
2764
2765     if (vp8_context->hme_16x_enabled) {
2766         if (params->use_16x_me)
2767             me_mode = VP8_ME_MODE_ME16X_BEFORE_ME4X;
2768         else
2769             me_mode = VP8_ME_MODE_ME4X_AFTER_ME16X;
2770     } else {
2771         me_mode = VP8_ME_MODE_ME4X_ONLY;
2772     }
2773
2774     memset(pcmd, 0, sizeof(*pcmd));
2775
2776     pcmd->dw1.max_num_mvs = 0x10;
2777     pcmd->dw1.bi_weight = 0;
2778
2779     pcmd->dw2.max_num_su = 57;
2780     pcmd->dw2.max_len_sp = 57;
2781
2782     pcmd->dw3.sub_mb_part_mask = 0x77;
2783     pcmd->dw3.inter_sad = 0;
2784     pcmd->dw3.intra_sad = 0;
2785     pcmd->dw3.bme_disable_fbr = 1;
2786     pcmd->dw3.sub_pel_mode = 3;
2787
2788     pcmd->dw4.picture_height_minus1 = params->down_scaled_height_in_mbs - 1;
2789     pcmd->dw4.picture_width = params->down_scaled_width_in_mbs;
2790
2791     if (pcmd->dw4.picture_height_minus1 < 2)
2792         pcmd->dw4.picture_height_minus1 = 2;
2793
2794     if (pcmd->dw4.picture_width < 3)
2795         pcmd->dw4.picture_width = 3;
2796
2797     pcmd->dw5.ref_height = 40;
2798     pcmd->dw5.ref_width = 48;
2799
2800     pcmd->dw6.me_mode = me_mode;
2801
2802     if (encoder_context->quality_level == ENCODER_DEFAULT_QUALITY)
2803         pcmd->dw6.super_combine_dist = 5;
2804     else if (encoder_context->quality_level == ENCODER_LOW_QUALITY)
2805         pcmd->dw6.super_combine_dist = 0;
2806     else
2807         pcmd->dw6.super_combine_dist = 1;
2808
2809     pcmd->dw6.max_vmv_range = 0x7fc;
2810
2811     pcmd->dw13.num_ref_idx_l0_minus1 = vp8_num_refs[vp8_context->ref_frame_ctrl] - 1;
2812     pcmd->dw13.num_ref_idx_l1_minus1 = 0;
2813
2814     me_method = (encoder_context->quality_level == ENCODER_DEFAULT_QUALITY) ? 6 : 4;
2815     memcpy(&pcmd->dw16, vp8_search_path[me_method], 14 * sizeof(pcmd->dw16));
2816
2817     pcmd->dw32.vp8_me_mv_output_data_bti = VP8_BTI_ME_MV_DATA;
2818     pcmd->dw33.vp8_me_mv_input_data_bti = VP8_BTI_16X_ME_MV_DATA;
2819     pcmd->dw34.vp8_me_distorion_bti = VP8_BTI_ME_DISTORTION;
2820     pcmd->dw35.vp8_me_min_dist_brc_bti = VP8_BTI_ME_MIN_DIST_BRC_DATA;
2821     pcmd->dw36.vp8_me_forward_ref_bti = VP8_BTI_VME_INTER_PRED;
2822
2823     i965_gpe_context_unmap_curbe(gpe_context);
2824 }
2825
2826 static void
2827 i965_encoder_vp8_vme_me_add_surfaces(VADriverContextP ctx,
2828                                      struct encode_state *encode_state,
2829                                      struct intel_encoder_context *encoder_context,
2830                                      struct i965_gpe_context *gpe_context,
2831                                      struct me_surface_parameters *params)
2832 {
2833     struct i965_encoder_vp8_context *vp8_context = encoder_context->vme_context;
2834     struct i965_encoder_vp8_surface *vp8_surface;
2835     struct i965_gpe_resource *me_gpe_buffer, *me_brc_distortion_buffer;
2836     struct object_surface *obj_surface;
2837     unsigned char brc_enabled = (vp8_context->internal_rate_mode == I965_BRC_CBR ||
2838                                  vp8_context->internal_rate_mode == I965_BRC_VBR);
2839
2840     if (brc_enabled)
2841         me_brc_distortion_buffer = &vp8_context->brc_distortion_buffer;
2842     else
2843         me_brc_distortion_buffer = &vp8_context->me_4x_distortion_buffer;
2844
2845     if (params->use_16x_me) {
2846         me_gpe_buffer = &vp8_context->me_16x_mv_data_buffer;
2847     } else {
2848         me_gpe_buffer = &vp8_context->me_4x_mv_data_buffer;
2849     }
2850
2851     i965_add_buffer_2d_gpe_surface(ctx,
2852                                    encoder_context,
2853                                    gpe_context,
2854                                    me_gpe_buffer,
2855                                    1,
2856                                    I965_SURFACEFORMAT_R8_UNORM,
2857                                    VP8_BTI_ME_MV_DATA);
2858
2859     if (vp8_context->hme_16x_enabled) {
2860         me_gpe_buffer = &vp8_context->me_16x_mv_data_buffer;
2861         i965_add_buffer_2d_gpe_surface(ctx,
2862                                        encoder_context,
2863                                        gpe_context,
2864                                        me_gpe_buffer,
2865                                        1,
2866                                        I965_SURFACEFORMAT_R8_UNORM,
2867                                        VP8_BTI_16X_ME_MV_DATA);
2868     }
2869
2870     if (!params->use_16x_me) {
2871         me_gpe_buffer = &vp8_context->me_4x_distortion_buffer;
2872         i965_add_buffer_2d_gpe_surface(ctx,
2873                                        encoder_context,
2874                                        gpe_context,
2875                                        me_gpe_buffer,
2876                                        1,
2877                                        I965_SURFACEFORMAT_R8_UNORM,
2878                                        VP8_BTI_ME_DISTORTION);
2879
2880         me_gpe_buffer = me_brc_distortion_buffer;
2881         i965_add_buffer_2d_gpe_surface(ctx,
2882                                        encoder_context,
2883                                        gpe_context,
2884                                        me_gpe_buffer,
2885                                        1,
2886                                        I965_SURFACEFORMAT_R8_UNORM,
2887                                        VP8_BTI_ME_MIN_DIST_BRC_DATA);
2888     }
2889
2890     vp8_surface = encode_state->reconstructed_object->private_data;
2891     assert(vp8_surface);
2892
2893     if (params->use_16x_me) {
2894         obj_surface = vp8_surface->scaled_16x_surface_obj;
2895     } else {
2896         obj_surface = vp8_surface->scaled_4x_surface_obj;
2897     }
2898
2899     i965_add_adv_gpe_surface(ctx,
2900                              encoder_context,
2901                              gpe_context,
2902                              obj_surface,
2903                              VP8_BTI_VME_INTER_PRED);
2904
2905     if (vp8_context->ref_last_frame != NULL &&
2906         vp8_context->ref_last_frame->bo != NULL) {
2907         vp8_surface = vp8_context->ref_last_frame->private_data;
2908         obj_surface = NULL;
2909
2910         if (vp8_surface) {
2911             if (params->use_16x_me) {
2912                 obj_surface = vp8_surface->scaled_16x_surface_obj;
2913             } else {
2914                 obj_surface = vp8_surface->scaled_4x_surface_obj;
2915             }
2916         }
2917
2918         if (obj_surface) {
2919             i965_add_adv_gpe_surface(ctx,
2920                                      encoder_context,
2921                                      gpe_context,
2922                                      obj_surface,
2923                                      VP8_BTI_ME_REF1_PIC);
2924         }
2925     }
2926
2927     if (vp8_context->ref_gf_frame != NULL &&
2928         vp8_context->ref_gf_frame->bo != NULL) {
2929         vp8_surface = vp8_context->ref_gf_frame->private_data;
2930         obj_surface = NULL;
2931
2932         if (vp8_surface) {
2933             if (params->use_16x_me) {
2934                 obj_surface = vp8_surface->scaled_16x_surface_obj;
2935             } else {
2936                 obj_surface = vp8_surface->scaled_4x_surface_obj;
2937             }
2938         }
2939
2940         if (obj_surface) {
2941             switch (vp8_context->ref_frame_ctrl) {
2942             case 2:
2943             case 6:
2944                 i965_add_adv_gpe_surface(ctx,
2945                                          encoder_context,
2946                                          gpe_context,
2947                                          obj_surface,
2948                                          VP8_BTI_ME_REF1_PIC);
2949                 break;
2950
2951             case 3:
2952             case 7:
2953                 i965_add_adv_gpe_surface(ctx,
2954                                          encoder_context,
2955                                          gpe_context,
2956                                          obj_surface,
2957                                          VP8_BTI_ME_REF2_PIC);
2958                 break;
2959             }
2960         }
2961     }
2962
2963     if (vp8_context->ref_arf_frame != NULL &&
2964         vp8_context->ref_arf_frame->bo != NULL) {
2965         vp8_surface = vp8_context->ref_arf_frame->private_data;
2966         obj_surface = NULL;
2967
2968         if (vp8_surface) {
2969             if (params->use_16x_me) {
2970                 obj_surface = vp8_surface->scaled_16x_surface_obj;
2971             } else {
2972                 obj_surface = vp8_surface->scaled_4x_surface_obj;
2973             }
2974         }
2975
2976         if (obj_surface) {
2977             switch (vp8_context->ref_frame_ctrl) {
2978             case 4:
2979                 i965_add_adv_gpe_surface(ctx,
2980                                          encoder_context,
2981                                          gpe_context,
2982                                          obj_surface,
2983                                          VP8_BTI_ME_REF1_PIC);
2984                 break;
2985
2986             case 5:
2987             case 6:
2988                 i965_add_adv_gpe_surface(ctx,
2989                                          encoder_context,
2990                                          gpe_context,
2991                                          obj_surface,
2992                                          VP8_BTI_ME_REF2_PIC);
2993                 break;
2994
2995             case 7:
2996                 i965_add_adv_gpe_surface(ctx,
2997                                          encoder_context,
2998                                          gpe_context,
2999                                          obj_surface,
3000                                          VP8_BTI_ME_REF3_PIC);
3001                 break;
3002             }
3003         }
3004     }
3005 }
3006
3007 static void
3008 i965_encoder_vp8_vme_init_brc_distorion_buffer(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
3009 {
3010     struct i965_encoder_vp8_context *vp8_context = encoder_context->vme_context;
3011
3012     i965_zero_gpe_resource(&vp8_context->brc_distortion_buffer);
3013 }
3014
3015 static VAStatus
3016 i965_encoder_vp8_vme_me(VADriverContextP ctx,
3017                         struct encode_state *encode_state,
3018                         struct intel_encoder_context *encoder_context,
3019                         int use_16x_me)
3020 {
3021     struct i965_encoder_vp8_context *vp8_context = encoder_context->vme_context;
3022     struct i965_encoder_vp8_me_context *me_context = &vp8_context->me_context;
3023     struct i965_gpe_table *gpe = vp8_context->gpe_table;
3024     struct gpe_media_object_walker_parameter media_object_walker_param;
3025     struct vp8_encoder_kernel_walker_parameter kernel_walker_params;
3026     struct me_curbe_parameters me_curbe_params;
3027     struct i965_gpe_context *gpe_context;
3028     struct me_surface_parameters me_surface_params;
3029     VAEncPictureParameterBufferVP8 *pic_param = (VAEncPictureParameterBufferVP8 *)encode_state->pic_param_ext->buffer;
3030     unsigned int down_scaled_width_in_mbs, down_scaled_height_in_mbs;
3031     unsigned int ref_frame_flag_final, ref_frame_flag;
3032     int gpe_index, media_function;
3033
3034     if (vp8_context->frame_type == MPEG_P_PICTURE) {
3035         ref_frame_flag = VP8_REF_FLAG_ALL;
3036
3037         if (pic_param->ref_last_frame == pic_param->ref_gf_frame) {
3038             ref_frame_flag &= ~VP8_REF_FLAG_GOLDEN;
3039         }
3040
3041         if (pic_param->ref_last_frame == pic_param->ref_arf_frame) {
3042             ref_frame_flag &= ~VP8_REF_FLAG_ALT;
3043         }
3044
3045         if (pic_param->ref_gf_frame == pic_param->ref_arf_frame) {
3046             ref_frame_flag &= ~VP8_REF_FLAG_ALT;
3047         }
3048     } else {
3049         ref_frame_flag = VP8_REF_FLAG_LAST;
3050     }
3051
3052     switch (vp8_context->ref_frame_ctrl) {
3053     case 0:
3054         ref_frame_flag_final = VP8_REF_FLAG_NONE;
3055         break;
3056
3057     case 1:
3058         ref_frame_flag_final = VP8_REF_FLAG_LAST;       // Last Ref only
3059         break;
3060
3061     case 2:
3062         ref_frame_flag_final = VP8_REF_FLAG_GOLDEN;     // Gold Ref only
3063         break;
3064
3065     case 4:
3066         ref_frame_flag_final = VP8_REF_FLAG_ALT;        // Alt Ref only
3067         break;
3068
3069     default:
3070         ref_frame_flag_final = ref_frame_flag;
3071     }
3072
3073     vp8_context->ref_frame_ctrl = ref_frame_flag_final;
3074     vp8_context->ref_ctrl_optimization_done = 1;
3075
3076     if (use_16x_me) {
3077         gpe_index = VP8_ME_16X;
3078         media_function = VP8_MEDIA_STATE_16X_ME;
3079         down_scaled_width_in_mbs = vp8_context->down_scaled_width_in_mb16x;
3080         down_scaled_height_in_mbs = vp8_context->down_scaled_height_in_mb16x;
3081     } else {
3082         gpe_index = VP8_ME_4X;
3083         media_function = VP8_MEDIA_STATE_4X_ME;
3084         down_scaled_width_in_mbs = vp8_context->down_scaled_width_in_mb4x;
3085         down_scaled_height_in_mbs = vp8_context->down_scaled_height_in_mb4x;
3086     }
3087
3088     gpe_context = &me_context->gpe_contexts[gpe_index];
3089
3090     gpe->context_init(ctx, gpe_context);
3091     gpe->reset_binding_table(ctx, gpe_context);
3092
3093     memset(&me_curbe_params, 0, sizeof(me_curbe_params));
3094     me_curbe_params.down_scaled_width_in_mbs = down_scaled_width_in_mbs;
3095     me_curbe_params.down_scaled_height_in_mbs = down_scaled_height_in_mbs;
3096     me_curbe_params.use_16x_me = use_16x_me;
3097     i965_encoder_vp8_vme_me_set_curbe(ctx, encode_state, encoder_context, gpe_context, &me_curbe_params);
3098
3099     if (vp8_context->brc_distortion_buffer_need_reset && !use_16x_me) {
3100         i965_encoder_vp8_vme_init_brc_distorion_buffer(ctx, encoder_context);
3101     }
3102
3103     memset(&me_surface_params, 0, sizeof(me_surface_params));
3104     me_surface_params.use_16x_me = use_16x_me;
3105     i965_encoder_vp8_vme_me_add_surfaces(ctx, encode_state, encoder_context, gpe_context, &me_surface_params);
3106
3107     gpe->setup_interface_data(ctx, gpe_context);
3108
3109     memset(&kernel_walker_params, 0, sizeof(kernel_walker_params));
3110     kernel_walker_params.resolution_x = down_scaled_width_in_mbs;
3111     kernel_walker_params.resolution_y = down_scaled_height_in_mbs;
3112     kernel_walker_params.no_dependency = 1;
3113     i965_init_media_object_walker_parameters(encoder_context, &kernel_walker_params, &media_object_walker_param);
3114
3115     i965_run_kernel_media_object_walker(ctx, encoder_context, gpe_context, media_function, &media_object_walker_param);
3116
3117     return VA_STATUS_SUCCESS;
3118 }
3119
3120 #define QUANT_INDEX(index, q_index, q_index_delta)                      \
3121     do {                                                                \
3122         index = quant_param->quantization_index[q_index] + quant_param->quantization_index_delta[q_index_delta]; \
3123         index = CLAMP(0, MAX_QP_VP8, index);                            \
3124     } while (0)
3125
3126 static void
3127 i965_encoder_vp8_vme_mbenc_set_i_frame_curbe(VADriverContextP ctx,
3128                                              struct encode_state *encode_state,
3129                                              struct intel_encoder_context *encoder_context,
3130                                              struct i965_gpe_context *gpe_context)
3131 {
3132     struct i965_encoder_vp8_context *vp8_context = encoder_context->vme_context;
3133     struct vp8_mbenc_i_frame_curbe_data *pcmd = i965_gpe_context_map_curbe(gpe_context);
3134     VAEncPictureParameterBufferVP8 *pic_param = (VAEncPictureParameterBufferVP8 *)encode_state->pic_param_ext->buffer;
3135     VAQMatrixBufferVP8 *quant_param = (VAQMatrixBufferVP8 *)encode_state->q_matrix->buffer;
3136     unsigned int segmentation_enabled = pic_param->pic_flags.bits.segmentation_enabled;
3137     unsigned short y_quanta_dc_idx, uv_quanta_dc_idx, uv_quanta_ac_idx;
3138
3139     if (!pcmd)
3140         return;
3141
3142     memset(pcmd, 0, sizeof(*pcmd));
3143
3144     pcmd->dw0.frame_width = vp8_context->frame_width;
3145     pcmd->dw0.frame_height = vp8_context->frame_height;
3146
3147     pcmd->dw1.frame_type = 0; /* key frame */
3148     pcmd->dw1.enable_segmentation = segmentation_enabled;
3149     pcmd->dw1.enable_hw_intra_prediction = (encoder_context->quality_level == ENCODER_LOW_QUALITY) ? 1 : 0;
3150     pcmd->dw1.enable_chroma_ip_enhancement = 1; /* Cannot be disabled */
3151     pcmd->dw1.enable_debug_dumps = 0;
3152     pcmd->dw1.enable_mpu_histogram_update = 1;
3153     pcmd->dw1.vme_distortion_measure = 2; /* HAAR transform */
3154     pcmd->dw1.vme_enable_tm_check = 0;
3155
3156     QUANT_INDEX(y_quanta_dc_idx, 0, 0);
3157     pcmd->dw2.lambda_seg_0 = (unsigned short)((quant_dc_vp8[y_quanta_dc_idx] * quant_dc_vp8[y_quanta_dc_idx]) / 4);
3158
3159     if (segmentation_enabled) {
3160         QUANT_INDEX(y_quanta_dc_idx, 1, 0);
3161         pcmd->dw2.lambda_seg_1 = (unsigned short)((quant_dc_vp8[y_quanta_dc_idx] * quant_dc_vp8[y_quanta_dc_idx]) / 4);
3162
3163         QUANT_INDEX(y_quanta_dc_idx, 2, 0);
3164         pcmd->dw3.lambda_seg_2 = (unsigned short)((quant_dc_vp8[y_quanta_dc_idx] * quant_dc_vp8[y_quanta_dc_idx]) / 4);
3165
3166         QUANT_INDEX(y_quanta_dc_idx, 3, 0);
3167         pcmd->dw3.lambda_seg_3 = (unsigned short)((quant_dc_vp8[y_quanta_dc_idx] * quant_dc_vp8[y_quanta_dc_idx]) / 4);
3168     }
3169
3170     pcmd->dw4.all_dc_bias_segment_0 = DC_BIAS_SEGMENT_DEFAULT_VAL_VP8;
3171
3172     if (segmentation_enabled) {
3173         pcmd->dw4.all_dc_bias_segment_1 = DC_BIAS_SEGMENT_DEFAULT_VAL_VP8;
3174         pcmd->dw5.all_dc_bias_segment_2 = DC_BIAS_SEGMENT_DEFAULT_VAL_VP8;
3175         pcmd->dw5.all_dc_bias_segment_3 = DC_BIAS_SEGMENT_DEFAULT_VAL_VP8;
3176     }
3177
3178     QUANT_INDEX(uv_quanta_dc_idx, 0, 1);
3179     pcmd->dw6.chroma_dc_de_quant_segment_0 = quant_dc_vp8[uv_quanta_dc_idx];
3180
3181     if (segmentation_enabled) {
3182         QUANT_INDEX(uv_quanta_dc_idx, 1, 1);
3183         pcmd->dw6.chroma_dc_de_quant_segment_1 = quant_dc_vp8[uv_quanta_dc_idx];
3184
3185         QUANT_INDEX(uv_quanta_dc_idx, 2, 1);
3186         pcmd->dw7.chroma_dc_de_quant_segment_2 = quant_dc_vp8[uv_quanta_dc_idx];
3187
3188         QUANT_INDEX(uv_quanta_dc_idx, 3, 1);
3189         pcmd->dw7.chroma_dc_de_quant_segment_3 = quant_dc_vp8[uv_quanta_dc_idx];
3190     }
3191
3192     QUANT_INDEX(uv_quanta_ac_idx, 0, 2);
3193     pcmd->dw8.chroma_ac_de_quant_segment0 = quant_ac_vp8[uv_quanta_ac_idx];
3194     pcmd->dw10.chroma_ac0_threshold0_segment0 = (unsigned short)((((((1) << 16) -
3195                                                                     1) * 1.0 / ((1 << 16) / quant_ac_vp8[uv_quanta_ac_idx]) -
3196                                                                    ((48 * quant_ac_vp8[uv_quanta_ac_idx]) >> 7)) *
3197                                                                   (1 << 13) + 3400) / 2217.0);
3198     pcmd->dw10.chroma_ac0_threshold1_segment0 = (unsigned short)((((((2) << 16) -
3199                                                                     1) * 1.0 / ((1 << 16) / quant_ac_vp8[uv_quanta_ac_idx]) -
3200                                                                    ((48 * quant_ac_vp8[uv_quanta_ac_idx]) >> 7)) *
3201                                                                   (1 << 13) + 3400) / 2217.0);
3202
3203     if (segmentation_enabled) {
3204         QUANT_INDEX(uv_quanta_ac_idx, 1, 2);
3205         pcmd->dw8.chroma_ac_de_quant_segment1 = quant_ac_vp8[uv_quanta_ac_idx];
3206         pcmd->dw10.chroma_ac0_threshold0_segment0 = (unsigned short)((((((1) << 16) -
3207                                                                         1) * 1.0 / ((1 << 16) /
3208                                                                                     quant_ac_vp8[uv_quanta_ac_idx]) -
3209                                                                        ((48 * quant_ac_vp8[uv_quanta_ac_idx]) >> 7)) *
3210                                                                       (1 << 13) + 3400) / 2217.0);
3211         pcmd->dw10.chroma_ac0_threshold1_segment0 = (unsigned short)((((((2) << 16) -
3212                                                                         1) * 1.0 / ((1 << 16) /
3213                                                                                     quant_ac_vp8[uv_quanta_ac_idx]) -
3214                                                                        ((48 * quant_ac_vp8[uv_quanta_ac_idx]) >> 7)) *
3215                                                                       (1 << 13) + 3400) / 2217.0);
3216
3217         QUANT_INDEX(uv_quanta_ac_idx, 2, 2);
3218         pcmd->dw9.chroma_ac_de_quant_segment2 = quant_ac_vp8[uv_quanta_ac_idx];
3219         pcmd->dw12.chroma_ac0_threshold0_segment2 = (unsigned short)((((((1) << 16) -
3220                                                                         1) * 1.0 / ((1 << 16) /
3221                                                                                     quant_ac_vp8[uv_quanta_ac_idx]) -
3222                                                                        ((48 * quant_ac_vp8[uv_quanta_ac_idx]) >> 7)) *
3223                                                                       (1 << 13) + 3400) / 2217.0);
3224         pcmd->dw12.chroma_ac0_threshold1_segment2 = (unsigned short)((((((2) << 16) -
3225                                                                         1) * 1.0 / ((1 << 16) /
3226                                                                                     quant_ac_vp8[uv_quanta_ac_idx]) -
3227                                                                        ((48 * quant_ac_vp8[uv_quanta_ac_idx]) >> 7)) *
3228                                                                       (1 << 13) + 3400) / 2217.0);
3229
3230         QUANT_INDEX(uv_quanta_ac_idx, 3, 2);
3231         pcmd->dw9.chroma_ac_de_quant_segment3 = quant_ac_vp8[uv_quanta_ac_idx];
3232         pcmd->dw13.chroma_ac0_threshold0_segment3 = (unsigned short)((((((1) << 16) -
3233                                                                         1) * 1.0 / ((1 << 16) /
3234                                                                                     quant_ac_vp8[uv_quanta_ac_idx]) -
3235                                                                        ((48 * quant_ac_vp8[uv_quanta_ac_idx]) >> 7)) *
3236                                                                       (1 << 13) + 3400) / 2217.0);
3237         pcmd->dw13.chroma_ac0_threshold1_segment3 = (unsigned short)((((((2) << 16) -
3238                                                                         1) * 1.0 / ((1 << 16) /
3239                                                                                     quant_ac_vp8[uv_quanta_ac_idx]) -
3240                                                                        ((48 * quant_ac_vp8[uv_quanta_ac_idx]) >> 7)) *
3241                                                                       (1 << 13) + 3400) / 2217.0);
3242     }
3243
3244     QUANT_INDEX(uv_quanta_dc_idx, 0, 1);
3245     pcmd->dw14.chroma_dc_threshold0_segment0 = (((1) << 16) - 1) / ((1 << 16) / quant_dc_vp8[uv_quanta_dc_idx]) -
3246         ((48 * quant_dc_vp8[uv_quanta_dc_idx]) >> 7);
3247     pcmd->dw14.chroma_dc_threshold1_segment0 = (((2) << 16) - 1) / ((1 << 16) / quant_dc_vp8[uv_quanta_dc_idx]) -
3248         ((48 * quant_dc_vp8[uv_quanta_dc_idx]) >> 7);
3249     pcmd->dw15.chroma_dc_threshold2_segment0 = (((3) << 16) - 1) / ((1 << 16) / quant_dc_vp8[uv_quanta_dc_idx]) -
3250         ((48 * quant_dc_vp8[uv_quanta_dc_idx]) >> 7);
3251     pcmd->dw15.chroma_dc_threshold3_segment0 = (((4) << 16) - 1) / ((1 << 16) / quant_dc_vp8[uv_quanta_dc_idx]) -
3252         ((48 * quant_dc_vp8[uv_quanta_dc_idx]) >> 7);
3253
3254     if (segmentation_enabled) {
3255         QUANT_INDEX(uv_quanta_dc_idx, 1, 1);
3256         pcmd->dw16.chroma_dc_threshold0_segment1 = (((1) << 16) - 1) / ((1 << 16) / quant_dc_vp8[uv_quanta_dc_idx]) -
3257             ((48 * quant_dc_vp8[uv_quanta_dc_idx]) >> 7);
3258         pcmd->dw16.chroma_dc_threshold1_segment1 = (((2) << 16) - 1) / ((1 << 16) / quant_dc_vp8[uv_quanta_dc_idx]) -
3259             ((48 * quant_dc_vp8[uv_quanta_dc_idx]) >> 7);
3260         pcmd->dw17.chroma_dc_threshold2_segment1 = (((3) << 16) - 1) / ((1 << 16) / quant_dc_vp8[uv_quanta_dc_idx]) -
3261             ((48 * quant_dc_vp8[uv_quanta_dc_idx]) >> 7);
3262         pcmd->dw17.chroma_dc_threshold3_segment1 = (((4) << 16) - 1) / ((1 << 16) / quant_dc_vp8[uv_quanta_dc_idx]) -
3263             ((48 * quant_dc_vp8[uv_quanta_dc_idx]) >> 7);
3264
3265         QUANT_INDEX(uv_quanta_dc_idx, 2, 1);
3266         pcmd->dw18.chroma_dc_threshold0_segment2 = (((1) << 16) - 1) / ((1 << 16) / quant_dc_vp8[uv_quanta_dc_idx]) -
3267             ((48 * quant_dc_vp8[uv_quanta_dc_idx]) >> 7);
3268         pcmd->dw18.chroma_dc_threshold1_segment2 = (((2) << 16) - 1) / ((1 << 16) / quant_dc_vp8[uv_quanta_dc_idx]) -
3269             ((48 * quant_dc_vp8[uv_quanta_dc_idx]) >> 7);
3270         pcmd->dw19.chroma_dc_threshold2_segment2 = (((3) << 16) - 1) / ((1 << 16) / quant_dc_vp8[uv_quanta_dc_idx]) -
3271             ((48 * quant_dc_vp8[uv_quanta_dc_idx]) >> 7);
3272         pcmd->dw19.chroma_dc_threshold3_segment2 = (((4) << 16) - 1) / ((1 << 16) / quant_dc_vp8[uv_quanta_dc_idx]) -
3273             ((48 * quant_dc_vp8[uv_quanta_dc_idx]) >> 7);
3274
3275         QUANT_INDEX(uv_quanta_dc_idx, 3, 1);
3276         pcmd->dw20.chroma_dc_threshold0_segment3 = (((1) << 16) - 1) / ((1 << 16) / quant_dc_vp8[uv_quanta_dc_idx]) -
3277             ((48 * quant_dc_vp8[uv_quanta_dc_idx]) >> 7);
3278         pcmd->dw20.chroma_dc_threshold1_segment3 = (((2) << 16) - 1) / ((1 << 16) / quant_dc_vp8[uv_quanta_dc_idx]) -
3279             ((48 * quant_dc_vp8[uv_quanta_dc_idx]) >> 7);
3280         pcmd->dw21.chroma_dc_threshold2_segment3 = (((3) << 16) - 1) / ((1 << 16) / quant_dc_vp8[uv_quanta_dc_idx]) -
3281             ((48 * quant_dc_vp8[uv_quanta_dc_idx]) >> 7);
3282         pcmd->dw21.chroma_dc_threshold3_segment3 = (((4) << 16) - 1) / ((1 << 16) / quant_dc_vp8[uv_quanta_dc_idx]) -
3283             ((48 * quant_dc_vp8[uv_quanta_dc_idx]) >> 7);
3284     }
3285
3286     QUANT_INDEX(uv_quanta_ac_idx, 0, 2);
3287     pcmd->dw22.chroma_ac1_threshold_segment0 = ((1 << (16)) - 1) / ((1 << 16) / quant_ac_vp8[uv_quanta_ac_idx]) -
3288         ((48 * quant_ac_vp8[uv_quanta_ac_idx]) >> 7);
3289
3290     if (segmentation_enabled) {
3291         QUANT_INDEX(uv_quanta_ac_idx, 1, 2);
3292         pcmd->dw22.chroma_ac1_threshold_segment1 = ((1 << (16)) - 1) / ((1 << 16) / quant_ac_vp8[uv_quanta_ac_idx]) -
3293             ((48 * quant_ac_vp8[uv_quanta_ac_idx]) >> 7);
3294
3295         QUANT_INDEX(uv_quanta_ac_idx, 2, 2);
3296         pcmd->dw23.chroma_ac1_threshold_segment2 = ((1 << (16)) - 1) / ((1 << 16) / quant_ac_vp8[uv_quanta_ac_idx]) -
3297             ((48 * quant_ac_vp8[uv_quanta_ac_idx]) >> 7);
3298
3299         QUANT_INDEX(uv_quanta_ac_idx, 3, 2);
3300         pcmd->dw23.chroma_ac1_threshold_segment3 =
3301             ((1 << (16)) - 1) / ((1 << 16) / quant_ac_vp8[uv_quanta_ac_idx]) -
3302             ((48 * quant_ac_vp8[uv_quanta_ac_idx]) >> 7);
3303     }
3304
3305     QUANT_INDEX(uv_quanta_dc_idx, 0, 0);
3306     pcmd->dw24.vme_16x16_cost_segment0 = i_frame_vme_costs_vp8[uv_quanta_dc_idx & 0x7F][0];
3307     pcmd->dw25.vme_4x4_cost_segment0 = i_frame_vme_costs_vp8[uv_quanta_dc_idx & 0x7F][1];
3308     pcmd->dw26.vme_16x16_non_dc_penalty_segment0 = i_frame_vme_costs_vp8[uv_quanta_dc_idx & 0x7F][2];
3309     pcmd->dw27.vme_4x4_non_dc_penalty_segment0 = i_frame_vme_costs_vp8[uv_quanta_dc_idx & 0x7F][3];
3310
3311     if (segmentation_enabled) {
3312         QUANT_INDEX(uv_quanta_dc_idx, 1, 0);
3313         pcmd->dw24.vme_16x16_cost_segment1 = i_frame_vme_costs_vp8[uv_quanta_dc_idx & 0x7F][0];
3314         pcmd->dw25.vme_4x4_cost_segment1 = i_frame_vme_costs_vp8[uv_quanta_dc_idx & 0x7F][1];
3315         pcmd->dw26.vme_16x16_non_dc_penalty_segment1 = i_frame_vme_costs_vp8[uv_quanta_dc_idx & 0x7F][2];
3316         pcmd->dw27.vme_4x4_non_dc_penalty_segment1 = i_frame_vme_costs_vp8[uv_quanta_dc_idx & 0x7F][3];
3317
3318         QUANT_INDEX(uv_quanta_dc_idx, 2, 0);
3319         pcmd->dw24.vme_16x16_cost_segment2 = i_frame_vme_costs_vp8[uv_quanta_dc_idx & 0x7F][0];
3320         pcmd->dw25.vme_4x4_cost_segment2 = i_frame_vme_costs_vp8[uv_quanta_dc_idx & 0x7F][1];
3321         pcmd->dw26.vme_16x16_non_dc_penalty_segment2 = i_frame_vme_costs_vp8[uv_quanta_dc_idx & 0x7F][2];
3322         pcmd->dw27.vme_4x4_non_dc_penalty_segment2 = i_frame_vme_costs_vp8[uv_quanta_dc_idx & 0x7F][3];
3323
3324         QUANT_INDEX(uv_quanta_dc_idx, 3, 0);
3325         pcmd->dw24.vme_16x16_cost_segment3 = i_frame_vme_costs_vp8[uv_quanta_dc_idx & 0x7F][0];
3326         pcmd->dw25.vme_4x4_cost_segment3 = i_frame_vme_costs_vp8[uv_quanta_dc_idx & 0x7F][1];
3327         pcmd->dw26.vme_16x16_non_dc_penalty_segment3 = i_frame_vme_costs_vp8[uv_quanta_dc_idx & 0x7F][2];
3328         pcmd->dw27.vme_4x4_non_dc_penalty_segment3 = i_frame_vme_costs_vp8[uv_quanta_dc_idx & 0x7F][3];
3329     }
3330
3331     pcmd->dw32.mb_enc_per_mb_out_data_surf_bti = VP8_BTI_MBENC_PER_MB_OUT;
3332     pcmd->dw33.mb_enc_curr_y_bti = VP8_BTI_MBENC_CURR_Y;
3333     pcmd->dw34.mb_enc_curr_uv_bti = VP8_BTI_MBENC_CURR_Y;
3334     pcmd->dw35.mb_mode_cost_luma_bti = VP8_BTI_MBENC_MB_MODE_COST_LUMA;
3335     pcmd->dw36.mb_enc_block_mode_cost_bti = VP8_BTI_MBENC_BLOCK_MODE_COST;
3336     pcmd->dw37.chroma_recon_surf_bti = VP8_BTI_MBENC_CHROMA_RECON;
3337     pcmd->dw38.segmentation_map_bti = VP8_BTI_MBENC_SEGMENTATION_MAP;
3338     pcmd->dw39.histogram_bti = VP8_BTI_MBENC_HISTOGRAM;
3339     pcmd->dw40.mb_enc_vme_debug_stream_out_bti = VP8_BTI_MBENC_I_VME_DEBUG_STREAMOUT;
3340     pcmd->dw41.vme_bti = VP8_BTI_MBENC_VME;
3341     pcmd->dw42.idist_surface_bti = VP8_BTI_MBENC_IDIST;
3342     pcmd->dw43.curr_y_down_scaled_bti = VP8_BTI_MBENC_CURR_Y_DOWNSCALED;
3343     pcmd->dw44.vme_coarse_intra_bti = VP8_BTI_MBENC_VME_COARSE_INTRA;
3344
3345     i965_gpe_context_unmap_curbe(gpe_context);
3346 }
3347
3348 static void
3349 i965_encoder_vp8_vme_mbenc_set_p_frame_curbe(VADriverContextP ctx,
3350                                              struct encode_state *encode_state,
3351                                              struct intel_encoder_context *encoder_context,
3352                                              struct i965_gpe_context *gpe_context)
3353 {
3354     struct i965_encoder_vp8_context *vp8_context = encoder_context->vme_context;
3355     struct vp8_mbenc_p_frame_curbe_data *pcmd = i965_gpe_context_map_curbe(gpe_context);
3356     VAEncPictureParameterBufferVP8 *pic_param = (VAEncPictureParameterBufferVP8 *)encode_state->pic_param_ext->buffer;
3357     VAQMatrixBufferVP8 *quant_param = (VAQMatrixBufferVP8 *)encode_state->q_matrix->buffer;
3358     unsigned int segmentation_enabled = pic_param->pic_flags.bits.segmentation_enabled;
3359     unsigned short qp_seg0, qp_seg1, qp_seg2, qp_seg3;
3360     unsigned char me_method = (encoder_context->quality_level == ENCODER_DEFAULT_QUALITY) ? 6 : 4;
3361
3362     if (!pcmd)
3363         return;
3364
3365     memset(pcmd, 0, sizeof(*pcmd));
3366
3367     QUANT_INDEX(qp_seg0, 0, 0);
3368     QUANT_INDEX(qp_seg1, 0, 0);
3369     QUANT_INDEX(qp_seg2, 0, 0);
3370     QUANT_INDEX(qp_seg3, 3, 0);
3371
3372     pcmd->dw0.frame_width = vp8_context->frame_width;
3373     pcmd->dw0.frame_height = vp8_context->frame_height;
3374
3375     pcmd->dw1.frame_type = 1;   // P-frame
3376     pcmd->dw1.multiple_pred = (encoder_context->quality_level == ENCODER_DEFAULT_QUALITY) ? 1 :
3377         ((encoder_context->quality_level == ENCODER_LOW_QUALITY) ? 0 : 2);
3378     pcmd->dw1.hme_enable = vp8_context->hme_enabled;
3379     pcmd->dw1.hme_combine_overlap = 1;
3380     pcmd->dw1.enable_temporal_scalability = 0;
3381     pcmd->dw1.ref_frame_flags = vp8_context->ref_frame_ctrl;
3382     pcmd->dw1.enable_segmentation = segmentation_enabled;
3383     pcmd->dw1.enable_segmentation_info_update = 1;
3384     pcmd->dw1.multi_reference_qp_check = 0;
3385     pcmd->dw1.mode_cost_enable_flag = 1;
3386     pcmd->dw1.main_ref = mainref_table_vp8[vp8_context->ref_frame_ctrl];
3387
3388     pcmd->dw2.lambda_intra_segment0 = quant_dc_vp8[qp_seg0];
3389     pcmd->dw2.lambda_inter_segment0 = (quant_dc_vp8[qp_seg0] >> 2);
3390
3391     pcmd->dw3.lambda_intra_segment1 = quant_dc_vp8[qp_seg1];
3392     pcmd->dw3.lambda_inter_segment1 = (quant_dc_vp8[qp_seg1] >> 2);
3393
3394     pcmd->dw4.lambda_intra_segment2 = quant_dc_vp8[qp_seg2];
3395     pcmd->dw4.lambda_inter_segment2 = (quant_dc_vp8[qp_seg2] >> 2);
3396
3397     pcmd->dw5.lambda_intra_segment3 = quant_dc_vp8[qp_seg3];
3398     pcmd->dw5.lambda_inter_segment3 = (quant_dc_vp8[qp_seg3] >> 2);
3399
3400     pcmd->dw6.reference_frame_sign_bias_3 = pic_param->pic_flags.bits.sign_bias_golden;
3401     pcmd->dw6.reference_frame_sign_bias_2 = pic_param->pic_flags.bits.sign_bias_alternate;
3402     pcmd->dw6.reference_frame_sign_bias_1 = pic_param->pic_flags.bits.sign_bias_golden ^ pic_param->pic_flags.bits.sign_bias_alternate;
3403     pcmd->dw6.reference_frame_sign_bias_0 = 0;
3404
3405     pcmd->dw7.raw_dist_threshold = (encoder_context->quality_level == ENCODER_DEFAULT_QUALITY) ? 50 :
3406         ((encoder_context->quality_level == ENCODER_LOW_QUALITY) ? 0 : 100);
3407     pcmd->dw7.temporal_layer_id = 0;
3408
3409     pcmd->dw8.early_ime_successful_stop_threshold = 0;
3410     pcmd->dw8.adaptive_search_enable = (encoder_context->quality_level != ENCODER_LOW_QUALITY) ? 1 : 0;
3411     pcmd->dw8.skip_mode_enable = 1;
3412     pcmd->dw8.bidirectional_mix_disbale = 0;
3413     pcmd->dw8.transform8x8_flag_for_inter_enable = 0;
3414     pcmd->dw8.early_ime_success_enable = 0;
3415
3416     pcmd->dw9.ref_pixel_bias_enable = 0;
3417     pcmd->dw9.unidirection_mix_enable = 0;
3418     pcmd->dw9.bidirectional_weight = 0;
3419     pcmd->dw9.ref_id_polarity_bits = 0;
3420     pcmd->dw9.max_num_of_motion_vectors = 0;
3421
3422     pcmd->dw10.max_fixed_search_path_length = (encoder_context->quality_level == ENCODER_DEFAULT_QUALITY) ? 25 :
3423         ((encoder_context->quality_level == ENCODER_LOW_QUALITY) ? 9 : 57);
3424     pcmd->dw10.maximum_search_path_length = 57;
3425
3426     pcmd->dw11.submacro_block_subPartition_mask = 0;
3427     pcmd->dw11.intra_sad_measure_adjustment = 2;
3428     pcmd->dw11.inter_sad_measure_adjustment = 2;
3429     pcmd->dw11.block_based_skip_enable = 0;
3430     pcmd->dw11.bme_disable_for_fbr_message = 0;
3431     pcmd->dw11.forward_trans_form_skip_check_enable = 0;
3432     pcmd->dw11.process_inter_chroma_pixels_mode = 0;
3433     pcmd->dw11.disable_field_cache_allocation = 0;
3434     pcmd->dw11.skip_mode_type = 0;
3435     pcmd->dw11.sub_pel_mode = 3;
3436     pcmd->dw11.dual_search_path_option = 0;
3437     pcmd->dw11.search_control = 0;
3438     pcmd->dw11.reference_access = 0;
3439     pcmd->dw11.source_access = 0;
3440     pcmd->dw11.inter_mb_type_road_map = 0;
3441     pcmd->dw11.source_block_size = 0;
3442
3443     pcmd->dw12.reference_search_windows_height = (encoder_context->quality_level != ENCODER_LOW_QUALITY) ? 40 : 28;
3444     pcmd->dw12.reference_search_windows_width = (encoder_context->quality_level != ENCODER_LOW_QUALITY) ? 48 : 28;
3445
3446     pcmd->dw13.mode_0_3_cost_seg0 = cost_table_vp8[qp_seg0][0];
3447     pcmd->dw14.mode_4_7_cost_seg0 = cost_table_vp8[qp_seg0][1];
3448     pcmd->dw15.mode_8_9_ref_id_chroma_cost_seg0 = cost_table_vp8[qp_seg0][2];
3449
3450     switch (me_method) {
3451     case 2:
3452         memcpy(&(pcmd->dw16), single_su_vp8, sizeof(single_su_vp8));
3453         break;
3454
3455     case 3:
3456         memcpy(&(pcmd->dw16), raster_scan_48x40_vp8, sizeof(raster_scan_48x40_vp8));
3457         break;
3458
3459     case 4:
3460     case 5:
3461         memcpy(&(pcmd->dw16), full_spiral_48x40_vp8, sizeof(full_spiral_48x40_vp8));
3462         break;
3463
3464     case 6:
3465     default:
3466         memcpy(&(pcmd->dw16), diamond_vp8, sizeof(diamond_vp8));
3467         break;
3468     }
3469
3470     pcmd->dw30.mv_0_3_cost_seg0 = cost_table_vp8[qp_seg0][3];
3471     pcmd->dw31.mv_4_7_cost_seg0 = cost_table_vp8[qp_seg0][4];
3472
3473     pcmd->dw32.bilinear_enable = 0;
3474     pcmd->dw32.intra_16x16_no_dc_penalty_segment0 = cost_table_vp8[qp_seg0][5];
3475     pcmd->dw32.intra_16x16_no_dc_penalty_segment1 = cost_table_vp8[qp_seg1][5];
3476
3477     pcmd->dw33.intra_16x16_no_dc_penalty_segment2 = cost_table_vp8[qp_seg2][5];
3478     pcmd->dw33.intra_16x16_no_dc_penalty_segment3 = cost_table_vp8[qp_seg3][5];
3479     pcmd->dw33.hme_combine_len = 8;
3480
3481     /* dw34 to dw 57 */
3482     memcpy(&(pcmd->dw34), mv_ref_cost_context_vp8, 24 * sizeof(unsigned int));
3483
3484     pcmd->dw58.enc_cost_16x16 = 0;
3485     pcmd->dw58.enc_cost_16x8 = 0x73c;
3486
3487     pcmd->dw59.enc_cost_8x8 = 0x365;
3488     pcmd->dw59.enc_cost_4x4 = 0xdc9;
3489
3490     pcmd->dw60.frame_count_probability_ref_frame_cost_0 = 0x0204;
3491     pcmd->dw60.frame_count_probability_ref_frame_cost_1 = 0x006a;
3492
3493     pcmd->dw61.frame_count_probability_ref_frame_cost_2 = 0x0967;
3494     pcmd->dw61.frame_count_probability_ref_frame_cost_3 = 0x0969;
3495
3496     switch (vp8_context->frame_num % vp8_context->gop_size) {
3497     case 1:
3498         pcmd->dw62.average_qp_of_last_ref_frame = quant_dc_vp8[vp8_context->average_i_frame_qp];
3499         pcmd->dw62.average_qp_of_gold_ref_frame = pcmd->dw62.average_qp_of_last_ref_frame;
3500         pcmd->dw62.average_qp_of_alt_ref_frame  = pcmd->dw62.average_qp_of_last_ref_frame;
3501         break;
3502
3503     case 2:
3504         pcmd->dw62.average_qp_of_last_ref_frame = quant_dc_vp8[vp8_context->average_p_frame_qp];
3505         pcmd->dw62.average_qp_of_gold_ref_frame = quant_dc_vp8[vp8_context->average_i_frame_qp];
3506         pcmd->dw62.average_qp_of_alt_ref_frame  = pcmd->dw62.average_qp_of_gold_ref_frame;
3507         break;
3508
3509     case 3:
3510         pcmd->dw62.average_qp_of_last_ref_frame = quant_dc_vp8[vp8_context->average_p_frame_qp];
3511         pcmd->dw62.average_qp_of_gold_ref_frame = quant_dc_vp8[vp8_context->average_p_frame_qp];
3512         pcmd->dw62.average_qp_of_alt_ref_frame  = quant_dc_vp8[vp8_context->average_i_frame_qp];
3513         break;
3514
3515     default:
3516         pcmd->dw62.average_qp_of_last_ref_frame = quant_dc_vp8[vp8_context->average_p_frame_qp];
3517         pcmd->dw62.average_qp_of_gold_ref_frame = pcmd->dw62.average_qp_of_last_ref_frame;
3518         pcmd->dw62.average_qp_of_alt_ref_frame  = pcmd->dw62.average_qp_of_last_ref_frame;
3519         break;
3520     }
3521
3522     pcmd->dw63.intra_4x4_no_dc_penalty_segment0 = cost_table_vp8[qp_seg0][6];
3523     pcmd->dw63.intra_4x4_no_dc_penalty_segment1 = cost_table_vp8[qp_seg1][6];
3524     pcmd->dw63.intra_4x4_no_dc_penalty_segment2 = cost_table_vp8[qp_seg2][6];
3525     pcmd->dw63.intra_4x4_no_dc_penalty_segment3 = cost_table_vp8[qp_seg3][6];
3526
3527     pcmd->dw64.mode_0_3_cost_seg1 = cost_table_vp8[qp_seg1][0];
3528     pcmd->dw65.mode_4_7_cost_seg1 = cost_table_vp8[qp_seg1][1];
3529     pcmd->dw66.mode_8_9_ref_id_chroma_cost_seg1 = cost_table_vp8[qp_seg1][2];
3530
3531     pcmd->dw67.mv_0_3_cost_seg1 = cost_table_vp8[qp_seg1][3];
3532     pcmd->dw68.mv_4_7_cost_seg1 = cost_table_vp8[qp_seg1][4];
3533
3534     pcmd->dw69.mode_0_3_cost_seg2 = cost_table_vp8[qp_seg2][0];
3535     pcmd->dw70.mode_4_7_cost_seg2 = cost_table_vp8[qp_seg2][1];
3536     pcmd->dw71.mode_8_9_ref_id_chroma_cost_seg2 = cost_table_vp8[qp_seg2][2];
3537
3538     pcmd->dw72.mv_0_3_cost_seg2 = cost_table_vp8[qp_seg2][3];
3539     pcmd->dw73.mv_4_7_cost_seg2 = cost_table_vp8[qp_seg2][4];
3540
3541     pcmd->dw74.mode_0_3_cost_seg3 = cost_table_vp8[qp_seg3][0];
3542     pcmd->dw75.mode_4_7_cost_seg3 = cost_table_vp8[qp_seg3][1];
3543     pcmd->dw76.mode_8_9_ref_id_chroma_cost_seg3 = cost_table_vp8[qp_seg3][2];
3544
3545     pcmd->dw77.mv_0_3_cost_seg3 = cost_table_vp8[qp_seg3][3];
3546     pcmd->dw78.mv_4_7_cost_seg3 = cost_table_vp8[qp_seg3][4];
3547
3548     pcmd->dw79.new_mv_skip_threshold_segment0 = new_mv_skip_threshold_vp8[qp_seg0];
3549     pcmd->dw79.new_mv_skip_threshold_segment1 = new_mv_skip_threshold_vp8[qp_seg1];
3550     pcmd->dw80.new_mv_skip_threshold_segment2 = new_mv_skip_threshold_vp8[qp_seg2];
3551     pcmd->dw80.new_mv_skip_threshold_segment3 = new_mv_skip_threshold_vp8[qp_seg3];
3552
3553     pcmd->dw81.per_mb_output_data_surface_bti = VP8_BTI_MBENC_PER_MB_OUT;
3554     pcmd->dw82.current_picture_y_surface_bti = VP8_BTI_MBENC_CURR_Y;
3555     pcmd->dw83.current_picture_interleaved_uv_surface_bti = VP8_BTI_MBENC_CURR_Y;
3556     pcmd->dw84.hme_mv_data_surface_bti = VP8_BTI_MBENC_MV_DATA_FROM_ME;
3557     pcmd->dw85.mv_data_surface_bti = VP8_BTI_MBENC_IND_MV_DATA;
3558     pcmd->dw86.mb_count_per_reference_frame_bti = VP8_BTI_MBENC_REF_MB_COUNT;
3559     pcmd->dw87.vme_inter_prediction_bti = VP8_BTI_MBENC_INTER_PRED;
3560     pcmd->dw88.active_ref1_bti = VP8_BTI_MBENC_REF1_PIC;
3561     pcmd->dw89.active_ref2_bti = VP8_BTI_MBENC_REF2_PIC;
3562     pcmd->dw90.active_ref3_bti = VP8_BTI_MBENC_REF3_PIC;
3563     pcmd->dw91.per_mb_quant_data_bti = VP8_BTI_MBENC_P_PER_MB_QUANT;
3564     pcmd->dw92.segment_map_bti = VP8_BTI_MBENC_SEGMENTATION_MAP;
3565     pcmd->dw93.inter_prediction_distortion_bti = VP8_BTI_MBENC_INTER_PRED_DISTORTION;
3566     pcmd->dw94.histogram_bti = VP8_BTI_MBENC_HISTOGRAM;
3567     pcmd->dw95.pred_mv_data_bti = VP8_BTI_MBENC_PRED_MV_DATA;
3568     pcmd->dw96.mode_cost_update_bti = VP8_BTI_MBENC_MODE_COST_UPDATE;
3569     pcmd->dw97.kernel_debug_dump_bti = VP8_BTI_MBENC_P_VME_DEBUG_STREAMOUT;
3570
3571     i965_gpe_context_unmap_curbe(gpe_context);
3572 }
3573
3574 #undef QUANT_INDEX
3575
3576 static void
3577 i965_encoder_vp8_vme_mbenc_set_curbe(VADriverContextP ctx,
3578                                      struct encode_state *encode_state,
3579                                      struct intel_encoder_context *encoder_context,
3580                                      struct i965_gpe_context *gpe_context)
3581 {
3582     struct i965_encoder_vp8_context *vp8_context = encoder_context->vme_context;
3583
3584     if (vp8_context->frame_type == MPEG_I_PICTURE)
3585         i965_encoder_vp8_vme_mbenc_set_i_frame_curbe(ctx, encode_state, encoder_context, gpe_context);
3586     else
3587         i965_encoder_vp8_vme_mbenc_set_p_frame_curbe(ctx, encode_state, encoder_context, gpe_context);
3588 }
3589
3590 static void
3591 i965_encoder_vp8_vme_mbenc_add_surfaces(VADriverContextP ctx,
3592                                         struct encode_state *encode_state,
3593                                         struct intel_encoder_context *encoder_context,
3594                                         struct i965_gpe_context *gpe_context,
3595                                         struct mbenc_surface_parameters *params)
3596 {
3597     struct i965_encoder_vp8_context *vp8_context = encoder_context->vme_context;
3598     struct i965_encoder_vp8_surface *vp8_surface;
3599     struct object_surface *obj_surface;
3600     VAEncPictureParameterBufferVP8 *pic_param = (VAEncPictureParameterBufferVP8 *)encode_state->pic_param_ext->buffer;
3601     unsigned int size = vp8_context->frame_width_in_mbs * vp8_context->frame_height_in_mbs * 16;
3602     unsigned int segmentation_enabled = pic_param->pic_flags.bits.segmentation_enabled;
3603
3604     /* Per MB output data buffer */
3605     i965_add_buffer_gpe_surface(ctx,
3606                                 encoder_context,
3607                                 gpe_context,
3608                                 &vp8_context->mb_coded_buffer,
3609                                 0,
3610                                 size,
3611                                 0,
3612                                 VP8_BTI_MBENC_PER_MB_OUT);
3613
3614     /* Current input surface Y & UV */
3615     i965_add_2d_gpe_surface(ctx,
3616                             encoder_context,
3617                             gpe_context,
3618                             encode_state->input_yuv_object,
3619                             0,
3620                             1,
3621                             I965_SURFACEFORMAT_R8_UNORM,
3622                             VP8_BTI_MBENC_CURR_Y);
3623
3624     i965_add_2d_gpe_surface(ctx,
3625                             encoder_context,
3626                             gpe_context,
3627                             encode_state->input_yuv_object,
3628                             1,
3629                             1,
3630                             I965_SURFACEFORMAT_R8_UNORM,
3631                             VP8_BTI_MBENC_CURR_UV);
3632
3633     /* Current surface for VME */
3634     i965_add_adv_gpe_surface(ctx,
3635                              encoder_context,
3636                              gpe_context,
3637                              encode_state->input_yuv_object,
3638                              VP8_BTI_MBENC_VME);
3639
3640     if (segmentation_enabled) {
3641         /* TODO check the internal segmetation buffer */
3642         dri_bo *bo = NULL;
3643
3644         if (encode_state->encmb_map)
3645             bo = encode_state->encmb_map->bo;
3646
3647         if (bo) {
3648             i965_add_dri_buffer_2d_gpe_surface(ctx,
3649                                                encoder_context,
3650                                                gpe_context,
3651                                                bo,
3652                                                vp8_context->frame_width_in_mbs,
3653                                                vp8_context->frame_height_in_mbs,
3654                                                vp8_context->frame_width_in_mbs,
3655                                                0,
3656                                                I965_SURFACEFORMAT_R8_UNORM,
3657                                                VP8_BTI_MBENC_SEGMENTATION_MAP);
3658         }
3659     }
3660
3661     /* Histogram buffer */
3662     size = VP8_HISTOGRAM_SIZE;
3663     i965_add_buffer_gpe_surface(ctx,
3664                                 encoder_context,
3665                                 gpe_context,
3666                                 &vp8_context->histogram_buffer,
3667                                 1,
3668                                 size,
3669                                 0,
3670                                 VP8_BTI_MBENC_HISTOGRAM);
3671
3672     if (vp8_context->frame_type == MPEG_I_PICTURE) {
3673         i965_add_buffer_2d_gpe_surface(ctx,
3674                                        encoder_context,
3675                                        gpe_context,
3676                                        &vp8_context->mb_mode_cost_luma_buffer,
3677                                        0,
3678                                        I965_SURFACEFORMAT_R8_UNORM,
3679                                        VP8_BTI_MBENC_MB_MODE_COST_LUMA);
3680
3681         i965_add_buffer_2d_gpe_surface(ctx,
3682                                        encoder_context,
3683                                        gpe_context,
3684                                        &vp8_context->block_mode_cost_buffer,
3685                                        0,
3686                                        I965_SURFACEFORMAT_R8_UNORM,
3687                                        VP8_BTI_MBENC_BLOCK_MODE_COST);
3688
3689         /* Chroma recon buffer */
3690         size = vp8_context->frame_width_in_mbs * vp8_context->frame_height_in_mbs * 64;
3691         i965_add_buffer_gpe_surface(ctx,
3692                                     encoder_context,
3693                                     gpe_context,
3694                                     &vp8_context->chroma_recon_buffer,
3695                                     0,
3696                                     size,
3697                                     0,
3698                                     VP8_BTI_MBENC_CHROMA_RECON);
3699
3700         if (params->i_frame_dist_in_use) {
3701             i965_add_buffer_2d_gpe_surface(ctx,
3702                                            encoder_context,
3703                                            gpe_context,
3704                                            params->me_brc_distortion_buffer,
3705                                            1,
3706                                            I965_SURFACEFORMAT_R8_UNORM,
3707                                            VP8_BTI_MBENC_IDIST);
3708
3709
3710             vp8_surface = encode_state->reconstructed_object->private_data;
3711             assert(vp8_surface);
3712
3713             if (vp8_surface && vp8_surface->scaled_4x_surface_obj) {
3714                 obj_surface = vp8_surface->scaled_4x_surface_obj;
3715             } else
3716                 obj_surface = NULL;
3717
3718             if (obj_surface) {
3719                 i965_add_2d_gpe_surface(ctx,
3720                                         encoder_context,
3721                                         gpe_context,
3722                                         obj_surface,
3723                                         0,
3724                                         0,
3725                                         I965_SURFACEFORMAT_R8_UNORM,
3726                                         VP8_BTI_MBENC_CURR_Y_DOWNSCALED);
3727
3728                 i965_add_adv_gpe_surface(ctx,
3729                                          encoder_context,
3730                                          gpe_context,
3731                                          obj_surface,
3732                                          VP8_BTI_MBENC_VME_COARSE_INTRA);
3733             }
3734         }
3735     } else {
3736         size = vp8_context->frame_width_in_mbs * vp8_context->frame_height_in_mbs * 64;
3737
3738         i965_add_buffer_gpe_surface(ctx,
3739                                     encoder_context,
3740                                     gpe_context,
3741                                     &vp8_context->mb_coded_buffer,
3742                                     1,
3743                                     size,
3744                                     vp8_context->mv_offset,
3745                                     VP8_BTI_MBENC_IND_MV_DATA);
3746
3747         if (vp8_context->hme_enabled) {
3748             i965_add_buffer_2d_gpe_surface(ctx,
3749                                            encoder_context,
3750                                            gpe_context,
3751                                            &vp8_context->me_4x_mv_data_buffer,
3752                                            1,
3753                                            I965_SURFACEFORMAT_R8_UNORM,
3754                                            VP8_BTI_MBENC_MV_DATA_FROM_ME);
3755         }
3756
3757         i965_add_buffer_gpe_surface(ctx,
3758                                     encoder_context,
3759                                     gpe_context,
3760                                     &vp8_context->reference_frame_mb_count_buffer ,
3761                                     0,
3762                                     32, /* sizeof(unsigned int) * 8 */
3763                                     0,
3764                                     VP8_BTI_MBENC_REF_MB_COUNT);
3765
3766         i965_add_adv_gpe_surface(ctx,
3767                                  encoder_context,
3768                                  gpe_context,
3769                                  encode_state->input_yuv_object,
3770                                  VP8_BTI_MBENC_INTER_PRED);
3771
3772         if (vp8_context->ref_last_frame &&
3773             vp8_context->ref_last_frame->bo) {
3774             obj_surface = vp8_context->ref_last_frame;
3775
3776             switch (vp8_context->ref_frame_ctrl) {
3777             case 1:
3778             case 3:
3779             case 5:
3780             case 7:
3781                 i965_add_adv_gpe_surface(ctx,
3782                                          encoder_context,
3783                                          gpe_context,
3784                                          obj_surface,
3785                                          VP8_BTI_MBENC_REF1_PIC);
3786                 break;
3787             }
3788         }
3789
3790         if (vp8_context->ref_gf_frame &&
3791             vp8_context->ref_gf_frame->bo) {
3792             obj_surface = vp8_context->ref_gf_frame;
3793
3794             switch (vp8_context->ref_frame_ctrl) {
3795             case 2:
3796             case 6:
3797                 i965_add_adv_gpe_surface(ctx,
3798                                          encoder_context,
3799                                          gpe_context,
3800                                          obj_surface,
3801                                          VP8_BTI_MBENC_REF1_PIC);
3802                 break;
3803
3804             case 3:
3805             case 7:
3806                 i965_add_adv_gpe_surface(ctx,
3807                                          encoder_context,
3808                                          gpe_context,
3809                                          obj_surface,
3810                                          VP8_BTI_MBENC_REF2_PIC);
3811                 break;
3812             }
3813         }
3814
3815         if (vp8_context->ref_arf_frame &&
3816             vp8_context->ref_arf_frame->bo) {
3817             obj_surface = vp8_context->ref_arf_frame;
3818
3819             switch (vp8_context->ref_frame_ctrl) {
3820             case 4:
3821                 i965_add_adv_gpe_surface(ctx,
3822                                          encoder_context,
3823                                          gpe_context,
3824                                          obj_surface,
3825                                          VP8_BTI_MBENC_REF1_PIC);
3826                 break;
3827
3828             case 5:
3829             case 6:
3830                 i965_add_adv_gpe_surface(ctx,
3831                                          encoder_context,
3832                                          gpe_context,
3833                                          obj_surface,
3834                                          VP8_BTI_MBENC_REF2_PIC);
3835                 break;
3836
3837             case 7:
3838                 i965_add_adv_gpe_surface(ctx,
3839                                          encoder_context,
3840                                          gpe_context,
3841                                          obj_surface,
3842                                          VP8_BTI_MBENC_REF3_PIC);
3843                 break;
3844             }
3845         }
3846
3847         i965_add_buffer_2d_gpe_surface(ctx,
3848                                        encoder_context,
3849                                        gpe_context,
3850                                        &vp8_context->per_mb_quant_data_buffer,
3851                                        1,
3852                                        I965_SURFACEFORMAT_R8_UNORM,
3853                                        VP8_BTI_MBENC_P_PER_MB_QUANT);
3854
3855         i965_add_buffer_2d_gpe_surface(ctx,
3856                                        encoder_context,
3857                                        gpe_context,
3858                                        &vp8_context->me_4x_distortion_buffer,
3859                                        0,
3860                                        I965_SURFACEFORMAT_R8_UNORM,
3861                                        VP8_BTI_MBENC_INTER_PRED_DISTORTION);
3862
3863         size = vp8_context->frame_width_in_mbs * vp8_context->frame_height_in_mbs * 16;
3864         i965_add_buffer_gpe_surface(ctx,
3865                                     encoder_context,
3866                                     gpe_context,
3867                                     &vp8_context->pred_mv_data_buffer,
3868                                     0,
3869                                     size,
3870                                     0,
3871                                     VP8_BTI_MBENC_PRED_MV_DATA);
3872
3873         size = 16 * sizeof(unsigned int);
3874         i965_add_buffer_gpe_surface(ctx,
3875                                     encoder_context,
3876                                     gpe_context,
3877                                     &vp8_context->mode_cost_update_buffer,
3878                                     1,
3879                                     size,
3880                                     0,
3881                                     VP8_BTI_MBENC_MODE_COST_UPDATE);
3882     }
3883 }
3884
3885 static void
3886 i965_encoder_vp8_vme_mbenc_init_constant_buffer(VADriverContextP ctx,
3887                                                 struct encode_state *encode_state,
3888                                                 struct intel_encoder_context *encoder_context)
3889 {
3890     struct i965_encoder_vp8_context *vp8_context = encoder_context->vme_context;
3891     char *pbuffer = NULL;
3892
3893     i965_zero_gpe_resource(&vp8_context->mb_mode_cost_luma_buffer);
3894     i965_zero_gpe_resource(&vp8_context->block_mode_cost_buffer);
3895
3896     pbuffer = i965_map_gpe_resource(&vp8_context->mb_mode_cost_luma_buffer);
3897
3898     if (!pbuffer)
3899         return;
3900
3901     memcpy(pbuffer, mb_mode_cost_luma_vp8, sizeof(mb_mode_cost_luma_vp8));
3902     i965_unmap_gpe_resource(&vp8_context->mb_mode_cost_luma_buffer);
3903
3904     pbuffer = i965_map_gpe_resource(&vp8_context->block_mode_cost_buffer);
3905
3906     if (!pbuffer)
3907         return;
3908
3909     memcpy(pbuffer, block_mode_cost_vp8, sizeof(block_mode_cost_vp8));
3910     i965_unmap_gpe_resource(&vp8_context->block_mode_cost_buffer);
3911 }
3912
3913 static VAStatus
3914 i965_encoder_vp8_vme_mbenc(VADriverContextP ctx,
3915                            struct encode_state *encode_state,
3916                            struct intel_encoder_context *encoder_context,
3917                            int is_phase2,
3918                            int is_iframe_dist)
3919 {
3920     struct i965_encoder_vp8_context *vp8_context = encoder_context->vme_context;
3921     struct i965_encoder_vp8_mbenc_context *mbenc_context = &vp8_context->mbenc_context;
3922     struct i965_gpe_table *gpe = vp8_context->gpe_table;
3923     struct i965_gpe_context *gpe_context;
3924     struct mbenc_surface_parameters mbenc_surface_params;
3925     struct gpe_media_object_walker_parameter media_object_walker_param;
3926     struct vp8_encoder_kernel_walker_parameter kernel_walker_param;
3927     int is_intra = (vp8_context->frame_type == MPEG_I_PICTURE);
3928     int gpe_index, media_function;
3929
3930     if (is_iframe_dist) {
3931         gpe_index = VP8_MBENC_I_FRAME_DIST;
3932         media_function = VP8_MEDIA_STATE_ENC_I_FRAME_DIST;
3933     } else if (!is_phase2) {
3934         if (is_intra) {
3935             gpe_index = VP8_MBENC_I_FRAME_LUMA;
3936             media_function = VP8_MEDIA_STATE_ENC_I_FRAME_LUMA;
3937         } else {
3938             gpe_index = VP8_MBENC_P_FRAME;
3939             media_function = VP8_MEDIA_STATE_ENC_P_FRAME;
3940         }
3941     } else {
3942         gpe_index = VP8_MBENC_I_FRAME_CHROMA;
3943         media_function = VP8_MEDIA_STATE_ENC_I_FRAME_CHROMA;
3944     }
3945
3946     gpe_context = &mbenc_context->gpe_contexts[gpe_index];
3947
3948     if (!is_phase2 || (is_phase2 && vp8_context->brc_mbenc_phase1_ignored)) {
3949         if (!vp8_context->mbenc_curbe_updated_in_brc_update || is_iframe_dist) {
3950             VAEncPictureParameterBufferVP8 *pic_param =
3951                 (VAEncPictureParameterBufferVP8 *) encode_state->pic_param_ext->buffer;
3952             unsigned int ref_frame_flag_final, ref_frame_flag;
3953
3954             if (!vp8_context->ref_ctrl_optimization_done) {
3955                 if (!is_intra) {
3956                     ref_frame_flag = VP8_REF_FLAG_ALL;
3957
3958                     if (pic_param->ref_last_frame == pic_param->ref_gf_frame) {
3959                         ref_frame_flag &= ~VP8_REF_FLAG_GOLDEN;
3960                     }
3961
3962                     if (pic_param->ref_last_frame == pic_param->ref_arf_frame) {
3963                         ref_frame_flag &= ~VP8_REF_FLAG_ALT;
3964                     }
3965
3966                     if (pic_param->ref_gf_frame == pic_param->ref_arf_frame) {
3967                         ref_frame_flag &= ~VP8_REF_FLAG_ALT;
3968                     }
3969                 } else {
3970                     ref_frame_flag = VP8_REF_FLAG_LAST;
3971                 }
3972
3973                 switch (vp8_context->ref_frame_ctrl) {
3974                 case 0:
3975                     ref_frame_flag_final = VP8_REF_FLAG_NONE;
3976                     break;
3977
3978                 case 1:
3979                     ref_frame_flag_final = VP8_REF_FLAG_LAST;
3980                     break;
3981
3982                 case 2:
3983                     ref_frame_flag_final = VP8_REF_FLAG_GOLDEN;
3984                     break;
3985
3986                 case 4:
3987                     ref_frame_flag_final = VP8_REF_FLAG_ALT;
3988                     break;
3989
3990                 default:
3991                     ref_frame_flag_final = ref_frame_flag;
3992                 }
3993
3994                 vp8_context->ref_frame_ctrl = ref_frame_flag_final;
3995             }
3996
3997             i965_encoder_vp8_vme_mbenc_set_curbe(ctx, encode_state, encoder_context, gpe_context);
3998         }
3999
4000         if (is_intra) {
4001             i965_encoder_vp8_vme_mbenc_init_constant_buffer(ctx, encode_state, encoder_context);
4002         }
4003
4004         if (vp8_context->brc_distortion_buffer_need_reset && is_iframe_dist) {
4005             i965_encoder_vp8_vme_init_brc_distorion_buffer(ctx, encoder_context);
4006         }
4007     }
4008
4009     if (!is_phase2 || (is_phase2 && vp8_context->brc_mbenc_phase1_ignored)) {
4010         i965_zero_gpe_resource(&vp8_context->histogram_buffer);
4011     }
4012
4013     gpe->reset_binding_table(ctx, gpe_context);
4014
4015     memset(&mbenc_surface_params, 0, sizeof(mbenc_surface_params));
4016     mbenc_surface_params.i_frame_dist_in_use = is_iframe_dist;
4017
4018     if (is_iframe_dist)
4019         mbenc_surface_params.me_brc_distortion_buffer = &vp8_context->brc_distortion_buffer;
4020     else
4021         mbenc_surface_params.me_brc_distortion_buffer = &vp8_context->me_4x_distortion_buffer;
4022
4023     i965_encoder_vp8_vme_mbenc_add_surfaces(ctx, encode_state, encoder_context, gpe_context, &mbenc_surface_params);
4024
4025     gpe->setup_interface_data(ctx, gpe_context);
4026
4027     memset(&kernel_walker_param, 0, sizeof(kernel_walker_param));
4028
4029     kernel_walker_param.use_scoreboard = vp8_context->use_hw_scoreboard;
4030
4031     if (is_iframe_dist) {
4032         kernel_walker_param.resolution_x = vp8_context->down_scaled_width_in_mb4x;
4033         kernel_walker_param.resolution_y = vp8_context->down_scaled_height_in_mb4x;
4034     } else {
4035         kernel_walker_param.resolution_x = vp8_context->frame_width_in_mbs;
4036         kernel_walker_param.resolution_y = vp8_context->frame_height_in_mbs;
4037     }
4038
4039     if (is_intra && !is_phase2)
4040         kernel_walker_param.no_dependency = 1;
4041     else
4042         kernel_walker_param.walker_degree = VP8_ENCODER_45_DEGREE;
4043
4044     i965_init_media_object_walker_parameters(encoder_context, &kernel_walker_param, &media_object_walker_param);
4045
4046     i965_run_kernel_media_object_walker(ctx, encoder_context, gpe_context, media_function, &media_object_walker_param);
4047
4048     return VA_STATUS_SUCCESS;
4049 }
4050
4051 static void
4052 i965_encoder_vp8_vme_brc_update_set_curbe(VADriverContextP ctx,
4053                                           struct encode_state *encode_state,
4054                                           struct intel_encoder_context *encoder_context,
4055                                           struct i965_gpe_context *gpe_context)
4056 {
4057     struct i965_encoder_vp8_context *vp8_context = encoder_context->vme_context;
4058     struct vp8_brc_update_curbe_data *pcmd = i965_gpe_context_map_curbe(gpe_context);
4059     VAEncPictureParameterBufferVP8 *pic_param = (VAEncPictureParameterBufferVP8 *)encode_state->pic_param_ext->buffer;
4060     VAQMatrixBufferVP8 *quant_param = (VAQMatrixBufferVP8 *)encode_state->q_matrix->buffer;
4061     int is_intra = (vp8_context->frame_type == MPEG_I_PICTURE);
4062
4063     if (!pcmd)
4064         return;
4065
4066     memset(pcmd, 0, sizeof(*pcmd));
4067
4068     pcmd->dw2.picture_header_size = 0;
4069
4070     pcmd->dw3.start_global_adjust_frame0 = 10;
4071     pcmd->dw3.start_global_adjust_frame1= 50;
4072
4073     pcmd->dw4.start_global_adjust_frame2 = 100;
4074     pcmd->dw4.start_global_adjust_frame3 = 150;
4075
4076     pcmd->dw5.target_size_flag = 0;
4077
4078     if (vp8_context->brc_init_current_target_buf_full_in_bits > (double)vp8_context->brc_init_reset_buf_size_in_bits) {
4079         vp8_context->brc_init_current_target_buf_full_in_bits -= (double)vp8_context->brc_init_reset_buf_size_in_bits;
4080         pcmd->dw5.target_size_flag = 1;
4081     }
4082
4083     pcmd->dw0.target_size = (unsigned int)vp8_context->brc_init_current_target_buf_full_in_bits;
4084
4085     pcmd->dw5.curr_frame_type = is_intra ? 2 : 0;
4086     pcmd->dw5.brc_flag = 16 * vp8_context->internal_rate_mode;
4087     pcmd->dw5.max_num_paks = vp8_context->num_brc_pak_passes;
4088
4089     pcmd->dw6.tid = 0;
4090     pcmd->dw6.num_t_levels = 1;
4091
4092     pcmd->dw8.start_global_adjust_mult0 = 1;
4093     pcmd->dw8.start_global_adjust_mult1 = 1;
4094     pcmd->dw8.start_global_adjust_mult2 = 3;
4095     pcmd->dw8.start_global_adjust_mult3 = 2;
4096
4097     pcmd->dw9.start_global_adjust_div0 = 40;
4098     pcmd->dw9.start_global_adjust_div1 = 5;
4099     pcmd->dw9.start_global_adjust_div2 = 5;
4100     pcmd->dw9.start_global_adjust_mult4 = 1;
4101
4102     pcmd->dw10.start_global_adjust_div3 = 3;
4103     pcmd->dw10.start_global_adjust_div4 = 1;
4104     pcmd->dw10.qp_threshold0 = 20;
4105     pcmd->dw10.qp_threshold1 = 40;
4106
4107     pcmd->dw11.qp_threshold2 = 60;
4108     pcmd->dw11.qp_threshold3 = 90;
4109     pcmd->dw11.g_rate_ratio_threshold0 = 40;
4110     pcmd->dw11.g_rate_ratio_threshold1 = 75;
4111
4112     pcmd->dw12.g_rate_ratio_threshold2 = 97;
4113     pcmd->dw12.g_rate_ratio_threshold3 = 103;
4114     pcmd->dw12.g_rate_ratio_threshold4 = 125;
4115     pcmd->dw12.g_rate_ratio_threshold5 = 160;
4116
4117     pcmd->dw13.g_rate_ratio_threshold_qp0 = -3;
4118     pcmd->dw13.g_rate_ratio_threshold_qp1 = -2;
4119     pcmd->dw13.g_rate_ratio_threshold_qp2 = -1;
4120     pcmd->dw13.g_rate_ratio_threshold_qp3 = 0;
4121
4122     pcmd->dw14.g_rate_ratio_threshold_qp4 = 1;
4123     pcmd->dw14.g_rate_ratio_threshold_qp5 = 2;
4124     pcmd->dw14.g_rate_ratio_threshold_qp6 = 3;
4125     pcmd->dw14.index_of_previous_qp = 0;
4126
4127     pcmd->dw15.frame_width_in_mb = vp8_context->frame_width_in_mbs;
4128     pcmd->dw15.frame_height_in_mb = vp8_context->frame_height_in_mbs;
4129
4130     pcmd->dw16.p_frame_qp_seg0 = quant_param->quantization_index[0];
4131     pcmd->dw16.p_frame_qp_seg1 = quant_param->quantization_index[1];
4132     pcmd->dw16.p_frame_qp_seg2 = quant_param->quantization_index[2];
4133     pcmd->dw16.p_frame_qp_seg3 = quant_param->quantization_index[3];
4134
4135     pcmd->dw17.key_frame_qp_seg0 = quant_param->quantization_index[0];
4136     pcmd->dw17.key_frame_qp_seg1 = quant_param->quantization_index[1];
4137     pcmd->dw17.key_frame_qp_seg2 = quant_param->quantization_index[2];
4138     pcmd->dw17.key_frame_qp_seg3 = quant_param->quantization_index[3];
4139
4140     pcmd->dw18.qdelta_plane0 = 0;
4141     pcmd->dw18.qdelta_plane1 = 0;
4142     pcmd->dw18.qdelta_plane2 = 0;
4143     pcmd->dw18.qdelta_plane3 = 0;
4144
4145     pcmd->dw19.qdelta_plane4 = 0;
4146     pcmd->dw19.main_ref = is_intra ? 0 : mainref_table_vp8[vp8_context->ref_frame_ctrl];
4147     pcmd->dw19.ref_frame_flags = is_intra ? 0 : vp8_context->ref_frame_ctrl;
4148
4149     pcmd->dw20.seg_on = pic_param->pic_flags.bits.segmentation_enabled;
4150     pcmd->dw20.brc_method = vp8_context->internal_rate_mode;
4151     pcmd->dw20.mb_rc = 0;
4152
4153     pcmd->dw20.vme_intra_prediction = (encoder_context->quality_level == ENCODER_LOW_QUALITY) ? 1 : 0;
4154
4155     pcmd->dw22.historyt_buffer_bti = VP8_BTI_BRC_UPDATE_HISTORY;
4156     pcmd->dw23.pak_statistics_bti = VP8_BTI_BRC_UPDATE_PAK_STATISTICS_OUTPUT;
4157     pcmd->dw24.mfx_vp8_encoder_cfg_read_bti = VP8_BTI_BRC_UPDATE_MFX_ENCODER_CFG_READ;
4158     pcmd->dw25.mfx_vp8_encoder_cfg_write_bti = VP8_BTI_BRC_UPDATE_MFX_ENCODER_CFG_WRITE;
4159     pcmd->dw26.mbenc_curbe_read_bti = VP8_BTI_BRC_UPDATE_MBENC_CURBE_READ;
4160     pcmd->dw27.mbenc_curbe_write_bti = VP8_BTI_BRC_UPDATE_MBENC_CURBE_WRITE;
4161     pcmd->dw28.distortion_bti = VP8_BTI_BRC_UPDATE_DISTORTION_SURFACE;
4162     pcmd->dw29.constant_data_bti = VP8_BTI_BRC_UPDATE_CONSTANT_DATA;
4163     pcmd->dw30.segment_map_bti = VP8_BTI_BRC_UPDATE_SEGMENT_MAP;
4164     pcmd->dw31.mpu_curbe_read_bti = VP8_BTI_BRC_UPDATE_MPU_CURBE_READ;
4165     pcmd->dw32.mpu_curbe_write_bti = VP8_BTI_BRC_UPDATE_MPU_CURBE_WRITE;
4166     pcmd->dw33.tpu_curbe_read_bti = VP8_BTI_BRC_UPDATE_TPU_CURBE_READ;
4167     pcmd->dw34.tpu_curbe_write_bti = VP8_BTI_BRC_UPDATE_TPU_CURBE_WRITE;
4168
4169     vp8_context->brc_init_current_target_buf_full_in_bits += vp8_context->brc_init_reset_input_bits_per_frame;
4170
4171     i965_gpe_context_unmap_curbe(gpe_context);
4172 }
4173
4174 static void
4175 i965_encoder_vp8_vme_mpu_set_curbe(VADriverContextP ctx,
4176                                    struct encode_state *encode_state,
4177                                    struct intel_encoder_context *encoder_context,
4178                                    struct i965_gpe_context *gpe_context);
4179 static void
4180 i965_encoder_vp8_pak_tpu_set_curbe(VADriverContextP ctx,
4181                                    struct encode_state *encode_state,
4182                                    struct intel_encoder_context *encoder_context,
4183                                    struct i965_gpe_context *gpe_context);
4184
4185 static void
4186 i965_encoder_vp8_vme_brc_update_add_surfaces(VADriverContextP ctx,
4187                                              struct encode_state *encode_state,
4188                                              struct intel_encoder_context *encoder_context,
4189                                              struct i965_gpe_context *gpe_context,
4190                                              struct brc_update_surface_parameters *params)
4191 {
4192     struct i965_encoder_vp8_context *vp8_context = encoder_context->vme_context;
4193     unsigned int size;
4194     int is_intra = (vp8_context->frame_type == MPEG_I_PICTURE);
4195
4196     /* BRC history buffer */
4197     size = VP8_BRC_HISTORY_BUFFER_SIZE;
4198     i965_add_buffer_gpe_surface(ctx,
4199                                 encoder_context,
4200                                 gpe_context,
4201                                 &vp8_context->brc_history_buffer,
4202                                 0,
4203                                 size,
4204                                 0,
4205                                 VP8_BTI_BRC_UPDATE_HISTORY);
4206
4207     /* PAK Statistics buffer */
4208     size = sizeof(struct vp8_brc_pak_statistics);
4209     i965_add_buffer_gpe_surface(ctx,
4210                                 encoder_context,
4211                                 gpe_context,
4212                                 &vp8_context->brc_pak_statistics_buffer,
4213                                 0,
4214                                 size,
4215                                 0,
4216                                 VP8_BTI_BRC_UPDATE_PAK_STATISTICS_OUTPUT);
4217
4218     /* Encoder CFG command surface - read only */
4219     size = VP8_BRC_IMG_STATE_SIZE_PER_PASS * VP8_BRC_MAXIMUM_NUM_PASSES;
4220     i965_add_buffer_gpe_surface(ctx,
4221                                 encoder_context,
4222                                 gpe_context,
4223                                 &vp8_context->brc_vp8_cfg_command_write_buffer,
4224                                 0,
4225                                 size,
4226                                 0,
4227                                 VP8_BTI_BRC_UPDATE_MFX_ENCODER_CFG_READ);
4228
4229     /* Encoder CFG command surface - write only */
4230     i965_add_buffer_gpe_surface(ctx,
4231                                 encoder_context,
4232                                 gpe_context,
4233                                 &vp8_context->brc_vp8_cfg_command_write_buffer,
4234                                 0,
4235                                 size,
4236                                 0,
4237                                 VP8_BTI_BRC_UPDATE_MFX_ENCODER_CFG_WRITE);
4238
4239     /* MBEnc CURBE Buffer - read only */
4240     size = ALIGN(params->mbenc_gpe_context->curbe.length, 64);
4241     i965_add_dri_buffer_gpe_surface(ctx,
4242                                     encoder_context,
4243                                     gpe_context,
4244                                     params->mbenc_gpe_context->curbe.bo,
4245                                     0,
4246                                     size,
4247                                     params->mbenc_gpe_context->curbe.offset,
4248                                     VP8_BTI_BRC_UPDATE_MBENC_CURBE_READ);
4249
4250     /* MBEnc CURBE Buffer - write only */
4251     i965_add_dri_buffer_gpe_surface(ctx,
4252                                     encoder_context,
4253                                     gpe_context,
4254                                     params->mbenc_gpe_context->curbe.bo,
4255                                     0,
4256                                     size,
4257                                     params->mbenc_gpe_context->curbe.offset,
4258                                     VP8_BTI_BRC_UPDATE_MBENC_CURBE_WRITE);
4259
4260     /* BRC Distortion data buffer - input/output */
4261     i965_add_buffer_2d_gpe_surface(ctx,
4262                                    encoder_context,
4263                                    gpe_context,
4264                                    is_intra ? &vp8_context->brc_distortion_buffer : &vp8_context->me_4x_distortion_buffer,
4265                                    1,
4266                                    I965_SURFACEFORMAT_R8_UNORM,
4267                                    VP8_BTI_BRC_UPDATE_DISTORTION_SURFACE);
4268
4269     /* Constant Data Surface */
4270     size = VP8_BRC_CONSTANT_DATA_SIZE;
4271     i965_add_buffer_gpe_surface(ctx,
4272                                 encoder_context,
4273                                 gpe_context,
4274                                 &vp8_context->brc_vp8_constant_data_buffer,
4275                                 0,
4276                                 size,
4277                                 0,
4278                                 VP8_BTI_BRC_UPDATE_CONSTANT_DATA);
4279
4280     /* Segmap surface */
4281     i965_add_buffer_2d_gpe_surface(ctx,
4282                                    encoder_context,
4283                                    gpe_context,
4284                                    &vp8_context->brc_segment_map_buffer,
4285                                    0,
4286                                    I965_SURFACEFORMAT_R8_UNORM,
4287                                    VP8_BTI_BRC_UPDATE_SEGMENT_MAP);
4288
4289     /* MPU CURBE Buffer - read only */
4290     size = ALIGN(params->mpu_gpe_context->curbe.length, 64);
4291     i965_add_dri_buffer_gpe_surface(ctx,
4292                                     encoder_context,
4293                                     gpe_context,
4294                                     params->mpu_gpe_context->curbe.bo,
4295                                     0,
4296                                     size,
4297                                     params->mpu_gpe_context->curbe.offset,
4298                                     VP8_BTI_BRC_UPDATE_MPU_CURBE_READ);
4299
4300     /* MPU CURBE Buffer - write only */
4301     size = ALIGN(params->mpu_gpe_context->curbe.length, 64);
4302     i965_add_dri_buffer_gpe_surface(ctx,
4303                                     encoder_context,
4304                                     gpe_context,
4305                                     params->mpu_gpe_context->curbe.bo,
4306                                     0,
4307                                     size,
4308                                     params->mpu_gpe_context->curbe.offset,
4309                                     VP8_BTI_BRC_UPDATE_MPU_CURBE_WRITE);
4310
4311     /* TPU CURBE Buffer - read only */
4312     size = ALIGN(params->tpu_gpe_context->curbe.length, 64);
4313     i965_add_dri_buffer_gpe_surface(ctx,
4314                                     encoder_context,
4315                                     gpe_context,
4316                                     params->tpu_gpe_context->curbe.bo,
4317                                     0,
4318                                     size,
4319                                     params->tpu_gpe_context->curbe.offset,
4320                                     VP8_BTI_BRC_UPDATE_TPU_CURBE_READ);
4321
4322     /* TPU CURBE Buffer - write only */
4323     size = ALIGN(params->tpu_gpe_context->curbe.length, 64);
4324     i965_add_dri_buffer_gpe_surface(ctx,
4325                                     encoder_context,
4326                                     gpe_context,
4327                                     params->tpu_gpe_context->curbe.bo,
4328                                     0,
4329                                     size,
4330                                     params->tpu_gpe_context->curbe.offset,
4331                                     VP8_BTI_BRC_UPDATE_TPU_CURBE_WRITE);
4332 }
4333
4334 static void
4335 i965_encoder_vp8_vme_init_brc_update_constant_data(VADriverContextP ctx,
4336                                                    struct encode_state *encode_state,
4337                                                    struct intel_encoder_context *encoder_context)
4338 {
4339     struct i965_encoder_vp8_context *vp8_context = encoder_context->vme_context;
4340     char *pbuffer;
4341
4342     pbuffer = i965_map_gpe_resource(&vp8_context->brc_vp8_constant_data_buffer);
4343
4344     if (!pbuffer)
4345         return;
4346
4347     memcpy(pbuffer,
4348            brc_qpadjustment_distthreshold_maxframethreshold_distqpadjustment_ipb_vp8,
4349            sizeof(brc_qpadjustment_distthreshold_maxframethreshold_distqpadjustment_ipb_vp8));
4350     pbuffer += sizeof(brc_qpadjustment_distthreshold_maxframethreshold_distqpadjustment_ipb_vp8);
4351
4352     memcpy(pbuffer, brc_iframe_cost_vp8, sizeof(brc_iframe_cost_vp8));
4353     pbuffer += sizeof(brc_iframe_cost_vp8);
4354
4355     memcpy(pbuffer, brc_pframe_cost_vp8, sizeof(brc_pframe_cost_vp8));
4356     pbuffer += sizeof(brc_pframe_cost_vp8);
4357
4358     memcpy(pbuffer, quant_dc_vp8, sizeof(quant_dc_vp8));
4359     pbuffer += sizeof(quant_dc_vp8);
4360
4361     memcpy(pbuffer, quant_ac_vp8, sizeof(quant_ac_vp8));
4362     pbuffer += sizeof(quant_ac_vp8);
4363
4364     memcpy(pbuffer, brc_skip_mv_threshold_vp8, sizeof(brc_skip_mv_threshold_vp8));
4365
4366     i965_unmap_gpe_resource(&vp8_context->brc_vp8_constant_data_buffer);
4367 }
4368
4369 static void
4370 i965_encoder_vp8_vme_init_mfx_config_command(VADriverContextP ctx,
4371                                              struct encode_state *encode_state,
4372                                              struct intel_encoder_context *encoder_context,
4373                                              struct vp8_mpu_encoder_config_parameters *params);
4374
4375 static VAStatus
4376 i965_encoder_vp8_vme_brc_update(VADriverContextP ctx,
4377                                 struct encode_state *encode_state,
4378                                 struct intel_encoder_context *encoder_context)
4379 {
4380     struct i965_encoder_vp8_context *vp8_context = encoder_context->vme_context;
4381     struct i965_encoder_vp8_brc_update_context *brc_update_context = &vp8_context->brc_update_context;
4382     struct i965_encoder_vp8_mbenc_context *mbenc_context = &vp8_context->mbenc_context;
4383     struct i965_encoder_vp8_mpu_context *mpu_context = &vp8_context->mpu_context;
4384     struct i965_encoder_vp8_tpu_context *tpu_context = &vp8_context->tpu_context;
4385     struct i965_gpe_table *gpe = vp8_context->gpe_table;
4386     struct i965_gpe_context *gpe_context, *mbenc_gpe_context, *mpu_gpe_context, *tpu_gpe_context;
4387     struct brc_update_surface_parameters brc_update_surface_params;
4388     struct gpe_media_object_parameter media_object_param;
4389     struct vp8_mpu_encoder_config_parameters config_params;
4390     VAEncPictureParameterBufferVP8 *pic_param = (VAEncPictureParameterBufferVP8 *)encode_state->pic_param_ext->buffer;
4391     unsigned int ref_frame_flag_final, ref_frame_flag;
4392     int is_intra = (vp8_context->frame_type == MPEG_I_PICTURE);
4393     int media_function = VP8_MEDIA_STATE_BRC_UPDATE;
4394     int i;
4395
4396     gpe_context = &brc_update_context->gpe_contexts[0];
4397
4398     if (is_intra)
4399         mbenc_gpe_context = &mbenc_context->gpe_contexts[VP8_MBENC_I_FRAME_LUMA];
4400     else
4401         mbenc_gpe_context = &mbenc_context->gpe_contexts[VP8_MBENC_P_FRAME];
4402
4403     mpu_gpe_context = &mpu_context->gpe_contexts[0];
4404     tpu_gpe_context = &tpu_context->gpe_contexts[0];
4405
4406     if (!is_intra) {
4407         ref_frame_flag = VP8_REF_FLAG_ALL;
4408
4409         if (pic_param->ref_last_frame == pic_param->ref_gf_frame) {
4410             ref_frame_flag &= ~VP8_REF_FLAG_GOLDEN;
4411         }
4412
4413         if (pic_param->ref_last_frame == pic_param->ref_arf_frame) {
4414             ref_frame_flag &= ~VP8_REF_FLAG_ALT;
4415         }
4416
4417         if (pic_param->ref_gf_frame == pic_param->ref_arf_frame) {
4418             ref_frame_flag &= ~VP8_REF_FLAG_ALT;
4419         }
4420     } else {
4421         ref_frame_flag = VP8_REF_FLAG_LAST;
4422     }
4423
4424     switch (vp8_context->ref_frame_ctrl) {
4425     case 0:
4426         ref_frame_flag_final = VP8_REF_FLAG_NONE;
4427         break;
4428
4429     case 1:
4430         ref_frame_flag_final = VP8_REF_FLAG_LAST;       // Last Ref only
4431         break;
4432
4433     case 2:
4434         ref_frame_flag_final = VP8_REF_FLAG_GOLDEN;     // Gold Ref only
4435         break;
4436
4437     case 4:
4438         ref_frame_flag_final = VP8_REF_FLAG_ALT;        // Alt Ref only
4439         break;
4440
4441     default:
4442         ref_frame_flag_final = ref_frame_flag;
4443     }
4444
4445     vp8_context->ref_frame_ctrl = ref_frame_flag_final;
4446     i965_encoder_vp8_vme_mbenc_set_curbe(ctx, encode_state, encoder_context, mbenc_gpe_context);
4447     vp8_context->mbenc_curbe_updated_in_brc_update = 1;
4448
4449     /* Set MPU & TPU curbe here */
4450     i965_encoder_vp8_vme_mpu_set_curbe(ctx, encode_state, encoder_context, mpu_gpe_context);
4451     vp8_context->mpu_curbe_updated_in_brc_update = 1;
4452
4453     i965_encoder_vp8_pak_tpu_set_curbe(ctx, encode_state, encoder_context, tpu_gpe_context);
4454     vp8_context->tpu_curbe_updated_in_brc_update = 1;
4455
4456     gpe->context_init(ctx, gpe_context);
4457     gpe->reset_binding_table(ctx, gpe_context);
4458
4459     i965_encoder_vp8_vme_brc_update_set_curbe(ctx, encode_state, encoder_context, gpe_context);
4460
4461     if (vp8_context->brc_constant_buffer_supported) {
4462         i965_encoder_vp8_vme_init_brc_update_constant_data(ctx, encode_state, encoder_context);
4463     }
4464
4465     memset(&config_params, 0, sizeof(config_params));
4466     config_params.buffer_size = VP8_HEADER_METADATA_SIZE;
4467     config_params.config_buffer = &vp8_context->brc_vp8_cfg_command_write_buffer;
4468
4469     for (i = 0; i < VP8_BRC_MAXIMUM_NUM_PASSES; i++) {
4470         config_params.is_first_pass = !i;
4471         config_params.command_offset = i * VP8_HEADER_METADATA_SIZE;
4472         i965_encoder_vp8_vme_init_mfx_config_command(ctx, encode_state, encoder_context, &config_params);
4473     }
4474
4475     vp8_context->mfx_encoder_config_command_initialized = 1;
4476
4477     memset(&brc_update_surface_params, 0, sizeof(brc_update_surface_params));
4478     brc_update_surface_params.mbenc_gpe_context = mbenc_gpe_context;
4479     brc_update_surface_params.mpu_gpe_context = mpu_gpe_context;
4480     brc_update_surface_params.tpu_gpe_context = tpu_gpe_context;
4481     i965_encoder_vp8_vme_brc_update_add_surfaces(ctx, encode_state, encoder_context, gpe_context, &brc_update_surface_params);
4482
4483     gpe->setup_interface_data(ctx, gpe_context);
4484
4485     memset(&media_object_param, 0, sizeof(media_object_param));
4486     i965_run_kernel_media_object(ctx, encoder_context, gpe_context, media_function, &media_object_param);
4487
4488     return VA_STATUS_SUCCESS;
4489 }
4490
4491 static void
4492 i965_encoder_vp8_vme_mpu_set_curbe(VADriverContextP ctx,
4493                                    struct encode_state *encode_state,
4494                                    struct intel_encoder_context *encoder_context,
4495                                    struct i965_gpe_context *gpe_context)
4496 {
4497     struct i965_encoder_vp8_context *vp8_context = encoder_context->vme_context;
4498     struct vp8_mpu_curbe_data *pcmd = i965_gpe_context_map_curbe(gpe_context);
4499     VAEncSequenceParameterBufferVP8 *seq_param = (VAEncSequenceParameterBufferVP8 *)encode_state->seq_param_ext->buffer;
4500     VAEncPictureParameterBufferVP8 *pic_param = (VAEncPictureParameterBufferVP8 *)encode_state->pic_param_ext->buffer;
4501     VAQMatrixBufferVP8 *quant_param = (VAQMatrixBufferVP8 *)encode_state->q_matrix->buffer;
4502
4503     if (!pcmd)
4504         return;
4505
4506     memset(pcmd, 0, sizeof(*pcmd));
4507
4508     pcmd->dw0.frame_width = vp8_context->frame_width;
4509     pcmd->dw0.frame_height = vp8_context->frame_height;
4510
4511     pcmd->dw1.frame_type = pic_param->pic_flags.bits.frame_type;
4512     pcmd->dw1.version = pic_param->pic_flags.bits.version;
4513     pcmd->dw1.show_frame = pic_param->pic_flags.bits.show_frame;
4514     pcmd->dw1.horizontal_scale_code = seq_param->frame_width_scale;
4515     pcmd->dw1.vertical_scale_code = seq_param->frame_height_scale;
4516     pcmd->dw1.color_space_type = pic_param->pic_flags.bits.color_space;
4517     pcmd->dw1.clamp_type = pic_param->pic_flags.bits.clamping_type;
4518     pcmd->dw1.partition_num_l2 = pic_param->pic_flags.bits.num_token_partitions;
4519     pcmd->dw1.enable_segmentation = pic_param->pic_flags.bits.segmentation_enabled;
4520     pcmd->dw1.seg_map_update = pic_param->pic_flags.bits.segmentation_enabled ? pic_param->pic_flags.bits.update_mb_segmentation_map : 0;
4521     pcmd->dw1.segmentation_feature_update = pic_param->pic_flags.bits.update_segment_feature_data;
4522     pcmd->dw1.segmentation_feature_mode = 1;
4523     pcmd->dw1.loop_filter_type = pic_param->pic_flags.bits.loop_filter_type;
4524     pcmd->dw1.sharpness_level = pic_param->sharpness_level;
4525     pcmd->dw1.loop_filter_adjustment_on = pic_param->pic_flags.bits.loop_filter_adj_enable;
4526     pcmd->dw1.mb_no_coeffiscient_skip = pic_param->pic_flags.bits.mb_no_coeff_skip;
4527     pcmd->dw1.golden_reference_copy_flag = pic_param->pic_flags.bits.copy_buffer_to_golden;
4528     pcmd->dw1.alternate_reference_copy_flag = pic_param->pic_flags.bits.copy_buffer_to_alternate;
4529     pcmd->dw1.last_frame_update = pic_param->pic_flags.bits.refresh_last;
4530     pcmd->dw1.sign_bias_golden = pic_param->pic_flags.bits.sign_bias_golden;
4531     pcmd->dw1.sign_bias_alt_ref = pic_param->pic_flags.bits.sign_bias_alternate;
4532     pcmd->dw1.refresh_entropy_p = pic_param->pic_flags.bits.refresh_entropy_probs;
4533
4534     pcmd->dw2.loop_filter_level = pic_param->loop_filter_level[0];
4535     pcmd->dw2.qindex = quant_param->quantization_index[0];
4536     pcmd->dw2.y1_dc_qindex = quant_param->quantization_index_delta[0];
4537     pcmd->dw2.y2_dc_qindex = quant_param->quantization_index_delta[3];
4538
4539     pcmd->dw3.y2_ac_qindex = quant_param->quantization_index_delta[4];
4540     pcmd->dw3.uv_dc_qindex = quant_param->quantization_index_delta[1];
4541     pcmd->dw3.uv_ac_qindex = quant_param->quantization_index_delta[2];
4542     pcmd->dw3.feature_data0_segment0 = quant_param->quantization_index[0];
4543
4544     pcmd->dw4.feature_data0_segment1 = quant_param->quantization_index[1];
4545     pcmd->dw4.feature_data0_segment2 = quant_param->quantization_index[2];
4546     pcmd->dw4.feature_data0_segment3 = quant_param->quantization_index[3];
4547     pcmd->dw4.feature_data1_segment0 = pic_param->loop_filter_level[0];
4548
4549     pcmd->dw5.feature_data1_segment1 = pic_param->loop_filter_level[1];
4550     pcmd->dw5.feature_data1_segment2 = pic_param->loop_filter_level[2];
4551     pcmd->dw5.feature_data1_segment3 = pic_param->loop_filter_level[3];
4552     pcmd->dw5.ref_lf_delta0 = pic_param->ref_lf_delta[0];
4553
4554     pcmd->dw6.ref_lf_delta1 = pic_param->ref_lf_delta[1];
4555     pcmd->dw6.ref_lf_delta2 = pic_param->ref_lf_delta[2];
4556     pcmd->dw6.ref_lf_delta3 = pic_param->ref_lf_delta[3];
4557     pcmd->dw6.mode_lf_delta0 = pic_param->mode_lf_delta[0];
4558
4559     pcmd->dw7.mode_lf_delta1 = pic_param->mode_lf_delta[1];
4560     pcmd->dw7.mode_lf_delta2 = pic_param->mode_lf_delta[2];
4561     pcmd->dw7.mode_lf_delta3 = pic_param->mode_lf_delta[3];
4562     pcmd->dw7.mc_filter_select = pic_param->pic_flags.bits.version > 0 ? 1 : 0;
4563     pcmd->dw7.chroma_full_pixel_mc_filter_mode = pic_param->pic_flags.bits.version < 3 ? 0 : 1;
4564     pcmd->dw7.max_num_pak_passes = vp8_context->num_brc_pak_passes;
4565     pcmd->dw7.forced_token_surface_read = 1;
4566     pcmd->dw7.mode_cost_enable_flag = 1;
4567
4568     pcmd->dw8.num_t_levels = 1;
4569     pcmd->dw8.temporal_layer_id = 0;
4570
4571     pcmd->dw12.histogram_bti = VP8_BTI_MPU_HISTOGRAM;
4572     pcmd->dw13.reference_mode_probability_bti = VP8_BTI_MPU_REF_MODE_PROBABILITY;
4573     pcmd->dw14.mode_probability_bti = VP8_BTI_MPU_CURR_MODE_PROBABILITY;
4574     pcmd->dw15.reference_token_probability_bti = VP8_BTI_MPU_REF_TOKEN_PROBABILITY;
4575     pcmd->dw16.token_probability_bti = VP8_BTI_MPU_CURR_TOKEN_PROBABILITY;
4576     pcmd->dw17.frame_header_bitstream_bti = VP8_BTI_MPU_HEADER_BITSTREAM;
4577     pcmd->dw18.header_meta_data_bti = VP8_BTI_MPU_HEADER_METADATA;
4578     pcmd->dw19.picture_state_bti = VP8_BTI_MPU_PICTURE_STATE;
4579     pcmd->dw20.mpu_bitstream_bti = VP8_BTI_MPU_MPU_BITSTREAM;
4580     pcmd->dw21.token_bits_data_bti = VP8_BTI_MPU_TOKEN_BITS_DATA_TABLE;
4581     pcmd->dw22.kernel_debug_dump_bti = VP8_BTI_MPU_VME_DEBUG_STREAMOUT;
4582     pcmd->dw23.entropy_cost_bti = VP8_BTI_MPU_ENTROPY_COST_TABLE;
4583     pcmd->dw24.mode_cost_update_bti = VP8_BTI_MPU_MODE_COST_UPDATE;
4584
4585     i965_gpe_context_unmap_curbe(gpe_context);
4586 }
4587
4588 static void
4589 i965_encoder_vp8_vme_mpu_add_surfaces(VADriverContextP ctx,
4590                                       struct encode_state *encode_state,
4591                                       struct intel_encoder_context *encoder_context,
4592                                       struct i965_gpe_context *gpe_context)
4593 {
4594     struct i965_encoder_vp8_context *vp8_context = encoder_context->vme_context;
4595     unsigned int size;
4596     unsigned char brc_enabled = (vp8_context->internal_rate_mode == I965_BRC_CBR ||
4597                                  vp8_context->internal_rate_mode == I965_BRC_VBR);
4598
4599     /* Histogram buffer */
4600     size = VP8_HISTOGRAM_SIZE;
4601     i965_add_buffer_gpe_surface(ctx,
4602                                 encoder_context,
4603                                 gpe_context,
4604                                 &vp8_context->histogram_buffer,
4605                                 1,
4606                                 size,
4607                                 0,
4608                                 VP8_BTI_MPU_HISTOGRAM);
4609
4610     // Reference mode probability
4611     size = VP8_MODE_PROPABILITIES_SIZE;
4612     i965_add_buffer_gpe_surface(ctx,
4613                                 encoder_context,
4614                                 gpe_context,
4615                                 &vp8_context->pak_mpu_tpu_ref_mode_probs_buffer,
4616                                 1,
4617                                 size,
4618                                 0,
4619                                 VP8_BTI_MPU_REF_MODE_PROBABILITY);
4620
4621     // Mode probability
4622     i965_add_buffer_gpe_surface(ctx,
4623                                 encoder_context,
4624                                 gpe_context,
4625                                 &vp8_context->pak_mpu_tpu_mode_probs_buffer,
4626                                 1,
4627                                 size,
4628                                 0,
4629                                 VP8_BTI_MPU_CURR_MODE_PROBABILITY);
4630
4631     // Reference Token probability
4632     size = VP8_COEFFS_PROPABILITIES_SIZE;
4633     i965_add_buffer_gpe_surface(ctx,
4634                                 encoder_context,
4635                                 gpe_context,
4636                                 &vp8_context->pak_mpu_tpu_ref_coeff_probs_buffer,
4637                                 1,
4638                                 size,
4639                                 0,
4640                                 VP8_BTI_MPU_REF_TOKEN_PROBABILITY);
4641
4642     // Token probability
4643     i965_add_buffer_gpe_surface(ctx,
4644                                 encoder_context,
4645                                 gpe_context,
4646                                 &vp8_context->pak_mpu_tpu_coeff_probs_buffer,
4647                                 1,
4648                                 size,
4649                                 0,
4650                                 VP8_BTI_MPU_CURR_TOKEN_PROBABILITY);
4651
4652     // Frame header
4653     size = VP8_FRAME_HEADER_SIZE;
4654     i965_add_buffer_gpe_surface(ctx,
4655                                 encoder_context,
4656                                 gpe_context,
4657                                 &vp8_context->pak_frame_header_buffer,
4658                                 0,
4659                                 size,
4660                                 0,
4661                                 VP8_BTI_MPU_HEADER_BITSTREAM);
4662
4663     // Header Metadata
4664     size = VP8_HEADER_METADATA_SIZE;
4665
4666     if (brc_enabled) {
4667         i965_add_buffer_gpe_surface(ctx,
4668                                     encoder_context,
4669                                     gpe_context,
4670                                     &vp8_context->brc_vp8_cfg_command_write_buffer,
4671                                     0,
4672                                     size,
4673                                     0,
4674                                     VP8_BTI_MPU_HEADER_METADATA);
4675     } else {
4676         i965_add_buffer_gpe_surface(ctx,
4677                                     encoder_context,
4678                                     gpe_context,
4679                                     &vp8_context->pak_mpu_tpu_picture_state_buffer,
4680                                     0,
4681                                     size,
4682                                     VP8_HEADER_METADATA_OFFSET,
4683                                     VP8_BTI_MPU_HEADER_METADATA);
4684     }
4685
4686     // Picture state MFX_VP8_PIC_STATE
4687     size = 38 * sizeof(unsigned int);
4688     i965_add_buffer_gpe_surface(ctx,
4689                                 encoder_context,
4690                                 gpe_context,
4691                                 &vp8_context->pak_mpu_tpu_picture_state_buffer,
4692                                 0,
4693                                 size,
4694                                 0,
4695                                 VP8_BTI_MPU_PICTURE_STATE);
4696
4697     // Mpu Bitstream
4698     size = VP8_MPU_BITSTREAM_SIZE;
4699     i965_add_buffer_gpe_surface(ctx,
4700                                 encoder_context,
4701                                 gpe_context,
4702                                 &vp8_context->pak_mpu_tpu_mpu_bitstream_buffer,
4703                                 0,
4704                                 size,
4705                                 0,
4706                                 VP8_BTI_MPU_MPU_BITSTREAM);
4707
4708     // Token bits Data Surface
4709     size = VP8_TOKEN_BITS_DATA_SIZE;
4710     i965_add_buffer_gpe_surface(ctx,
4711                                 encoder_context,
4712                                 gpe_context,
4713                                 &vp8_context->pak_mpu_tpu_token_bits_data_buffer,
4714                                 1,
4715                                 size,
4716                                 0,
4717                                 VP8_BTI_MPU_TOKEN_BITS_DATA_TABLE);
4718
4719     // Entropy cost table
4720     size = VP8_ENTROPY_COST_TABLE_SIZE;
4721     i965_add_buffer_gpe_surface(ctx,
4722                                 encoder_context,
4723                                 gpe_context,
4724                                 &vp8_context->pak_mpu_tpu_entropy_cost_table_buffer,
4725                                 1,
4726                                 size,
4727                                 0,
4728                                 VP8_BTI_MPU_ENTROPY_COST_TABLE);
4729
4730     //Mode Cost Update Surface
4731     size = 16 * sizeof(unsigned int);
4732     i965_add_buffer_gpe_surface(ctx,
4733                                 encoder_context,
4734                                 gpe_context,
4735                                 &vp8_context->mode_cost_update_buffer,
4736                                 0,
4737                                 size,
4738                                 0,
4739                                 VP8_BTI_MPU_MODE_COST_UPDATE);
4740 }
4741
4742 static void
4743 i965_encoder_vp8_vme_update_key_frame_mpu_tpu_buffer(VADriverContextP ctx,
4744                                                      struct encode_state *encode_state,
4745                                                      struct intel_encoder_context *encoder_context)
4746 {
4747     struct i965_encoder_vp8_context *vp8_context = encoder_context->vme_context;
4748     char *key_buffer, *pbuffer;
4749
4750     key_buffer = i965_map_gpe_resource(&vp8_context->pak_mpu_tpu_key_frame_token_probability_buffer);
4751
4752     if (!key_buffer)
4753         return;
4754
4755     pbuffer = i965_map_gpe_resource(&vp8_context->pak_mpu_tpu_coeff_probs_buffer);
4756
4757     if (!pbuffer) {
4758         i965_unmap_gpe_resource(&vp8_context->pak_mpu_tpu_key_frame_token_probability_buffer);
4759
4760         return;
4761     }
4762
4763     memcpy(pbuffer, key_buffer, VP8_COEFFS_PROPABILITIES_SIZE);
4764     i965_unmap_gpe_resource(&vp8_context->pak_mpu_tpu_coeff_probs_buffer);
4765     i965_unmap_gpe_resource(&vp8_context->pak_mpu_tpu_key_frame_token_probability_buffer);
4766
4767     pbuffer = i965_map_gpe_resource(&vp8_context->pak_mpu_tpu_ref_coeff_probs_buffer);
4768
4769     if (!pbuffer)
4770         return;
4771
4772     memcpy(pbuffer, vp8_default_coef_probs, sizeof(vp8_default_coef_probs));
4773     i965_unmap_gpe_resource(&vp8_context->pak_mpu_tpu_ref_coeff_probs_buffer);
4774
4775     pbuffer = i965_map_gpe_resource(&vp8_context->pak_mpu_tpu_hw_token_probability_pak_pass_2_buffer);
4776
4777     if (!pbuffer)
4778         return;
4779
4780     memcpy(pbuffer, vp8_default_coef_probs, sizeof(vp8_default_coef_probs));
4781     i965_unmap_gpe_resource(&vp8_context->pak_mpu_tpu_hw_token_probability_pak_pass_2_buffer);
4782 }
4783
4784 static void
4785 i965_encoder_vp8_vme_init_mfx_config_command(VADriverContextP ctx,
4786                                              struct encode_state *encode_state,
4787                                              struct intel_encoder_context *encoder_context,
4788                                              struct vp8_mpu_encoder_config_parameters *params)
4789 {
4790     struct i965_encoder_vp8_context *vp8_context = encoder_context->vme_context;
4791     struct vp8_mfx_encoder_cfg_cmd *pcmd;
4792     VAEncSequenceParameterBufferVP8 *seq_param = (VAEncSequenceParameterBufferVP8 *)encode_state->seq_param_ext->buffer;
4793     VAEncPictureParameterBufferVP8 *pic_param = (VAEncPictureParameterBufferVP8 *)encode_state->pic_param_ext->buffer;
4794     VAQMatrixBufferVP8 *quant_param = (VAQMatrixBufferVP8 *)encode_state->q_matrix->buffer;
4795     unsigned int segmentation_enabled = pic_param->pic_flags.bits.segmentation_enabled;
4796     int i;
4797     char *pbuffer;
4798     unsigned char brc_enabled = (vp8_context->internal_rate_mode == I965_BRC_CBR ||
4799                                  vp8_context->internal_rate_mode == I965_BRC_VBR);
4800
4801     pbuffer = i965_map_gpe_resource(params->config_buffer);
4802
4803     if (!pbuffer)
4804         return;
4805
4806     pbuffer += params->command_offset;
4807     memset(pbuffer, 0, params->buffer_size);
4808
4809     pcmd = (struct vp8_mfx_encoder_cfg_cmd *)pbuffer;
4810
4811     pcmd->dw0.value = (MFX_VP8_ENCODER_CFG | (sizeof(*pcmd) / 4 - 2));
4812
4813     pcmd->dw1.rate_control_initial_pass = params->is_first_pass ? 1 : 0;
4814     pcmd->dw1.per_segment_delta_qindex_loop_filter_disable  = (params->is_first_pass || !brc_enabled);
4815     pcmd->dw1.token_statistics_output_enable = 1;
4816
4817     if (segmentation_enabled) {
4818         for (i = 1; i < 4; i++) {
4819             if ((quant_param->quantization_index[i] != quant_param->quantization_index[0]) ||
4820                 (pic_param->loop_filter_level[i] != pic_param->loop_filter_level[0])) {
4821                 pcmd->dw1.update_segment_feature_data_flag = 1;
4822                 break;
4823             }
4824         }
4825     }
4826
4827     if (brc_enabled) {
4828         pcmd->dw2.max_frame_bit_count_rate_control_enable_mask = 1;
4829         pcmd->dw2.min_frame_bit_count_rate_control_enable_mask = 1;
4830     }
4831
4832     pcmd->dw22.show_frame = pic_param->pic_flags.bits.show_frame;
4833     pcmd->dw22.bitstream_format_version = pic_param->pic_flags.bits.version;
4834
4835     pcmd->dw23.horizontal_size_code = ((seq_param->frame_width_scale << 14) | seq_param->frame_width);
4836     pcmd->dw23.vertical_size_code = ((seq_param->frame_height_scale << 14) | seq_param->frame_height);
4837
4838     //Add batch buffer end command
4839     pbuffer += sizeof(*pcmd);
4840     *((unsigned int *)pbuffer) = MI_BATCH_BUFFER_END;
4841
4842     i965_unmap_gpe_resource(params->config_buffer);
4843 }
4844
4845 static VAStatus
4846 i965_encoder_vp8_vme_mpu(VADriverContextP ctx,
4847                          struct encode_state *encode_state,
4848                          struct intel_encoder_context *encoder_context)
4849 {
4850     struct i965_encoder_vp8_context *vp8_context = encoder_context->vme_context;
4851     struct i965_encoder_vp8_mpu_context *mpu_context = &vp8_context->mpu_context;
4852     struct i965_gpe_table *gpe = vp8_context->gpe_table;
4853     struct gpe_media_object_parameter media_object_param;
4854     struct i965_gpe_context *gpe_context;
4855     struct vp8_mpu_encoder_config_parameters config_params;
4856     int media_function = VP8_MEDIA_STATE_MPU;
4857
4858     gpe_context = &mpu_context->gpe_contexts[0];
4859     /* gpe->context_init(ctx, gpe_context); */
4860     gpe->reset_binding_table(ctx, gpe_context);
4861
4862     if (vp8_context->frame_type == MPEG_I_PICTURE)
4863         i965_encoder_vp8_vme_update_key_frame_mpu_tpu_buffer(ctx, encode_state, encoder_context);
4864
4865     if (!vp8_context->mfx_encoder_config_command_initialized) {
4866         memset(&config_params, 0, sizeof(config_params));
4867         config_params.is_first_pass = !vp8_context->curr_pass;
4868         config_params.command_offset = VP8_HEADER_METADATA_OFFSET;
4869         config_params.buffer_size = VP8_PICTURE_STATE_SIZE;
4870         config_params.config_buffer = &vp8_context->pak_mpu_tpu_picture_state_buffer;
4871         i965_encoder_vp8_vme_init_mfx_config_command(ctx, encode_state, encoder_context, &config_params);
4872     }
4873
4874     if (!vp8_context->mpu_curbe_updated_in_brc_update)
4875         i965_encoder_vp8_vme_mpu_set_curbe(ctx, encode_state, encoder_context, gpe_context);
4876
4877     i965_encoder_vp8_vme_mpu_add_surfaces(ctx, encode_state, encoder_context, gpe_context);
4878     gpe->setup_interface_data(ctx, gpe_context);
4879
4880     memset(&media_object_param, 0, sizeof(media_object_param));
4881     i965_run_kernel_media_object(ctx, encoder_context, gpe_context, media_function, &media_object_param);
4882
4883     return VA_STATUS_SUCCESS;
4884 }
4885
4886 static VAStatus
4887 i965_encoder_vp8_vme_gpe_kernel_function(VADriverContextP ctx,
4888                                          struct encode_state *encode_state,
4889                                          struct intel_encoder_context *encoder_context)
4890 {
4891     struct i965_encoder_vp8_context *vp8_context = encoder_context->vme_context;
4892     int is_intra = (vp8_context->frame_type == MPEG_I_PICTURE);
4893     unsigned char brc_enabled = (vp8_context->internal_rate_mode == I965_BRC_CBR ||
4894                                  vp8_context->internal_rate_mode == I965_BRC_VBR);
4895     unsigned char scaling_enabled = vp8_context->hme_supported;
4896     unsigned char scaling_16x_enabled = vp8_context->hme_16x_supported;
4897     unsigned char hme_enabled = vp8_context->hme_enabled;
4898     unsigned char hme_16x_enabled = vp8_context->hme_16x_enabled;
4899
4900     if (brc_enabled) {
4901         if (!vp8_context->brc_initted || vp8_context->brc_need_reset) {
4902             i965_encoder_vp8_vme_brc_init_reset(ctx, encode_state, encoder_context);
4903         }
4904     }
4905
4906     if (scaling_enabled) {
4907         i965_encoder_vp8_vme_scaling(ctx, encode_state, encoder_context, 0);
4908
4909         if (scaling_16x_enabled)
4910             i965_encoder_vp8_vme_scaling(ctx, encode_state, encoder_context, 1);
4911     }
4912
4913     if (hme_enabled) {
4914         if (hme_16x_enabled)
4915             i965_encoder_vp8_vme_me(ctx, encode_state, encoder_context, 1);
4916
4917         i965_encoder_vp8_vme_me(ctx, encode_state, encoder_context, 0);
4918     }
4919
4920     if (brc_enabled) {
4921         if (is_intra) {
4922             i965_encoder_vp8_vme_mbenc(ctx, encode_state, encoder_context, 0, 1);
4923         }
4924
4925         i965_encoder_vp8_vme_brc_update(ctx, encode_state, encoder_context);
4926     }
4927
4928     vp8_context->brc_initted = 1;
4929     vp8_context->brc_mbenc_phase1_ignored = 0;
4930
4931     if (is_intra && encoder_context->quality_level == ENCODER_LOW_QUALITY) {
4932         vp8_context->brc_mbenc_phase1_ignored = 1;
4933     } else {
4934         i965_encoder_vp8_vme_mbenc(ctx, encode_state, encoder_context, 0, 0);
4935     }
4936
4937     if (is_intra) {
4938         i965_encoder_vp8_vme_mbenc(ctx, encode_state, encoder_context, 1, 0);
4939     }
4940
4941     i965_encoder_vp8_vme_mpu(ctx, encode_state, encoder_context);
4942
4943     return VA_STATUS_SUCCESS;
4944 }
4945
4946 static VAStatus
4947 i965_encoder_vp8_vme_gpe_kernel_final(VADriverContextP ctx,
4948                                       struct encode_state *encode_state,
4949                                       struct intel_encoder_context *encoder_context)
4950 {
4951     struct i965_encoder_vp8_context *vp8_context = encoder_context->vme_context;
4952     struct i965_encoder_vp8_mbenc_context *mbenc_context = &vp8_context->mbenc_context;
4953     struct i965_encoder_vp8_mpu_context *mpu_context = &vp8_context->mpu_context;
4954
4955     dri_bo_unreference(mbenc_context->luma_chroma_dynamic_buffer);
4956     mbenc_context->luma_chroma_dynamic_buffer = NULL;
4957
4958     dri_bo_unreference(mpu_context->dynamic_buffer);
4959     mpu_context->dynamic_buffer = NULL;
4960
4961     return VA_STATUS_SUCCESS;
4962 }
4963
4964 static void
4965 i965_encoder_vp8_vme_set_status_buffer(VADriverContextP ctx,
4966                                        struct encode_state *encode_state,
4967                                        struct intel_encoder_context *encoder_context)
4968 {
4969     struct i965_encoder_vp8_context *vp8_context = encoder_context->vme_context;
4970     struct i965_encoder_vp8_encode_status_buffer *encode_status_buffer = &vp8_context->encode_status_buffer;
4971     struct vp8_encode_status *encode_status;
4972     char *pbuffer;
4973
4974     dri_bo_unreference(encode_status_buffer->bo);
4975     encode_status_buffer->bo = encode_state->coded_buf_object->buffer_store->bo;
4976     dri_bo_reference(encode_status_buffer->bo);
4977
4978     encode_status_buffer->base_offset = offsetof(struct i965_coded_buffer_segment, codec_private_data);
4979     encode_status_buffer->size = ALIGN(sizeof(struct vp8_encode_status), sizeof(unsigned int) * 2);
4980
4981     encode_status_buffer->bitstream_byte_count_offset = offsetof(struct vp8_encode_status, bitstream_byte_count_per_frame);
4982     encode_status_buffer->image_status_mask_offset = offsetof(struct vp8_encode_status, image_status_mask);
4983     encode_status_buffer->image_status_ctrl_offset = offsetof(struct vp8_encode_status, image_status_ctrl);
4984
4985     dri_bo_map(encode_status_buffer->bo, 1);
4986
4987     if (!encode_status_buffer->bo->virtual)
4988         return;
4989
4990     pbuffer = encode_status_buffer->bo->virtual;
4991     pbuffer += encode_status_buffer->base_offset;
4992     encode_status = (struct vp8_encode_status *)pbuffer;
4993     memset(encode_status, 0, sizeof(*encode_status));
4994
4995     dri_bo_unmap(encode_status_buffer->bo);
4996 }
4997
4998 static VAStatus
4999 i965_encoder_vp8_vme_pipeline(VADriverContextP ctx,
5000                               VAProfile profile,
5001                               struct encode_state *encode_state,
5002                               struct intel_encoder_context *encoder_context)
5003 {
5004     struct i965_encoder_vp8_context *vp8_context = encoder_context->vme_context;
5005
5006     vp8_context->is_render_context = 1;
5007
5008     i965_encoder_vp8_vme_set_status_buffer(ctx, encode_state, encoder_context);
5009
5010     i965_encoder_vp8_get_paramters(ctx, encode_state, encoder_context);
5011
5012     i965_encoder_vp8_vme_gpe_kernel_init(ctx, encode_state, encoder_context);
5013     i965_encoder_vp8_vme_gpe_kernel_function(ctx, encode_state, encoder_context);
5014     i965_encoder_vp8_vme_gpe_kernel_final(ctx, encode_state, encoder_context);
5015
5016     vp8_context->frame_num++;
5017     vp8_context->brc_need_reset = 0;
5018
5019     vp8_context->mbenc_curbe_updated_in_brc_update = 0;
5020     vp8_context->mpu_curbe_updated_in_brc_update = 0;
5021     vp8_context->mfx_encoder_config_command_initialized = 0;
5022
5023     return VA_STATUS_SUCCESS;
5024 }
5025
5026 static void
5027 i965_encoder_vp8_vme_kernel_context_destroy(struct i965_encoder_vp8_context *vp8_context)
5028 {
5029     struct i965_gpe_table *gpe = vp8_context->gpe_table;
5030     int i;
5031
5032     for (i = 0; i < NUM_VP8_BRC_RESET; i++)
5033         gpe->context_destroy(&vp8_context->brc_init_reset_context.gpe_contexts[i]);
5034
5035     for (i = 0; i < NUM_VP8_SCALING; i++)
5036         gpe->context_destroy(&vp8_context->scaling_context.gpe_contexts[i]);
5037
5038     for (i = 0; i < NUM_VP8_ME; i++)
5039         gpe->context_destroy(&vp8_context->me_context.gpe_contexts[i]);
5040
5041     for (i = 0; i < NUM_VP8_MBENC; i++)
5042         gpe->context_destroy(&vp8_context->mbenc_context.gpe_contexts[i]);
5043
5044     for (i = 0; i < NUM_VP8_BRC_UPDATE; i++)
5045         gpe->context_destroy(&vp8_context->brc_update_context.gpe_contexts[i]);
5046
5047     for (i = 0; i < NUM_VP8_MPU; i++)
5048         gpe->context_destroy(&vp8_context->mpu_context.gpe_contexts[i]);
5049
5050     i965_encoder_vp8_vme_free_resources(vp8_context);
5051 }
5052
5053 static void
5054 i965_encoder_vp8_vme_context_destroy(void *context)
5055 {
5056     struct i965_encoder_vp8_context *vp8_context = context;
5057     struct i965_encoder_vp8_encode_status_buffer *encode_status_buffer = &vp8_context->encode_status_buffer;
5058
5059     i965_encoder_vp8_vme_kernel_context_destroy(vp8_context);
5060
5061     dri_bo_unreference(encode_status_buffer->bo);
5062     encode_status_buffer->bo = NULL;
5063
5064     free(vp8_context);
5065 }
5066
5067 static void
5068 i965_encoder_vp8_vme_brc_init_reset_context_init(VADriverContextP ctx,
5069                                                  struct i965_encoder_vp8_context *vp8_context,
5070                                                  struct i965_encoder_vp8_brc_init_reset_context *brc_init_reset_context)
5071 {
5072     struct i965_gpe_table *gpe = vp8_context->gpe_table;
5073     struct i965_gpe_context *gpe_context = NULL;
5074     struct vp8_encoder_kernel_parameters kernel_params;
5075     struct vp8_encoder_scoreboard_parameters scoreboard_params;
5076     int i;
5077
5078     kernel_params.curbe_size = sizeof(struct vp8_brc_init_reset_curbe_data);
5079     kernel_params.inline_data_size = 0;
5080     kernel_params.external_data_size = 0;
5081
5082     memset(&scoreboard_params, 0, sizeof(scoreboard_params));
5083     scoreboard_params.mask = 0xFF;
5084     scoreboard_params.enable = vp8_context->use_hw_scoreboard;
5085     scoreboard_params.type = vp8_context->use_hw_non_stalling_scoreborad;
5086
5087     for (i = 0; i < NUM_VP8_BRC_RESET; i++) {
5088         gpe_context = &brc_init_reset_context->gpe_contexts[i];
5089         i965_encoder_vp8_gpe_context_init_once(ctx, gpe_context, &kernel_params, vp8_context->idrt_entry_size);
5090         i965_encoder_vp8_gpe_context_vfe_scoreboard_init(gpe_context, &scoreboard_params);
5091         gpe->load_kernels(ctx,
5092                           gpe_context,
5093                           &vp8_kernels_brc_init_reset[i],
5094                           1);
5095     }
5096 }
5097
5098 static void
5099 i965_encoder_vp8_vme_scaling_context_init(VADriverContextP ctx,
5100                                           struct i965_encoder_vp8_context *vp8_context,
5101                                           struct i965_encoder_vp8_scaling_context *scaling_context)
5102 {
5103     struct i965_gpe_table *gpe = vp8_context->gpe_table;
5104     struct i965_gpe_context *gpe_context = NULL;
5105     struct vp8_encoder_kernel_parameters kernel_params;
5106     struct vp8_encoder_scoreboard_parameters scoreboard_params;
5107     int i;
5108
5109     kernel_params.curbe_size = sizeof(struct vp8_scaling_curbe_data);
5110     kernel_params.inline_data_size = 0;
5111     kernel_params.external_data_size = 0;
5112
5113     memset(&scoreboard_params, 0, sizeof(scoreboard_params));
5114     scoreboard_params.mask = 0xFF;
5115     scoreboard_params.enable = vp8_context->use_hw_scoreboard;
5116     scoreboard_params.type = vp8_context->use_hw_non_stalling_scoreborad;
5117
5118     for (i = 0; i < NUM_VP8_SCALING; i++) {
5119         gpe_context = &scaling_context->gpe_contexts[i];
5120         i965_encoder_vp8_gpe_context_init_once(ctx, gpe_context, &kernel_params, vp8_context->idrt_entry_size);
5121         i965_encoder_vp8_gpe_context_vfe_scoreboard_init(gpe_context, &scoreboard_params);
5122         gpe->load_kernels(ctx,
5123                           gpe_context,
5124                           &vp8_kernels_scaling[i],
5125                           1);
5126     }
5127 }
5128
5129 static void
5130 i965_encoder_vp8_vme_me_context_init(VADriverContextP ctx,
5131                                      struct i965_encoder_vp8_context *vp8_context,
5132                                      struct i965_encoder_vp8_me_context *me_context)
5133 {
5134     struct i965_gpe_table *gpe = vp8_context->gpe_table;
5135     struct i965_gpe_context *gpe_context = NULL;
5136     struct vp8_encoder_kernel_parameters kernel_params;
5137     struct vp8_encoder_scoreboard_parameters scoreboard_params;
5138     int i;
5139
5140     kernel_params.curbe_size = sizeof(struct vp8_me_curbe_data);
5141     kernel_params.inline_data_size = 0;
5142     kernel_params.external_data_size = 0;
5143
5144     memset(&scoreboard_params, 0, sizeof(scoreboard_params));
5145     scoreboard_params.mask = 0xFF;
5146     scoreboard_params.enable = vp8_context->use_hw_scoreboard;
5147     scoreboard_params.type = vp8_context->use_hw_non_stalling_scoreborad;
5148
5149     for (i = 0; i < NUM_VP8_ME; i++) {
5150         gpe_context = &me_context->gpe_contexts[i];
5151         i965_encoder_vp8_gpe_context_init_once(ctx, gpe_context, &kernel_params, vp8_context->idrt_entry_size);
5152         i965_encoder_vp8_gpe_context_vfe_scoreboard_init(gpe_context, &scoreboard_params);
5153         gpe->load_kernels(ctx,
5154                           gpe_context,
5155                           &vp8_kernels_me[i],
5156                           1);
5157     }
5158 }
5159
5160 static void
5161 i965_encoder_vp8_vme_mbenc_context_init(VADriverContextP ctx,
5162                                         struct i965_encoder_vp8_context *vp8_context,
5163                                         struct i965_encoder_vp8_mbenc_context *mbenc_context)
5164 {
5165     struct i965_gpe_table *gpe = vp8_context->gpe_table;
5166     struct i965_gpe_context *gpe_context = NULL;
5167     struct vp8_encoder_kernel_parameters kernel_params;
5168     struct vp8_encoder_scoreboard_parameters scoreboard_params;
5169     int i;
5170
5171     kernel_params.curbe_size = MAX(sizeof(struct vp8_mbenc_i_frame_curbe_data), sizeof(struct vp8_mbenc_p_frame_curbe_data));
5172     kernel_params.inline_data_size = 0;
5173     kernel_params.external_data_size = 0;
5174
5175     memset(&scoreboard_params, 0, sizeof(scoreboard_params));
5176     scoreboard_params.mask = 0xFF;
5177     scoreboard_params.enable = vp8_context->use_hw_scoreboard;
5178     scoreboard_params.type = vp8_context->use_hw_non_stalling_scoreborad;
5179
5180     for (i = 0; i < NUM_VP8_MBENC; i++) {
5181         gpe_context = &mbenc_context->gpe_contexts[i];
5182         i965_encoder_vp8_gpe_context_init_once(ctx, gpe_context, &kernel_params, vp8_context->idrt_entry_size);
5183         i965_encoder_vp8_gpe_context_vfe_scoreboard_init(gpe_context, &scoreboard_params);
5184         gpe->load_kernels(ctx,
5185                           gpe_context,
5186                           &vp8_kernels_mbenc[i],
5187                           1);
5188     }
5189 }
5190
5191 static void
5192 i965_encoder_vp8_vme_brc_update_context_init(VADriverContextP ctx,
5193                                              struct i965_encoder_vp8_context *vp8_context,
5194                                              struct i965_encoder_vp8_brc_update_context *brc_update_context)
5195 {
5196     struct i965_gpe_table *gpe = vp8_context->gpe_table;
5197     struct i965_gpe_context *gpe_context = NULL;
5198     struct vp8_encoder_kernel_parameters kernel_params;
5199     struct vp8_encoder_scoreboard_parameters scoreboard_params;
5200     int i;
5201
5202     kernel_params.curbe_size = sizeof(struct vp8_brc_update_curbe_data);
5203     kernel_params.inline_data_size = 0;
5204     kernel_params.external_data_size = 0;
5205
5206     memset(&scoreboard_params, 0, sizeof(scoreboard_params));
5207     scoreboard_params.mask = 0xFF;
5208     scoreboard_params.enable = vp8_context->use_hw_scoreboard;
5209     scoreboard_params.type = vp8_context->use_hw_non_stalling_scoreborad;
5210
5211     for (i = 0; i < NUM_VP8_BRC_UPDATE; i++) {
5212         gpe_context = &brc_update_context->gpe_contexts[i];
5213         i965_encoder_vp8_gpe_context_init_once(ctx, gpe_context, &kernel_params, vp8_context->idrt_entry_size);
5214         i965_encoder_vp8_gpe_context_vfe_scoreboard_init(gpe_context, &scoreboard_params);
5215         gpe->load_kernels(ctx,
5216                           gpe_context,
5217                           &vp8_kernels_brc_update[i],
5218                           1);
5219     }
5220 }
5221
5222 static void
5223 i965_encoder_vp8_vme_mpu_context_init(VADriverContextP ctx,
5224                                       struct i965_encoder_vp8_context *vp8_context,
5225                                       struct i965_encoder_vp8_mpu_context *mpu_context)
5226 {
5227     struct i965_gpe_table *gpe = vp8_context->gpe_table;
5228     struct i965_gpe_context *gpe_context = NULL;
5229     struct vp8_encoder_kernel_parameters kernel_params;
5230     struct vp8_encoder_scoreboard_parameters scoreboard_params;
5231     int i;
5232
5233     kernel_params.curbe_size = sizeof(struct vp8_mpu_curbe_data);
5234     kernel_params.inline_data_size = 0;
5235     kernel_params.external_data_size = 0;
5236
5237     memset(&scoreboard_params, 0, sizeof(scoreboard_params));
5238     scoreboard_params.mask = 0xFF;
5239     scoreboard_params.enable = vp8_context->use_hw_scoreboard;
5240     scoreboard_params.type = vp8_context->use_hw_non_stalling_scoreborad;
5241
5242     for (i = 0; i < NUM_VP8_MPU; i++) {
5243         gpe_context = &mpu_context->gpe_contexts[i];
5244         i965_encoder_vp8_gpe_context_init_once(ctx, gpe_context, &kernel_params, vp8_context->idrt_entry_size);
5245         i965_encoder_vp8_gpe_context_vfe_scoreboard_init(gpe_context, &scoreboard_params);
5246         gpe->load_kernels(ctx,
5247                           gpe_context,
5248                           &vp8_kernels_mpu[i],
5249                           1);
5250     }
5251 }
5252
5253 static Bool
5254 i965_encoder_vp8_vme_var_init(VADriverContextP ctx,
5255                               struct intel_encoder_context *encoder_context,
5256                               struct i965_encoder_vp8_context *vp8_context)
5257 {
5258     struct i965_driver_data *i965 = i965_driver_data(ctx);
5259
5260     vp8_context->mocs = i965->intel.mocs_state;
5261
5262     vp8_context->gpe_table = &i965->gpe_table;
5263
5264     vp8_context->min_scaled_dimension = 48;
5265     vp8_context->min_scaled_dimension_in_mbs = WIDTH_IN_MACROBLOCKS(vp8_context->min_scaled_dimension);
5266
5267     vp8_context->vdbox_idc = BSD_RING0;
5268     vp8_context->vdbox_mmio_base = VDBOX0_MMIO_BASE;
5269
5270     /* TODO: This is a WA for VDBOX loading balance only, */
5271     if (i965->intel.has_bsd2) {
5272         srandom(time(NULL));
5273         vp8_context->vdbox_idc = (random() % 2 ? BSD_RING1 : BSD_RING0);
5274     }
5275
5276     if (vp8_context->vdbox_idc == BSD_RING1)
5277         vp8_context->vdbox_mmio_base = VDBOX1_MMIO_BASE;
5278
5279     vp8_context->frame_type = MPEG_I_PICTURE;
5280
5281     vp8_context->use_hw_scoreboard = 1;
5282     vp8_context->use_hw_non_stalling_scoreborad = 1; /* default: non-stalling */
5283     vp8_context->brc_distortion_buffer_supported = 1;
5284     vp8_context->brc_constant_buffer_supported = 1;
5285     vp8_context->repak_supported = 1;
5286     vp8_context->multiple_pass_brc_supported = 0;
5287     vp8_context->is_first_frame = 1;
5288     vp8_context->is_first_two_frame = 1;
5289     vp8_context->gop_size = 30;
5290     vp8_context->hme_supported = 1;
5291     vp8_context->hme_16x_supported = 1;
5292     vp8_context->hme_enabled = 0;
5293     vp8_context->hme_16x_enabled = 0;
5294     vp8_context->brc_initted = 0;
5295     vp8_context->frame_num = 0;
5296     vp8_context->framerate = (struct intel_fraction) { 30, 1 };
5297
5298     return True;
5299 }
5300
5301 static Bool
5302 i965_encoder_vp8_vme_kernels_context_init(VADriverContextP ctx,
5303                                           struct intel_encoder_context *encoder_context,
5304                                           struct i965_encoder_vp8_context *vp8_context)
5305 {
5306     i965_encoder_vp8_vme_brc_init_reset_context_init(ctx, vp8_context, &vp8_context->brc_init_reset_context);
5307     i965_encoder_vp8_vme_scaling_context_init(ctx, vp8_context, &vp8_context->scaling_context);
5308     i965_encoder_vp8_vme_me_context_init(ctx, vp8_context, &vp8_context->me_context);
5309     i965_encoder_vp8_vme_mbenc_context_init(ctx, vp8_context, &vp8_context->mbenc_context);
5310     i965_encoder_vp8_vme_brc_update_context_init(ctx, vp8_context, &vp8_context->brc_update_context);
5311     i965_encoder_vp8_vme_mpu_context_init(ctx, vp8_context, &vp8_context->mpu_context);
5312
5313     return True;
5314 }
5315
5316 extern Bool
5317 gen8_encoder_vp8_context_init(VADriverContextP, struct intel_encoder_context *, struct i965_encoder_vp8_context *);
5318
5319 extern Bool
5320 gen9_encoder_vp8_context_init(VADriverContextP, struct intel_encoder_context *, struct i965_encoder_vp8_context *);
5321
5322 Bool
5323 i965_encoder_vp8_vme_context_init(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
5324 {
5325     struct i965_driver_data *i965 = i965_driver_data(ctx);
5326     struct i965_encoder_vp8_context *vp8_context = NULL;
5327
5328     vp8_context = calloc(1, sizeof(struct i965_encoder_vp8_context));
5329
5330     if (!vp8_context)
5331         return False;
5332
5333     i965_encoder_vp8_vme_var_init(ctx, encoder_context, vp8_context);
5334
5335     if (IS_CHERRYVIEW(i965->intel.device_info))
5336         gen8_encoder_vp8_context_init(ctx, encoder_context, vp8_context);
5337     else if (IS_GEN9(i965->intel.device_info)) {
5338         gen9_encoder_vp8_context_init(ctx, encoder_context, vp8_context);
5339     } else {
5340         free(vp8_context);
5341
5342         return False;
5343     }
5344
5345     i965_encoder_vp8_vme_kernels_context_init(ctx, encoder_context, vp8_context);
5346
5347     encoder_context->vme_context = vp8_context;
5348     encoder_context->vme_pipeline = i965_encoder_vp8_vme_pipeline;
5349     encoder_context->vme_context_destroy = i965_encoder_vp8_vme_context_destroy;
5350
5351     return True;
5352 }
5353
5354 /*
5355  * PAK part
5356  */
5357 static void
5358 i965_encoder_vp8_pak_pre_pipeline(struct encode_state *encode_state,
5359                                   struct intel_encoder_context *encoder_context)
5360 {
5361     /* No thing to do */
5362 }
5363
5364 static void
5365 i965_encoder_vp8_pak_kernels_context_destroy(struct i965_encoder_vp8_context *vp8_context)
5366 {
5367     struct i965_gpe_table *gpe = vp8_context->gpe_table;
5368     int i;
5369
5370     for (i = 0; i < NUM_VP8_TPU; i++)
5371         gpe->context_destroy(&vp8_context->tpu_context.gpe_contexts[i]);
5372 }
5373
5374
5375 static void
5376 i965_encoder_vp8_pak_context_destroy(void *context)
5377 {
5378     struct i965_encoder_vp8_context *vp8_context = context;
5379     int i;
5380
5381     dri_bo_unreference(vp8_context->post_deblocking_output.bo);
5382     vp8_context->post_deblocking_output.bo = NULL;
5383
5384     dri_bo_unreference(vp8_context->pre_deblocking_output.bo);
5385     vp8_context->pre_deblocking_output.bo = NULL;
5386
5387     dri_bo_unreference(vp8_context->uncompressed_picture_source.bo);
5388     vp8_context->uncompressed_picture_source.bo = NULL;
5389
5390     dri_bo_unreference(vp8_context->indirect_pak_bse_object.bo);
5391     vp8_context->indirect_pak_bse_object.bo = NULL;
5392
5393     for (i = 0; i < MAX_MFX_REFERENCE_SURFACES; i++){
5394         dri_bo_unreference(vp8_context->reference_surfaces[i].bo);
5395         vp8_context->reference_surfaces[i].bo = NULL;
5396     }
5397
5398     i965_encoder_vp8_pak_kernels_context_destroy(vp8_context);
5399
5400     /* vme & pak same the same structure, so don't free the context here */
5401 }
5402
5403 static void
5404 i965_encoder_vp8_pak_pipe_mode_select(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
5405 {
5406     struct intel_batchbuffer *batch = encoder_context->base.batch;
5407     struct i965_encoder_vp8_context *vp8_context = encoder_context->mfc_context;
5408
5409     BEGIN_BCS_BATCH(batch, 5);
5410
5411     OUT_BCS_BATCH(batch, MFX_PIPE_MODE_SELECT | (5 - 2));
5412     OUT_BCS_BATCH(batch,
5413                   (MFX_LONG_MODE << 17) | /* Must be long format for encoder */
5414                   (MFD_MODE_VLD << 15) |  /* VLD mode */
5415                   ((!!vp8_context->post_deblocking_output.bo) << 9)  | /* Post Deblocking Output */
5416                   ((!!vp8_context->pre_deblocking_output.bo) << 8)  |  /* Pre Deblocking Output */
5417                   (1 << 4)  | /* encoding mode */
5418                   (MFX_FORMAT_VP8 << 0));
5419     OUT_BCS_BATCH(batch, 0);
5420     OUT_BCS_BATCH(batch, 0);
5421     OUT_BCS_BATCH(batch, 0);
5422
5423     ADVANCE_BCS_BATCH(batch);
5424 }
5425
5426 static void
5427 i965_encoder_vp8_pak_surface_state(VADriverContextP ctx,
5428                                    struct object_surface *obj_surface,
5429                                    int id,
5430                                    struct intel_encoder_context *encoder_context)
5431 {
5432     struct intel_batchbuffer *batch = encoder_context->base.batch;
5433
5434     BEGIN_BCS_BATCH(batch, 6);
5435
5436     OUT_BCS_BATCH(batch, MFX_SURFACE_STATE | (6 - 2));
5437     OUT_BCS_BATCH(batch, id);
5438     OUT_BCS_BATCH(batch,
5439                   ((obj_surface->orig_height - 1) << 18) |
5440                   ((obj_surface->orig_width - 1) << 4));
5441     OUT_BCS_BATCH(batch,
5442                   (MFX_SURFACE_PLANAR_420_8 << 28) | /* 420 planar YUV surface */
5443                   (1 << 27) | /* must be 1 for interleave U/V, hardware requirement */
5444                   ((obj_surface->width - 1) << 3) |  /* pitch */
5445                   (0 << 2)  | /* must be 0 for interleave U/V */
5446                   (1 << 1)  | /* must be tiled */
5447                   (I965_TILEWALK_YMAJOR << 0));  /* tile walk, TILEWALK_YMAJOR */
5448     OUT_BCS_BATCH(batch,
5449                   (0 << 16) |                    /* must be 0 for interleave U/V */
5450                   (obj_surface->height));        /* y offset for U(cb) */
5451     OUT_BCS_BATCH(batch, 0);
5452
5453     ADVANCE_BCS_BATCH(batch);
5454 }
5455
5456 #define PAK_OUT_BUFFER_2DW(buf_bo, is_target, delta)  do {              \
5457         if (buf_bo) {                                                   \
5458             OUT_BCS_RELOC64(batch,                                      \
5459                             buf_bo,                                     \
5460                             I915_GEM_DOMAIN_RENDER,                     \
5461                             is_target ? I915_GEM_DOMAIN_RENDER : 0,     \
5462                             delta);                                     \
5463         } else {                                                        \
5464             OUT_BCS_BATCH(batch, 0);                                    \
5465             OUT_BCS_BATCH(batch, 0);                                    \
5466         }                                                               \
5467     } while (0)
5468
5469 #define PAK_OUT_BUFFER_3DW(buf_bo, is_target, delta, attr)  do {        \
5470         PAK_OUT_BUFFER_2DW(buf_bo, is_target, delta);                   \
5471         OUT_BCS_BATCH(batch, attr);                                     \
5472     } while (0)
5473
5474
5475
5476 static void
5477 i965_encoder_vp8_pak_pipe_buf_addr_state(VADriverContextP ctx,
5478                                          struct intel_encoder_context *encoder_context)
5479 {
5480     struct intel_batchbuffer *batch = encoder_context->base.batch;
5481     struct i965_encoder_vp8_context *vp8_context = encoder_context->mfc_context;
5482     int i;
5483
5484     BEGIN_BCS_BATCH(batch, 61);
5485
5486     OUT_BCS_BATCH(batch, MFX_PIPE_BUF_ADDR_STATE | (61 - 2));
5487
5488     /* the DW1-3 is for pre_deblocking */
5489     PAK_OUT_BUFFER_3DW(vp8_context->pre_deblocking_output.bo, 1, 0, vp8_context->mocs);
5490
5491     /* the DW4-6 is for the post_deblocking */
5492     PAK_OUT_BUFFER_3DW(vp8_context->post_deblocking_output.bo, 1, 0, vp8_context->mocs);
5493
5494     /* the DW7-9 is for the uncompressed_picture */
5495     PAK_OUT_BUFFER_3DW(vp8_context->uncompressed_picture_source.bo, 0, 0, vp8_context->mocs);
5496
5497     /* the DW10-12 is for the mb status */
5498     PAK_OUT_BUFFER_3DW(vp8_context->pak_stream_out_buffer.bo, 1, 0, vp8_context->mocs);
5499
5500     /* the DW13-15 is for the intra_row_store_scratch */
5501     PAK_OUT_BUFFER_3DW(vp8_context->pak_intra_row_store_scratch_buffer.bo, 1, 0, vp8_context->mocs);
5502
5503     /* the DW16-18 is for the deblocking filter */
5504     PAK_OUT_BUFFER_3DW(vp8_context->pak_deblocking_filter_row_store_scratch_buffer.bo, 1, 0, vp8_context->mocs);
5505
5506     /* the DW 19-50 is for Reference pictures*/
5507     for (i = 0; i < ARRAY_ELEMS(vp8_context->reference_surfaces); i++) {
5508         PAK_OUT_BUFFER_2DW(vp8_context->reference_surfaces[i].bo, 0, 0);
5509     }
5510
5511     /* DW 51 */
5512     OUT_BCS_BATCH(batch, vp8_context->mocs);
5513
5514     /* The DW 52-54 is for the MB status buffer */
5515     PAK_OUT_BUFFER_3DW(NULL, 0, 0, 0);
5516
5517     /* the DW 55-57 is the ILDB buffer */
5518     PAK_OUT_BUFFER_3DW(NULL, 0, 0, 0);
5519
5520     /* the DW 58-60 is the second ILDB buffer */
5521     PAK_OUT_BUFFER_3DW(NULL, 0, 0, 0);
5522
5523     ADVANCE_BCS_BATCH(batch);
5524 }
5525
5526 static void
5527 i965_encoder_vp8_pak_ind_obj_base_addr_state(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
5528 {
5529     struct intel_batchbuffer *batch = encoder_context->base.batch;
5530     struct i965_encoder_vp8_context *vp8_context = encoder_context->mfc_context;
5531     int vme_size = ALIGN((vp8_context->mb_coded_buffer_size - vp8_context->mv_offset), 0x1000);
5532
5533     BEGIN_BCS_BATCH(batch, 26);
5534
5535     OUT_BCS_BATCH(batch, MFX_IND_OBJ_BASE_ADDR_STATE | (26 - 2));
5536
5537     /* the DW1-5 is for the MFX indirect bistream */
5538     PAK_OUT_BUFFER_3DW(vp8_context->indirect_pak_bse_object.bo, 1, vp8_context->indirect_pak_bse_object.offset, vp8_context->mocs);
5539     PAK_OUT_BUFFER_2DW(vp8_context->indirect_pak_bse_object.bo, 1, vp8_context->indirect_pak_bse_object.end_offset);
5540
5541     /* the DW6-10 is for MFX Indirect MV Object Base Address */
5542     PAK_OUT_BUFFER_3DW(vp8_context->mb_coded_buffer.bo, 0, vp8_context->mv_offset, vp8_context->mocs);
5543     PAK_OUT_BUFFER_2DW(vp8_context->mb_coded_buffer.bo, 0, (vp8_context->mv_offset + vme_size));
5544
5545     /* the DW11-15 is for MFX IT-COFF. Not used on encoder */
5546     PAK_OUT_BUFFER_3DW(NULL, 0, 0, 0);
5547     PAK_OUT_BUFFER_2DW(NULL, 0, 0);
5548
5549     /* the DW16-20 is for MFX indirect DBLK. Not used on encoder */
5550     PAK_OUT_BUFFER_3DW(NULL, 0, 0, 0);
5551     PAK_OUT_BUFFER_2DW(NULL, 0, 0);
5552
5553     /* the DW21-25 is for MFC Indirect PAK-BSE Object Base Address for Encoder*/
5554     PAK_OUT_BUFFER_3DW(vp8_context->indirect_pak_bse_object.bo, 1, vp8_context->indirect_pak_bse_object.offset, vp8_context->mocs);
5555     PAK_OUT_BUFFER_2DW(vp8_context->indirect_pak_bse_object.bo, 1, vp8_context->indirect_pak_bse_object.end_offset);
5556
5557     ADVANCE_BCS_BATCH(batch);
5558 }
5559
5560 static void
5561 i965_encoder_vp8_pak_bsp_buf_base_addr_state(VADriverContextP ctx,
5562                                              struct encode_state *encode_state,
5563                                              struct intel_encoder_context *encoder_context)
5564 {
5565     struct intel_batchbuffer *batch = encoder_context->base.batch;
5566     struct i965_encoder_vp8_context *vp8_context = encoder_context->mfc_context;
5567     VAEncPictureParameterBufferVP8 *pic_param = (VAEncPictureParameterBufferVP8 *)encode_state->pic_param_ext->buffer;
5568     int num_partitions = (1 << pic_param->pic_flags.bits.num_token_partitions);
5569     int offset;
5570     unsigned int token_size = vp8_context->frame_width * vp8_context->frame_height * 2;
5571     unsigned int part_size = token_size / num_partitions;
5572     unsigned int part0_size = (vp8_context->frame_width * vp8_context->frame_height) / 4 + VP8_INTERMEDIATE_PARTITION0_SIZE;
5573
5574     BEGIN_BCS_BATCH(batch, 32);
5575     OUT_BCS_BATCH(batch, MFX_VP8_BSP_BUF_BASE_ADDR_STATE | (32 - 2));
5576
5577     /* The 4th parameter in PAK_OUT_BUFFER_3DW() is not a MOCS index for this command per doc */
5578     /* DW1-3 */
5579     PAK_OUT_BUFFER_3DW(vp8_context->pak_frame_header_buffer.bo, 1, 0, 0);
5580     /* DW4-6 */
5581     PAK_OUT_BUFFER_3DW(vp8_context->pak_intermediate_buffer.bo, 1, 0, 0);
5582
5583     /* DW7-DW14 */
5584     offset = ALIGN(part0_size, 64);
5585     OUT_BCS_BATCH(batch, offset);
5586     offset = ALIGN(offset + part_size, 64);
5587     OUT_BCS_BATCH(batch, offset);
5588     offset = ALIGN(offset + part_size, 64);
5589     OUT_BCS_BATCH(batch, offset);
5590     offset = ALIGN(offset + part_size, 64);
5591     OUT_BCS_BATCH(batch, offset);
5592     offset = ALIGN(offset + part_size, 64);
5593     OUT_BCS_BATCH(batch, offset);
5594     offset = ALIGN(offset + part_size, 64);
5595     OUT_BCS_BATCH(batch, offset);
5596     offset = ALIGN(offset + part_size, 64);
5597     OUT_BCS_BATCH(batch, offset);
5598     offset = ALIGN(offset + part_size, 64);
5599     OUT_BCS_BATCH(batch, offset);
5600
5601     /* DW15 */
5602     OUT_BCS_BATCH(batch, token_size + part0_size);
5603
5604     /* DW16-18 */
5605     PAK_OUT_BUFFER_3DW(vp8_context->indirect_pak_bse_object.bo, 1, vp8_context->indirect_pak_bse_object.offset, 0);
5606
5607     /* DW19 */
5608     OUT_BCS_BATCH(batch, 0);
5609
5610     /* DW20-22 */
5611     PAK_OUT_BUFFER_3DW(NULL, 0, 0, 0);
5612
5613     /* DW23-25 */
5614     if (vp8_context->repak_pass_iter_val > 0 &&
5615         vp8_context->frame_type == MPEG_I_PICTURE &&
5616         vp8_context->repak_pass_iter_val == vp8_context->curr_pass)
5617         PAK_OUT_BUFFER_3DW(vp8_context->pak_mpu_tpu_key_frame_token_probability_buffer.bo, 1, 0, 0);
5618     else
5619         PAK_OUT_BUFFER_3DW(vp8_context->pak_mpu_tpu_coeff_probs_buffer.bo, 1, 0, 0);
5620
5621     /* DW26-28 */
5622     PAK_OUT_BUFFER_3DW(vp8_context->pak_mpu_tpu_pak_token_statistics_buffer.bo, 1, 0, 0);
5623
5624     /* DW29-31 */
5625     PAK_OUT_BUFFER_3DW(vp8_context->pak_mpc_row_store_scratch_buffer.bo, 1, 0, 0);
5626
5627     ADVANCE_BCS_BATCH(batch);
5628 }
5629
5630 static void
5631 i965_encoder_vp8_pak_insert_batch_buffers(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
5632 {
5633     struct intel_batchbuffer *batch = encoder_context->base.batch;
5634     struct i965_encoder_vp8_context *vp8_context = encoder_context->mfc_context;
5635     struct i965_gpe_table *gpe = vp8_context->gpe_table;
5636     struct gpe_mi_batch_buffer_start_parameter batch_param;
5637     unsigned char brc_enabled = (vp8_context->internal_rate_mode == I965_BRC_CBR ||
5638                                  vp8_context->internal_rate_mode == I965_BRC_VBR);
5639
5640     memset(&batch_param, 0, sizeof(batch_param));
5641     batch_param.bo = vp8_context->pak_mpu_tpu_picture_state_buffer.bo;
5642     batch_param.is_second_level = 1; /* Must be the second batch buffer */
5643     gpe->mi_batch_buffer_start(ctx, batch, &batch_param);
5644
5645     if (brc_enabled) {
5646         batch_param.bo = vp8_context->brc_vp8_cfg_command_write_buffer.bo;
5647
5648         if (vp8_context->repak_pass_iter_val == 0) {
5649             batch_param.offset = vp8_context->curr_pass * VP8_BRC_IMG_STATE_SIZE_PER_PASS;
5650         } else {
5651
5652             if (vp8_context->repak_pass_iter_val == vp8_context->curr_pass)
5653                 batch_param.offset = 0;
5654             else
5655                 batch_param.offset = vp8_context->curr_pass * VP8_BRC_IMG_STATE_SIZE_PER_PASS;
5656         }
5657
5658         gpe->mi_batch_buffer_start(ctx, batch, &batch_param);
5659     }
5660
5661     batch_param.bo = vp8_context->mb_coded_buffer.bo;
5662     gpe->mi_batch_buffer_start(ctx, batch, &batch_param);
5663 }
5664
5665 static void
5666 i965_encoder_vp8_pak_picture_level(VADriverContextP ctx,
5667                                    struct encode_state *encode_state,
5668                                    struct intel_encoder_context *encoder_context)
5669 {
5670     struct intel_batchbuffer *batch = encoder_context->base.batch;
5671     struct i965_encoder_vp8_context *vp8_context = encoder_context->mfc_context;
5672     struct i965_encoder_vp8_encode_status_buffer *encode_status_buffer = &vp8_context->encode_status_buffer;
5673     struct i965_gpe_table *gpe = vp8_context->gpe_table;
5674     struct gpe_mi_conditional_batch_buffer_end_parameter mi_param;
5675     unsigned char brc_enabled = (vp8_context->internal_rate_mode == I965_BRC_CBR ||
5676                                  vp8_context->internal_rate_mode == I965_BRC_VBR);
5677
5678     if (brc_enabled &&
5679         vp8_context->curr_pass > 0 &&
5680         (vp8_context->curr_pass < vp8_context->repak_pass_iter_val ||
5681          vp8_context->repak_pass_iter_val == 0)) {
5682         memset(&mi_param, 0, sizeof(mi_param));
5683         mi_param.bo = encode_status_buffer->bo;
5684         mi_param.offset = (encode_status_buffer->base_offset +
5685                            encode_status_buffer->image_status_mask_offset);
5686         gpe->mi_conditional_batch_buffer_end(ctx, batch, &mi_param);
5687     }
5688
5689     if ((vp8_context->repak_pass_iter_val > 0) && (vp8_context->curr_pass == vp8_context->repak_pass_iter_val)) {
5690         memset(&mi_param, 0, sizeof(mi_param));
5691         mi_param.bo = vp8_context->pak_mpu_tpu_repak_decision_buffer.bo;
5692         mi_param.offset = 0;
5693         gpe->mi_conditional_batch_buffer_end(ctx, batch, &mi_param);
5694     }
5695
5696     i965_encoder_vp8_pak_pipe_mode_select(ctx, encoder_context);
5697     i965_encoder_vp8_pak_surface_state(ctx, encode_state->reconstructed_object, 0, encoder_context);
5698     i965_encoder_vp8_pak_surface_state(ctx, encode_state->input_yuv_object, 4, encoder_context);
5699     i965_encoder_vp8_pak_pipe_buf_addr_state(ctx, encoder_context);
5700     i965_encoder_vp8_pak_ind_obj_base_addr_state(ctx, encoder_context);
5701     i965_encoder_vp8_pak_bsp_buf_base_addr_state(ctx, encode_state, encoder_context);
5702     i965_encoder_vp8_pak_insert_batch_buffers(ctx, encoder_context);
5703 }
5704
5705 static void
5706 i965_encoder_vp8_pak_set_pak_status_in_tpu_curbe(VADriverContextP ctx,
5707                                                  struct intel_encoder_context *encoder_context,
5708                                                  int ipass)
5709 {
5710     struct intel_batchbuffer *batch = encoder_context->base.batch;
5711     struct i965_encoder_vp8_context *vp8_context = encoder_context->mfc_context;
5712     struct i965_encoder_vp8_tpu_context *tpu_context = &vp8_context->tpu_context;
5713     struct i965_gpe_table *gpe = vp8_context->gpe_table;
5714     struct i965_gpe_context *tpu_gpe_context;
5715     struct gpe_mi_store_data_imm_parameter mi_store_data_imm_param;
5716     struct gpe_mi_store_register_mem_parameter mi_store_register_mem_param;
5717
5718     tpu_gpe_context = &tpu_context->gpe_contexts[0];
5719
5720     memset(&mi_store_data_imm_param, 0, sizeof(mi_store_data_imm_param));
5721     mi_store_data_imm_param.bo = tpu_gpe_context->curbe.bo;
5722     mi_store_data_imm_param.offset = tpu_gpe_context->curbe.offset + sizeof(unsigned int) * 6;
5723     mi_store_data_imm_param.dw0 = (vp8_context->curr_pass + 1) << 8;
5724
5725     gpe->mi_store_data_imm(ctx, batch, &mi_store_data_imm_param);
5726
5727     if (ipass == 0) {
5728         memset(&mi_store_register_mem_param, 0, sizeof(mi_store_register_mem_param));
5729         mi_store_register_mem_param.bo = tpu_gpe_context->curbe.bo;
5730         mi_store_register_mem_param.offset = tpu_gpe_context->curbe.offset + sizeof(unsigned int) * 8;
5731         mi_store_register_mem_param.mmio_offset = vp8_context->vdbox_mmio_base + VP8_MFX_BRC_CUMULATIVE_DQ_INDEX01_REG_OFFSET;
5732         gpe->mi_store_register_mem(ctx, batch, &mi_store_register_mem_param);
5733
5734         mi_store_register_mem_param.offset = tpu_gpe_context->curbe.offset + sizeof(unsigned int) * 9;
5735         mi_store_register_mem_param.mmio_offset = vp8_context->vdbox_mmio_base + VP8_MFX_BRC_CUMULATIVE_DQ_INDEX23_REG_OFFSET;
5736         gpe->mi_store_register_mem(ctx, batch, &mi_store_register_mem_param);
5737
5738         mi_store_register_mem_param.offset = tpu_gpe_context->curbe.offset + sizeof(unsigned int) * 10;
5739         mi_store_register_mem_param.mmio_offset = vp8_context->vdbox_mmio_base + VP8_MFX_BRC_CUMULATIVE_D_LOOP_FILTER01_REG_OFFSET;
5740         gpe->mi_store_register_mem(ctx, batch, &mi_store_register_mem_param);
5741
5742         mi_store_register_mem_param.offset = tpu_gpe_context->curbe.offset + sizeof(unsigned int) * 11;
5743         mi_store_register_mem_param.mmio_offset = vp8_context->vdbox_mmio_base + VP8_MFX_BRC_CUMULATIVE_D_LOOP_FILTER23_REG_OFFSET;
5744         gpe->mi_store_register_mem(ctx, batch, &mi_store_register_mem_param);
5745     }
5746 }
5747
5748 static void
5749 i965_encoder_vp8_pak_slice_level_brc(VADriverContextP ctx,
5750                                      struct intel_encoder_context *encoder_context,
5751                                      int ipass)
5752 {
5753     struct i965_encoder_vp8_context *vp8_context = encoder_context->mfc_context;
5754     unsigned int *pbuffer;
5755
5756     i965_encoder_vp8_read_pak_statistics(ctx, encoder_context, ipass);
5757
5758     pbuffer = i965_map_gpe_resource(&vp8_context->pak_mpu_tpu_picture_state_buffer);
5759
5760     if (!pbuffer)
5761         return;
5762
5763     pbuffer += 38;
5764     *pbuffer = 0x05000000;
5765     i965_unmap_gpe_resource(&vp8_context->pak_mpu_tpu_picture_state_buffer);
5766
5767     i965_encoder_vp8_pak_set_pak_status_in_tpu_curbe(ctx, encoder_context, ipass);
5768 }
5769
5770 static void
5771 i965_encoder_vp8_pak_slice_level(VADriverContextP ctx,
5772                                  struct encode_state *encode_state,
5773                                  struct intel_encoder_context *encoder_context)
5774 {
5775     struct i965_encoder_vp8_context *vp8_context = encoder_context->mfc_context;
5776     unsigned char brc_enabled = (vp8_context->internal_rate_mode == I965_BRC_CBR ||
5777                                  vp8_context->internal_rate_mode == I965_BRC_VBR);
5778     unsigned int *pbuffer;
5779
5780     i965_encoder_vp8_read_encode_status(ctx, encoder_context);
5781
5782     if (vp8_context->num_brc_pak_passes == VP8_BRC_SINGLE_PASS) {
5783         if (brc_enabled) {
5784             i965_encoder_vp8_read_pak_statistics(ctx, encoder_context, vp8_context->curr_pass);
5785
5786             /* Workaround: */
5787             pbuffer = i965_map_gpe_resource(&vp8_context->pak_mpu_tpu_picture_state_buffer);
5788
5789             if (!pbuffer)
5790                 return;
5791
5792             pbuffer += 38;
5793             *pbuffer = 0x05000000;
5794             i965_unmap_gpe_resource(&vp8_context->pak_mpu_tpu_picture_state_buffer);
5795         }
5796
5797         vp8_context->submit_batchbuffer = 1;
5798     } else {
5799         if ((brc_enabled) &&
5800             ((vp8_context->curr_pass < vp8_context->num_passes && vp8_context->repak_pass_iter_val > 0) ||
5801              (vp8_context->curr_pass <= vp8_context->num_passes && vp8_context->repak_pass_iter_val == 0))){
5802             i965_encoder_vp8_pak_slice_level_brc(ctx, encoder_context, vp8_context->curr_pass);
5803
5804             if (vp8_context->tpu_required)
5805                 vp8_context->submit_batchbuffer = 1;
5806             else
5807                 vp8_context->submit_batchbuffer = 0;
5808         } else {
5809             if (brc_enabled) {
5810                 i965_encoder_vp8_read_pak_statistics(ctx, encoder_context, vp8_context->curr_pass);
5811             }
5812
5813             pbuffer = i965_map_gpe_resource(&vp8_context->pak_mpu_tpu_picture_state_buffer);
5814
5815             if (!pbuffer)
5816                 return;
5817
5818             pbuffer += 38;
5819             *pbuffer = 0x05000000;
5820             i965_map_gpe_resource(&vp8_context->pak_mpu_tpu_picture_state_buffer);
5821
5822             vp8_context->submit_batchbuffer = 1;
5823         }
5824     }
5825 }
5826
5827 static void
5828 i965_encoder_vp8_pak_tpu_set_curbe(VADriverContextP ctx,
5829                                    struct encode_state *encode_state,
5830                                    struct intel_encoder_context *encoder_context,
5831                                    struct i965_gpe_context *gpe_context)
5832 {
5833     struct i965_encoder_vp8_context *vp8_context = encoder_context->mfc_context;
5834     struct vp8_tpu_curbe_data *pcmd = i965_gpe_context_map_curbe(gpe_context);
5835     VAEncPictureParameterBufferVP8 *pic_param = (VAEncPictureParameterBufferVP8 *)encode_state->pic_param_ext->buffer;
5836     VAQMatrixBufferVP8 *quant_param = (VAQMatrixBufferVP8 *)encode_state->q_matrix->buffer;
5837
5838     if (!pcmd)
5839         return;
5840
5841     memset(pcmd, 0, sizeof(*pcmd));
5842
5843     pcmd->dw0.mbs_in_frame = vp8_context->frame_width_in_mbs * vp8_context->frame_height_in_mbs;
5844
5845     pcmd->dw1.frame_type = pic_param->pic_flags.bits.frame_type;
5846     pcmd->dw1.enable_segmentation = pic_param->pic_flags.bits.segmentation_enabled;
5847     pcmd->dw1.rebinarization_frame_hdr = (vp8_context->repak_pass_iter_val ? 1 : 0);
5848
5849     pcmd->dw1.refresh_entropy_p = pic_param->pic_flags.bits.refresh_entropy_probs;
5850     pcmd->dw1.mb_no_coeffiscient_skip = pic_param->pic_flags.bits.mb_no_coeff_skip;
5851
5852     pcmd->dw3.max_qp = pic_param->clamp_qindex_high;
5853     pcmd->dw3.min_qp = pic_param->clamp_qindex_low;
5854
5855     pcmd->dw4.loop_filter_level_segment0 = pic_param->loop_filter_level[0];
5856     pcmd->dw4.loop_filter_level_segment1 = pic_param->loop_filter_level[1];
5857     pcmd->dw4.loop_filter_level_segment2 = pic_param->loop_filter_level[2];
5858     pcmd->dw4.loop_filter_level_segment3 = pic_param->loop_filter_level[3];
5859
5860     pcmd->dw5.quantization_index_segment0 = quant_param->quantization_index[0];
5861     pcmd->dw5.quantization_index_segment1 = quant_param->quantization_index[1];
5862     pcmd->dw5.quantization_index_segment2 = quant_param->quantization_index[2];
5863     pcmd->dw5.quantization_index_segment3 = quant_param->quantization_index[3];
5864
5865     pcmd->dw6.pak_pass_num = (vp8_context->internal_rate_mode > 0 ? vp8_context->num_brc_pak_passes : 0) << 8;
5866
5867     if (vp8_context->repak_pass_iter_val > 0) { // TODO: more check
5868         pcmd->dw7.skip_cost_delta_threshold = 100;
5869         pcmd->dw7.token_cost_delta_threshold = 50;
5870     } else {
5871         pcmd->dw7.skip_cost_delta_threshold = 0;
5872         pcmd->dw7.token_cost_delta_threshold = 0;
5873     }
5874
5875     pcmd->dw12.pak_token_statistics_bti = VP8_BTI_TPU_PAK_TOKEN_STATISTICS;
5876     pcmd->dw13.token_update_flags_bti = VP8_BTI_TPU_TOKEN_UPDATE_FLAGS;
5877     pcmd->dw14.entropy_cost_table_bti = VP8_BTI_TPU_ENTROPY_COST_TABLE;
5878     pcmd->dw15.frame_header_bitstream_bti = VP8_BTI_TPU_HEADER_BITSTREAM;
5879     pcmd->dw16.default_token_probability_bti = VP8_BTI_TPU_DEFAULT_TOKEN_PROBABILITY;
5880     pcmd->dw17.picture_state_bti = VP8_BTI_TPU_PICTURE_STATE;
5881     pcmd->dw18.mpu_curbe_data_bti = VP8_BTI_TPU_MPU_CURBE_DATA;
5882     pcmd->dw19.header_meta_data_bti = VP8_BTI_TPU_HEADER_METADATA;
5883     pcmd->dw20.token_probability_bti = VP8_BTI_TPU_TOKEN_PROBABILITY;
5884     pcmd->dw21.pak_hardware_token_probability_pass1_bti = VP8_BTI_TPU_PAK_HW_PASS1_PROBABILITY;
5885     pcmd->dw22.key_frame_token_probability_bti = VP8_BTI_TPU_KEY_TOKEN_PROBABILITY;
5886     pcmd->dw23.updated_token_probability_bti = VP8_BTI_TPU_UPDATED_TOKEN_PROBABILITY;
5887     pcmd->dw24.pak_hardware_token_probability_pass2_bti = VP8_BTI_TPU_PAK_HW_PASS2_PROBABILITY;
5888     pcmd->dw25.kernel_debug_dump_bti = VP8_BTI_TPU_VME_DEBUG_STREAMOUT;
5889     pcmd->dw26.repak_decision_surface_bti = VP8_BTI_TPU_REPAK_DECISION;
5890
5891     i965_gpe_context_unmap_curbe(gpe_context);
5892 }
5893
5894 static void
5895 i965_encoder_vp8_tpu_add_surfaces(VADriverContextP ctx,
5896                                   struct encode_state *encode_state,
5897                                   struct intel_encoder_context *encoder_context,
5898                                   struct i965_gpe_context *gpe_context)
5899 {
5900     struct i965_encoder_vp8_context *vp8_context = encoder_context->mfc_context;
5901     unsigned int size;
5902     unsigned char brc_enabled = (vp8_context->internal_rate_mode == I965_BRC_CBR ||
5903                                  vp8_context->internal_rate_mode == I965_BRC_VBR);
5904
5905     // Pak token statistics
5906     size = VP8_TOKEN_STATISTICS_SIZE;
5907     i965_add_buffer_gpe_surface(ctx,
5908                                 encoder_context,
5909                                 gpe_context,
5910                                 &vp8_context->pak_mpu_tpu_pak_token_statistics_buffer,
5911                                 1,
5912                                 size,
5913                                 0,
5914                                 VP8_BTI_TPU_PAK_TOKEN_STATISTICS);
5915
5916     // Pak token Update flags
5917     size = VP8_COEFFS_PROPABILITIES_SIZE;
5918     i965_add_buffer_gpe_surface(ctx,
5919                                 encoder_context,
5920                                 gpe_context,
5921                                 &vp8_context->pak_mpu_tpu_pak_token_update_flags_buffer,
5922                                 0,
5923                                 size,
5924                                 0,
5925                                 VP8_BTI_TPU_TOKEN_UPDATE_FLAGS);
5926
5927     // Entropy cost
5928     size = VP8_ENTROPY_COST_TABLE_SIZE;
5929     i965_add_buffer_gpe_surface(ctx,
5930                                 encoder_context,
5931                                 gpe_context,
5932                                 &vp8_context->pak_mpu_tpu_entropy_cost_table_buffer,
5933                                 1,
5934                                 size,
5935                                 0,
5936                                 VP8_BTI_TPU_ENTROPY_COST_TABLE);
5937
5938     // Frame header
5939     size = VP8_FRAME_HEADER_SIZE;
5940     i965_add_buffer_gpe_surface(ctx,
5941                                 encoder_context,
5942                                 gpe_context,
5943                                 &vp8_context->pak_frame_header_buffer,
5944                                 0,
5945                                 size,
5946                                 0,
5947                                 VP8_BTI_TPU_HEADER_BITSTREAM);
5948
5949     // Default token token probability
5950     size = VP8_COEFFS_PROPABILITIES_SIZE;
5951     i965_add_buffer_gpe_surface(ctx,
5952                                 encoder_context,
5953                                 gpe_context,
5954                                 &vp8_context->pak_mpu_tpu_default_token_probability_buffer,
5955                                 0,
5956                                 size,
5957                                 0,
5958                                 VP8_BTI_TPU_DEFAULT_TOKEN_PROBABILITY);
5959
5960     // Picture state surface
5961     size = VP8_PICTURE_STATE_SIZE;
5962     i965_add_buffer_gpe_surface(ctx,
5963                                 encoder_context,
5964                                 gpe_context,
5965                                 &vp8_context->pak_mpu_tpu_picture_state_buffer,
5966                                 0,
5967                                 size,
5968                                 0,
5969                                 VP8_BTI_TPU_PICTURE_STATE);
5970
5971     // MPU Curbe info from TPU
5972     size = VP8_TOKEN_BITS_DATA_SIZE;
5973     i965_add_buffer_gpe_surface(ctx,
5974                                 encoder_context,
5975                                 gpe_context,
5976                                 &vp8_context->pak_mpu_tpu_token_bits_data_buffer,
5977                                 0,
5978                                 size,
5979                                 0,
5980                                 VP8_BTI_TPU_MPU_CURBE_DATA);
5981
5982     // Encoder CFG command surface
5983     size = VP8_HEADER_METADATA_SIZE;
5984
5985     if (brc_enabled) {
5986         i965_add_buffer_gpe_surface(ctx,
5987                                     encoder_context,
5988                                     gpe_context,
5989                                     &vp8_context->brc_vp8_cfg_command_write_buffer,
5990                                     0,
5991                                     size,
5992                                     0,
5993                                     VP8_BTI_TPU_HEADER_METADATA);
5994     } else {
5995         i965_add_buffer_gpe_surface(ctx,
5996                                     encoder_context,
5997                                     gpe_context,
5998                                     &vp8_context->pak_mpu_tpu_picture_state_buffer,
5999                                     0,
6000                                     size,
6001                                     VP8_HEADER_METADATA_OFFSET,
6002                                     VP8_BTI_TPU_HEADER_METADATA);
6003     }
6004
6005     // Current frame token probability
6006     size = VP8_COEFFS_PROPABILITIES_SIZE;
6007     i965_add_buffer_gpe_surface(ctx,
6008                                 encoder_context,
6009                                 gpe_context,
6010                                 &vp8_context->pak_mpu_tpu_coeff_probs_buffer,
6011                                 0,
6012                                 size,
6013                                 0,
6014                                 VP8_BTI_TPU_TOKEN_PROBABILITY);
6015
6016     // Hardware token probability pass 1
6017     i965_add_buffer_gpe_surface(ctx,
6018                                 encoder_context,
6019                                 gpe_context,
6020                                 &vp8_context->pak_mpu_tpu_ref_coeff_probs_buffer,
6021                                 0,
6022                                 size,
6023                                 0,
6024                                 VP8_BTI_TPU_PAK_HW_PASS1_PROBABILITY);
6025
6026     // key frame token probability
6027     i965_add_buffer_gpe_surface(ctx,
6028                                 encoder_context,
6029                                 gpe_context,
6030                                 &vp8_context->pak_mpu_tpu_updated_token_probability_buffer,
6031                                 0,
6032                                 size,
6033                                 0,
6034                                 VP8_BTI_TPU_UPDATED_TOKEN_PROBABILITY);
6035
6036     // update token probability
6037     i965_add_buffer_gpe_surface(ctx,
6038                                 encoder_context,
6039                                 gpe_context,
6040                                 &vp8_context->pak_mpu_tpu_key_frame_token_probability_buffer,
6041                                 0,
6042                                 size,
6043                                 0,
6044                                 VP8_BTI_TPU_KEY_TOKEN_PROBABILITY);
6045
6046     // Hardware token probability pass 2
6047     i965_add_buffer_gpe_surface(ctx,
6048                                 encoder_context,
6049                                 gpe_context,
6050                                 &vp8_context->pak_mpu_tpu_hw_token_probability_pak_pass_2_buffer,
6051                                 0,
6052                                 size,
6053                                 0,
6054                                 VP8_BTI_TPU_PAK_HW_PASS2_PROBABILITY);
6055
6056     // Repak Decision
6057     i965_add_buffer_gpe_surface(ctx,
6058                                 encoder_context,
6059                                 gpe_context,
6060                                 &vp8_context->pak_mpu_tpu_repak_decision_buffer,
6061                                 0,
6062                                 size,
6063                                 0,
6064                                 VP8_BTI_TPU_REPAK_DECISION);
6065 }
6066
6067 static void
6068 i965_encoder_vp8_pak_tpu(VADriverContextP ctx,
6069                          struct encode_state *encode_state,
6070                          struct intel_encoder_context *encoder_context)
6071 {
6072     struct i965_encoder_vp8_context *vp8_context = encoder_context->mfc_context;
6073     struct i965_encoder_vp8_tpu_context *tpu_context = &vp8_context->tpu_context;
6074     struct i965_gpe_table *gpe = vp8_context->gpe_table;
6075     struct gpe_media_object_parameter media_object_param;
6076     struct i965_gpe_context *gpe_context;
6077     int media_function = VP8_MEDIA_STATE_TPU;
6078
6079     gpe_context = &tpu_context->gpe_contexts[0];
6080     /* gpe->context_init(ctx, gpe_context); */
6081     gpe->reset_binding_table(ctx, gpe_context);
6082
6083     if (!vp8_context->tpu_curbe_updated_in_brc_update)
6084         i965_encoder_vp8_pak_tpu_set_curbe(ctx, encode_state, encoder_context, gpe_context);
6085
6086     i965_encoder_vp8_tpu_add_surfaces(ctx, encode_state, encoder_context, gpe_context);
6087     gpe->setup_interface_data(ctx, gpe_context);
6088
6089     memset(&media_object_param, 0, sizeof(media_object_param));
6090     i965_run_kernel_media_object(ctx, encoder_context, gpe_context, media_function, &media_object_param);
6091 }
6092
6093 #define PAK_REFERENCE_BO(dst_bo, src_bo, is_ref_bo)     \
6094     do {                                                \
6095         dri_bo_unreference(dst_bo);                     \
6096         dst_bo = src_bo;                                \
6097         if (is_ref_bo)                                  \
6098             dri_bo_reference(dst_bo);                   \
6099     } while (0)
6100
6101 static void
6102 i965_encoder_vp8_pak_pipeline_prepare(VADriverContextP ctx,
6103                                       struct encode_state *encode_state,
6104                                       struct intel_encoder_context *encoder_context)
6105 {
6106     struct i965_encoder_vp8_context *vp8_context = encoder_context->mfc_context;
6107     struct object_surface *obj_surface;
6108     struct object_buffer *obj_buffer;
6109     struct i965_coded_buffer_segment *coded_buffer_segment;
6110     VAEncPictureParameterBufferVP8 *pic_param = (VAEncPictureParameterBufferVP8 *)encode_state->pic_param_ext->buffer;
6111     dri_bo *bo;
6112     int i;
6113
6114     /* reconstructed surface */
6115     obj_surface = encode_state->reconstructed_object;
6116     i965_check_alloc_surface_bo(ctx, obj_surface, 1, VA_FOURCC_NV12, SUBSAMPLE_YUV420);
6117
6118     if (pic_param->loop_filter_level[0] == 0) {
6119         PAK_REFERENCE_BO(vp8_context->pre_deblocking_output.bo, obj_surface->bo, 1);
6120         PAK_REFERENCE_BO(vp8_context->post_deblocking_output.bo, NULL, 0);
6121     } else {
6122         PAK_REFERENCE_BO(vp8_context->pre_deblocking_output.bo, NULL, 0);
6123         PAK_REFERENCE_BO(vp8_context->post_deblocking_output.bo, obj_surface->bo, 1);
6124     }
6125
6126     /* set vp8 reference frames */
6127     for (i = 0; i < ARRAY_ELEMS(vp8_context->reference_surfaces); i++) {
6128         obj_surface = encode_state->reference_objects[i];
6129
6130         if (obj_surface && obj_surface->bo) {
6131             PAK_REFERENCE_BO(vp8_context->reference_surfaces[i].bo, obj_surface->bo, 1);
6132         } else {
6133             PAK_REFERENCE_BO(vp8_context->reference_surfaces[i].bo, NULL, 0);
6134         }
6135     }
6136
6137     /* input YUV surface */
6138     obj_surface = encode_state->input_yuv_object;
6139     PAK_REFERENCE_BO(vp8_context->uncompressed_picture_source.bo, obj_surface->bo, 1);
6140
6141     /* coded buffer */
6142     obj_buffer = encode_state->coded_buf_object;
6143     bo = obj_buffer->buffer_store->bo;
6144     vp8_context->indirect_pak_bse_object.offset = I965_CODEDBUFFER_HEADER_SIZE;
6145     vp8_context->indirect_pak_bse_object.end_offset = ALIGN((obj_buffer->size_element - 0x1000), 0x1000);
6146     PAK_REFERENCE_BO(vp8_context->indirect_pak_bse_object.bo, bo, 1);
6147
6148     /* set the internal flag to 0 to indicate the coded size is unknown */
6149     dri_bo_map(bo, 1);
6150
6151     if (!bo->virtual)
6152         return;
6153
6154     coded_buffer_segment = (struct i965_coded_buffer_segment *)bo->virtual;
6155     coded_buffer_segment->mapped = 0;
6156     coded_buffer_segment->codec = encoder_context->codec;
6157     coded_buffer_segment->status_support = 1;
6158     dri_bo_unmap(bo);
6159 }
6160
6161 static VAStatus
6162 i965_encoder_vp8_pak_pipeline_final(VADriverContextP ctx,
6163                                     struct encode_state *encode_state,
6164                                     struct intel_encoder_context *encoder_context)
6165 {
6166     struct i965_encoder_vp8_context *vp8_context = encoder_context->mfc_context;
6167     struct i965_encoder_vp8_tpu_context *tpu_context = &vp8_context->tpu_context;
6168
6169     dri_bo_unreference(tpu_context->dynamic_buffer);
6170     tpu_context->dynamic_buffer = NULL;
6171
6172     return VA_STATUS_SUCCESS;
6173 }
6174
6175 #undef PAK_REFERENCE_BO
6176
6177 static VAStatus
6178 i965_encoder_vp8_pak_pipeline(VADriverContextP ctx,
6179                               VAProfile profile,
6180                               struct encode_state *encode_state,
6181                               struct intel_encoder_context *encoder_context)
6182 {
6183     struct i965_encoder_vp8_context *vp8_context = encoder_context->mfc_context;
6184     struct intel_batchbuffer *batch = encoder_context->base.batch;
6185
6186     i965_encoder_vp8_pak_pipeline_prepare(ctx, encode_state, encoder_context);
6187
6188     vp8_context->is_render_context = 0;
6189     vp8_context->submit_batchbuffer = 1;
6190
6191     for (vp8_context->curr_pass = 0; vp8_context->curr_pass <= vp8_context->num_passes; vp8_context->curr_pass++) {
6192         vp8_context->tpu_required = ((vp8_context->curr_pass == (vp8_context->num_passes - 1) &&
6193                                       vp8_context->repak_pass_iter_val > 0) ||
6194                                      (vp8_context->curr_pass == vp8_context->num_passes &&
6195                                       vp8_context->repak_pass_iter_val == 0));
6196
6197         if (vp8_context->submit_batchbuffer)
6198             intel_batchbuffer_start_atomic_bcs_override(batch, 0x1000, vp8_context->vdbox_idc);
6199
6200         intel_batchbuffer_emit_mi_flush(batch);
6201         i965_encoder_vp8_pak_picture_level(ctx, encode_state, encoder_context);
6202         i965_encoder_vp8_pak_slice_level(ctx, encode_state, encoder_context);
6203
6204         if (vp8_context->submit_batchbuffer) {
6205             intel_batchbuffer_end_atomic(batch);
6206             intel_batchbuffer_flush(batch);
6207         }
6208
6209         if (vp8_context->tpu_required) {
6210             assert(vp8_context->submit_batchbuffer);
6211             i965_encoder_vp8_pak_tpu(ctx, encode_state, encoder_context);
6212         }
6213     }
6214
6215     if (!vp8_context->is_first_frame && vp8_context->is_first_two_frame)
6216         vp8_context->is_first_two_frame = 0;
6217
6218     vp8_context->is_first_frame = 0;
6219     vp8_context->tpu_curbe_updated_in_brc_update = 0;
6220
6221     i965_encoder_vp8_pak_pipeline_final(ctx, encode_state, encoder_context);
6222
6223     return VA_STATUS_SUCCESS;
6224 }
6225
6226 static void
6227 i965_encoder_vp8_pak_tpu_context_init(VADriverContextP ctx,
6228                                       struct i965_encoder_vp8_context *vp8_context,
6229                                       struct i965_encoder_vp8_tpu_context *tpu_context)
6230 {
6231     struct i965_gpe_table *gpe = vp8_context->gpe_table;
6232     struct i965_gpe_context *gpe_context = NULL;
6233     struct vp8_encoder_kernel_parameters kernel_params;
6234     struct vp8_encoder_scoreboard_parameters scoreboard_params;
6235     int i;
6236
6237     kernel_params.curbe_size = sizeof(struct vp8_tpu_curbe_data);
6238     kernel_params.inline_data_size = 0;
6239     kernel_params.external_data_size = 0;
6240
6241     memset(&scoreboard_params, 0, sizeof(scoreboard_params));
6242     scoreboard_params.mask = 0xFF;
6243     scoreboard_params.enable = vp8_context->use_hw_scoreboard;
6244     scoreboard_params.type = vp8_context->use_hw_non_stalling_scoreborad;
6245
6246     for (i = 0; i < NUM_VP8_TPU; i++) {
6247         gpe_context = &tpu_context->gpe_contexts[i];
6248         i965_encoder_vp8_gpe_context_init_once(ctx, gpe_context, &kernel_params, vp8_context->idrt_entry_size);
6249         i965_encoder_vp8_gpe_context_vfe_scoreboard_init(gpe_context, &scoreboard_params);
6250         gpe->load_kernels(ctx,
6251                           gpe_context,
6252                           &vp8_kernels_tpu[i],
6253                           1);
6254     }
6255 }
6256
6257 static void
6258 i965_encoder_vp8_pak_kernels_context_init(VADriverContextP ctx,
6259                                           struct intel_encoder_context *encoder_context,
6260                                           struct i965_encoder_vp8_context *vp8_context)
6261 {
6262     i965_encoder_vp8_pak_tpu_context_init(ctx, vp8_context, &vp8_context->tpu_context);
6263 }
6264
6265 static VAStatus
6266 i965_encoder_vp8_get_status(VADriverContextP ctx,
6267                             struct intel_encoder_context *encoder_context,
6268                             struct i965_coded_buffer_segment *coded_buffer_segment)
6269 {
6270     struct vp8_encode_status *encode_state = (struct vp8_encode_status *)coded_buffer_segment->codec_private_data;
6271
6272     coded_buffer_segment->base.size = encode_state->bitstream_byte_count_per_frame;
6273
6274     return VA_STATUS_SUCCESS;
6275 }
6276
6277 Bool
6278 i965_encoder_vp8_pak_context_init(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
6279 {
6280     /* VME & PAK share the same context */
6281     struct i965_encoder_vp8_context *vp8_context = encoder_context->vme_context;
6282
6283     assert(vp8_context);
6284     i965_encoder_vp8_pak_kernels_context_init(ctx, encoder_context, vp8_context);
6285
6286     encoder_context->mfc_context = vp8_context;
6287     encoder_context->mfc_context_destroy = i965_encoder_vp8_pak_context_destroy;
6288     encoder_context->mfc_pipeline = i965_encoder_vp8_pak_pipeline;
6289     encoder_context->mfc_brc_prepare = i965_encoder_vp8_pak_pre_pipeline;
6290     encoder_context->get_status = i965_encoder_vp8_get_status;
6291
6292     return True;
6293 }