src/i965_gpe_utils.c

   1 /*
   2  * Copyright © 2012 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Xiang Haihao <haihao.xiang@intel.com>
  25  */
  26
  27 #include <stdio.h>
  28 #include <stdlib.h>
  29 #include <string.h>
  30 #include <assert.h>
  31
  32 #include "intel_batchbuffer.h"
  33 #include "intel_driver.h"
  34
  35 #include "i965_drv_video.h"
  36 #include "i965_gpe_utils.h"
  37
  38 static void
  39 i965_gpe_select(VADriverContextP ctx,
  40                 struct i965_gpe_context *gpe_context,
  41                 struct intel_batchbuffer *batch)
  42 {
  43     BEGIN_BATCH(batch, 1);
  44     OUT_BATCH(batch, CMD_PIPELINE_SELECT | PIPELINE_SELECT_MEDIA);
  45     ADVANCE_BATCH(batch);
  46 }
  47
  48 static void
  49 gen6_gpe_state_base_address(VADriverContextP ctx,
  50                             struct i965_gpe_context *gpe_context,
  51                             struct intel_batchbuffer *batch)
  52 {
  53     BEGIN_BATCH(batch, 10);
  54
  55     OUT_BATCH(batch, CMD_STATE_BASE_ADDRESS | (10 - 2));
  56     OUT_BATCH(batch, BASE_ADDRESS_MODIFY);              /* General State Base Address */
  57     OUT_RELOC(batch,
  58               gpe_context->surface_state_binding_table.bo,
  59               I915_GEM_DOMAIN_INSTRUCTION,
  60               0,
  61               BASE_ADDRESS_MODIFY);                     /* Surface state base address */
  62     OUT_BATCH(batch, BASE_ADDRESS_MODIFY);              /* Dynamic State Base Address */
  63     OUT_BATCH(batch, BASE_ADDRESS_MODIFY);              /* Indirect Object Base Address */
  64     OUT_BATCH(batch, BASE_ADDRESS_MODIFY);              /* Instruction Base Address */
  65     OUT_BATCH(batch, BASE_ADDRESS_MODIFY);              /* General State Access Upper Bound */
  66     OUT_BATCH(batch, BASE_ADDRESS_MODIFY);              /* Dynamic State Access Upper Bound */
  67     OUT_BATCH(batch, BASE_ADDRESS_MODIFY);              /* Indirect Object Access Upper Bound */
  68     OUT_BATCH(batch, BASE_ADDRESS_MODIFY);              /* Instruction Access Upper Bound */
  69
  70     ADVANCE_BATCH(batch);
  71 }
  72
  73 static void
  74 gen6_gpe_vfe_state(VADriverContextP ctx,
  75                    struct i965_gpe_context *gpe_context,
  76                    struct intel_batchbuffer *batch)
  77 {
  78
  79     BEGIN_BATCH(batch, 8);
  80
  81     OUT_BATCH(batch, CMD_MEDIA_VFE_STATE | (8 - 2));
  82     OUT_BATCH(batch, 0);                                        /* Scratch Space Base Pointer and Space */
  83     OUT_BATCH(batch,
  84               gpe_context->vfe_state.max_num_threads << 16 |    /* Maximum Number of Threads */
  85               gpe_context->vfe_state.num_urb_entries << 8 |     /* Number of URB Entries */
  86               gpe_context->vfe_state.gpgpu_mode << 2);          /* MEDIA Mode */
  87     OUT_BATCH(batch, 0);                                        /* Debug: Object ID */
  88     OUT_BATCH(batch,
  89               gpe_context->vfe_state.urb_entry_size << 16 |     /* URB Entry Allocation Size */
  90               gpe_context->vfe_state.curbe_allocation_size);    /* CURBE Allocation Size */
  91     /* the vfe_desc5/6/7 will decide whether the scoreboard is used. */
  92     OUT_BATCH(batch, gpe_context->vfe_desc5.dword);
  93     OUT_BATCH(batch, gpe_context->vfe_desc6.dword);
  94     OUT_BATCH(batch, gpe_context->vfe_desc7.dword);
  95
  96     ADVANCE_BATCH(batch);
  97
  98 }
  99
 100 static void
 101 gen6_gpe_curbe_load(VADriverContextP ctx,
 102                     struct i965_gpe_context *gpe_context,
 103                     struct intel_batchbuffer *batch)
 104 {
 105     BEGIN_BATCH(batch, 4);
 106
 107     OUT_BATCH(batch, CMD_MEDIA_CURBE_LOAD | (4 - 2));
 108     OUT_BATCH(batch, 0);
 109     OUT_BATCH(batch, gpe_context->curbe.length);
 110     OUT_RELOC(batch, gpe_context->curbe.bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
 111
 112     ADVANCE_BATCH(batch);
 113 }
 114
 115 static void
 116 gen6_gpe_idrt(VADriverContextP ctx,
 117               struct i965_gpe_context *gpe_context,
 118               struct intel_batchbuffer *batch)
 119 {
 120     BEGIN_BATCH(batch, 4);
 121
 122     OUT_BATCH(batch, CMD_MEDIA_INTERFACE_LOAD | (4 - 2));
 123     OUT_BATCH(batch, 0);
 124     OUT_BATCH(batch, gpe_context->idrt.max_entries * gpe_context->idrt.entry_size);
 125     OUT_RELOC(batch, gpe_context->idrt.bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
 126
 127     ADVANCE_BATCH(batch);
 128 }
 129
 130 void
 131 i965_gpe_load_kernels(VADriverContextP ctx,
 132                       struct i965_gpe_context *gpe_context,
 133                       struct i965_kernel *kernel_list,
 134                       unsigned int num_kernels)
 135 {
 136     struct i965_driver_data *i965 = i965_driver_data(ctx);
 137     int i;
 138
 139     assert(num_kernels <= MAX_GPE_KERNELS);
 140     memcpy(gpe_context->kernels, kernel_list, sizeof(*kernel_list) * num_kernels);
 141     gpe_context->num_kernels = num_kernels;
 142
 143     for (i = 0; i < num_kernels; i++) {
 144         struct i965_kernel *kernel = &gpe_context->kernels[i];
 145
 146         kernel->bo = dri_bo_alloc(i965->intel.bufmgr,
 147                                   kernel->name,
 148                                   kernel->size,
 149                                   0x1000);
 150         assert(kernel->bo);
 151         dri_bo_subdata(kernel->bo, 0, kernel->size, kernel->bin);
 152     }
 153 }
 154
 155 void
 156 i965_gpe_context_destroy(struct i965_gpe_context *gpe_context)
 157 {
 158     int i;
 159
 160     dri_bo_unreference(gpe_context->surface_state_binding_table.bo);
 161     gpe_context->surface_state_binding_table.bo = NULL;
 162
 163     dri_bo_unreference(gpe_context->idrt.bo);
 164     gpe_context->idrt.bo = NULL;
 165
 166     dri_bo_unreference(gpe_context->curbe.bo);
 167     gpe_context->curbe.bo = NULL;
 168
 169     for (i = 0; i < gpe_context->num_kernels; i++) {
 170         struct i965_kernel *kernel = &gpe_context->kernels[i];
 171
 172         dri_bo_unreference(kernel->bo);
 173         kernel->bo = NULL;
 174     }
 175 }
 176
 177 void
 178 i965_gpe_context_init(VADriverContextP ctx,
 179                       struct i965_gpe_context *gpe_context)
 180 {
 181     struct i965_driver_data *i965 = i965_driver_data(ctx);
 182     dri_bo *bo;
 183
 184     dri_bo_unreference(gpe_context->surface_state_binding_table.bo);
 185     bo = dri_bo_alloc(i965->intel.bufmgr,
 186                       "surface state & binding table",
 187                       gpe_context->surface_state_binding_table.length,
 188                       4096);
 189     assert(bo);
 190     gpe_context->surface_state_binding_table.bo = bo;
 191
 192     dri_bo_unreference(gpe_context->idrt.bo);
 193     bo = dri_bo_alloc(i965->intel.bufmgr,
 194                       "interface descriptor table",
 195                       gpe_context->idrt.entry_size * gpe_context->idrt.max_entries,
 196                       4096);
 197     assert(bo);
 198     gpe_context->idrt.bo = bo;
 199
 200     dri_bo_unreference(gpe_context->curbe.bo);
 201     bo = dri_bo_alloc(i965->intel.bufmgr,
 202                       "curbe buffer",
 203                       gpe_context->curbe.length,
 204                       4096);
 205     assert(bo);
 206     gpe_context->curbe.bo = bo;
 207 }
 208
 209 void
 210 gen6_gpe_pipeline_setup(VADriverContextP ctx,
 211                         struct i965_gpe_context *gpe_context,
 212                         struct intel_batchbuffer *batch)
 213 {
 214     intel_batchbuffer_emit_mi_flush(batch);
 215
 216     i965_gpe_select(ctx, gpe_context, batch);
 217     gen6_gpe_state_base_address(ctx, gpe_context, batch);
 218     gen6_gpe_vfe_state(ctx, gpe_context, batch);
 219     gen6_gpe_curbe_load(ctx, gpe_context, batch);
 220     gen6_gpe_idrt(ctx, gpe_context, batch);
 221 }
 222
 223 static void
 224 gen8_gpe_pipeline_end(VADriverContextP ctx,
 225                       struct i965_gpe_context *gpe_context,
 226                       struct intel_batchbuffer *batch)
 227 {
 228     /* No thing to do */
 229 }
 230
 231 static void
 232 i965_gpe_set_surface_tiling(struct i965_surface_state *ss, unsigned int tiling)
 233 {
 234     switch (tiling) {
 235     case I915_TILING_NONE:
 236         ss->ss3.tiled_surface = 0;
 237         ss->ss3.tile_walk = 0;
 238         break;
 239     case I915_TILING_X:
 240         ss->ss3.tiled_surface = 1;
 241         ss->ss3.tile_walk = I965_TILEWALK_XMAJOR;
 242         break;
 243     case I915_TILING_Y:
 244         ss->ss3.tiled_surface = 1;
 245         ss->ss3.tile_walk = I965_TILEWALK_YMAJOR;
 246         break;
 247     }
 248 }
 249
 250 static void
 251 i965_gpe_set_surface2_tiling(struct i965_surface_state2 *ss, unsigned int tiling)
 252 {
 253     switch (tiling) {
 254     case I915_TILING_NONE:
 255         ss->ss2.tiled_surface = 0;
 256         ss->ss2.tile_walk = 0;
 257         break;
 258     case I915_TILING_X:
 259         ss->ss2.tiled_surface = 1;
 260         ss->ss2.tile_walk = I965_TILEWALK_XMAJOR;
 261         break;
 262     case I915_TILING_Y:
 263         ss->ss2.tiled_surface = 1;
 264         ss->ss2.tile_walk = I965_TILEWALK_YMAJOR;
 265         break;
 266     }
 267 }
 268
 269 static void
 270 gen7_gpe_set_surface_tiling(struct gen7_surface_state *ss, unsigned int tiling)
 271 {
 272     switch (tiling) {
 273     case I915_TILING_NONE:
 274         ss->ss0.tiled_surface = 0;
 275         ss->ss0.tile_walk = 0;
 276         break;
 277     case I915_TILING_X:
 278         ss->ss0.tiled_surface = 1;
 279         ss->ss0.tile_walk = I965_TILEWALK_XMAJOR;
 280         break;
 281     case I915_TILING_Y:
 282         ss->ss0.tiled_surface = 1;
 283         ss->ss0.tile_walk = I965_TILEWALK_YMAJOR;
 284         break;
 285     }
 286 }
 287
 288 static void
 289 gen7_gpe_set_surface2_tiling(struct gen7_surface_state2 *ss, unsigned int tiling)
 290 {
 291     switch (tiling) {
 292     case I915_TILING_NONE:
 293         ss->ss2.tiled_surface = 0;
 294         ss->ss2.tile_walk = 0;
 295         break;
 296     case I915_TILING_X:
 297         ss->ss2.tiled_surface = 1;
 298         ss->ss2.tile_walk = I965_TILEWALK_XMAJOR;
 299         break;
 300     case I915_TILING_Y:
 301         ss->ss2.tiled_surface = 1;
 302         ss->ss2.tile_walk = I965_TILEWALK_YMAJOR;
 303         break;
 304     }
 305 }
 306
 307 static void
 308 gen8_gpe_set_surface_tiling(struct gen8_surface_state *ss, unsigned int tiling)
 309 {
 310     switch (tiling) {
 311     case I915_TILING_NONE:
 312         ss->ss0.tiled_surface = 0;
 313         ss->ss0.tile_walk = 0;
 314         break;
 315     case I915_TILING_X:
 316         ss->ss0.tiled_surface = 1;
 317         ss->ss0.tile_walk = I965_TILEWALK_XMAJOR;
 318         break;
 319     case I915_TILING_Y:
 320         ss->ss0.tiled_surface = 1;
 321         ss->ss0.tile_walk = I965_TILEWALK_YMAJOR;
 322         break;
 323     }
 324 }
 325
 326 static void
 327 gen8_gpe_set_surface2_tiling(struct gen8_surface_state2 *ss, unsigned int tiling)
 328 {
 329     switch (tiling) {
 330     case I915_TILING_NONE:
 331         ss->ss2.tiled_surface = 0;
 332         ss->ss2.tile_walk = 0;
 333         break;
 334     case I915_TILING_X:
 335         ss->ss2.tiled_surface = 1;
 336         ss->ss2.tile_walk = I965_TILEWALK_XMAJOR;
 337         break;
 338     case I915_TILING_Y:
 339         ss->ss2.tiled_surface = 1;
 340         ss->ss2.tile_walk = I965_TILEWALK_YMAJOR;
 341         break;
 342     }
 343 }
 344
 345 static void
 346 i965_gpe_set_surface2_state(VADriverContextP ctx,
 347                             struct object_surface *obj_surface,
 348                             struct i965_surface_state2 *ss)
 349 {
 350     int w, h, w_pitch;
 351     unsigned int tiling, swizzle;
 352
 353     assert(obj_surface->bo);
 354     assert(obj_surface->fourcc == VA_FOURCC_NV12);
 355
 356     dri_bo_get_tiling(obj_surface->bo, &tiling, &swizzle);
 357     w = obj_surface->orig_width;
 358     h = obj_surface->orig_height;
 359     w_pitch = obj_surface->width;
 360
 361     memset(ss, 0, sizeof(*ss));
 362     /* ss0 */
 363     ss->ss0.surface_base_address = obj_surface->bo->offset;
 364     /* ss1 */
 365     ss->ss1.cbcr_pixel_offset_v_direction = 2;
 366     ss->ss1.width = w - 1;
 367     ss->ss1.height = h - 1;
 368     /* ss2 */
 369     ss->ss2.surface_format = MFX_SURFACE_PLANAR_420_8;
 370     ss->ss2.interleave_chroma = 1;
 371     ss->ss2.pitch = w_pitch - 1;
 372     ss->ss2.half_pitch_for_chroma = 0;
 373     i965_gpe_set_surface2_tiling(ss, tiling);
 374     /* ss3: UV offset for interleave mode */
 375     ss->ss3.x_offset_for_cb = obj_surface->x_cb_offset;
 376     ss->ss3.y_offset_for_cb = obj_surface->y_cb_offset;
 377 }
 378
 379 void
 380 i965_gpe_surface2_setup(VADriverContextP ctx,
 381                         struct i965_gpe_context *gpe_context,
 382                         struct object_surface *obj_surface,
 383                         unsigned long binding_table_offset,
 384                         unsigned long surface_state_offset)
 385 {
 386     struct i965_surface_state2 *ss;
 387     dri_bo *bo;
 388
 389     bo = gpe_context->surface_state_binding_table.bo;
 390     dri_bo_map(bo, 1);
 391     assert(bo->virtual);
 392
 393     ss = (struct i965_surface_state2 *)((char *)bo->virtual + surface_state_offset);
 394     i965_gpe_set_surface2_state(ctx, obj_surface, ss);
 395     dri_bo_emit_reloc(bo,
 396                       I915_GEM_DOMAIN_RENDER, 0,
 397                       0,
 398                       surface_state_offset + offsetof(struct i965_surface_state2, ss0),
 399                       obj_surface->bo);
 400
 401     *((unsigned int *)((char *)bo->virtual + binding_table_offset)) = surface_state_offset;
 402     dri_bo_unmap(bo);
 403 }
 404
 405 static void
 406 i965_gpe_set_media_rw_surface_state(VADriverContextP ctx,
 407                                     struct object_surface *obj_surface,
 408                                     struct i965_surface_state *ss)
 409 {
 410     int w, h, w_pitch;
 411     unsigned int tiling, swizzle;
 412
 413     dri_bo_get_tiling(obj_surface->bo, &tiling, &swizzle);
 414     w = obj_surface->orig_width;
 415     h = obj_surface->orig_height;
 416     w_pitch = obj_surface->width;
 417
 418     memset(ss, 0, sizeof(*ss));
 419     /* ss0 */
 420     ss->ss0.surface_type = I965_SURFACE_2D;
 421     ss->ss0.surface_format = I965_SURFACEFORMAT_R8_UNORM;
 422     /* ss1 */
 423     ss->ss1.base_addr = obj_surface->bo->offset;
 424     /* ss2 */
 425     ss->ss2.width = w / 4 - 1;  /* in DWORDs for media read & write message */
 426     ss->ss2.height = h - 1;
 427     /* ss3 */
 428     ss->ss3.pitch = w_pitch - 1;
 429     i965_gpe_set_surface_tiling(ss, tiling);
 430 }
 431
 432 void
 433 i965_gpe_media_rw_surface_setup(VADriverContextP ctx,
 434                                 struct i965_gpe_context *gpe_context,
 435                                 struct object_surface *obj_surface,
 436                                 unsigned long binding_table_offset,
 437                                 unsigned long surface_state_offset,
 438                                 int write_enabled)
 439 {
 440     struct i965_surface_state *ss;
 441     dri_bo *bo;
 442
 443     bo = gpe_context->surface_state_binding_table.bo;
 444     dri_bo_map(bo, True);
 445     assert(bo->virtual);
 446
 447     ss = (struct i965_surface_state *)((char *)bo->virtual + surface_state_offset);
 448     i965_gpe_set_media_rw_surface_state(ctx, obj_surface, ss);
 449     dri_bo_emit_reloc(bo,
 450                       I915_GEM_DOMAIN_RENDER, write_enabled ? I915_GEM_DOMAIN_RENDER : 0,
 451                       0,
 452                       surface_state_offset + offsetof(struct i965_surface_state, ss1),
 453                       obj_surface->bo);
 454
 455     *((unsigned int *)((char *)bo->virtual + binding_table_offset)) = surface_state_offset;
 456     dri_bo_unmap(bo);
 457 }
 458
 459 static void
 460 i965_gpe_set_buffer_surface_state(VADriverContextP ctx,
 461                                   struct i965_buffer_surface *buffer_surface,
 462                                   struct i965_surface_state *ss)
 463 {
 464     int num_entries;
 465
 466     assert(buffer_surface->bo);
 467     num_entries = buffer_surface->num_blocks * buffer_surface->size_block / buffer_surface->pitch;
 468
 469     memset(ss, 0, sizeof(*ss));
 470     /* ss0 */
 471     ss->ss0.render_cache_read_mode = 1;
 472     ss->ss0.surface_type = I965_SURFACE_BUFFER;
 473     /* ss1 */
 474     ss->ss1.base_addr = buffer_surface->bo->offset;
 475     /* ss2 */
 476     ss->ss2.width = ((num_entries - 1) & 0x7f);
 477     ss->ss2.height = (((num_entries - 1) >> 7) & 0x1fff);
 478     /* ss3 */
 479     ss->ss3.depth = (((num_entries - 1) >> 20) & 0x7f);
 480     ss->ss3.pitch = buffer_surface->pitch - 1;
 481 }
 482
 483 void
 484 i965_gpe_buffer_suface_setup(VADriverContextP ctx,
 485                              struct i965_gpe_context *gpe_context,
 486                              struct i965_buffer_surface *buffer_surface,
 487                              unsigned long binding_table_offset,
 488                              unsigned long surface_state_offset)
 489 {
 490     struct i965_surface_state *ss;
 491     dri_bo *bo;
 492
 493     bo = gpe_context->surface_state_binding_table.bo;
 494     dri_bo_map(bo, 1);
 495     assert(bo->virtual);
 496
 497     ss = (struct i965_surface_state *)((char *)bo->virtual + surface_state_offset);
 498     i965_gpe_set_buffer_surface_state(ctx, buffer_surface, ss);
 499     dri_bo_emit_reloc(bo,
 500                       I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
 501                       0,
 502                       surface_state_offset + offsetof(struct i965_surface_state, ss1),
 503                       buffer_surface->bo);
 504
 505     *((unsigned int *)((char *)bo->virtual + binding_table_offset)) = surface_state_offset;
 506     dri_bo_unmap(bo);
 507 }
 508
 509 static void
 510 gen7_gpe_set_surface2_state(VADriverContextP ctx,
 511                             struct object_surface *obj_surface,
 512                             struct gen7_surface_state2 *ss)
 513 {
 514     int w, h, w_pitch;
 515     unsigned int tiling, swizzle;
 516
 517     assert(obj_surface->bo);
 518     assert(obj_surface->fourcc == VA_FOURCC_NV12);
 519
 520     dri_bo_get_tiling(obj_surface->bo, &tiling, &swizzle);
 521     w = obj_surface->orig_width;
 522     h = obj_surface->orig_height;
 523     w_pitch = obj_surface->width;
 524
 525     memset(ss, 0, sizeof(*ss));
 526     /* ss0 */
 527     ss->ss0.surface_base_address = obj_surface->bo->offset;
 528     /* ss1 */
 529     ss->ss1.cbcr_pixel_offset_v_direction = 2;
 530     ss->ss1.width = w - 1;
 531     ss->ss1.height = h - 1;
 532     /* ss2 */
 533     ss->ss2.surface_format = MFX_SURFACE_PLANAR_420_8;
 534     ss->ss2.interleave_chroma = 1;
 535     ss->ss2.pitch = w_pitch - 1;
 536     ss->ss2.half_pitch_for_chroma = 0;
 537     gen7_gpe_set_surface2_tiling(ss, tiling);
 538     /* ss3: UV offset for interleave mode */
 539     ss->ss3.x_offset_for_cb = obj_surface->x_cb_offset;
 540     ss->ss3.y_offset_for_cb = obj_surface->y_cb_offset;
 541 }
 542
 543 void
 544 gen7_gpe_surface2_setup(VADriverContextP ctx,
 545                         struct i965_gpe_context *gpe_context,
 546                         struct object_surface *obj_surface,
 547                         unsigned long binding_table_offset,
 548                         unsigned long surface_state_offset)
 549 {
 550     struct gen7_surface_state2 *ss;
 551     dri_bo *bo;
 552
 553     bo = gpe_context->surface_state_binding_table.bo;
 554     dri_bo_map(bo, 1);
 555     assert(bo->virtual);
 556
 557     ss = (struct gen7_surface_state2 *)((char *)bo->virtual + surface_state_offset);
 558     gen7_gpe_set_surface2_state(ctx, obj_surface, ss);
 559     dri_bo_emit_reloc(bo,
 560                       I915_GEM_DOMAIN_RENDER, 0,
 561                       0,
 562                       surface_state_offset + offsetof(struct gen7_surface_state2, ss0),
 563                       obj_surface->bo);
 564
 565     *((unsigned int *)((char *)bo->virtual + binding_table_offset)) = surface_state_offset;
 566     dri_bo_unmap(bo);
 567 }
 568
 569 static void
 570 gen7_gpe_set_media_rw_surface_state(VADriverContextP ctx,
 571                                     struct object_surface *obj_surface,
 572                                     struct gen7_surface_state *ss)
 573 {
 574     int w, h, w_pitch;
 575     unsigned int tiling, swizzle;
 576
 577     dri_bo_get_tiling(obj_surface->bo, &tiling, &swizzle);
 578     w = obj_surface->orig_width;
 579     h = obj_surface->orig_height;
 580     w_pitch = obj_surface->width;
 581
 582     memset(ss, 0, sizeof(*ss));
 583     /* ss0 */
 584     ss->ss0.surface_type = I965_SURFACE_2D;
 585     ss->ss0.surface_format = I965_SURFACEFORMAT_R8_UNORM;
 586     /* ss1 */
 587     ss->ss1.base_addr = obj_surface->bo->offset;
 588     /* ss2 */
 589     ss->ss2.width = w / 4 - 1;  /* in DWORDs for media read & write message */
 590     ss->ss2.height = h - 1;
 591     /* ss3 */
 592     ss->ss3.pitch = w_pitch - 1;
 593     gen7_gpe_set_surface_tiling(ss, tiling);
 594 }
 595
 596 static void
 597 gen75_gpe_set_media_chroma_surface_state(VADriverContextP ctx,
 598                                     struct object_surface *obj_surface,
 599                                     struct gen7_surface_state *ss)
 600 {
 601     int w, w_pitch;
 602     unsigned int tiling, swizzle;
 603     int cbcr_offset;
 604
 605     dri_bo_get_tiling(obj_surface->bo, &tiling, &swizzle);
 606     w = obj_surface->orig_width;
 607     w_pitch = obj_surface->width;
 608
 609     cbcr_offset = obj_surface->height * obj_surface->width;
 610     memset(ss, 0, sizeof(*ss));
 611     /* ss0 */
 612     ss->ss0.surface_type = I965_SURFACE_2D;
 613     ss->ss0.surface_format = I965_SURFACEFORMAT_R8_UNORM;
 614     /* ss1 */
 615     ss->ss1.base_addr = obj_surface->bo->offset + cbcr_offset;
 616     /* ss2 */
 617     ss->ss2.width = w / 4 - 1;  /* in DWORDs for media read & write message */
 618     ss->ss2.height = (obj_surface->height / 2) -1;
 619     /* ss3 */
 620     ss->ss3.pitch = w_pitch - 1;
 621     gen7_gpe_set_surface_tiling(ss, tiling);
 622 }
 623
 624 void
 625 gen7_gpe_media_rw_surface_setup(VADriverContextP ctx,
 626                                 struct i965_gpe_context *gpe_context,
 627                                 struct object_surface *obj_surface,
 628                                 unsigned long binding_table_offset,
 629                                 unsigned long surface_state_offset,
 630                                 int write_enabled)
 631 {
 632     struct gen7_surface_state *ss;
 633     dri_bo *bo;
 634
 635     bo = gpe_context->surface_state_binding_table.bo;
 636     dri_bo_map(bo, True);
 637     assert(bo->virtual);
 638
 639     ss = (struct gen7_surface_state *)((char *)bo->virtual + surface_state_offset);
 640     gen7_gpe_set_media_rw_surface_state(ctx, obj_surface, ss);
 641     dri_bo_emit_reloc(bo,
 642                       I915_GEM_DOMAIN_RENDER, write_enabled ? I915_GEM_DOMAIN_RENDER : 0,
 643                       0,
 644                       surface_state_offset + offsetof(struct gen7_surface_state, ss1),
 645                       obj_surface->bo);
 646
 647     *((unsigned int *)((char *)bo->virtual + binding_table_offset)) = surface_state_offset;
 648     dri_bo_unmap(bo);
 649 }
 650
 651 void
 652 gen75_gpe_media_chroma_surface_setup(VADriverContextP ctx,
 653                                 struct i965_gpe_context *gpe_context,
 654                                 struct object_surface *obj_surface,
 655                                 unsigned long binding_table_offset,
 656                                 unsigned long surface_state_offset,
 657                                 int write_enabled)
 658 {
 659     struct gen7_surface_state *ss;
 660     dri_bo *bo;
 661     int cbcr_offset;
 662
 663         assert(obj_surface->fourcc == VA_FOURCC_NV12);
 664     bo = gpe_context->surface_state_binding_table.bo;
 665     dri_bo_map(bo, True);
 666     assert(bo->virtual);
 667
 668     cbcr_offset = obj_surface->height * obj_surface->width;
 669     ss = (struct gen7_surface_state *)((char *)bo->virtual + surface_state_offset);
 670     gen75_gpe_set_media_chroma_surface_state(ctx, obj_surface, ss);
 671     dri_bo_emit_reloc(bo,
 672                       I915_GEM_DOMAIN_RENDER, write_enabled ? I915_GEM_DOMAIN_RENDER : 0,
 673                       cbcr_offset,
 674                       surface_state_offset + offsetof(struct gen7_surface_state, ss1),
 675                       obj_surface->bo);
 676
 677     *((unsigned int *)((char *)bo->virtual + binding_table_offset)) = surface_state_offset;
 678     dri_bo_unmap(bo);
 679 }
 680
 681
 682 static void
 683 gen7_gpe_set_buffer_surface_state(VADriverContextP ctx,
 684                                   struct i965_buffer_surface *buffer_surface,
 685                                   struct gen7_surface_state *ss)
 686 {
 687     int num_entries;
 688
 689     assert(buffer_surface->bo);
 690     num_entries = buffer_surface->num_blocks * buffer_surface->size_block / buffer_surface->pitch;
 691
 692     memset(ss, 0, sizeof(*ss));
 693     /* ss0 */
 694     ss->ss0.surface_type = I965_SURFACE_BUFFER;
 695     /* ss1 */
 696     ss->ss1.base_addr = buffer_surface->bo->offset;
 697     /* ss2 */
 698     ss->ss2.width = ((num_entries - 1) & 0x7f);
 699     ss->ss2.height = (((num_entries - 1) >> 7) & 0x3fff);
 700     /* ss3 */
 701     ss->ss3.depth = (((num_entries - 1) >> 21) & 0x3f);
 702     ss->ss3.pitch = buffer_surface->pitch - 1;
 703 }
 704
 705 void
 706 gen7_gpe_buffer_suface_setup(VADriverContextP ctx,
 707                              struct i965_gpe_context *gpe_context,
 708                              struct i965_buffer_surface *buffer_surface,
 709                              unsigned long binding_table_offset,
 710                              unsigned long surface_state_offset)
 711 {
 712     struct gen7_surface_state *ss;
 713     dri_bo *bo;
 714
 715     bo = gpe_context->surface_state_binding_table.bo;
 716     dri_bo_map(bo, 1);
 717     assert(bo->virtual);
 718
 719     ss = (struct gen7_surface_state *)((char *)bo->virtual + surface_state_offset);
 720     gen7_gpe_set_buffer_surface_state(ctx, buffer_surface, ss);
 721     dri_bo_emit_reloc(bo,
 722                       I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
 723                       0,
 724                       surface_state_offset + offsetof(struct gen7_surface_state, ss1),
 725                       buffer_surface->bo);
 726
 727     *((unsigned int *)((char *)bo->virtual + binding_table_offset)) = surface_state_offset;
 728     dri_bo_unmap(bo);
 729 }
 730
 731 static void
 732 gen8_gpe_set_surface2_state(VADriverContextP ctx,
 733                             struct object_surface *obj_surface,
 734                             struct gen8_surface_state2 *ss)
 735 {
 736     struct i965_driver_data *i965 = i965_driver_data(ctx);
 737     int w, h, w_pitch;
 738     unsigned int tiling, swizzle;
 739
 740     assert(obj_surface->bo);
 741     assert(obj_surface->fourcc == VA_FOURCC_NV12);
 742
 743     dri_bo_get_tiling(obj_surface->bo, &tiling, &swizzle);
 744     w = obj_surface->orig_width;
 745     h = obj_surface->orig_height;
 746     w_pitch = obj_surface->width;
 747
 748     memset(ss, 0, sizeof(*ss));
 749     /* ss0 */
 750     if (IS_GEN9(i965->intel.device_info))
 751         ss->ss5.surface_object_mocs = GEN9_CACHE_PTE;
 752
 753     ss->ss6.base_addr = (uint32_t)obj_surface->bo->offset64;
 754     ss->ss7.base_addr_high = (uint32_t)(obj_surface->bo->offset64 >> 32);
 755     /* ss1 */
 756     ss->ss1.cbcr_pixel_offset_v_direction = 2;
 757     ss->ss1.width = w - 1;
 758     ss->ss1.height = h - 1;
 759     /* ss2 */
 760     ss->ss2.surface_format = MFX_SURFACE_PLANAR_420_8;
 761     ss->ss2.interleave_chroma = 1;
 762     ss->ss2.pitch = w_pitch - 1;
 763     ss->ss2.half_pitch_for_chroma = 0;
 764     gen8_gpe_set_surface2_tiling(ss, tiling);
 765     /* ss3: UV offset for interleave mode */
 766     ss->ss3.x_offset_for_cb = obj_surface->x_cb_offset;
 767     ss->ss3.y_offset_for_cb = obj_surface->y_cb_offset;
 768 }
 769
 770 void
 771 gen8_gpe_surface2_setup(VADriverContextP ctx,
 772                         struct i965_gpe_context *gpe_context,
 773                         struct object_surface *obj_surface,
 774                         unsigned long binding_table_offset,
 775                         unsigned long surface_state_offset)
 776 {
 777     struct gen8_surface_state2 *ss;
 778     dri_bo *bo;
 779
 780     bo = gpe_context->surface_state_binding_table.bo;
 781     dri_bo_map(bo, 1);
 782     assert(bo->virtual);
 783
 784     ss = (struct gen8_surface_state2 *)((char *)bo->virtual + surface_state_offset);
 785     gen8_gpe_set_surface2_state(ctx, obj_surface, ss);
 786     dri_bo_emit_reloc(bo,
 787                       I915_GEM_DOMAIN_RENDER, 0,
 788                       0,
 789                       surface_state_offset + offsetof(struct gen8_surface_state2, ss6),
 790                       obj_surface->bo);
 791
 792     *((unsigned int *)((char *)bo->virtual + binding_table_offset)) = surface_state_offset;
 793     dri_bo_unmap(bo);
 794 }
 795
 796 static void
 797 gen8_gpe_set_media_rw_surface_state(VADriverContextP ctx,
 798                                     struct object_surface *obj_surface,
 799                                     struct gen8_surface_state *ss)
 800 {
 801     struct i965_driver_data *i965 = i965_driver_data(ctx);
 802     int w, h, w_pitch;
 803     unsigned int tiling, swizzle;
 804
 805     dri_bo_get_tiling(obj_surface->bo, &tiling, &swizzle);
 806     w = obj_surface->orig_width;
 807     h = obj_surface->orig_height;
 808     w_pitch = obj_surface->width;
 809
 810     memset(ss, 0, sizeof(*ss));
 811     /* ss0 */
 812     if (IS_GEN9(i965->intel.device_info))
 813         ss->ss1.surface_mocs = GEN9_CACHE_PTE;
 814
 815     ss->ss0.surface_type = I965_SURFACE_2D;
 816     ss->ss0.surface_format = I965_SURFACEFORMAT_R8_UNORM;
 817     /* ss1 */
 818     ss->ss8.base_addr = (uint32_t)obj_surface->bo->offset64;
 819     ss->ss9.base_addr_high = (uint32_t)(obj_surface->bo->offset64 >> 32);
 820     /* ss2 */
 821     ss->ss2.width = w / 4 - 1;  /* in DWORDs for media read & write message */
 822     ss->ss2.height = h - 1;
 823     /* ss3 */
 824     ss->ss3.pitch = w_pitch - 1;
 825     gen8_gpe_set_surface_tiling(ss, tiling);
 826 }
 827
 828 static void
 829 gen8_gpe_set_media_chroma_surface_state(VADriverContextP ctx,
 830                                     struct object_surface *obj_surface,
 831                                     struct gen8_surface_state *ss)
 832 {
 833     struct i965_driver_data *i965 = i965_driver_data(ctx);
 834     int w, w_pitch;
 835     unsigned int tiling, swizzle;
 836     int cbcr_offset;
 837     uint64_t base_offset;
 838
 839     dri_bo_get_tiling(obj_surface->bo, &tiling, &swizzle);
 840     w = obj_surface->orig_width;
 841     w_pitch = obj_surface->width;
 842
 843     cbcr_offset = obj_surface->height * obj_surface->width;
 844     memset(ss, 0, sizeof(*ss));
 845     /* ss0 */
 846     if (IS_GEN9(i965->intel.device_info))
 847         ss->ss1.surface_mocs = GEN9_CACHE_PTE;
 848
 849     ss->ss0.surface_type = I965_SURFACE_2D;
 850     ss->ss0.surface_format = I965_SURFACEFORMAT_R8_UNORM;
 851     /* ss1 */
 852     base_offset = obj_surface->bo->offset64 + cbcr_offset;
 853     ss->ss8.base_addr = (uint32_t) base_offset;
 854     ss->ss9.base_addr_high = (uint32_t) (base_offset >> 32);
 855     /* ss2 */
 856     ss->ss2.width = w / 4 - 1;  /* in DWORDs for media read & write message */
 857     ss->ss2.height = (obj_surface->height / 2) -1;
 858     /* ss3 */
 859     ss->ss3.pitch = w_pitch - 1;
 860     gen8_gpe_set_surface_tiling(ss, tiling);
 861 }
 862
 863 void
 864 gen8_gpe_media_rw_surface_setup(VADriverContextP ctx,
 865                                 struct i965_gpe_context *gpe_context,
 866                                 struct object_surface *obj_surface,
 867                                 unsigned long binding_table_offset,
 868                                 unsigned long surface_state_offset,
 869                                 int write_enabled)
 870 {
 871     struct gen8_surface_state *ss;
 872     dri_bo *bo;
 873
 874     bo = gpe_context->surface_state_binding_table.bo;
 875     dri_bo_map(bo, True);
 876     assert(bo->virtual);
 877
 878     ss = (struct gen8_surface_state *)((char *)bo->virtual + surface_state_offset);
 879     gen8_gpe_set_media_rw_surface_state(ctx, obj_surface, ss);
 880     dri_bo_emit_reloc(bo,
 881                       I915_GEM_DOMAIN_RENDER, write_enabled ? I915_GEM_DOMAIN_RENDER : 0,
 882                       0,
 883                       surface_state_offset + offsetof(struct gen8_surface_state, ss8),
 884                       obj_surface->bo);
 885
 886     *((unsigned int *)((char *)bo->virtual + binding_table_offset)) = surface_state_offset;
 887     dri_bo_unmap(bo);
 888 }
 889
 890 void
 891 gen8_gpe_media_chroma_surface_setup(VADriverContextP ctx,
 892                                 struct i965_gpe_context *gpe_context,
 893                                 struct object_surface *obj_surface,
 894                                 unsigned long binding_table_offset,
 895                                 unsigned long surface_state_offset,
 896                                 int write_enabled)
 897 {
 898     struct gen8_surface_state *ss;
 899     dri_bo *bo;
 900     int cbcr_offset;
 901
 902         assert(obj_surface->fourcc == VA_FOURCC_NV12);
 903     bo = gpe_context->surface_state_binding_table.bo;
 904     dri_bo_map(bo, True);
 905     assert(bo->virtual);
 906
 907     cbcr_offset = obj_surface->height * obj_surface->width;
 908     ss = (struct gen8_surface_state *)((char *)bo->virtual + surface_state_offset);
 909     gen8_gpe_set_media_chroma_surface_state(ctx, obj_surface, ss);
 910     dri_bo_emit_reloc(bo,
 911                       I915_GEM_DOMAIN_RENDER, write_enabled ? I915_GEM_DOMAIN_RENDER : 0,
 912                       cbcr_offset,
 913                       surface_state_offset + offsetof(struct gen8_surface_state, ss8),
 914                       obj_surface->bo);
 915
 916     *((unsigned int *)((char *)bo->virtual + binding_table_offset)) = surface_state_offset;
 917     dri_bo_unmap(bo);
 918 }
 919
 920
 921 static void
 922 gen8_gpe_set_buffer_surface_state(VADriverContextP ctx,
 923                                   struct i965_buffer_surface *buffer_surface,
 924                                   struct gen8_surface_state *ss)
 925 {
 926     struct i965_driver_data *i965 = i965_driver_data(ctx);
 927     int num_entries;
 928
 929     assert(buffer_surface->bo);
 930     num_entries = buffer_surface->num_blocks * buffer_surface->size_block / buffer_surface->pitch;
 931
 932     memset(ss, 0, sizeof(*ss));
 933     /* ss0 */
 934     ss->ss0.surface_type = I965_SURFACE_BUFFER;
 935     if (IS_GEN9(i965->intel.device_info))
 936         ss->ss1.surface_mocs = GEN9_CACHE_PTE;
 937
 938     /* ss1 */
 939     ss->ss8.base_addr = (uint32_t)buffer_surface->bo->offset64;
 940     ss->ss9.base_addr_high = (uint32_t)(buffer_surface->bo->offset64 >> 32);
 941     /* ss2 */
 942     ss->ss2.width = ((num_entries - 1) & 0x7f);
 943     ss->ss2.height = (((num_entries - 1) >> 7) & 0x3fff);
 944     /* ss3 */
 945     ss->ss3.depth = (((num_entries - 1) >> 21) & 0x3f);
 946     ss->ss3.pitch = buffer_surface->pitch - 1;
 947 }
 948
 949 void
 950 gen8_gpe_buffer_suface_setup(VADriverContextP ctx,
 951                              struct i965_gpe_context *gpe_context,
 952                              struct i965_buffer_surface *buffer_surface,
 953                              unsigned long binding_table_offset,
 954                              unsigned long surface_state_offset)
 955 {
 956     struct gen8_surface_state *ss;
 957     dri_bo *bo;
 958
 959     bo = gpe_context->surface_state_binding_table.bo;
 960     dri_bo_map(bo, 1);
 961     assert(bo->virtual);
 962
 963     ss = (struct gen8_surface_state *)((char *)bo->virtual + surface_state_offset);
 964     gen8_gpe_set_buffer_surface_state(ctx, buffer_surface, ss);
 965     dri_bo_emit_reloc(bo,
 966                       I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
 967                       0,
 968                       surface_state_offset + offsetof(struct gen8_surface_state, ss8),
 969                       buffer_surface->bo);
 970
 971     *((unsigned int *)((char *)bo->virtual + binding_table_offset)) = surface_state_offset;
 972     dri_bo_unmap(bo);
 973 }
 974
 975 static void
 976 gen8_gpe_state_base_address(VADriverContextP ctx,
 977                             struct i965_gpe_context *gpe_context,
 978                             struct intel_batchbuffer *batch)
 979 {
 980     BEGIN_BATCH(batch, 16);
 981
 982     OUT_BATCH(batch, CMD_STATE_BASE_ADDRESS | 14);
 983
 984     OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);                          //General State Base Address
 985     OUT_BATCH(batch, 0);
 986     OUT_BATCH(batch, 0);
 987
 988         /*DW4 Surface state base address */
 989     OUT_RELOC64(batch, gpe_context->surface_state_binding_table.bo, I915_GEM_DOMAIN_INSTRUCTION, 0, BASE_ADDRESS_MODIFY); /* Surface state base address */
 990
 991         /*DW6. Dynamic state base address */
 992     if (gpe_context->dynamic_state.bo)
 993         OUT_RELOC64(batch, gpe_context->dynamic_state.bo,
 994                   I915_GEM_DOMAIN_RENDER | I915_GEM_DOMAIN_SAMPLER,
 995                   0, BASE_ADDRESS_MODIFY);
 996     else {
 997         OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
 998         OUT_BATCH(batch, 0);
 999     }
1000
1001
1002         /*DW8. Indirect Object base address */
1003     if (gpe_context->indirect_state.bo)
1004         OUT_RELOC64(batch, gpe_context->indirect_state.bo,
1005                   I915_GEM_DOMAIN_SAMPLER,
1006                   0, BASE_ADDRESS_MODIFY);
1007     else {
1008         OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
1009         OUT_BATCH(batch, 0);
1010     }
1011
1012
1013         /*DW10. Instruct base address */
1014     if (gpe_context->instruction_state.bo)
1015         OUT_RELOC64(batch, gpe_context->instruction_state.bo,
1016                   I915_GEM_DOMAIN_INSTRUCTION,
1017                   0, BASE_ADDRESS_MODIFY);
1018     else {
1019         OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
1020         OUT_BATCH(batch, 0);
1021     }
1022
1023         /* DW12. Size limitation */
1024     OUT_BATCH(batch, 0xFFFFF000 | BASE_ADDRESS_MODIFY);         //General State Access Upper Bound
1025     OUT_BATCH(batch, 0xFFFFF000 | BASE_ADDRESS_MODIFY);         //Dynamic State Access Upper Bound
1026     OUT_BATCH(batch, 0xFFFFF000 | BASE_ADDRESS_MODIFY);         //Indirect Object Access Upper Bound
1027     OUT_BATCH(batch, 0xFFFFF000 | BASE_ADDRESS_MODIFY);         //Instruction Access Upper Bound
1028
1029     /*
1030       OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);                                //LLC Coherent Base Address
1031       OUT_BATCH(batch, 0xFFFFF000 | BASE_ADDRESS_MODIFY );              //LLC Coherent Upper Bound
1032     */
1033
1034     ADVANCE_BATCH(batch);
1035 }
1036
1037 static void
1038 gen8_gpe_vfe_state(VADriverContextP ctx,
1039                    struct i965_gpe_context *gpe_context,
1040                    struct intel_batchbuffer *batch)
1041 {
1042
1043     BEGIN_BATCH(batch, 9);
1044
1045     OUT_BATCH(batch, CMD_MEDIA_VFE_STATE | (9 - 2));
1046     /* Scratch Space Base Pointer and Space */
1047     OUT_BATCH(batch, 0);
1048     OUT_BATCH(batch, 0);
1049
1050     OUT_BATCH(batch,
1051               gpe_context->vfe_state.max_num_threads << 16 |    /* Maximum Number of Threads */
1052               gpe_context->vfe_state.num_urb_entries << 8 |     /* Number of URB Entries */
1053               gpe_context->vfe_state.gpgpu_mode << 2);          /* MEDIA Mode */
1054     OUT_BATCH(batch, 0);                                        /* Debug: Object ID */
1055     OUT_BATCH(batch,
1056               gpe_context->vfe_state.urb_entry_size << 16 |     /* URB Entry Allocation Size */
1057               gpe_context->vfe_state.curbe_allocation_size);    /* CURBE Allocation Size */
1058
1059     /* the vfe_desc5/6/7 will decide whether the scoreboard is used. */
1060     OUT_BATCH(batch, gpe_context->vfe_desc5.dword);
1061     OUT_BATCH(batch, gpe_context->vfe_desc6.dword);
1062     OUT_BATCH(batch, gpe_context->vfe_desc7.dword);
1063
1064     ADVANCE_BATCH(batch);
1065
1066 }
1067
1068
1069 static void
1070 gen8_gpe_curbe_load(VADriverContextP ctx,
1071                     struct i965_gpe_context *gpe_context,
1072                     struct intel_batchbuffer *batch)
1073 {
1074     BEGIN_BATCH(batch, 4);
1075
1076     OUT_BATCH(batch, CMD_MEDIA_CURBE_LOAD | (4 - 2));
1077     OUT_BATCH(batch, 0);
1078     OUT_BATCH(batch, ALIGN(gpe_context->curbe.length, 64));
1079     OUT_BATCH(batch, gpe_context->curbe.offset);
1080
1081     ADVANCE_BATCH(batch);
1082 }
1083
1084 static void
1085 gen8_gpe_idrt(VADriverContextP ctx,
1086               struct i965_gpe_context *gpe_context,
1087               struct intel_batchbuffer *batch)
1088 {
1089     BEGIN_BATCH(batch, 6);
1090
1091     OUT_BATCH(batch, CMD_MEDIA_STATE_FLUSH);
1092     OUT_BATCH(batch, 0);
1093
1094     OUT_BATCH(batch, CMD_MEDIA_INTERFACE_LOAD | (4 - 2));
1095     OUT_BATCH(batch, 0);
1096     OUT_BATCH(batch, gpe_context->idrt.max_entries * gpe_context->idrt.entry_size);
1097     OUT_BATCH(batch, gpe_context->idrt.offset);
1098
1099     ADVANCE_BATCH(batch);
1100 }
1101
1102
1103 void
1104 gen8_gpe_pipeline_setup(VADriverContextP ctx,
1105                         struct i965_gpe_context *gpe_context,
1106                         struct intel_batchbuffer *batch)
1107 {
1108     intel_batchbuffer_emit_mi_flush(batch);
1109
1110     i965_gpe_select(ctx, gpe_context, batch);
1111     gen8_gpe_state_base_address(ctx, gpe_context, batch);
1112     gen8_gpe_vfe_state(ctx, gpe_context, batch);
1113     gen8_gpe_curbe_load(ctx, gpe_context, batch);
1114     gen8_gpe_idrt(ctx, gpe_context, batch);
1115 }
1116
1117 void
1118 gen8_gpe_context_init(VADriverContextP ctx,
1119                       struct i965_gpe_context *gpe_context)
1120 {
1121     struct i965_driver_data *i965 = i965_driver_data(ctx);
1122     dri_bo *bo;
1123     int bo_size;
1124     unsigned int start_offset, end_offset;
1125
1126     dri_bo_unreference(gpe_context->surface_state_binding_table.bo);
1127     bo = dri_bo_alloc(i965->intel.bufmgr,
1128                       "surface state & binding table",
1129                       gpe_context->surface_state_binding_table.length,
1130                       4096);
1131     assert(bo);
1132     gpe_context->surface_state_binding_table.bo = bo;
1133
1134     bo_size = gpe_context->idrt.max_entries * ALIGN(gpe_context->idrt.entry_size, 64) +
1135         ALIGN(gpe_context->curbe.length, 64) +
1136         gpe_context->sampler.max_entries * ALIGN(gpe_context->sampler.entry_size, 64);
1137     dri_bo_unreference(gpe_context->dynamic_state.bo);
1138     bo = dri_bo_alloc(i965->intel.bufmgr,
1139                       "surface state & binding table",
1140                       bo_size,
1141                       4096);
1142     assert(bo);
1143     gpe_context->dynamic_state.bo = bo;
1144     gpe_context->dynamic_state.bo_size = bo_size;
1145
1146     end_offset = 0;
1147     gpe_context->dynamic_state.end_offset = 0;
1148
1149     /* Constant buffer offset */
1150     start_offset = ALIGN(end_offset, 64);
1151     dri_bo_unreference(gpe_context->curbe.bo);
1152     gpe_context->curbe.bo = bo;
1153     dri_bo_reference(gpe_context->curbe.bo);
1154     gpe_context->curbe.offset = start_offset;
1155     end_offset = start_offset + gpe_context->curbe.length;
1156
1157     /* Interface descriptor offset */
1158     start_offset = ALIGN(end_offset, 64);
1159     dri_bo_unreference(gpe_context->idrt.bo);
1160     gpe_context->idrt.bo = bo;
1161     dri_bo_reference(gpe_context->idrt.bo);
1162     gpe_context->idrt.offset = start_offset;
1163     end_offset = start_offset + ALIGN(gpe_context->idrt.entry_size, 64) * gpe_context->idrt.max_entries;
1164
1165     /* Sampler state offset */
1166     start_offset = ALIGN(end_offset, 64);
1167     dri_bo_unreference(gpe_context->sampler.bo);
1168     gpe_context->sampler.bo = bo;
1169     dri_bo_reference(gpe_context->sampler.bo);
1170     gpe_context->sampler.offset = start_offset;
1171     end_offset = start_offset + ALIGN(gpe_context->sampler.entry_size, 64) * gpe_context->sampler.max_entries;
1172
1173     /* update the end offset of dynamic_state */
1174     gpe_context->dynamic_state.end_offset = end_offset;
1175 }
1176
1177
1178 void
1179 gen8_gpe_context_destroy(struct i965_gpe_context *gpe_context)
1180 {
1181     dri_bo_unreference(gpe_context->surface_state_binding_table.bo);
1182     gpe_context->surface_state_binding_table.bo = NULL;
1183
1184     dri_bo_unreference(gpe_context->instruction_state.bo);
1185     gpe_context->instruction_state.bo = NULL;
1186
1187     dri_bo_unreference(gpe_context->dynamic_state.bo);
1188     gpe_context->dynamic_state.bo = NULL;
1189
1190     dri_bo_unreference(gpe_context->indirect_state.bo);
1191     gpe_context->indirect_state.bo = NULL;
1192
1193     dri_bo_unreference(gpe_context->curbe.bo);
1194     gpe_context->curbe.bo = NULL;
1195
1196     dri_bo_unreference(gpe_context->idrt.bo);
1197     gpe_context->idrt.bo = NULL;
1198
1199     dri_bo_unreference(gpe_context->sampler.bo);
1200     gpe_context->sampler.bo = NULL;
1201 }
1202
1203
1204 void
1205 gen8_gpe_load_kernels(VADriverContextP ctx,
1206                       struct i965_gpe_context *gpe_context,
1207                       struct i965_kernel *kernel_list,
1208                       unsigned int num_kernels)
1209 {
1210     struct i965_driver_data *i965 = i965_driver_data(ctx);
1211     int i, kernel_size = 0;
1212     unsigned int kernel_offset, end_offset;
1213     unsigned char *kernel_ptr;
1214     struct i965_kernel *kernel;
1215
1216     assert(num_kernels <= MAX_GPE_KERNELS);
1217     memcpy(gpe_context->kernels, kernel_list, sizeof(*kernel_list) * num_kernels);
1218     gpe_context->num_kernels = num_kernels;
1219
1220     for (i = 0; i < num_kernels; i++) {
1221         kernel = &gpe_context->kernels[i];
1222
1223         kernel_size += ALIGN(kernel->size, 64);
1224     }
1225
1226     gpe_context->instruction_state.bo = dri_bo_alloc(i965->intel.bufmgr,
1227                                   "kernel shader",
1228                                   kernel_size,
1229                                   0x1000);
1230     if (gpe_context->instruction_state.bo == NULL) {
1231         WARN_ONCE("failure to allocate the buffer space for kernel shader\n");
1232         return;
1233     }
1234
1235     assert(gpe_context->instruction_state.bo);
1236
1237     gpe_context->instruction_state.bo_size = kernel_size;
1238     gpe_context->instruction_state.end_offset = 0;
1239     end_offset = 0;
1240
1241     dri_bo_map(gpe_context->instruction_state.bo, 1);
1242     kernel_ptr = (unsigned char *)(gpe_context->instruction_state.bo->virtual);
1243     for (i = 0; i < num_kernels; i++) {
1244         kernel_offset = ALIGN(end_offset, 64);
1245         kernel = &gpe_context->kernels[i];
1246         kernel->kernel_offset = kernel_offset;
1247
1248         if (kernel->size) {
1249             memcpy(kernel_ptr + kernel_offset, kernel->bin, kernel->size);
1250
1251             end_offset = kernel_offset + kernel->size;
1252         }
1253     }
1254
1255     gpe_context->instruction_state.end_offset = end_offset;
1256
1257     dri_bo_unmap(gpe_context->instruction_state.bo);
1258
1259     return;
1260 }
1261
1262 static void
1263 gen9_gpe_state_base_address(VADriverContextP ctx,
1264                             struct i965_gpe_context *gpe_context,
1265                             struct intel_batchbuffer *batch)
1266 {
1267     struct i965_driver_data *i965 = i965_driver_data(ctx);
1268     BEGIN_BATCH(batch, 19);
1269
1270     OUT_BATCH(batch, CMD_STATE_BASE_ADDRESS | (19 - 2));
1271
1272     OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);                          //General State Base Address
1273     OUT_BATCH(batch, 0);
1274     OUT_BATCH(batch, 0);
1275
1276         /*DW4 Surface state base address */
1277     OUT_RELOC64(batch, gpe_context->surface_state_binding_table.bo, I915_GEM_DOMAIN_INSTRUCTION, 0, BASE_ADDRESS_MODIFY | (i965->intel.mocs_state << 4)); /* Surface state base address */
1278
1279         /*DW6. Dynamic state base address */
1280     if (gpe_context->dynamic_state.bo)
1281         OUT_RELOC64(batch, gpe_context->dynamic_state.bo,
1282                   I915_GEM_DOMAIN_RENDER | I915_GEM_DOMAIN_SAMPLER,
1283                   I915_GEM_DOMAIN_RENDER,
1284                   BASE_ADDRESS_MODIFY | (i965->intel.mocs_state << 4));
1285     else {
1286         OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
1287         OUT_BATCH(batch, 0);
1288     }
1289
1290
1291         /*DW8. Indirect Object base address */
1292     if (gpe_context->indirect_state.bo)
1293         OUT_RELOC64(batch, gpe_context->indirect_state.bo,
1294                   I915_GEM_DOMAIN_SAMPLER,
1295                   0, BASE_ADDRESS_MODIFY | (i965->intel.mocs_state << 4));
1296     else {
1297         OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
1298         OUT_BATCH(batch, 0);
1299     }
1300
1301
1302         /*DW10. Instruct base address */
1303     if (gpe_context->instruction_state.bo)
1304         OUT_RELOC64(batch, gpe_context->instruction_state.bo,
1305                   I915_GEM_DOMAIN_INSTRUCTION,
1306                   0, BASE_ADDRESS_MODIFY | (i965->intel.mocs_state << 4));
1307     else {
1308         OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
1309         OUT_BATCH(batch, 0);
1310     }
1311
1312
1313         /* DW12. Size limitation */
1314     OUT_BATCH(batch, 0xFFFFF000 | BASE_ADDRESS_MODIFY);         //General State Access Upper Bound
1315     OUT_BATCH(batch, 0xFFFFF000 | BASE_ADDRESS_MODIFY);         //Dynamic State Access Upper Bound
1316     OUT_BATCH(batch, 0xFFFFF000 | BASE_ADDRESS_MODIFY);         //Indirect Object Access Upper Bound
1317     OUT_BATCH(batch, 0xFFFFF000 | BASE_ADDRESS_MODIFY);         //Instruction Access Upper Bound
1318
1319     /* the bindless surface state address */
1320     OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
1321     OUT_BATCH(batch, 0);
1322     OUT_BATCH(batch, 0xFFFFF000);
1323
1324     ADVANCE_BATCH(batch);
1325 }
1326
1327 static void
1328 gen9_gpe_select(VADriverContextP ctx,
1329                 struct i965_gpe_context *gpe_context,
1330                 struct intel_batchbuffer *batch)
1331 {
1332     BEGIN_BATCH(batch, 1);
1333     OUT_BATCH(batch, CMD_PIPELINE_SELECT | PIPELINE_SELECT_MEDIA |
1334                      GEN9_PIPELINE_SELECTION_MASK |
1335                      GEN9_MEDIA_DOP_GATE_OFF |
1336                      GEN9_MEDIA_DOP_GATE_MASK |
1337                      GEN9_FORCE_MEDIA_AWAKE_ON |
1338                      GEN9_FORCE_MEDIA_AWAKE_MASK);
1339     ADVANCE_BATCH(batch);
1340 }
1341
1342 void
1343 gen9_gpe_pipeline_setup(VADriverContextP ctx,
1344                         struct i965_gpe_context *gpe_context,
1345                         struct intel_batchbuffer *batch)
1346 {
1347     intel_batchbuffer_emit_mi_flush(batch);
1348
1349     gen9_gpe_select(ctx, gpe_context, batch);
1350     gen9_gpe_state_base_address(ctx, gpe_context, batch);
1351     gen8_gpe_vfe_state(ctx, gpe_context, batch);
1352     gen8_gpe_curbe_load(ctx, gpe_context, batch);
1353     gen8_gpe_idrt(ctx, gpe_context, batch);
1354 }
1355
1356 void
1357 gen9_gpe_pipeline_end(VADriverContextP ctx,
1358                       struct i965_gpe_context *gpe_context,
1359                       struct intel_batchbuffer *batch)
1360 {
1361     BEGIN_BATCH(batch, 1);
1362     OUT_BATCH(batch, CMD_PIPELINE_SELECT | PIPELINE_SELECT_MEDIA |
1363               GEN9_PIPELINE_SELECTION_MASK |
1364               GEN9_MEDIA_DOP_GATE_ON |
1365               GEN9_MEDIA_DOP_GATE_MASK |
1366               GEN9_FORCE_MEDIA_AWAKE_OFF |
1367               GEN9_FORCE_MEDIA_AWAKE_MASK);
1368     ADVANCE_BATCH(batch);
1369 }
1370
1371 Bool
1372 i965_allocate_gpe_resource(dri_bufmgr *bufmgr,
1373                            struct i965_gpe_resource *res,
1374                            int size,
1375                            const char *name)
1376 {
1377     if (!res || !size)
1378         return false;
1379
1380     res->size = size;
1381     res->bo = dri_bo_alloc(bufmgr, name, res->size, 4096);
1382     res->map = NULL;
1383
1384     return (res->bo != NULL);
1385 }
1386
1387 void
1388 i965_object_surface_to_2d_gpe_resource_with_align(struct i965_gpe_resource *res,
1389                                        struct object_surface *obj_surface,
1390                                        unsigned int alignment)
1391 {
1392     unsigned int swizzle;
1393
1394     res->type = I965_GPE_RESOURCE_2D;
1395     res->width = ALIGN(obj_surface->orig_width,(1 << alignment));
1396     res->height = ALIGN(obj_surface->orig_height,(1 << alignment));
1397     res->pitch = obj_surface->width;
1398     res->size = obj_surface->size;
1399     res->cb_cr_pitch = obj_surface->cb_cr_pitch;
1400     res->x_cb_offset = obj_surface->x_cb_offset;
1401     res->y_cb_offset = obj_surface->y_cb_offset;
1402     res->bo = obj_surface->bo;
1403     res->map = NULL;
1404
1405     dri_bo_reference(res->bo);
1406     dri_bo_get_tiling(obj_surface->bo, &res->tiling, &swizzle);
1407 }
1408
1409 void
1410 i965_object_surface_to_2d_gpe_resource(struct i965_gpe_resource *res,
1411                                                   struct object_surface *obj_surface)
1412 {
1413     i965_object_surface_to_2d_gpe_resource_with_align(res,obj_surface,0);
1414 }
1415
1416 void
1417 i965_dri_object_to_buffer_gpe_resource(struct i965_gpe_resource *res,
1418                                        dri_bo *bo)
1419 {
1420     unsigned int swizzle;
1421
1422     res->type = I965_GPE_RESOURCE_BUFFER;
1423     res->width = bo->size;
1424     res->height = 1;
1425     res->pitch = res->width;
1426     res->size = res->pitch * res->width;
1427     res->bo = bo;
1428     res->map = NULL;
1429
1430     dri_bo_reference(res->bo);
1431     dri_bo_get_tiling(res->bo, &res->tiling, &swizzle);
1432 }
1433
1434 void
1435 i965_dri_object_to_2d_gpe_resource(struct i965_gpe_resource *res,
1436                                    dri_bo *bo,
1437                                    unsigned int width,
1438                                    unsigned int height,
1439                                    unsigned int pitch)
1440 {
1441     unsigned int swizzle;
1442
1443     res->type = I965_GPE_RESOURCE_2D;
1444     res->width = width;
1445     res->height = height;
1446     res->pitch = pitch;
1447     res->size = res->pitch * res->width;
1448     res->bo = bo;
1449     res->map = NULL;
1450
1451     dri_bo_reference(res->bo);
1452     dri_bo_get_tiling(res->bo, &res->tiling, &swizzle);
1453 }
1454
1455 void
1456 i965_zero_gpe_resource(struct i965_gpe_resource *res)
1457 {
1458     if (res->bo) {
1459         dri_bo_map(res->bo, 1);
1460         memset(res->bo->virtual, 0, res->size);
1461         dri_bo_unmap(res->bo);
1462     }
1463 }
1464
1465 void
1466 i965_free_gpe_resource(struct i965_gpe_resource *res)
1467 {
1468     dri_bo_unreference(res->bo);
1469     res->bo = NULL;
1470     res->map = NULL;
1471 }
1472
1473 void *
1474 i965_map_gpe_resource(struct i965_gpe_resource *res)
1475 {
1476     int ret;
1477
1478     if (res->bo) {
1479         ret = dri_bo_map(res->bo, 1);
1480
1481         if (ret == 0)
1482             res->map = res->bo->virtual;
1483         else
1484             res->map = NULL;
1485     } else
1486         res->map = NULL;
1487
1488     return res->map;
1489 }
1490
1491 void
1492 i965_unmap_gpe_resource(struct i965_gpe_resource *res)
1493 {
1494     if (res->bo && res->map)
1495         dri_bo_unmap(res->bo);
1496
1497     res->map = NULL;
1498 }
1499
1500 void
1501 gen8_gpe_mi_flush_dw(VADriverContextP ctx,
1502                      struct intel_batchbuffer *batch,
1503                      struct gpe_mi_flush_dw_parameter *params)
1504 {
1505     int video_pipeline_cache_invalidate = 0;
1506     int post_sync_operation = MI_FLUSH_DW_NOWRITE;
1507
1508     if (params->video_pipeline_cache_invalidate)
1509         video_pipeline_cache_invalidate = MI_FLUSH_DW_VIDEO_PIPELINE_CACHE_INVALIDATE;
1510
1511     if (params->bo)
1512         post_sync_operation = MI_FLUSH_DW_WRITE_QWORD;
1513
1514     __OUT_BATCH(batch, (MI_FLUSH_DW2 |
1515                         video_pipeline_cache_invalidate |
1516                         post_sync_operation |
1517                         (5 - 2))); /* Always use PPGTT */
1518
1519     if (params->bo) {
1520         __OUT_RELOC64(batch,
1521                       params->bo,
1522                       I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
1523                       params->offset);
1524     } else {
1525         __OUT_BATCH(batch, 0);
1526         __OUT_BATCH(batch, 0);
1527     }
1528
1529     __OUT_BATCH(batch, params->dw0);
1530     __OUT_BATCH(batch, params->dw1);
1531 }
1532
1533 void
1534 gen8_gpe_mi_store_data_imm(VADriverContextP ctx,
1535                            struct intel_batchbuffer *batch,
1536                            struct gpe_mi_store_data_imm_parameter *params)
1537 {
1538     if (params->is_qword) {
1539         __OUT_BATCH(batch, MI_STORE_DATA_IMM |
1540                     (1 << 21) |
1541                     (5 - 2)); /* Always use PPGTT */
1542     } else {
1543         __OUT_BATCH(batch, MI_STORE_DATA_IMM | (4 - 2)); /* Always use PPGTT */
1544     }
1545
1546     __OUT_RELOC64(batch,
1547                   params->bo,
1548                   I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
1549                   params->offset);
1550     __OUT_BATCH(batch, params->dw0);
1551
1552     if (params->is_qword)
1553         __OUT_BATCH(batch, params->dw1);
1554 }
1555
1556 void
1557 gen8_gpe_mi_store_register_mem(VADriverContextP ctx,
1558                                struct intel_batchbuffer *batch,
1559                                struct gpe_mi_store_register_mem_parameter *params)
1560 {
1561     __OUT_BATCH(batch, (MI_STORE_REGISTER_MEM | (4 - 2))); /* Always use PPGTT */
1562     __OUT_BATCH(batch, params->mmio_offset);
1563     __OUT_RELOC64(batch,
1564                   params->bo,
1565                   I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
1566                   params->offset);
1567 }
1568
1569 void
1570 gen8_gpe_mi_load_register_mem(VADriverContextP ctx,
1571                               struct intel_batchbuffer *batch,
1572                               struct gpe_mi_load_register_mem_parameter *params)
1573 {
1574     __OUT_BATCH(batch, (MI_LOAD_REGISTER_MEM | (4 - 2))); /* Always use PPGTT */
1575     __OUT_BATCH(batch, params->mmio_offset);
1576     __OUT_RELOC64(batch,
1577                   params->bo,
1578                   I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
1579                   params->offset);
1580 }
1581
1582 void
1583 gen8_gpe_mi_load_register_imm(VADriverContextP ctx,
1584                               struct intel_batchbuffer *batch,
1585                               struct gpe_mi_load_register_imm_parameter *params)
1586 {
1587     __OUT_BATCH(batch, (MI_LOAD_REGISTER_IMM | (3 - 2)));
1588     __OUT_BATCH(batch, params->mmio_offset);
1589     __OUT_BATCH(batch, params->data);
1590 }
1591
1592 void
1593 gen8_gpe_mi_load_register_reg(VADriverContextP ctx,
1594                               struct intel_batchbuffer *batch,
1595                               struct gpe_mi_load_register_reg_parameter *params)
1596 {
1597     __OUT_BATCH(batch, (MI_LOAD_REGISTER_REG | (3 - 2)));
1598     __OUT_BATCH(batch, params->src_mmio_offset);
1599     __OUT_BATCH(batch, params->dst_mmio_offset);
1600 }
1601
1602 void
1603 gen9_gpe_mi_math(VADriverContextP ctx,
1604                  struct intel_batchbuffer *batch,
1605                  struct gpe_mi_math_parameter *params)
1606 {
1607     __OUT_BATCH(batch, (MI_MATH | (params->num_instructions - 1)));
1608     intel_batchbuffer_data(batch, params->instruction_list, params->num_instructions * 4);
1609 }
1610
1611 void
1612 gen9_gpe_mi_conditional_batch_buffer_end(VADriverContextP ctx,
1613                                          struct intel_batchbuffer *batch,
1614                                          struct gpe_mi_conditional_batch_buffer_end_parameter *params)
1615 {
1616     int compare_mask_mode_enabled = MI_COMPARE_MASK_MODE_ENANBLED;
1617
1618     if (params->compare_mask_mode_disabled)
1619         compare_mask_mode_enabled = 0;
1620
1621     __OUT_BATCH(batch, (MI_CONDITIONAL_BATCH_BUFFER_END |
1622                         (1 << 21) |
1623                         compare_mask_mode_enabled |
1624                         (4 - 2))); /* Always use PPGTT */
1625     __OUT_BATCH(batch, params->compare_data);
1626     __OUT_RELOC64(batch,
1627                   params->bo,
1628                   I915_GEM_DOMAIN_RENDER | I915_GEM_DOMAIN_INSTRUCTION, 0,
1629                   params->offset);
1630 }
1631
1632 void
1633 gen8_gpe_mi_batch_buffer_start(VADriverContextP ctx,
1634                                struct intel_batchbuffer *batch,
1635                                struct gpe_mi_batch_buffer_start_parameter *params)
1636 {
1637     __OUT_BATCH(batch, (MI_BATCH_BUFFER_START |
1638                         (!!params->is_second_level << 22) |
1639                         (!params->use_global_gtt << 8) |
1640                         (1 << 0)));
1641     __OUT_RELOC64(batch,
1642                 params->bo,
1643                 I915_GEM_DOMAIN_RENDER | I915_GEM_DOMAIN_INSTRUCTION, 0,
1644                 params->offset);
1645 }
1646
1647 void
1648 gen8_gpe_context_set_dynamic_buffer(VADriverContextP ctx,
1649                                     struct i965_gpe_context *gpe_context,
1650                                     struct gpe_dynamic_state_parameter *ds)
1651 {
1652     if (!ds->bo || !gpe_context)
1653         return;
1654
1655     dri_bo_unreference(gpe_context->dynamic_state.bo);
1656     gpe_context->dynamic_state.bo = ds->bo;
1657     dri_bo_reference(gpe_context->dynamic_state.bo);
1658     gpe_context->dynamic_state.bo_size = ds->bo_size;
1659
1660     /* curbe buffer is a part of the dynamic buffer */
1661     dri_bo_unreference(gpe_context->curbe.bo);
1662     gpe_context->curbe.bo = ds->bo;
1663     dri_bo_reference(gpe_context->curbe.bo);
1664     gpe_context->curbe.offset = ds->curbe_offset;
1665
1666     /* idrt buffer is a part of the dynamic buffer */
1667     dri_bo_unreference(gpe_context->idrt.bo);
1668     gpe_context->idrt.bo = ds->bo;
1669     dri_bo_reference(gpe_context->idrt.bo);
1670     gpe_context->idrt.offset = ds->idrt_offset;
1671
1672     /* sampler buffer is a part of the dynamic buffer */
1673     dri_bo_unreference(gpe_context->sampler.bo);
1674     gpe_context->sampler.bo = ds->bo;
1675     dri_bo_reference(gpe_context->sampler.bo);
1676     gpe_context->sampler.offset = ds->sampler_offset;
1677
1678     return;
1679 }
1680
1681 void *
1682 i965_gpe_context_map_curbe(struct i965_gpe_context *gpe_context)
1683 {
1684     dri_bo_map(gpe_context->curbe.bo, 1);
1685
1686     return (char *)gpe_context->curbe.bo->virtual + gpe_context->curbe.offset;
1687 }
1688
1689 void
1690 i965_gpe_context_unmap_curbe(struct i965_gpe_context *gpe_context)
1691 {
1692     dri_bo_unmap(gpe_context->curbe.bo);
1693 }
1694
1695 void
1696 gen9_gpe_reset_binding_table(VADriverContextP ctx,
1697                               struct i965_gpe_context *gpe_context)
1698 {
1699     unsigned int *binding_table;
1700     unsigned int binding_table_offset = gpe_context->surface_state_binding_table.binding_table_offset;
1701     int i;
1702
1703     dri_bo_map(gpe_context->surface_state_binding_table.bo, 1);
1704     binding_table = (unsigned int*)((char *)gpe_context->surface_state_binding_table.bo->virtual + binding_table_offset);
1705
1706     for (i = 0; i < gpe_context->surface_state_binding_table.max_entries; i++) {
1707         *(binding_table + i) = gpe_context->surface_state_binding_table.surface_state_offset + i * SURFACE_STATE_PADDED_SIZE_GEN9;
1708     }
1709
1710     dri_bo_unmap(gpe_context->surface_state_binding_table.bo);
1711 }
1712
1713 void
1714 gen8_gpe_setup_interface_data(VADriverContextP ctx,
1715                               struct i965_gpe_context *gpe_context)
1716 {
1717     struct gen8_interface_descriptor_data *desc;
1718     int i;
1719     dri_bo *bo;
1720     unsigned char *desc_ptr;
1721
1722     bo = gpe_context->idrt.bo;
1723     dri_bo_map(bo, 1);
1724     assert(bo->virtual);
1725     desc_ptr = (unsigned char *)bo->virtual + gpe_context->idrt.offset;
1726     desc = (struct gen8_interface_descriptor_data *)desc_ptr;
1727
1728     for (i = 0; i < gpe_context->num_kernels; i++) {
1729         struct i965_kernel *kernel;
1730
1731         kernel = &gpe_context->kernels[i];
1732         assert(sizeof(*desc) == 32);
1733
1734         /*Setup the descritor table*/
1735         memset(desc, 0, sizeof(*desc));
1736         desc->desc0.kernel_start_pointer = kernel->kernel_offset >> 6;
1737         desc->desc3.sampler_count = 0;
1738         desc->desc3.sampler_state_pointer = (gpe_context->sampler.offset >> 5);
1739         desc->desc4.binding_table_entry_count = 0;
1740         desc->desc4.binding_table_pointer = (gpe_context->surface_state_binding_table.binding_table_offset >> 5);
1741         desc->desc5.constant_urb_entry_read_offset = 0;
1742         desc->desc5.constant_urb_entry_read_length = ALIGN(gpe_context->curbe.length, 32) >> 5; // in registers
1743
1744         desc++;
1745     }
1746
1747     dri_bo_unmap(bo);
1748 }
1749
1750 static void
1751 gen9_gpe_set_surface_tiling(struct gen9_surface_state *ss, unsigned int tiling)
1752 {
1753     switch (tiling) {
1754     case I915_TILING_NONE:
1755         ss->ss0.tiled_surface = 0;
1756         ss->ss0.tile_walk = 0;
1757         break;
1758     case I915_TILING_X:
1759         ss->ss0.tiled_surface = 1;
1760         ss->ss0.tile_walk = I965_TILEWALK_XMAJOR;
1761         break;
1762     case I915_TILING_Y:
1763         ss->ss0.tiled_surface = 1;
1764         ss->ss0.tile_walk = I965_TILEWALK_YMAJOR;
1765         break;
1766     }
1767 }
1768
1769 static void
1770 gen9_gpe_set_surface2_tiling(struct gen9_surface_state2 *ss, unsigned int tiling)
1771 {
1772     switch (tiling) {
1773     case I915_TILING_NONE:
1774         ss->ss2.tiled_surface = 0;
1775         ss->ss2.tile_walk = 0;
1776         break;
1777     case I915_TILING_X:
1778         ss->ss2.tiled_surface = 1;
1779         ss->ss2.tile_walk = I965_TILEWALK_XMAJOR;
1780         break;
1781     case I915_TILING_Y:
1782         ss->ss2.tiled_surface = 1;
1783         ss->ss2.tile_walk = I965_TILEWALK_YMAJOR;
1784         break;
1785     }
1786 }
1787
1788 static void
1789 gen9_gpe_set_2d_surface_state(struct gen9_surface_state *ss,
1790                               unsigned int cacheability_control,
1791                               unsigned int format,
1792                               unsigned int tiling,
1793                               unsigned int width,
1794                               unsigned int height,
1795                               unsigned int pitch,
1796                               uint64_t base_offset,
1797                               unsigned int y_offset)
1798 {
1799     memset(ss, 0, sizeof(*ss));
1800
1801     /* Always set 1(align 4 mode) */
1802     ss->ss0.vertical_alignment = 1;
1803     ss->ss0.horizontal_alignment = 1;
1804
1805     ss->ss0.surface_format = format;
1806     ss->ss0.surface_type = I965_SURFACE_2D;
1807
1808     ss->ss1.surface_mocs = cacheability_control;
1809
1810     ss->ss2.width = width - 1;
1811     ss->ss2.height = height - 1;
1812
1813     ss->ss3.pitch = pitch - 1;
1814
1815     ss->ss5.y_offset = y_offset;
1816
1817     ss->ss7.shader_chanel_select_a = HSW_SCS_ALPHA;
1818     ss->ss7.shader_chanel_select_b = HSW_SCS_BLUE;
1819     ss->ss7.shader_chanel_select_g = HSW_SCS_GREEN;
1820     ss->ss7.shader_chanel_select_r = HSW_SCS_RED;
1821
1822     ss->ss8.base_addr = (uint32_t)base_offset;
1823     ss->ss9.base_addr_high = (uint32_t)(base_offset >> 32);
1824
1825     gen9_gpe_set_surface_tiling(ss, tiling);
1826 }
1827
1828 /* This is only for NV12 format */
1829 static void
1830 gen9_gpe_set_adv_surface_state(struct gen9_surface_state2 *ss,
1831                                unsigned int v_direction,
1832                                unsigned int cacheability_control,
1833                                unsigned int format,
1834                                unsigned int tiling,
1835                                unsigned int width,
1836                                unsigned int height,
1837                                unsigned int pitch,
1838                                uint64_t base_offset,
1839                                unsigned int y_cb_offset)
1840 {
1841     memset(ss, 0, sizeof(*ss));
1842
1843     ss->ss1.cbcr_pixel_offset_v_direction = v_direction;
1844     ss->ss1.width = width - 1;
1845     ss->ss1.height = height - 1;
1846
1847     ss->ss2.surface_format = format;
1848     ss->ss2.interleave_chroma = 1;
1849     ss->ss2.pitch = pitch - 1;
1850
1851     ss->ss3.y_offset_for_cb = y_cb_offset;
1852
1853     ss->ss5.surface_object_mocs = cacheability_control;
1854
1855     ss->ss6.base_addr = (uint32_t)base_offset;
1856     ss->ss7.base_addr_high = (uint32_t)(base_offset >> 32);
1857
1858     gen9_gpe_set_surface2_tiling(ss, tiling);
1859 }
1860
1861 static void
1862 gen9_gpe_set_buffer2_surface_state(struct gen9_surface_state *ss,
1863                                    unsigned int cacheability_control,
1864                                    unsigned int format,
1865                                    unsigned int size,
1866                                    unsigned int pitch,
1867                                    uint64_t base_offset)
1868 {
1869     memset(ss, 0, sizeof(*ss));
1870
1871     ss->ss0.surface_format = format;
1872     ss->ss0.surface_type = I965_SURFACE_BUFFER;
1873
1874     ss->ss1.surface_mocs = cacheability_control;
1875
1876     ss->ss2.width = (size - 1) & 0x7F;
1877     ss->ss2.height = ((size - 1) & 0x1FFF80) >> 7;
1878
1879     ss->ss3.depth = ((size - 1) & 0xFE00000) >> 21;
1880     ss->ss3.pitch = pitch - 1;
1881
1882     ss->ss7.shader_chanel_select_a = HSW_SCS_ALPHA;
1883     ss->ss7.shader_chanel_select_b = HSW_SCS_BLUE;
1884     ss->ss7.shader_chanel_select_g = HSW_SCS_GREEN;
1885     ss->ss7.shader_chanel_select_r = HSW_SCS_RED;
1886
1887     ss->ss8.base_addr = (uint32_t)base_offset;
1888     ss->ss9.base_addr_high = (uint32_t)(base_offset >> 32);
1889 }
1890
1891 void
1892 gen9_gpe_context_add_surface(struct i965_gpe_context *gpe_context,
1893                              struct i965_gpe_surface *gpe_surface,
1894                              int index)
1895 {
1896     char *buf;
1897     unsigned int tiling, swizzle, width, height, pitch, tile_alignment, y_offset = 0;
1898     unsigned int surface_state_offset = gpe_context->surface_state_binding_table.surface_state_offset +
1899         index * SURFACE_STATE_PADDED_SIZE_GEN9;
1900     unsigned int binding_table_offset = gpe_context->surface_state_binding_table.binding_table_offset +
1901         index * 4;
1902     struct i965_gpe_resource *gpe_resource = gpe_surface->gpe_resource;
1903
1904     dri_bo_get_tiling(gpe_resource->bo, &tiling, &swizzle);
1905
1906     dri_bo_map(gpe_context->surface_state_binding_table.bo, 1);
1907     buf = (char *)gpe_context->surface_state_binding_table.bo->virtual;
1908     *((unsigned int *)(buf + binding_table_offset)) = surface_state_offset;
1909
1910     if (gpe_surface->is_2d_surface && gpe_surface->is_override_offset) {
1911         struct gen9_surface_state *ss = (struct gen9_surface_state *)(buf + surface_state_offset);
1912
1913         width = gpe_resource->width;
1914         height = gpe_resource->height;
1915         pitch = gpe_resource->pitch;
1916
1917         if (gpe_surface->is_media_block_rw) {
1918             if (gpe_surface->is_16bpp)
1919                 width = (ALIGN(width * 2, 4) >> 2);
1920             else
1921                 width = (ALIGN(width, 4) >> 2);
1922         }
1923
1924
1925         gen9_gpe_set_2d_surface_state(ss,
1926                                       gpe_surface->cacheability_control,
1927                                       gpe_surface->format,
1928                                       tiling,
1929                                       width, height, pitch,
1930                                       gpe_resource->bo->offset64 + gpe_surface->offset,
1931                                       0);
1932
1933         dri_bo_emit_reloc(gpe_context->surface_state_binding_table.bo,
1934                           I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
1935                           gpe_surface->offset,
1936                           surface_state_offset + offsetof(struct gen9_surface_state, ss8),
1937                           gpe_resource->bo);
1938     } else if (gpe_surface->is_2d_surface && gpe_surface->is_uv_surface) {
1939         unsigned int cbcr_offset;
1940         struct gen9_surface_state *ss = (struct gen9_surface_state *)(buf + surface_state_offset);
1941
1942         width = gpe_resource->width;
1943         height = gpe_resource->height / 2;
1944         pitch = gpe_resource->pitch;
1945
1946         if (gpe_surface->is_media_block_rw) {
1947             if (gpe_surface->is_16bpp)
1948                 width = (ALIGN(width * 2, 4) >> 2);
1949             else
1950                 width = (ALIGN(width, 4) >> 2);
1951         }
1952
1953         if (tiling == I915_TILING_Y) {
1954             tile_alignment = 32;
1955         } else if (tiling == I915_TILING_X) {
1956             tile_alignment = 8;
1957         } else
1958             tile_alignment = 1;
1959
1960         y_offset = (gpe_resource->y_cb_offset % tile_alignment);
1961         cbcr_offset = ALIGN_FLOOR(gpe_resource->y_cb_offset, tile_alignment) * pitch;
1962
1963         gen9_gpe_set_2d_surface_state(ss,
1964                                       gpe_surface->cacheability_control,
1965                                       I965_SURFACEFORMAT_R16_UINT,
1966                                       tiling,
1967                                       width, height, pitch,
1968                                       gpe_resource->bo->offset64 + cbcr_offset,
1969                                       y_offset);
1970
1971         dri_bo_emit_reloc(gpe_context->surface_state_binding_table.bo,
1972                           I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
1973                           cbcr_offset,
1974                           surface_state_offset + offsetof(struct gen9_surface_state, ss8),
1975                           gpe_resource->bo);
1976     } else if (gpe_surface->is_2d_surface) {
1977         struct gen9_surface_state *ss = (struct gen9_surface_state *)(buf + surface_state_offset);
1978
1979         width = gpe_resource->width;
1980         height = gpe_resource->height;
1981         pitch = gpe_resource->pitch;
1982
1983         if (gpe_surface->is_media_block_rw) {
1984             if (gpe_surface->is_16bpp)
1985                 width = (ALIGN(width * 2, 4) >> 2);
1986             else
1987                 width = (ALIGN(width, 4) >> 2);
1988         }
1989
1990         gen9_gpe_set_2d_surface_state(ss,
1991                                       gpe_surface->cacheability_control,
1992                                       gpe_surface->format,
1993                                       tiling,
1994                                       width, height, pitch,
1995                                       gpe_resource->bo->offset64,
1996                                       y_offset);
1997
1998         dri_bo_emit_reloc(gpe_context->surface_state_binding_table.bo,
1999                           I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
2000                           0,
2001                           surface_state_offset + offsetof(struct gen9_surface_state, ss8),
2002                           gpe_resource->bo);
2003     } else if (gpe_surface->is_adv_surface) {
2004         struct gen9_surface_state2 *ss = (struct gen9_surface_state2 *)(buf + surface_state_offset);
2005
2006         width = gpe_resource->width;
2007         height = gpe_resource->height;
2008         pitch = gpe_resource->pitch;
2009
2010         gen9_gpe_set_adv_surface_state(ss,
2011                                        gpe_surface->v_direction,
2012                                        gpe_surface->cacheability_control,
2013                                        MFX_SURFACE_PLANAR_420_8,
2014                                        tiling,
2015                                        width, height, pitch,
2016                                        gpe_resource->bo->offset64,
2017                                        gpe_resource->y_cb_offset);
2018
2019         dri_bo_emit_reloc(gpe_context->surface_state_binding_table.bo,
2020                           I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
2021                           0,
2022                           surface_state_offset + offsetof(struct gen9_surface_state2, ss6),
2023                           gpe_resource->bo);
2024     } else {
2025         struct gen9_surface_state *ss = (struct gen9_surface_state *)(buf + surface_state_offset);
2026         unsigned int format;
2027
2028         assert(gpe_surface->is_buffer);
2029
2030         if (gpe_surface->is_raw_buffer) {
2031             format = I965_SURFACEFORMAT_RAW;
2032             pitch = 1;
2033         } else {
2034             format = I965_SURFACEFORMAT_R32_UINT;
2035             pitch = sizeof(unsigned int);
2036         }
2037
2038         gen9_gpe_set_buffer2_surface_state(ss,
2039                                            gpe_surface->cacheability_control,
2040                                            format,
2041                                            gpe_surface->size,
2042                                            pitch,
2043                                            gpe_resource->bo->offset64 + gpe_surface->offset);
2044
2045         dri_bo_emit_reloc(gpe_context->surface_state_binding_table.bo,
2046                           I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
2047                           gpe_surface->offset,
2048                           surface_state_offset + offsetof(struct gen9_surface_state, ss8),
2049                           gpe_resource->bo);
2050     }
2051
2052     dri_bo_unmap(gpe_context->surface_state_binding_table.bo);
2053 }
2054
2055 bool
2056 i965_gpe_allocate_2d_resource(dri_bufmgr *bufmgr,
2057                            struct i965_gpe_resource *res,
2058                            int width,
2059                            int height,
2060                            int pitch,
2061                            const char *name)
2062 {
2063     int bo_size;
2064
2065     if (!res)
2066         return false;
2067
2068     res->type = I965_GPE_RESOURCE_2D;
2069     res->width = width;
2070     res->height = height;
2071     res->pitch = pitch;
2072
2073     bo_size = ALIGN(height, 16) * pitch;
2074     res->size = bo_size;
2075
2076     res->bo = dri_bo_alloc(bufmgr, name, res->size, 4096);
2077     res->map = NULL;
2078
2079     return true;
2080 }
2081
2082 void
2083 gen8_gpe_media_state_flush(VADriverContextP ctx,
2084                            struct i965_gpe_context *gpe_context,
2085                            struct intel_batchbuffer *batch)
2086 {
2087     BEGIN_BATCH(batch, 2);
2088
2089     OUT_BATCH(batch, CMD_MEDIA_STATE_FLUSH | (2 - 2));
2090     OUT_BATCH(batch, 0);
2091
2092     ADVANCE_BATCH(batch);
2093 }
2094
2095 void
2096 gen8_gpe_media_object(VADriverContextP ctx,
2097                       struct i965_gpe_context *gpe_context,
2098                       struct intel_batchbuffer *batch,
2099                       struct gpe_media_object_parameter *param)
2100 {
2101     int batch_size, subdata_size;
2102
2103     batch_size = 6;
2104     subdata_size = 0;
2105     if (param->pinline_data && param->inline_size) {
2106         subdata_size = ALIGN(param->inline_size, 4);
2107         batch_size += subdata_size / 4;
2108     }
2109     BEGIN_BATCH(batch, batch_size);
2110     OUT_BATCH(batch, CMD_MEDIA_OBJECT | (batch_size - 2));
2111     OUT_BATCH(batch, param->interface_offset);
2112     OUT_BATCH(batch, param->use_scoreboard << 21);
2113     OUT_BATCH(batch, 0);
2114     OUT_BATCH(batch, (param->scoreboard_y << 16 |
2115                       param->scoreboard_x));
2116     OUT_BATCH(batch, param->scoreboard_mask);
2117
2118     if (subdata_size)
2119         intel_batchbuffer_data(batch, param->pinline_data, subdata_size);
2120
2121     ADVANCE_BATCH(batch);
2122 }
2123
2124 void
2125 gen8_gpe_media_object_walker(VADriverContextP ctx,
2126                              struct i965_gpe_context *gpe_context,
2127                              struct intel_batchbuffer *batch,
2128                              struct gpe_media_object_walker_parameter *param)
2129 {
2130     int walker_length;
2131
2132     walker_length = 17;
2133     if (param->inline_size)
2134         walker_length += ALIGN(param->inline_size, 4) / 4;
2135     BEGIN_BATCH(batch, walker_length);
2136     OUT_BATCH(batch, CMD_MEDIA_OBJECT_WALKER | (walker_length - 2));
2137     OUT_BATCH(batch, param->interface_offset);
2138     OUT_BATCH(batch, param->use_scoreboard << 21);
2139     OUT_BATCH(batch, 0);
2140     OUT_BATCH(batch, 0);
2141     OUT_BATCH(batch, (param->group_id_loop_select << 8 |
2142                       param->scoreboard_mask)); // DW5
2143     OUT_BATCH(batch, (param->color_count_minus1 << 24 |
2144                       param->middle_loop_extra_steps << 16 |
2145                       param->mid_loop_unit_y << 12 |
2146                       param->mid_loop_unit_x << 8));
2147     OUT_BATCH(batch, ((param->global_loop_exec_count & 0x3ff) << 16 |
2148                       (param->local_loop_exec_count & 0x3ff)));
2149     OUT_BATCH(batch, param->block_resolution.value);
2150     OUT_BATCH(batch, param->local_start.value);
2151     OUT_BATCH(batch, 0); // DW10
2152     OUT_BATCH(batch, param->local_outer_loop_stride.value);
2153     OUT_BATCH(batch, param->local_inner_loop_unit.value);
2154     OUT_BATCH(batch, param->global_resolution.value);
2155     OUT_BATCH(batch, param->global_start.value);
2156     OUT_BATCH(batch, param->global_outer_loop_stride.value);
2157     OUT_BATCH(batch, param->global_inner_loop_unit.value);
2158
2159     if (param->pinline_data && param->inline_size)
2160         intel_batchbuffer_data(batch, param->pinline_data, ALIGN(param->inline_size, 4));
2161
2162     ADVANCE_BATCH(batch);
2163 }
2164
2165
2166 void
2167 intel_vpp_init_media_object_walker_parameter(struct intel_vpp_kernel_walker_parameter *kernel_walker_param,
2168                                         struct gpe_media_object_walker_parameter *walker_param)
2169 {
2170     memset(walker_param, 0, sizeof(*walker_param));
2171
2172     walker_param->use_scoreboard = kernel_walker_param->use_scoreboard;
2173
2174     walker_param->block_resolution.x = kernel_walker_param->resolution_x;
2175     walker_param->block_resolution.y = kernel_walker_param->resolution_y;
2176
2177     walker_param->global_resolution.x = kernel_walker_param->resolution_x;
2178     walker_param->global_resolution.y = kernel_walker_param->resolution_y;
2179
2180     walker_param->global_outer_loop_stride.x = kernel_walker_param->resolution_x;
2181     walker_param->global_outer_loop_stride.y = 0;
2182
2183     walker_param->global_inner_loop_unit.x = 0;
2184     walker_param->global_inner_loop_unit.y = kernel_walker_param->resolution_y;
2185
2186     walker_param->local_loop_exec_count = 0xFFFF;  //MAX VALUE
2187     walker_param->global_loop_exec_count = 0xFFFF;  //MAX VALUE
2188
2189     if (kernel_walker_param->no_dependency) {
2190         /* The no_dependency is used for VPP */
2191         walker_param->scoreboard_mask = 0;
2192         walker_param->use_scoreboard = 0;
2193         // Raster scan walking pattern
2194         walker_param->local_outer_loop_stride.x = 0;
2195         walker_param->local_outer_loop_stride.y = 1;
2196         walker_param->local_inner_loop_unit.x = 1;
2197         walker_param->local_inner_loop_unit.y = 0;
2198         walker_param->local_end.x = kernel_walker_param->resolution_x - 1;
2199         walker_param->local_end.y = 0;
2200     } else {
2201         walker_param->local_end.x = 0;
2202         walker_param->local_end.y = 0;
2203
2204         // 26 degree
2205         walker_param->scoreboard_mask = 0x0F;
2206         walker_param->local_outer_loop_stride.x = 1;
2207         walker_param->local_outer_loop_stride.y = 0;
2208         walker_param->local_inner_loop_unit.x = -2;
2209         walker_param->local_inner_loop_unit.y = 1;
2210     }
2211 }
2212
2213 void
2214 gen8_gpe_reset_binding_table(VADriverContextP ctx, struct i965_gpe_context *gpe_context)
2215 {
2216     unsigned int *binding_table;
2217     unsigned int binding_table_offset = gpe_context->surface_state_binding_table.binding_table_offset;
2218     int i;
2219
2220     dri_bo_map(gpe_context->surface_state_binding_table.bo, 1);
2221     binding_table = (unsigned int*)((char *)gpe_context->surface_state_binding_table.bo->virtual + binding_table_offset);
2222
2223     for (i = 0; i < gpe_context->surface_state_binding_table.max_entries; i++) {
2224         *(binding_table + i) = gpe_context->surface_state_binding_table.surface_state_offset + i * SURFACE_STATE_PADDED_SIZE_GEN8;
2225     }
2226
2227     dri_bo_unmap(gpe_context->surface_state_binding_table.bo);
2228 }
2229
2230 static void
2231 gen8_gpe_set_2d_surface_state(struct gen8_surface_state *ss,
2232                               unsigned int vert_line_stride_offset,
2233                               unsigned int vert_line_stride,
2234                               unsigned int cacheability_control,
2235                               unsigned int format,
2236                               unsigned int tiling,
2237                               unsigned int width,
2238                               unsigned int height,
2239                               unsigned int pitch,
2240                               unsigned int base_offset,
2241                               unsigned int y_offset)
2242 {
2243     memset(ss, 0, sizeof(*ss));
2244
2245     ss->ss0.vert_line_stride_ofs = vert_line_stride_offset;
2246     ss->ss0.vert_line_stride = vert_line_stride;
2247     ss->ss0.surface_format = format;
2248     ss->ss0.surface_type = I965_SURFACE_2D;
2249
2250     ss->ss1.surface_mocs = cacheability_control;
2251
2252     ss->ss2.width = width - 1;
2253     ss->ss2.height = height - 1;
2254
2255     ss->ss3.pitch = pitch - 1;
2256
2257     ss->ss5.y_offset = y_offset;
2258
2259     ss->ss7.shader_chanel_select_a = HSW_SCS_ALPHA;
2260     ss->ss7.shader_chanel_select_b = HSW_SCS_BLUE;
2261     ss->ss7.shader_chanel_select_g = HSW_SCS_GREEN;
2262     ss->ss7.shader_chanel_select_r = HSW_SCS_RED;
2263
2264     ss->ss8.base_addr = base_offset;
2265
2266     gen8_gpe_set_surface_tiling(ss, tiling);
2267 }
2268
2269 static void
2270 gen8_gpe_set_adv_surface_state(struct gen8_surface_state2 *ss,
2271                                unsigned int v_direction,
2272                                unsigned int cacheability_control,
2273                                unsigned int format,
2274                                unsigned int tiling,
2275                                unsigned int width,
2276                                unsigned int height,
2277                                unsigned int pitch,
2278                                unsigned int base_offset,
2279                                unsigned int y_cb_offset)
2280 {
2281     memset(ss, 0, sizeof(*ss));
2282
2283     ss->ss1.cbcr_pixel_offset_v_direction = v_direction;
2284     ss->ss1.width = width - 1;
2285     ss->ss1.height = height - 1;
2286
2287     ss->ss2.surface_format = format;
2288     ss->ss2.interleave_chroma = 1;
2289     ss->ss2.pitch = pitch - 1;
2290
2291     ss->ss3.y_offset_for_cb = y_cb_offset;
2292
2293     ss->ss5.surface_object_mocs = cacheability_control;
2294
2295     ss->ss6.base_addr = base_offset;
2296
2297     gen8_gpe_set_surface2_tiling(ss, tiling);
2298 }
2299
2300 static void
2301 gen8_gpe_set_buffer2_surface_state(struct gen8_surface_state *ss,
2302                                    unsigned int cacheability_control,
2303                                    unsigned int format,
2304                                    unsigned int size,
2305                                    unsigned int pitch,
2306                                    unsigned int base_offset)
2307 {
2308     memset(ss, 0, sizeof(*ss));
2309
2310     ss->ss0.surface_format = format;
2311     ss->ss0.surface_type = I965_SURFACE_BUFFER;
2312
2313     ss->ss1.surface_mocs = cacheability_control;
2314
2315     ss->ss2.width = (size - 1) & 0x7F;
2316     ss->ss2.height = ((size - 1) & 0x1FFF80) >> 7;
2317
2318     ss->ss3.depth = ((size - 1) & 0xFE00000) >> 21;
2319     ss->ss3.pitch = pitch - 1;
2320
2321     ss->ss7.shader_chanel_select_a = HSW_SCS_ALPHA;
2322     ss->ss7.shader_chanel_select_b = HSW_SCS_BLUE;
2323     ss->ss7.shader_chanel_select_g = HSW_SCS_GREEN;
2324     ss->ss7.shader_chanel_select_r = HSW_SCS_RED;
2325
2326     ss->ss8.base_addr = base_offset;
2327 }
2328
2329 void
2330 gen8_gpe_context_add_surface(struct i965_gpe_context *gpe_context,
2331                              struct i965_gpe_surface *gpe_surface,
2332                              int index)
2333 {
2334     char *buf;
2335     unsigned int tiling, swizzle, width, height, pitch, tile_alignment, y_offset = 0;
2336     unsigned int surface_state_offset = gpe_context->surface_state_binding_table.surface_state_offset +
2337         index * SURFACE_STATE_PADDED_SIZE_GEN8;
2338     unsigned int binding_table_offset = gpe_context->surface_state_binding_table.binding_table_offset +
2339         index * 4;
2340     struct i965_gpe_resource *gpe_resource = gpe_surface->gpe_resource;
2341
2342     dri_bo_get_tiling(gpe_resource->bo, &tiling, &swizzle);
2343
2344     dri_bo_map(gpe_context->surface_state_binding_table.bo, 1);
2345     buf = (char *)gpe_context->surface_state_binding_table.bo->virtual;
2346     *((unsigned int *)(buf + binding_table_offset)) = surface_state_offset;
2347
2348     if (gpe_surface->is_2d_surface) {
2349         struct gen8_surface_state *ss = (struct gen8_surface_state *)(buf + surface_state_offset);
2350         unsigned int target_offset;
2351
2352         width = gpe_resource->width;
2353         height = gpe_resource->height;
2354         pitch = gpe_resource->pitch;
2355
2356         if (gpe_surface->is_override_offset) {
2357             y_offset = 0;
2358             target_offset = gpe_surface->offset;
2359         } else if (gpe_surface->is_uv_surface) {
2360             height /= 2;
2361
2362             if (tiling == I915_TILING_Y) {
2363                 tile_alignment = 32;
2364             } else if (tiling == I915_TILING_X) {
2365                 tile_alignment = 8;
2366             } else
2367                 tile_alignment = 1;
2368
2369             y_offset = (gpe_resource->y_cb_offset % tile_alignment);
2370             target_offset = ALIGN_FLOOR(gpe_resource->y_cb_offset, tile_alignment) * pitch;
2371         } else {
2372             y_offset = 0;
2373             target_offset = 0;
2374         }
2375
2376         if (gpe_surface->is_media_block_rw) {
2377             width = (ALIGN(width, 4) >> 2);
2378         }
2379
2380         gen8_gpe_set_2d_surface_state(ss,
2381                                       gpe_surface->vert_line_stride_offset,
2382                                       gpe_surface->vert_line_stride,
2383                                       gpe_surface->cacheability_control,
2384                                       gpe_surface->format,
2385                                       tiling,
2386                                       width, height, pitch,
2387                                       gpe_resource->bo->offset64 + target_offset,
2388                                       y_offset);
2389
2390         dri_bo_emit_reloc(gpe_context->surface_state_binding_table.bo,
2391                           I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
2392                           target_offset,
2393                           surface_state_offset + offsetof(struct gen8_surface_state, ss8),
2394                           gpe_resource->bo);
2395     } else if (gpe_surface->is_adv_surface) {
2396         struct gen8_surface_state2 *ss = (struct gen8_surface_state2 *)(buf + surface_state_offset);
2397
2398         width = gpe_resource->width;
2399         height = gpe_resource->height;
2400         pitch = gpe_resource->pitch;
2401
2402         gen8_gpe_set_adv_surface_state(ss,
2403                                        gpe_surface->v_direction,
2404                                        gpe_surface->cacheability_control,
2405                                        MFX_SURFACE_PLANAR_420_8,
2406                                        tiling,
2407                                        width, height, pitch,
2408                                        gpe_resource->bo->offset64,
2409                                        gpe_resource->y_cb_offset);
2410
2411         dri_bo_emit_reloc(gpe_context->surface_state_binding_table.bo,
2412                           I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
2413                           0,
2414                           surface_state_offset + offsetof(struct gen8_surface_state2, ss6),
2415                           gpe_resource->bo);
2416     } else {
2417         struct gen8_surface_state *ss = (struct gen8_surface_state *)(buf + surface_state_offset);
2418         unsigned int format;
2419
2420         assert(gpe_surface->is_buffer);
2421
2422         if (gpe_surface->is_raw_buffer) {
2423             format = I965_SURFACEFORMAT_RAW;
2424             pitch = 1;
2425         } else {
2426             format = I965_SURFACEFORMAT_R32_UINT;
2427             pitch = sizeof(unsigned int);
2428         }
2429
2430         gen8_gpe_set_buffer2_surface_state(ss,
2431                                            gpe_surface->cacheability_control,
2432                                            format,
2433                                            gpe_surface->size,
2434                                            pitch,
2435                                            gpe_resource->bo->offset64 + gpe_surface->offset);
2436
2437         dri_bo_emit_reloc(gpe_context->surface_state_binding_table.bo,
2438                           I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
2439                           gpe_surface->offset,
2440                           surface_state_offset + offsetof(struct gen8_surface_state, ss8),
2441                           gpe_resource->bo);
2442     }
2443
2444     dri_bo_unmap(gpe_context->surface_state_binding_table.bo);
2445 }
2446
2447 void
2448 gen8_gpe_mi_conditional_batch_buffer_end(VADriverContextP ctx,
2449                                          struct intel_batchbuffer *batch,
2450                                          struct gpe_mi_conditional_batch_buffer_end_parameter *param)
2451 {
2452     __OUT_BATCH(batch, (MI_CONDITIONAL_BATCH_BUFFER_END |
2453                         (1 << 21) |
2454                         (4 - 2))); /* Always use PPGTT */
2455     __OUT_BATCH(batch, param->compare_data);
2456     __OUT_RELOC64(batch,
2457                   param->bo,
2458                   I915_GEM_DOMAIN_RENDER | I915_GEM_DOMAIN_INSTRUCTION, 0,
2459                   param->offset);
2460
2461 }
2462
2463 void
2464 gen8_gpe_pipe_control(VADriverContextP ctx,
2465                       struct intel_batchbuffer *batch,
2466                       struct gpe_pipe_control_parameter *param)
2467 {
2468     int render_target_cache_flush_enable = CMD_PIPE_CONTROL_WC_FLUSH;
2469     int dc_flush_enable = 0;
2470     int state_cache_invalidation_enable = 0;
2471     int constant_cache_invalidation_enable = 0;
2472     int vf_cache_invalidation_enable = 0;
2473     int instruction_cache_invalidation_enable = 0;
2474     int post_sync_operation = CMD_PIPE_CONTROL_NOWRITE;
2475     int use_global_gtt = CMD_PIPE_CONTROL_GLOBAL_GTT_GEN8;
2476     int cs_stall_enable = !param->disable_cs_stall;
2477
2478     switch (param->flush_mode) {
2479     case PIPE_CONTROL_FLUSH_WRITE_CACHE:
2480         render_target_cache_flush_enable = CMD_PIPE_CONTROL_WC_FLUSH;
2481         dc_flush_enable = CMD_PIPE_CONTROL_DC_FLUSH;
2482         break;
2483
2484     case PIPE_CONTROL_FLUSH_READ_CACHE:
2485         render_target_cache_flush_enable = 0;
2486         state_cache_invalidation_enable = CMD_PIPE_CONTROL_SC_INVALIDATION_GEN8;
2487         constant_cache_invalidation_enable = CMD_PIPE_CONTROL_CC_INVALIDATION_GEN8;
2488         vf_cache_invalidation_enable = CMD_PIPE_CONTROL_VFC_INVALIDATION_GEN8;
2489         instruction_cache_invalidation_enable = CMD_PIPE_CONTROL_IS_FLUSH;
2490         break;
2491
2492     case PIPE_CONTROL_FLUSH_NONE:
2493     default:
2494         render_target_cache_flush_enable = 0;
2495         break;
2496     }
2497
2498     if (param->bo) {
2499         post_sync_operation = CMD_PIPE_CONTROL_WRITE_QWORD;
2500         use_global_gtt = CMD_PIPE_CONTROL_LOCAL_PGTT_GEN8;
2501     } else {
2502         post_sync_operation = CMD_PIPE_CONTROL_NOWRITE;
2503         render_target_cache_flush_enable = CMD_PIPE_CONTROL_WC_FLUSH;
2504         state_cache_invalidation_enable = CMD_PIPE_CONTROL_SC_INVALIDATION_GEN8;
2505         constant_cache_invalidation_enable = CMD_PIPE_CONTROL_CC_INVALIDATION_GEN8;
2506         vf_cache_invalidation_enable = CMD_PIPE_CONTROL_VFC_INVALIDATION_GEN8;
2507         instruction_cache_invalidation_enable = CMD_PIPE_CONTROL_IS_FLUSH;
2508     }
2509
2510     __OUT_BATCH(batch, CMD_PIPE_CONTROL | (6 - 2));
2511     __OUT_BATCH(batch, (render_target_cache_flush_enable |
2512                         dc_flush_enable |
2513                         state_cache_invalidation_enable |
2514                         constant_cache_invalidation_enable |
2515                         vf_cache_invalidation_enable |
2516                         instruction_cache_invalidation_enable |
2517                         post_sync_operation |
2518                         use_global_gtt |
2519                         cs_stall_enable |
2520                         CMD_PIPE_CONTROL_FLUSH_ENABLE));
2521
2522     if (param->bo)
2523         __OUT_RELOC64(batch,
2524                       param->bo,
2525                       I915_GEM_DOMAIN_RENDER | I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_RENDER,
2526                       param->offset);
2527     else {
2528         __OUT_BATCH(batch, 0);
2529         __OUT_BATCH(batch, 0);
2530     }
2531
2532     __OUT_BATCH(batch, param->dw0);
2533     __OUT_BATCH(batch, param->dw1);
2534 }
2535
2536 void
2537 i965_init_media_object_walker_parameter(struct gpe_encoder_kernel_walker_parameter *kernel_walker_param,
2538                                         struct gpe_media_object_walker_parameter *walker_param)
2539 {
2540     memset(walker_param, 0, sizeof(*walker_param));
2541
2542     walker_param->use_scoreboard = kernel_walker_param->use_scoreboard;
2543
2544     walker_param->block_resolution.x = kernel_walker_param->resolution_x;
2545     walker_param->block_resolution.y = kernel_walker_param->resolution_y;
2546
2547     walker_param->global_resolution.x = kernel_walker_param->resolution_x;
2548     walker_param->global_resolution.y = kernel_walker_param->resolution_y;
2549
2550     walker_param->global_outer_loop_stride.x = kernel_walker_param->resolution_x;
2551     walker_param->global_outer_loop_stride.y = 0;
2552
2553     walker_param->global_inner_loop_unit.x = 0;
2554     walker_param->global_inner_loop_unit.y = kernel_walker_param->resolution_y;
2555
2556     walker_param->local_loop_exec_count = 0xFFFF;  //MAX VALUE
2557     walker_param->global_loop_exec_count = 0xFFFF;  //MAX VALUE
2558
2559     if (kernel_walker_param->no_dependency) {
2560         walker_param->scoreboard_mask = 0;
2561         // Raster scan walking pattern
2562         walker_param->local_outer_loop_stride.x = 0;
2563         walker_param->local_outer_loop_stride.y = 1;
2564         walker_param->local_inner_loop_unit.x = 1;
2565         walker_param->local_inner_loop_unit.y = 0;
2566         walker_param->local_end.x = kernel_walker_param->resolution_x - 1;
2567         walker_param->local_end.y = 0;
2568     } else if (kernel_walker_param->use_vertical_raster_scan) {
2569         walker_param->scoreboard_mask = 0x1;
2570         walker_param->use_scoreboard = 0;
2571         // Raster scan walking pattern
2572         walker_param->local_outer_loop_stride.x = 1;
2573         walker_param->local_outer_loop_stride.y = 0;
2574         walker_param->local_inner_loop_unit.x = 0;
2575         walker_param->local_inner_loop_unit.y = 1;
2576         walker_param->local_end.x = 0;
2577         walker_param->local_end.y = kernel_walker_param->resolution_y - 1;
2578     } else {
2579         walker_param->local_end.x = 0;
2580         walker_param->local_end.y = 0;
2581
2582         if (kernel_walker_param->walker_degree == WALKER_45Z_DEGREE) {
2583             // 45z degree vp9
2584             walker_param->scoreboard_mask = 0x0F;
2585
2586             walker_param->global_loop_exec_count = 0x3FF;
2587             walker_param->local_loop_exec_count = 0x3FF;
2588
2589             walker_param->global_resolution.x = (unsigned int)(kernel_walker_param->resolution_x / 2.f) + 1;
2590             walker_param->global_resolution.y = 2 * kernel_walker_param->resolution_y;
2591
2592             walker_param->global_start.x = 0;
2593             walker_param->global_start.y = 0;
2594
2595             walker_param->global_outer_loop_stride.x = walker_param->global_resolution.x;
2596             walker_param->global_outer_loop_stride.y = 0;
2597
2598             walker_param->global_inner_loop_unit.x = 0;
2599             walker_param->global_inner_loop_unit.y = walker_param->global_resolution.y;
2600
2601             walker_param->block_resolution.x = walker_param->global_resolution.x;
2602             walker_param->block_resolution.y = walker_param->global_resolution.y;
2603
2604             walker_param->local_start.x = 0;
2605             walker_param->local_start.y = 0;
2606
2607             walker_param->local_outer_loop_stride.x = 1;
2608             walker_param->local_outer_loop_stride.y = 0;
2609
2610             walker_param->local_inner_loop_unit.x = -1;
2611             walker_param->local_inner_loop_unit.y = 4;
2612
2613             walker_param->middle_loop_extra_steps = 3;
2614             walker_param->mid_loop_unit_x = 0;
2615             walker_param->mid_loop_unit_y = 1;
2616         } else if (kernel_walker_param->walker_degree == WALKER_45_DEGREE) {
2617
2618             walker_param->scoreboard_mask = 0x03;
2619             // 45 order in local loop
2620             walker_param->local_outer_loop_stride.x = 1;
2621             walker_param->local_outer_loop_stride.y = 0;
2622             walker_param->local_inner_loop_unit.x = -1;
2623             walker_param->local_inner_loop_unit.y = 1;
2624         } else if (kernel_walker_param->walker_degree == WALKER_26Z_DEGREE) {
2625             // 26z HEVC
2626             walker_param->scoreboard_mask = 0x7f;
2627
2628             // z order in local loop
2629             walker_param->local_outer_loop_stride.x = 0;
2630             walker_param->local_outer_loop_stride.y = 1;
2631             walker_param->local_inner_loop_unit.x = 1;
2632             walker_param->local_inner_loop_unit.y = 0;
2633
2634             walker_param->block_resolution.x = 2;
2635             walker_param->block_resolution.y = 2;
2636
2637             walker_param->global_outer_loop_stride.x = 2;
2638             walker_param->global_outer_loop_stride.y = 0;
2639
2640             walker_param->global_inner_loop_unit.x = 0xFFF - 4 + 1;
2641             walker_param->global_inner_loop_unit.y = 2;
2642
2643         } else {
2644             // 26 degree
2645             walker_param->scoreboard_mask = 0x0F;
2646             walker_param->local_outer_loop_stride.x = 1;
2647             walker_param->local_outer_loop_stride.y = 0;
2648             walker_param->local_inner_loop_unit.x = -2;
2649             walker_param->local_inner_loop_unit.y = 1;
2650         }
2651     }
2652 }
2653
2654 void
2655 gen9_add_2d_gpe_surface(VADriverContextP ctx,
2656                         struct i965_gpe_context *gpe_context,
2657                         struct object_surface *obj_surface,
2658                         int is_uv_surface,
2659                         int is_media_block_rw,
2660                         unsigned int format,
2661                         int index)
2662 {
2663     struct i965_driver_data *i965 = i965_driver_data(ctx);
2664     struct i965_gpe_resource gpe_resource;
2665     struct i965_gpe_surface gpe_surface;
2666
2667     memset(&gpe_surface, 0, sizeof(gpe_surface));
2668
2669     i965_object_surface_to_2d_gpe_resource(&gpe_resource, obj_surface);
2670     gpe_surface.gpe_resource = &gpe_resource;
2671     gpe_surface.is_2d_surface = 1;
2672     gpe_surface.is_uv_surface = !!is_uv_surface;
2673     gpe_surface.is_media_block_rw = !!is_media_block_rw;
2674
2675     gpe_surface.cacheability_control = i965->intel.mocs_state;
2676     gpe_surface.format = format;
2677
2678     gen9_gpe_context_add_surface(gpe_context, &gpe_surface, index);
2679     i965_free_gpe_resource(&gpe_resource);
2680 }
2681
2682 void
2683 gen9_add_adv_gpe_surface(VADriverContextP ctx,
2684                          struct i965_gpe_context *gpe_context,
2685                          struct object_surface *obj_surface,
2686                          int index)
2687 {
2688     struct i965_driver_data *i965 = i965_driver_data(ctx);
2689     struct i965_gpe_resource gpe_resource;
2690     struct i965_gpe_surface gpe_surface;
2691
2692     memset(&gpe_surface, 0, sizeof(gpe_surface));
2693
2694     i965_object_surface_to_2d_gpe_resource(&gpe_resource, obj_surface);
2695     gpe_surface.gpe_resource = &gpe_resource;
2696     gpe_surface.is_adv_surface = 1;
2697     gpe_surface.cacheability_control = i965->intel.mocs_state;
2698     gpe_surface.v_direction = 2;
2699
2700     gen9_gpe_context_add_surface(gpe_context, &gpe_surface, index);
2701     i965_free_gpe_resource(&gpe_resource);
2702 }
2703
2704 void
2705 gen9_add_buffer_gpe_surface(VADriverContextP ctx,
2706                             struct i965_gpe_context *gpe_context,
2707                             struct i965_gpe_resource *gpe_buffer,
2708                             int is_raw_buffer,
2709                             unsigned int size,
2710                             unsigned int offset,
2711                             int index)
2712 {
2713     struct i965_driver_data *i965 = i965_driver_data(ctx);
2714     struct i965_gpe_surface gpe_surface;
2715
2716     memset(&gpe_surface, 0, sizeof(gpe_surface));
2717
2718     gpe_surface.gpe_resource = gpe_buffer;
2719     gpe_surface.is_buffer = 1;
2720     gpe_surface.is_raw_buffer = !!is_raw_buffer;
2721     gpe_surface.cacheability_control = i965->intel.mocs_state;
2722     gpe_surface.size = size;
2723     gpe_surface.offset = offset;
2724
2725     gen9_gpe_context_add_surface(gpe_context, &gpe_surface, index);
2726 }
2727
2728 void
2729 gen9_add_buffer_2d_gpe_surface(VADriverContextP ctx,
2730                                struct i965_gpe_context *gpe_context,
2731                                struct i965_gpe_resource *gpe_buffer,
2732                                int is_media_block_rw,
2733                                unsigned int format,
2734                                int index)
2735 {
2736     struct i965_driver_data *i965 = i965_driver_data(ctx);
2737     struct i965_gpe_surface gpe_surface;
2738
2739     memset(&gpe_surface, 0, sizeof(gpe_surface));
2740
2741     gpe_surface.gpe_resource = gpe_buffer;
2742     gpe_surface.is_2d_surface = 1;
2743     gpe_surface.is_media_block_rw = !!is_media_block_rw;
2744     gpe_surface.cacheability_control = i965->intel.mocs_state;
2745     gpe_surface.format = format;
2746
2747     gen9_gpe_context_add_surface(gpe_context, &gpe_surface, index);
2748 }
2749
2750 void
2751 gen9_add_dri_buffer_gpe_surface(VADriverContextP ctx,
2752                                 struct i965_gpe_context *gpe_context,
2753                                 dri_bo *bo,
2754                                 int is_raw_buffer,
2755                                 unsigned int size,
2756                                 unsigned int offset,
2757                                 int index)
2758 {
2759     struct i965_gpe_resource gpe_resource;
2760
2761     i965_dri_object_to_buffer_gpe_resource(&gpe_resource, bo);
2762     gen9_add_buffer_gpe_surface(ctx,
2763                                 gpe_context,
2764                                 &gpe_resource,
2765                                 is_raw_buffer,
2766                                 size,
2767                                 offset,
2768                                 index);
2769
2770     i965_free_gpe_resource(&gpe_resource);
2771 }
2772
2773 bool
2774 i965_gpe_table_init(VADriverContextP ctx)
2775 {
2776     struct i965_driver_data *i965 = i965_driver_data(ctx);
2777     struct i965_gpe_table *gpe = &i965->gpe_table;
2778
2779     if (IS_GEN8(i965->intel.device_info)) {
2780         gpe->context_init = gen8_gpe_context_init;
2781         gpe->context_destroy = gen8_gpe_context_destroy;
2782         gpe->context_add_surface = gen8_gpe_context_add_surface;
2783         gpe->reset_binding_table = gen8_gpe_reset_binding_table;
2784         gpe->load_kernels = gen8_gpe_load_kernels;
2785         gpe->setup_interface_data = gen8_gpe_setup_interface_data;
2786         gpe->set_dynamic_buffer = gen8_gpe_context_set_dynamic_buffer;
2787         gpe->media_object = gen8_gpe_media_object;
2788         gpe->media_object_walker = gen8_gpe_media_object_walker;
2789         gpe->media_state_flush = gen8_gpe_media_state_flush;
2790         gpe->pipe_control = gen8_gpe_pipe_control;
2791         gpe->pipeline_end = gen8_gpe_pipeline_end;
2792         gpe->pipeline_setup = gen8_gpe_pipeline_setup;
2793         gpe->mi_conditional_batch_buffer_end = gen8_gpe_mi_conditional_batch_buffer_end;
2794         gpe->mi_batch_buffer_start = gen8_gpe_mi_batch_buffer_start;
2795         gpe->mi_load_register_reg = gen8_gpe_mi_load_register_reg;
2796         gpe->mi_load_register_imm = gen8_gpe_mi_load_register_imm;
2797         gpe->mi_load_register_mem = gen8_gpe_mi_load_register_mem;
2798         gpe->mi_store_register_mem = gen8_gpe_mi_store_register_mem;
2799         gpe->mi_store_data_imm =gen8_gpe_mi_store_data_imm;
2800         gpe->mi_flush_dw = gen8_gpe_mi_flush_dw;
2801     } else if (IS_GEN9(i965->intel.device_info)) {
2802         gpe->context_init = gen8_gpe_context_init;
2803         gpe->context_destroy = gen8_gpe_context_destroy;
2804         gpe->context_add_surface = gen9_gpe_context_add_surface;
2805         gpe->reset_binding_table = gen9_gpe_reset_binding_table;
2806         gpe->load_kernels = gen8_gpe_load_kernels;
2807         gpe->setup_interface_data = gen8_gpe_setup_interface_data;
2808         gpe->set_dynamic_buffer = gen8_gpe_context_set_dynamic_buffer;
2809         gpe->media_object = gen8_gpe_media_object;
2810         gpe->media_object_walker = gen8_gpe_media_object_walker;
2811         gpe->media_state_flush = gen8_gpe_media_state_flush;
2812         gpe->pipe_control = gen8_gpe_pipe_control;
2813         gpe->pipeline_end = gen9_gpe_pipeline_end;
2814         gpe->pipeline_setup = gen9_gpe_pipeline_setup;
2815         gpe->mi_conditional_batch_buffer_end = gen9_gpe_mi_conditional_batch_buffer_end;
2816         gpe->mi_batch_buffer_start = gen8_gpe_mi_batch_buffer_start;
2817         gpe->mi_load_register_reg = gen8_gpe_mi_load_register_reg;
2818         gpe->mi_load_register_imm = gen8_gpe_mi_load_register_imm;
2819         gpe->mi_load_register_mem = gen8_gpe_mi_load_register_mem;
2820         gpe->mi_store_register_mem = gen8_gpe_mi_store_register_mem;
2821         gpe->mi_store_data_imm =gen8_gpe_mi_store_data_imm;
2822         gpe->mi_flush_dw = gen8_gpe_mi_flush_dw;
2823     } else {
2824         // TODO: for other platforms
2825     }
2826
2827     return true;
2828 }
2829
2830 void
2831 i965_gpe_table_terminate(VADriverContextP ctx)
2832 {
2833
2834 }