2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the
6 * "Software"), to deal in the Software without restriction, including
7 * without limitation the rights to use, copy, modify, merge, publish,
8 * distribute, sub license, and/or sell copies of the Software, and to
9 * permit persons to whom the Software is furnished to do so, subject to
10 * the following conditions:
12 * The above copyright notice and this permission notice (including the
13 * next paragraph) shall be included in all copies or substantial portions
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
19 * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
20 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
21 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
22 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25 * Xiang Haihao <haihao.xiang@intel.com>
29 #ifndef __I965_POST_PROCESSING_H__
30 #define __I965_POST_PROCESSING_H__
32 #include "i965_vpp_avs.h"
34 #define MAX_PP_SURFACES 48
39 PP_NV12_LOAD_SAVE_N12,
40 PP_NV12_LOAD_SAVE_PL3,
52 PP_RGBX_LOAD_SAVE_NV12,
53 PP_NV12_LOAD_SAVE_RGBX,
57 struct i965_post_processing_context;
59 struct pp_load_save_context
67 struct pp_scaling_context
69 int dest_x; /* in pixel */
70 int dest_y; /* in pixel */
73 float src_normalized_x;
74 float src_normalized_y;
80 int dest_x; /* in pixel */
81 int dest_y; /* in pixel */
84 float src_normalized_x;
85 float src_normalized_y;
92 DNDI_FRAME_IN_CURRENT = 0,
93 DNDI_FRAME_IN_PREVIOUS,
96 DNDI_FRAME_OUT_CURRENT,
97 DNDI_FRAME_OUT_PREVIOUS,
98 DNDI_FRAME_STORE_COUNT
101 typedef struct dndi_frame_store {
102 struct object_surface *obj_surface;
103 VASurfaceID surface_id; /* always relative to the input surface */
104 unsigned int is_scratch_surface : 1;
107 struct pp_dndi_context
111 DNDIFrameStore frame_store[DNDI_FRAME_STORE_COUNT];
113 /* Temporary flags live until the current picture is processed */
114 unsigned int is_di_enabled : 1;
115 unsigned int is_di_adv_enabled : 1;
116 unsigned int is_first_frame : 1;
117 unsigned int is_second_field : 1;
127 struct i965_post_processing_context;
131 struct i965_kernel kernel;
134 VAStatus (*initialize)(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
135 const struct i965_surface *src_surface,
136 const VARectangle *src_rect,
137 struct i965_surface *dst_surface,
138 const VARectangle *dst_rect,
142 struct pp_static_parameter
146 float procamp_constant_c0;
148 /* Load and Same r1.1 */
149 unsigned int source_packed_y_offset:8;
150 unsigned int source_packed_u_offset:8;
151 unsigned int source_packed_v_offset:8;
152 unsigned int source_rgb_layout:8; // 1 for |R|G|B|X| layout, 0 for |B|G|R|X| layout
155 /* Load and Save r1.2 */
157 unsigned int destination_packed_y_offset:8;
158 unsigned int destination_packed_u_offset:8;
159 unsigned int destination_packed_v_offset:8;
165 unsigned int pad0:24;
166 unsigned int destination_rgb_layout:8; // 1 for |R|G|B|X| layout, 0 for |B|G|R|X| layout
171 float procamp_constant_c1;
174 float procamp_constant_c2;
177 unsigned int statistics_surface_picth:16; /* Devided by 2 */
178 unsigned int pad1:16;
183 unsigned int pad0:24;
184 unsigned int top_field_first:8;
187 /* AVS/Scaling r1.6 */
188 float normalized_video_y_scaling_step;
192 float procamp_constant_c5;
197 float procamp_constant_c3;
203 float wg_csc_constant_c4;
206 float wg_csc_constant_c8;
209 float procamp_constant_c4;
218 float wg_csc_constant_c9;
223 float wg_csc_constant_c0;
226 float scaling_step_ratio;
229 float normalized_alpha_y_scaling;
232 float wg_csc_constant_c4;
235 float wg_csc_constant_c1;
238 int horizontal_origin_offset:16;
239 int vertical_origin_offset:16;
244 unsigned int color_pixel;
247 float wg_csc_constant_c2;
251 float wg_csc_constant_c3;
256 float wg_csc_constant_c6;
258 /* ALL r4.1 MBZ ???*/
265 unsigned int pad1:15;
267 unsigned int pad2:16;
272 unsigned int motion_history_coefficient_m2:8;
273 unsigned int motion_history_coefficient_m1:8;
274 unsigned int pad0:16;
279 float wg_csc_constant_c7;
282 float wg_csc_constant_c10;
285 float source_video_frame_normalized_horizontal_origin;
291 float wg_csc_constant_c11;
295 struct pp_inline_parameter
299 int destination_block_horizontal_origin:16;
300 int destination_block_vertical_origin:16;
305 float source_surface_block_normalized_horizontal_origin;
309 unsigned int variance_surface_vertical_origin:16;
310 unsigned int pad0:16;
314 /* AVS/Scaling r5.2 */
315 float source_surface_block_normalized_vertical_origin;
318 float alpha_surface_block_normalized_horizontal_origin;
321 float alpha_surface_block_normalized_vertical_origin;
324 unsigned int alpha_mask_x:16;
325 unsigned int alpha_mask_y:8;
326 unsigned int block_count_x:8;
329 /* we only support M*1 or 1*N block partitation now.
330 * -- it means asm code only need update this mask from grf6 for the last block
332 unsigned int block_horizontal_mask:16;
333 unsigned int block_vertical_mask:8;
334 unsigned int number_blocks:8;
336 /* AVS/Scaling r5.7 */
337 float normalized_video_x_scaling_step;
342 float video_step_delta;
344 /* r6.1 */ // sizeof(int) == 4?
345 unsigned int block_horizontal_mask_right:16;
346 unsigned int block_vertical_mask_bottom:8;
350 unsigned int block_horizontal_mask_middle:16;
351 unsigned int pad2:16;
354 unsigned int padx[5];
358 struct gen7_pp_static_parameter
362 unsigned int padx[6];
364 unsigned int di_statistics_surface_pitch_div2:16;
365 unsigned int di_statistics_surface_height_div4:16;
367 unsigned int di_top_field_first:8;
368 unsigned int pad0:16;
369 unsigned int pointer_to_inline_parameter:8; /* value: 7 */
374 /* Indicates whether the rgb is swapped for the src surface
375 * 0: RGBX(MSB. X-B-G-R). 1: BGRX(MSB: X-R-G-B)
377 unsigned int src_avs_rgb_swap:1;
378 unsigned int pad3:31;
381 unsigned int pad2:16;
382 unsigned int save_avs_rgb_swap:1; /* 0: RGB, 1: BGR */
383 unsigned int avs_wa_enable:1; /* must enabled for GEN7 */
384 unsigned int ief_enable:1;
385 unsigned int avs_wa_width:13;
388 float avs_wa_one_div_256_width;
391 float avs_wa_five_div_256_width;
394 unsigned int padx[3];
397 unsigned int di_destination_packed_y_component_offset:8;
398 unsigned int di_destination_packed_u_component_offset:8;
399 unsigned int di_destination_packed_v_component_offset:8;
400 unsigned int alpha:8;
404 float sampler_load_horizontal_scaling_step_ratio;
405 unsigned int padx[7];
409 float sampler_load_vertical_scaling_step;
411 unsigned int di_hoffset_svf_from_dvf:16;
412 unsigned int di_voffset_svf_from_dvf:16;
413 unsigned int padx[5];
417 float sampler_load_vertical_frame_origin;
418 unsigned int padx[7];
422 float sampler_load_horizontal_frame_origin;
423 unsigned int padx[7];
448 unsigned int padx[4];
452 struct gen7_pp_inline_parameter
456 unsigned int destination_block_horizontal_origin:16;
457 unsigned int destination_block_vertical_origin:16;
458 /* r9.1: 0xffffffff */
459 unsigned int constant_0;
465 float sampler_load_main_video_x_scaling_step;
468 /* r9.6: must be zero */
469 unsigned int avs_vertical_block_number;
471 unsigned int group_id_number;
475 unsigned int padx[8];
479 struct i965_post_processing_context
482 struct pp_module pp_modules[NUM_PP_MODULES];
483 void *pp_static_parameter;
484 void *pp_inline_parameter;
488 } surface_state_binding_table;
496 int num_interface_descriptors;
507 } sampler_state_table;
512 unsigned int vfe_start;
513 unsigned int cs_start;
515 unsigned int num_vfe_entries;
516 unsigned int num_cs_entries;
518 unsigned int size_vfe_entry;
519 unsigned int size_cs_entry;
523 unsigned int gpgpu_mode : 1;
524 unsigned int pad0 : 7;
525 unsigned int max_num_threads : 16;
526 unsigned int num_urb_entries : 8;
527 unsigned int urb_entry_size : 16;
528 unsigned int curbe_allocation_size : 16;
531 struct intel_vebox_context *vebox_proc_ctx;
533 struct pp_load_save_context pp_load_save_context;
534 struct pp_scaling_context pp_scaling_context;
535 struct pp_avs_context pp_avs_context;
536 struct pp_dndi_context pp_dndi_context;
537 struct pp_dn_context pp_dn_context;
538 void *private_context; /* pointer to the current private context */
539 void *pipeline_param; /* pointer to the pipeline parameter */
541 * \ref Extra filter flags used as a fast path.
543 * This corresponds to vaPutSurface() flags, for direct rendering,
544 * or to VAProcPipelineParameterBuffer.filter_flags when the VPP
545 * interfaces are used. In the latter case, this is just a copy of
548 unsigned int filter_flags;
550 int (*pp_x_steps)(void *private_context);
551 int (*pp_y_steps)(void *private_context);
552 int (*pp_set_block_parameter)(struct i965_post_processing_context *pp_context, int x, int y);
554 struct intel_batchbuffer *batch;
556 unsigned int block_horizontal_mask_left:16;
557 unsigned int block_horizontal_mask_right:16;
558 unsigned int block_vertical_mask_bottom:8;
563 unsigned int end_offset;
573 unsigned int end_offset;
576 unsigned int sampler_offset;
578 unsigned int idrt_offset;
580 unsigned int curbe_offset;
583 VAStatus (*intel_post_processing)(VADriverContextP ctx,
584 struct i965_post_processing_context *pp_context,
585 const struct i965_surface *src_surface,
586 const VARectangle *src_rect,
587 struct i965_surface *dst_surface,
588 const VARectangle *dst_rect,
590 void * filter_param);
591 void (*finalize)(VADriverContextP ctx,
592 struct i965_post_processing_context *pp_context);
595 struct i965_proc_context
597 struct hw_context base;
598 void *driver_context;
599 struct i965_post_processing_context pp_context;
603 i965_post_processing(
604 VADriverContextP ctx,
605 struct object_surface *obj_surface,
606 const VARectangle *src_rect,
607 const VARectangle *dst_rect,
608 unsigned int va_flags,
609 int *has_done_scaling,
610 VARectangle *calibrated_rect
614 i965_scaling_processing(
615 VADriverContextP ctx,
616 struct object_surface *src_surface_obj,
617 const VARectangle *src_rect,
618 struct object_surface *dst_surface_obj,
619 const VARectangle *dst_rect,
620 unsigned int va_flags
624 i965_image_processing(VADriverContextP ctx,
625 const struct i965_surface *src_surface,
626 const VARectangle *src_rect,
627 struct i965_surface *dst_surface,
628 const VARectangle *dst_rect);
631 i965_post_processing_terminate(VADriverContextP ctx);
633 i965_post_processing_init(VADriverContextP ctx);
637 i965_proc_picture(VADriverContextP ctx,
639 union codec_state *codec_state,
640 struct hw_context *hw_context);
642 #endif /* __I965_POST_PROCESSING_H__ */