2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the
6 * "Software"), to deal in the Software without restriction, including
7 * without limitation the rights to use, copy, modify, merge, publish,
8 * distribute, sub license, and/or sell copies of the Software, and to
9 * permit persons to whom the Software is furnished to do so, subject to
10 * the following conditions:
12 * The above copyright notice and this permission notice (including the
13 * next paragraph) shall be included in all copies or substantial portions
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
19 * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
20 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
21 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
22 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25 * Xiang Haihao <haihao.xiang@intel.com>
29 #ifndef __I965_POST_PROCESSING_H__
30 #define __I965_POST_PROCESSING_H__
32 #include "i965_vpp_avs.h"
35 #include <intel_bufmgr.h>
36 #include "i965_gpe_utils.h"
38 #define MAX_PP_SURFACES 48
40 struct i965_gpe_context;
45 PP_NV12_LOAD_SAVE_N12,
46 PP_NV12_LOAD_SAVE_PL3,
58 PP_RGBX_LOAD_SAVE_NV12,
59 PP_NV12_LOAD_SAVE_RGBX,
63 struct i965_post_processing_context;
65 struct pp_load_save_context
73 struct pp_scaling_context
75 int dest_x; /* in pixel */
76 int dest_y; /* in pixel */
79 float src_normalized_x;
80 float src_normalized_y;
86 int dest_x; /* in pixel */
87 int dest_y; /* in pixel */
90 float src_normalized_x;
91 float src_normalized_y;
98 DNDI_FRAME_IN_CURRENT = 0,
99 DNDI_FRAME_IN_PREVIOUS,
102 DNDI_FRAME_OUT_CURRENT,
103 DNDI_FRAME_OUT_PREVIOUS,
104 DNDI_FRAME_STORE_COUNT
107 typedef struct dndi_frame_store {
108 struct object_surface *obj_surface;
109 VASurfaceID surface_id; /* always relative to the input surface */
110 unsigned int is_scratch_surface : 1;
113 struct pp_dndi_context
117 DNDIFrameStore frame_store[DNDI_FRAME_STORE_COUNT];
119 /* Temporary flags live until the current picture is processed */
120 unsigned int is_di_enabled : 1;
121 unsigned int is_di_adv_enabled : 1;
122 unsigned int is_first_frame : 1;
123 unsigned int is_second_field : 1;
133 struct i965_post_processing_context;
137 struct i965_kernel kernel;
140 VAStatus (*initialize)(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
141 const struct i965_surface *src_surface,
142 const VARectangle *src_rect,
143 struct i965_surface *dst_surface,
144 const VARectangle *dst_rect,
148 struct pp_static_parameter
152 float procamp_constant_c0;
154 /* Load and Same r1.1 */
155 unsigned int source_packed_y_offset:8;
156 unsigned int source_packed_u_offset:8;
157 unsigned int source_packed_v_offset:8;
158 unsigned int source_rgb_layout:8; // 1 for |R|G|B|X| layout, 0 for |B|G|R|X| layout
161 /* Load and Save r1.2 */
163 unsigned int destination_packed_y_offset:8;
164 unsigned int destination_packed_u_offset:8;
165 unsigned int destination_packed_v_offset:8;
171 unsigned int pad0:24;
172 unsigned int destination_rgb_layout:8; // 1 for |R|G|B|X| layout, 0 for |B|G|R|X| layout
177 float procamp_constant_c1;
180 float procamp_constant_c2;
183 unsigned int statistics_surface_picth:16; /* Devided by 2 */
184 unsigned int pad1:16;
189 unsigned int pad0:24;
190 unsigned int top_field_first:8;
193 /* AVS/Scaling r1.6 */
194 float normalized_video_y_scaling_step;
198 float procamp_constant_c5;
203 float procamp_constant_c3;
209 float wg_csc_constant_c4;
212 float wg_csc_constant_c8;
215 float procamp_constant_c4;
224 float wg_csc_constant_c9;
229 float wg_csc_constant_c0;
232 float scaling_step_ratio;
235 float normalized_alpha_y_scaling;
238 float wg_csc_constant_c4;
241 float wg_csc_constant_c1;
244 int horizontal_origin_offset:16;
245 int vertical_origin_offset:16;
250 unsigned int color_pixel;
253 float wg_csc_constant_c2;
257 float wg_csc_constant_c3;
262 float wg_csc_constant_c6;
264 /* ALL r4.1 MBZ ???*/
271 unsigned int pad1:15;
273 unsigned int pad2:16;
278 unsigned int motion_history_coefficient_m2:8;
279 unsigned int motion_history_coefficient_m1:8;
280 unsigned int pad0:16;
285 float wg_csc_constant_c7;
288 float wg_csc_constant_c10;
291 float source_video_frame_normalized_horizontal_origin;
297 float wg_csc_constant_c11;
301 struct pp_inline_parameter
305 int destination_block_horizontal_origin:16;
306 int destination_block_vertical_origin:16;
311 float source_surface_block_normalized_horizontal_origin;
315 unsigned int variance_surface_vertical_origin:16;
316 unsigned int pad0:16;
320 /* AVS/Scaling r5.2 */
321 float source_surface_block_normalized_vertical_origin;
324 float alpha_surface_block_normalized_horizontal_origin;
327 float alpha_surface_block_normalized_vertical_origin;
330 unsigned int alpha_mask_x:16;
331 unsigned int alpha_mask_y:8;
332 unsigned int block_count_x:8;
335 /* we only support M*1 or 1*N block partitation now.
336 * -- it means asm code only need update this mask from grf6 for the last block
338 unsigned int block_horizontal_mask:16;
339 unsigned int block_vertical_mask:8;
340 unsigned int number_blocks:8;
342 /* AVS/Scaling r5.7 */
343 float normalized_video_x_scaling_step;
348 float video_step_delta;
350 /* r6.1 */ // sizeof(int) == 4?
351 unsigned int block_horizontal_mask_right:16;
352 unsigned int block_vertical_mask_bottom:8;
356 unsigned int block_horizontal_mask_middle:16;
357 unsigned int pad2:16;
360 unsigned int padx[5];
364 struct gen7_pp_static_parameter
368 unsigned int padx[6];
370 unsigned int di_statistics_surface_pitch_div2:16;
371 unsigned int di_statistics_surface_height_div4:16;
373 unsigned int di_top_field_first:8;
374 unsigned int pad0:16;
375 unsigned int pointer_to_inline_parameter:8; /* value: 7 */
380 /* Indicates whether the rgb is swapped for the src surface
381 * 0: RGBX(MSB. X-B-G-R). 1: BGRX(MSB: X-R-G-B)
383 unsigned int src_avs_rgb_swap:1;
384 unsigned int pad3:31;
387 unsigned int pad2:16;
388 unsigned int save_avs_rgb_swap:1; /* 0: RGB, 1: BGR */
389 unsigned int avs_wa_enable:1; /* must enabled for GEN7 */
390 unsigned int ief_enable:1;
391 unsigned int avs_wa_width:13;
394 float avs_wa_one_div_256_width;
397 float avs_wa_five_div_256_width;
400 unsigned int padx[3];
403 unsigned int di_destination_packed_y_component_offset:8;
404 unsigned int di_destination_packed_u_component_offset:8;
405 unsigned int di_destination_packed_v_component_offset:8;
406 unsigned int alpha:8;
410 float sampler_load_horizontal_scaling_step_ratio;
411 unsigned int padx[7];
415 float sampler_load_vertical_scaling_step;
417 unsigned int di_hoffset_svf_from_dvf:16;
418 unsigned int di_voffset_svf_from_dvf:16;
419 unsigned int padx[5];
423 float sampler_load_vertical_frame_origin;
424 unsigned int padx[7];
428 float sampler_load_horizontal_frame_origin;
429 unsigned int padx[7];
454 unsigned int padx[4];
458 struct gen7_pp_inline_parameter
462 unsigned int destination_block_horizontal_origin:16;
463 unsigned int destination_block_vertical_origin:16;
464 /* r9.1: 0xffffffff */
465 unsigned int constant_0;
471 float sampler_load_main_video_x_scaling_step;
474 /* r9.6: must be zero */
475 unsigned int avs_vertical_block_number;
477 unsigned int group_id_number;
481 unsigned int padx[8];
485 struct i965_post_processing_context
488 struct pp_module pp_modules[NUM_PP_MODULES];
489 void *pp_static_parameter;
490 void *pp_inline_parameter;
494 } surface_state_binding_table;
502 int num_interface_descriptors;
513 } sampler_state_table;
518 unsigned int vfe_start;
519 unsigned int cs_start;
521 unsigned int num_vfe_entries;
522 unsigned int num_cs_entries;
524 unsigned int size_vfe_entry;
525 unsigned int size_cs_entry;
529 unsigned int gpgpu_mode : 1;
530 unsigned int pad0 : 7;
531 unsigned int max_num_threads : 16;
532 unsigned int num_urb_entries : 8;
533 unsigned int urb_entry_size : 16;
534 unsigned int curbe_allocation_size : 16;
537 struct intel_vebox_context *vebox_proc_ctx;
539 struct pp_load_save_context pp_load_save_context;
540 struct pp_scaling_context pp_scaling_context;
541 struct pp_avs_context pp_avs_context;
542 struct pp_dndi_context pp_dndi_context;
543 struct pp_dn_context pp_dn_context;
544 void *private_context; /* pointer to the current private context */
545 void *pipeline_param; /* pointer to the pipeline parameter */
547 * \ref Extra filter flags used as a fast path.
549 * This corresponds to vaPutSurface() flags, for direct rendering,
550 * or to VAProcPipelineParameterBuffer.filter_flags when the VPP
551 * interfaces are used. In the latter case, this is just a copy of
554 unsigned int filter_flags;
556 int (*pp_x_steps)(void *private_context);
557 int (*pp_y_steps)(void *private_context);
558 int (*pp_set_block_parameter)(struct i965_post_processing_context *pp_context, int x, int y);
560 struct intel_batchbuffer *batch;
562 unsigned int block_horizontal_mask_left:16;
563 unsigned int block_horizontal_mask_right:16;
564 unsigned int block_vertical_mask_bottom:8;
569 unsigned int end_offset;
579 unsigned int end_offset;
582 unsigned int sampler_offset;
584 unsigned int idrt_offset;
586 unsigned int curbe_offset;
589 VAStatus (*intel_post_processing)(VADriverContextP ctx,
590 struct i965_post_processing_context *pp_context,
591 const struct i965_surface *src_surface,
592 const VARectangle *src_rect,
593 struct i965_surface *dst_surface,
594 const VARectangle *dst_rect,
596 void * filter_param);
597 void (*finalize)(VADriverContextP ctx,
598 struct i965_post_processing_context *pp_context);
601 struct i965_gpe_context scaling_10bit_context;
602 int scaling_context_initialized;
605 struct i965_proc_context
607 struct hw_context base;
608 void *driver_context;
609 struct i965_post_processing_context pp_context;
613 i965_post_processing(
614 VADriverContextP ctx,
615 struct object_surface *obj_surface,
616 const VARectangle *src_rect,
617 const VARectangle *dst_rect,
618 unsigned int va_flags,
619 int *has_done_scaling,
620 VARectangle *calibrated_rect
624 i965_scaling_processing(
625 VADriverContextP ctx,
626 struct object_surface *src_surface_obj,
627 const VARectangle *src_rect,
628 struct object_surface *dst_surface_obj,
629 const VARectangle *dst_rect,
630 unsigned int va_flags
634 i965_image_processing(VADriverContextP ctx,
635 const struct i965_surface *src_surface,
636 const VARectangle *src_rect,
637 struct i965_surface *dst_surface,
638 const VARectangle *dst_rect);
641 i965_post_processing_terminate(VADriverContextP ctx);
643 i965_post_processing_init(VADriverContextP ctx);
647 i965_proc_picture(VADriverContextP ctx,
649 union codec_state *codec_state,
650 struct hw_context *hw_context);
652 #endif /* __I965_POST_PROCESSING_H__ */