2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the
6 * "Software"), to deal in the Software without restriction, including
7 * without limitation the rights to use, copy, modify, merge, publish,
8 * distribute, sub license, and/or sell copies of the Software, and to
9 * permit persons to whom the Software is furnished to do so, subject to
10 * the following conditions:
12 * The above copyright notice and this permission notice (including the
13 * next paragraph) shall be included in all copies or substantial portions
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
19 * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
20 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
21 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
22 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25 * Xiang Haihao <haihao.xiang@intel.com>
29 #ifndef __I965_POST_PROCESSING_H__
30 #define __I965_POST_PROCESSING_H__
32 #define MAX_PP_SURFACES 32
34 #define I965_PP_FLAG_TOP_FIELD 0x00000001
35 #define I965_PP_FLAG_BOTTOM_FIELD 0x00000002
37 #define I965_PP_FLAG_SCALING 0x00000010
38 #define I965_PP_FLAG_AVS 0x00000020
39 #define I965_PP_FLAG_DEINTERLACING 0x00000100 /* XXX: don't support MCDI yet */
40 #define I965_PP_FLAG_DENOISE 0x00000200
52 struct pp_load_save_context
58 struct pp_scaling_context
60 int dest_x; /* in pixel */
61 int dest_y; /* in pixel */
70 int dest_x; /* in pixel */
71 int dest_y; /* in pixel */
80 struct pp_dndi_context
88 struct i965_kernel kernel;
91 void (*initialize)(VADriverContextP ctx,
92 VASurfaceID in_surface_id, VASurfaceID out_surface_id,
93 const VARectangle *src_rect, const VARectangle *dst_rect);
96 struct pp_static_parameter
100 float procamp_constant_c0;
102 /* Load and Same r1.1 */
103 unsigned int source_packed_y_offset:8;
104 unsigned int source_packed_u_offset:8;
105 unsigned int source_packed_v_offset:8;
109 /* Load and Save r1.2 */
111 unsigned int destination_packed_y_offset:8;
112 unsigned int destination_packed_u_offset:8;
113 unsigned int destination_packed_v_offset:8;
119 unsigned int destination_rgb_format:8;
120 unsigned int pad0:24;
125 float procamp_constant_c1;
128 float procamp_constant_c2;
131 unsigned int statistics_surface_picth:16; /* Devided by 2 */
132 unsigned int pad1:16;
137 unsigned int pad0:24;
138 unsigned int top_field_first:8;
141 /* AVS/Scaling r1.6 */
142 float normalized_video_y_scaling_step;
146 float procamp_constant_c5;
151 float procamp_constant_c3;
157 float wg_csc_constant_c4;
160 float wg_csc_constant_c8;
163 float procamp_constant_c4;
172 float wg_csc_constant_c9;
177 float wg_csc_constant_c0;
180 float scaling_step_ratio;
183 float normalized_alpha_y_scaling;
186 float wg_csc_constant_c4;
189 float wg_csc_constant_c1;
192 int horizontal_origin_offset:16;
193 int vertical_origin_offset:16;
198 unsigned int color_pixel;
201 float wg_csc_constant_c2;
205 float wg_csc_constant_c3;
210 float wg_csc_constant_c6;
212 /* ALL r4.1 MBZ ???*/
219 unsigned int pad1:15;
221 unsigned int pad2:16;
226 unsigned int motion_history_coefficient_m2:8;
227 unsigned int motion_history_coefficient_m1:8;
228 unsigned int pad0:16;
233 float wg_csc_constant_c7;
236 float wg_csc_constant_c10;
239 float source_video_frame_normalized_horizontal_origin;
245 float wg_csc_constant_c11;
249 struct pp_inline_parameter
253 int destination_block_horizontal_origin:16;
254 int destination_block_vertical_origin:16;
259 float source_surface_block_normalized_horizontal_origin;
263 unsigned int variance_surface_vertical_origin:16;
264 unsigned int pad0:16;
268 /* AVS/Scaling r5.2 */
269 float source_surface_block_normalized_vertical_origin;
272 float alpha_surface_block_normalized_horizontal_origin;
275 float alpha_surface_block_normalized_vertical_origin;
278 unsigned int alpha_mask_x:16;
279 unsigned int alpha_mask_y:8;
280 unsigned int block_count_x:8;
283 unsigned int block_horizontal_mask:16;
284 unsigned int block_vertical_mask:8;
285 unsigned int number_blocks:8;
287 /* AVS/Scaling r5.7 */
288 float normalized_video_x_scaling_step;
293 float video_step_delta;
296 unsigned int padx[7];
300 struct i965_post_processing_context
303 struct pp_module pp_modules[NUM_PP_MODULES];
304 struct pp_static_parameter pp_static_parameter;
305 struct pp_inline_parameter pp_inline_parameter;
314 } surfaces[MAX_PP_SURFACES];
322 int num_interface_descriptors;
333 } sampler_state_table;
338 unsigned int vfe_start;
339 unsigned int cs_start;
341 unsigned int num_vfe_entries;
342 unsigned int num_cs_entries;
344 unsigned int size_vfe_entry;
345 unsigned int size_cs_entry;
353 struct pp_load_save_context pp_load_save_context;
354 struct pp_scaling_context pp_scaling_context;
355 struct pp_avs_context pp_avs_context;
356 struct pp_dndi_context pp_dndi_context;
359 int (*pp_x_steps)(void *private_context);
360 int (*pp_y_steps)(void *private_context);
361 int (*pp_set_block_parameter)(struct i965_post_processing_context *pp_context, int x, int y);
363 /* video process based on hsw vebox */
364 struct intel_vebox_context *pp_vebox_context;
368 i965_post_processing(
369 VADriverContextP ctx,
371 const VARectangle *src_rect,
372 const VARectangle *dst_rect,
374 int *has_done_scaling
378 i965_post_processing_terminate(VADriverContextP ctx);
380 i965_post_processing_init(VADriverContextP ctx);
382 #endif /* __I965_POST_PROCESSING_H__ */