2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the
6 * "Software"), to deal in the Software without restriction, including
7 * without limitation the rights to use, copy, modify, merge, publish,
8 * distribute, sub license, and/or sell copies of the Software, and to
9 * permit persons to whom the Software is furnished to do so, subject to
10 * the following conditions:
12 * The above copyright notice and this permission notice (including the
13 * next paragraph) shall be included in all copies or substantial portions
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
19 * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
20 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
21 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
22 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25 * Xiang Haihao <haihao.xiang@intel.com>
29 #ifndef __I965_POST_PROCESSING_H__
30 #define __I965_POST_PROCESSING_H__
32 #define MAX_PP_SURFACES 32
34 #define I965_PP_FLAG_DEINTERLACING_TOP_FISRT 1
35 #define I965_PP_FLAG_DEINTERLACING_BOTTOM_FIRST 2
36 #define I965_PP_FLAG_AVS 4
38 #define I965_PP_FLAG_DEINTERLACING (I965_PP_FLAG_DEINTERLACING_TOP_FISRT | I965_PP_FLAG_DEINTERLACING_BOTTOM_FIRST)
43 PP_NV12_LOAD_SAVE_N12,
44 PP_NV12_LOAD_SAVE_PL3,
53 #define NUM_PP_MODULES 9
55 struct i965_post_processing_context;
57 struct pp_load_save_context
63 struct pp_scaling_context
65 int dest_x; /* in pixel */
66 int dest_y; /* in pixel */
75 int dest_x; /* in pixel */
76 int dest_y; /* in pixel */
85 struct pp_dndi_context
99 struct i965_kernel kernel;
102 VAStatus (*initialize)(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
103 const struct i965_surface *src_surface,
104 const VARectangle *src_rect,
105 struct i965_surface *dst_surface,
106 const VARectangle *dst_rect,
110 struct pp_static_parameter
114 float procamp_constant_c0;
116 /* Load and Same r1.1 */
117 unsigned int source_packed_y_offset:8;
118 unsigned int source_packed_u_offset:8;
119 unsigned int source_packed_v_offset:8;
123 /* Load and Save r1.2 */
125 unsigned int destination_packed_y_offset:8;
126 unsigned int destination_packed_u_offset:8;
127 unsigned int destination_packed_v_offset:8;
133 unsigned int destination_rgb_format:8;
134 unsigned int pad0:24;
139 float procamp_constant_c1;
142 float procamp_constant_c2;
145 unsigned int statistics_surface_picth:16; /* Devided by 2 */
146 unsigned int pad1:16;
151 unsigned int pad0:24;
152 unsigned int top_field_first:8;
155 /* AVS/Scaling r1.6 */
156 float normalized_video_y_scaling_step;
160 float procamp_constant_c5;
165 float procamp_constant_c3;
171 float wg_csc_constant_c4;
174 float wg_csc_constant_c8;
177 float procamp_constant_c4;
186 float wg_csc_constant_c9;
191 float wg_csc_constant_c0;
194 float scaling_step_ratio;
197 float normalized_alpha_y_scaling;
200 float wg_csc_constant_c4;
203 float wg_csc_constant_c1;
206 int horizontal_origin_offset:16;
207 int vertical_origin_offset:16;
212 unsigned int color_pixel;
215 float wg_csc_constant_c2;
219 float wg_csc_constant_c3;
224 float wg_csc_constant_c6;
226 /* ALL r4.1 MBZ ???*/
233 unsigned int pad1:15;
235 unsigned int pad2:16;
240 unsigned int motion_history_coefficient_m2:8;
241 unsigned int motion_history_coefficient_m1:8;
242 unsigned int pad0:16;
247 float wg_csc_constant_c7;
250 float wg_csc_constant_c10;
253 float source_video_frame_normalized_horizontal_origin;
259 float wg_csc_constant_c11;
263 struct pp_inline_parameter
267 int destination_block_horizontal_origin:16;
268 int destination_block_vertical_origin:16;
273 float source_surface_block_normalized_horizontal_origin;
277 unsigned int variance_surface_vertical_origin:16;
278 unsigned int pad0:16;
282 /* AVS/Scaling r5.2 */
283 float source_surface_block_normalized_vertical_origin;
286 float alpha_surface_block_normalized_horizontal_origin;
289 float alpha_surface_block_normalized_vertical_origin;
292 unsigned int alpha_mask_x:16;
293 unsigned int alpha_mask_y:8;
294 unsigned int block_count_x:8;
297 unsigned int block_horizontal_mask:16;
298 unsigned int block_vertical_mask:8;
299 unsigned int number_blocks:8;
301 /* AVS/Scaling r5.7 */
302 float normalized_video_x_scaling_step;
307 float video_step_delta;
310 unsigned int padx[7];
314 struct i965_post_processing_context
317 struct pp_module pp_modules[NUM_PP_MODULES];
318 struct pp_static_parameter pp_static_parameter;
319 struct pp_inline_parameter pp_inline_parameter;
323 } surface_state_binding_table;
331 int num_interface_descriptors;
342 } sampler_state_table;
347 unsigned int vfe_start;
348 unsigned int cs_start;
350 unsigned int num_vfe_entries;
351 unsigned int num_cs_entries;
353 unsigned int size_vfe_entry;
354 unsigned int size_cs_entry;
362 struct pp_load_save_context pp_load_save_context;
363 struct pp_scaling_context pp_scaling_context;
364 struct pp_avs_context pp_avs_context;
365 struct pp_dndi_context pp_dndi_context;
366 struct pp_dn_context pp_dn_context;
369 int (*pp_x_steps)(void *private_context);
370 int (*pp_y_steps)(void *private_context);
371 int (*pp_set_block_parameter)(struct i965_post_processing_context *pp_context, int x, int y);
373 struct intel_batchbuffer *batch;
376 struct i965_proc_context
378 struct hw_context base;
379 struct i965_post_processing_context pp_context;
383 i965_post_processing(
384 VADriverContextP ctx,
386 const VARectangle *src_rect,
387 const VARectangle *dst_rect,
389 int *has_done_scaling
393 i965_image_processing(VADriverContextP ctx,
394 const struct i965_surface *src_surface,
395 const VARectangle *src_rect,
396 struct i965_surface *dst_surface,
397 const VARectangle *dst_rect);
400 i965_post_processing_terminate(VADriverContextP ctx);
402 i965_post_processing_init(VADriverContextP ctx);
404 #endif /* __I965_POST_PROCESSING_H__ */