src/i965_post_processing.h

   1 /*
   2  * Copyright © 2010 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the
   6  * "Software"), to deal in the Software without restriction, including
   7  * without limitation the rights to use, copy, modify, merge, publish,
   8  * distribute, sub license, and/or sell copies of the Software, and to
   9  * permit persons to whom the Software is furnished to do so, subject to
  10  * the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the
  13  * next paragraph) shall be included in all copies or substantial portions
  14  * of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  17  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  18  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  19  * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
  20  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  21  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  22  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors:
  25  *    Xiang Haihao <haihao.xiang@intel.com>
  26  *
  27  */
  28
  29 #ifndef __I965_POST_PROCESSING_H__
  30 #define __I965_POST_PROCESSING_H__
  31
  32 #define MAX_PP_SURFACES  48
  33
  34 #define I965_PP_FLAG_TOP_FIELD                 1
  35 #define I965_PP_FLAG_BOTTOM_FIELD              2
  36
  37 #define I965_PP_FLAG_AVS                       4
  38 #define I965_PP_FLAG_DEINTERLACING             8
  39
  40 enum
  41 {
  42     PP_NULL = 0,
  43     PP_NV12_LOAD_SAVE_N12,
  44     PP_NV12_LOAD_SAVE_PL3,
  45     PP_PL3_LOAD_SAVE_N12,
  46     PP_PL3_LOAD_SAVE_PL3,
  47     PP_NV12_SCALING,
  48     PP_NV12_AVS,
  49     PP_NV12_DNDI,
  50     PP_NV12_DN,
  51     NUM_PP_MODULES,
  52 };
  53
  54 struct pp_load_save_context
  55 {
  56     int dest_w;
  57     int dest_h;
  58 };
  59
  60 struct pp_scaling_context
  61 {
  62     int dest_x; /* in pixel */
  63     int dest_y; /* in pixel */
  64     int dest_w;
  65     int dest_h;
  66     int src_normalized_x;
  67     int src_normalized_y;
  68 };
  69
  70 struct pp_avs_context
  71 {
  72     int dest_x; /* in pixel */
  73     int dest_y; /* in pixel */
  74     int dest_w;
  75     int dest_h;
  76     int src_normalized_x;
  77     int src_normalized_y;
  78     int src_w;
  79     int src_h;
  80 };
  81
  82 struct pp_dndi_context
  83 {
  84     int dest_w;
  85     int dest_h;
  86 };
  87
  88 struct pp_dn_context
  89 {
  90     int dest_w;
  91     int dest_h;
  92 };
  93
  94 struct pp_module
  95 {
  96     struct i965_kernel kernel;
  97
  98     /* others */
  99     VAStatus (*initialize)(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
 100                        const struct i965_surface *src_surface,
 101                        const VARectangle *src_rect,
 102                        struct i965_surface *dst_surface,
 103                        const VARectangle *dst_rect,
 104                        void *filter_param);
 105 };
 106
 107 struct pp_static_parameter
 108 {
 109     struct {
 110         /* Procamp r1.0 */
 111         float procamp_constant_c0;
 112
 113         /* Load and Same r1.1 */
 114         unsigned int source_packed_y_offset:8;
 115         unsigned int source_packed_u_offset:8;
 116         unsigned int source_packed_v_offset:8;
 117         unsigned int pad0:8;
 118
 119         union {
 120             /* Load and Save r1.2 */
 121             struct {
 122                 unsigned int destination_packed_y_offset:8;
 123                 unsigned int destination_packed_u_offset:8;
 124                 unsigned int destination_packed_v_offset:8;
 125                 unsigned int pad0:8;
 126             } load_and_save;
 127
 128             /* CSC r1.2 */
 129             struct {
 130                 unsigned int destination_rgb_format:8;
 131                 unsigned int pad0:24;
 132             } csc;
 133         } r1_2;
 134
 135         /* Procamp r1.3 */
 136         float procamp_constant_c1;
 137
 138         /* Procamp r1.4 */
 139         float procamp_constant_c2;
 140
 141         /* DI r1.5 */
 142         unsigned int statistics_surface_picth:16;  /* Devided by 2 */
 143         unsigned int pad1:16;
 144
 145         union {
 146             /* DI r1.6 */
 147             struct {
 148                 unsigned int pad0:24;
 149                 unsigned int top_field_first:8;
 150             } di;
 151
 152             /* AVS/Scaling r1.6 */
 153             float normalized_video_y_scaling_step;
 154         } r1_6;
 155
 156         /* Procamp r1.7 */
 157         float procamp_constant_c5;
 158     } grf1;
 159
 160     struct {
 161         /* Procamp r2.0 */
 162         float procamp_constant_c3;
 163
 164         /* MBZ r2.1*/
 165         unsigned int pad0;
 166
 167         /* WG+CSC r2.2 */
 168         float wg_csc_constant_c4;
 169
 170         /* WG+CSC r2.3 */
 171         float wg_csc_constant_c8;
 172
 173         /* Procamp r2.4 */
 174         float procamp_constant_c4;
 175
 176         /* MBZ r2.5 */
 177         unsigned int pad1;
 178
 179         /* MBZ r2.6 */
 180         unsigned int pad2;
 181
 182         /* WG+CSC r2.7 */
 183         float wg_csc_constant_c9;
 184     } grf2;
 185
 186     struct {
 187         /* WG+CSC r3.0 */
 188         float wg_csc_constant_c0;
 189
 190         /* Blending r3.1 */
 191         float scaling_step_ratio;
 192
 193         /* Blending r3.2 */
 194         float normalized_alpha_y_scaling;
 195
 196         /* WG+CSC r3.3 */
 197         float wg_csc_constant_c4;
 198
 199         /* WG+CSC r3.4 */
 200         float wg_csc_constant_c1;
 201
 202         /* ALL r3.5 */
 203         int horizontal_origin_offset:16;
 204         int vertical_origin_offset:16;
 205
 206         /* Shared r3.6*/
 207         union {
 208             /* Color filll */
 209             unsigned int color_pixel;
 210
 211             /* WG+CSC */
 212             float wg_csc_constant_c2;
 213         } r3_6;
 214
 215         /* WG+CSC r3.7 */
 216         float wg_csc_constant_c3;
 217     } grf3;
 218
 219     struct {
 220         /* WG+CSC r4.0 */
 221         float wg_csc_constant_c6;
 222
 223         /* ALL r4.1 MBZ ???*/
 224         unsigned int pad0;
 225
 226         /* Shared r4.2 */
 227         union {
 228             /* AVS */
 229             struct {
 230                 unsigned int pad1:15;
 231                 unsigned int nlas:1;
 232                 unsigned int pad2:16;
 233             } avs;
 234
 235             /* DI */
 236             struct {
 237                 unsigned int motion_history_coefficient_m2:8;
 238                 unsigned int motion_history_coefficient_m1:8;
 239                 unsigned int pad0:16;
 240             } di;
 241         } r4_2;
 242
 243         /* WG+CSC r4.3 */
 244         float wg_csc_constant_c7;
 245
 246         /* WG+CSC r4.4 */
 247         float wg_csc_constant_c10;
 248
 249         /* AVS r4.5 */
 250         float source_video_frame_normalized_horizontal_origin;
 251
 252         /* MBZ r4.6 */
 253         unsigned int pad1;
 254
 255         /* WG+CSC r4.7 */
 256         float wg_csc_constant_c11;
 257     } grf4;
 258 };
 259
 260 struct pp_inline_parameter
 261 {
 262     struct {
 263         /* ALL r5.0 */
 264         int destination_block_horizontal_origin:16;
 265         int destination_block_vertical_origin:16;
 266
 267         /* Shared r5.1 */
 268         union {
 269             /* AVS/Scaling */
 270             float source_surface_block_normalized_horizontal_origin;
 271
 272             /* FMD */
 273             struct {
 274                 unsigned int variance_surface_vertical_origin:16;
 275                 unsigned int pad0:16;
 276             } fmd;
 277         } r5_1;
 278
 279         /* AVS/Scaling r5.2 */
 280         float source_surface_block_normalized_vertical_origin;
 281
 282         /* Alpha r5.3 */
 283         float alpha_surface_block_normalized_horizontal_origin;
 284
 285         /* Alpha r5.4 */
 286         float alpha_surface_block_normalized_vertical_origin;
 287
 288         /* Alpha r5.5 */
 289         unsigned int alpha_mask_x:16;
 290         unsigned int alpha_mask_y:8;
 291         unsigned int block_count_x:8;
 292
 293         /* r5.6 */
 294         unsigned int block_horizontal_mask:16;
 295         unsigned int block_vertical_mask:8;
 296         unsigned int number_blocks:8;
 297
 298         /* AVS/Scaling r5.7 */
 299         float normalized_video_x_scaling_step;
 300     } grf5;
 301
 302     struct {
 303         /* AVS r6.0 */
 304         float video_step_delta;
 305
 306         /* r6.1-r6.7 */
 307         unsigned int padx[7];
 308     } grf6;
 309 };
 310
 311 struct gen7_pp_static_parameter
 312 {
 313     struct {
 314         /* r1.0-r1.5 */
 315         unsigned int padx[6];
 316         /* r1.6 */
 317         unsigned int di_statistics_surface_pitch_div2:16;
 318         unsigned int di_statistics_surface_height_div4:16;
 319         /* r1.7 */
 320         unsigned int di_top_field_first:8;
 321         unsigned int pad0:16;
 322         unsigned int pointer_to_inline_parameter:8; /* value: 7 */
 323     } grf1;
 324
 325     struct {
 326         /* r2.0-r2.6 */
 327         unsigned int padx[7];
 328         /* r2.7 */
 329         unsigned int di_destination_packed_y_component_offset:8;
 330         unsigned int di_destination_packed_u_component_offset:8;
 331         unsigned int di_destination_packed_v_component_offset:8;
 332         unsigned int pad0:8;
 333     } grf2;
 334
 335     struct {
 336         float sampler_load_horizontal_scaling_step_ratio;
 337         unsigned int padx[7];
 338     } grf3;
 339
 340     struct {
 341         float sampler_load_vertical_scaling_step;
 342         unsigned int pad0;
 343         unsigned int di_hoffset_svf_from_dvf:16;
 344         unsigned int di_voffset_svf_from_dvf:16;
 345         unsigned int padx[5];
 346     } grf4;
 347
 348     struct {
 349         float sampler_load_vertical_frame_origin;
 350         unsigned int padx[7];
 351     } grf5;
 352
 353     struct {
 354         float sampler_load_horizontal_frame_origin;
 355         unsigned int padx[7];
 356     } grf6;
 357 };
 358
 359 struct gen7_pp_inline_parameter
 360 {
 361     struct {
 362         /* r7.0 */
 363         unsigned int destination_block_horizontal_origin:16;
 364         unsigned int destination_block_vertical_origin:16;
 365         /* r7.1: 0xffffffff */
 366         unsigned int constant_0;
 367         /* r7.2 */
 368         unsigned int pad0;
 369         /* r7.3 */
 370         unsigned int pad1;
 371         /* r7.4 */
 372         float sampler_load_main_video_x_scaling_step;
 373         /* r7.5 */
 374         unsigned int pad2;
 375         /* r7.6: must be zero */
 376         unsigned int avs_vertical_block_number;
 377         /* r7.7: 0 */
 378         unsigned int group_id_number;
 379     } grf7;
 380
 381     struct {
 382         unsigned int padx[8];
 383     } grf8;
 384 };
 385
 386 struct i965_post_processing_context
 387 {
 388     int current_pp;
 389     struct pp_module pp_modules[NUM_PP_MODULES];
 390     void *pp_static_parameter;
 391     void *pp_inline_parameter;
 392
 393     struct {
 394         dri_bo *bo;
 395     } surface_state_binding_table;
 396
 397     struct {
 398         dri_bo *bo;
 399     } curbe;
 400
 401     struct {
 402         dri_bo *bo;
 403         int num_interface_descriptors;
 404     } idrt;
 405
 406     struct {
 407         dri_bo *bo;
 408     } vfe_state;
 409
 410     struct {
 411         dri_bo *bo;
 412         dri_bo *bo_8x8;
 413         dri_bo *bo_8x8_uv;
 414     } sampler_state_table;
 415
 416     struct {
 417         unsigned int size;
 418
 419         unsigned int vfe_start;
 420         unsigned int cs_start;
 421
 422         unsigned int num_vfe_entries;
 423         unsigned int num_cs_entries;
 424
 425         unsigned int size_vfe_entry;
 426         unsigned int size_cs_entry;
 427     } urb;
 428
 429     struct {
 430         dri_bo *bo;
 431     } stmm;
 432
 433     union {
 434         struct pp_load_save_context pp_load_save_context;
 435         struct pp_scaling_context pp_scaling_context;
 436         struct pp_avs_context pp_avs_context;
 437         struct pp_dndi_context pp_dndi_context;
 438         struct pp_dn_context pp_dn_context;
 439     } private_context;
 440
 441     int (*pp_x_steps)(void *private_context);
 442     int (*pp_y_steps)(void *private_context);
 443     int (*pp_set_block_parameter)(struct i965_post_processing_context *pp_context, int x, int y);
 444     struct intel_batchbuffer *batch;
 445
 446     /* video process based on hsw vebox */
 447     struct intel_vebox_context *pp_vebox_context;
 448 };
 449
 450 VASurfaceID
 451 i965_post_processing(
 452     VADriverContextP   ctx,
 453     VASurfaceID        surface,
 454     const VARectangle *src_rect,
 455     const VARectangle *dst_rect,
 456     unsigned int       flags,
 457     int                *has_done_scaling
 458 );
 459
 460 VAStatus
 461 i965_image_processing(VADriverContextP ctx,
 462                       const struct i965_surface *src_surface,
 463                       const VARectangle *src_rect,
 464                       struct i965_surface *dst_surface,
 465                       const VARectangle *dst_rect);
 466
 467 Bool
 468 i965_post_processing_terminate(VADriverContextP ctx);
 469 Bool
 470 i965_post_processing_init(VADriverContextP ctx);
 471
 472 #endif /* __I965_POST_PROCESSING_H__ */