2 * Copyright © 2006 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Eric Anholt <eric@anholt.net>
25 * Keith Packard <keithp@keithp.com>
26 * Xiang Haihao <haihao.xiang@intel.com>
31 * Most of rendering codes are ported from xf86-video-intel/src/i965_video.c
40 #include <va/va_drmcommon.h>
42 #include "intel_batchbuffer.h"
43 #include "intel_driver.h"
44 #include "i965_defines.h"
45 #include "i965_drv_video.h"
46 #include "i965_structs.h"
47 #include "i965_yuv_coefs.h"
49 #include "i965_render.h"
50 #include "i965_post_processing.h"
52 #define SF_KERNEL_NUM_GRF 16
53 #define SF_MAX_THREADS 1
55 static const uint32_t sf_kernel_static[][4] =
57 #include "shaders/render/exa_sf.g4b"
60 #define PS_KERNEL_NUM_GRF 48
61 #define PS_MAX_THREADS 32
63 #define I965_GRF_BLOCKS(nreg) ((nreg + 15) / 16 - 1)
65 static const uint32_t ps_kernel_static[][4] =
67 #include "shaders/render/exa_wm_xy.g4b"
68 #include "shaders/render/exa_wm_src_affine.g4b"
69 #include "shaders/render/exa_wm_src_sample_planar.g4b"
70 #include "shaders/render/exa_wm_yuv_color_balance.g4b"
71 #include "shaders/render/exa_wm_yuv_rgb.g4b"
72 #include "shaders/render/exa_wm_write.g4b"
74 static const uint32_t ps_subpic_kernel_static[][4] =
76 #include "shaders/render/exa_wm_xy.g4b"
77 #include "shaders/render/exa_wm_src_affine.g4b"
78 #include "shaders/render/exa_wm_src_sample_argb.g4b"
79 #include "shaders/render/exa_wm_write.g4b"
83 static const uint32_t sf_kernel_static_gen5[][4] =
85 #include "shaders/render/exa_sf.g4b.gen5"
88 static const uint32_t ps_kernel_static_gen5[][4] =
90 #include "shaders/render/exa_wm_xy.g4b.gen5"
91 #include "shaders/render/exa_wm_src_affine.g4b.gen5"
92 #include "shaders/render/exa_wm_src_sample_planar.g4b.gen5"
93 #include "shaders/render/exa_wm_yuv_color_balance.g4b.gen5"
94 #include "shaders/render/exa_wm_yuv_rgb.g4b.gen5"
95 #include "shaders/render/exa_wm_write.g4b.gen5"
97 static const uint32_t ps_subpic_kernel_static_gen5[][4] =
99 #include "shaders/render/exa_wm_xy.g4b.gen5"
100 #include "shaders/render/exa_wm_src_affine.g4b.gen5"
101 #include "shaders/render/exa_wm_src_sample_argb.g4b.gen5"
102 #include "shaders/render/exa_wm_write.g4b.gen5"
105 /* programs for Sandybridge */
106 static const uint32_t sf_kernel_static_gen6[][4] =
110 static const uint32_t ps_kernel_static_gen6[][4] = {
111 #include "shaders/render/exa_wm_src_affine.g6b"
112 #include "shaders/render/exa_wm_src_sample_planar.g6b"
113 #include "shaders/render/exa_wm_yuv_color_balance.g6b"
114 #include "shaders/render/exa_wm_yuv_rgb.g6b"
115 #include "shaders/render/exa_wm_write.g6b"
118 static const uint32_t ps_subpic_kernel_static_gen6[][4] = {
119 #include "shaders/render/exa_wm_src_affine.g6b"
120 #include "shaders/render/exa_wm_src_sample_argb.g6b"
121 #include "shaders/render/exa_wm_write.g6b"
124 /* programs for Ivybridge */
125 static const uint32_t sf_kernel_static_gen7[][4] =
129 static const uint32_t ps_kernel_static_gen7[][4] = {
130 #include "shaders/render/exa_wm_src_affine.g7b"
131 #include "shaders/render/exa_wm_src_sample_planar.g7b"
132 #include "shaders/render/exa_wm_yuv_color_balance.g7b"
133 #include "shaders/render/exa_wm_yuv_rgb.g7b"
134 #include "shaders/render/exa_wm_write.g7b"
137 static const uint32_t ps_subpic_kernel_static_gen7[][4] = {
138 #include "shaders/render/exa_wm_src_affine.g7b"
139 #include "shaders/render/exa_wm_src_sample_argb.g7b"
140 #include "shaders/render/exa_wm_write.g7b"
143 /* Programs for Haswell */
144 static const uint32_t ps_kernel_static_gen7_haswell[][4] = {
145 #include "shaders/render/exa_wm_src_affine.g7b"
146 #include "shaders/render/exa_wm_src_sample_planar.g7b.haswell"
147 #include "shaders/render/exa_wm_yuv_color_balance.g7b.haswell"
148 #include "shaders/render/exa_wm_yuv_rgb.g7b"
149 #include "shaders/render/exa_wm_write.g7b"
153 #define SURFACE_STATE_PADDED_SIZE MAX(SURFACE_STATE_PADDED_SIZE_GEN6, SURFACE_STATE_PADDED_SIZE_GEN7)
155 #define SURFACE_STATE_OFFSET(index) (SURFACE_STATE_PADDED_SIZE * index)
156 #define BINDING_TABLE_OFFSET SURFACE_STATE_OFFSET(MAX_RENDER_SURFACES)
158 static uint32_t float_to_uint (float f)
176 static struct i965_kernel render_kernels_gen4[] = {
181 sizeof(sf_kernel_static),
188 sizeof(ps_kernel_static),
195 ps_subpic_kernel_static,
196 sizeof(ps_subpic_kernel_static),
201 static struct i965_kernel render_kernels_gen5[] = {
205 sf_kernel_static_gen5,
206 sizeof(sf_kernel_static_gen5),
212 ps_kernel_static_gen5,
213 sizeof(ps_kernel_static_gen5),
220 ps_subpic_kernel_static_gen5,
221 sizeof(ps_subpic_kernel_static_gen5),
226 static struct i965_kernel render_kernels_gen6[] = {
230 sf_kernel_static_gen6,
231 sizeof(sf_kernel_static_gen6),
237 ps_kernel_static_gen6,
238 sizeof(ps_kernel_static_gen6),
245 ps_subpic_kernel_static_gen6,
246 sizeof(ps_subpic_kernel_static_gen6),
251 static struct i965_kernel render_kernels_gen7[] = {
255 sf_kernel_static_gen7,
256 sizeof(sf_kernel_static_gen7),
262 ps_kernel_static_gen7,
263 sizeof(ps_kernel_static_gen7),
270 ps_subpic_kernel_static_gen7,
271 sizeof(ps_subpic_kernel_static_gen7),
276 static struct i965_kernel render_kernels_gen7_haswell[] = {
280 sf_kernel_static_gen7,
281 sizeof(sf_kernel_static_gen7),
287 ps_kernel_static_gen7_haswell,
288 sizeof(ps_kernel_static_gen7_haswell),
295 ps_subpic_kernel_static_gen7,
296 sizeof(ps_subpic_kernel_static_gen7),
301 #define URB_VS_ENTRIES 8
302 #define URB_VS_ENTRY_SIZE 1
304 #define URB_GS_ENTRIES 0
305 #define URB_GS_ENTRY_SIZE 0
307 #define URB_CLIP_ENTRIES 0
308 #define URB_CLIP_ENTRY_SIZE 0
310 #define URB_SF_ENTRIES 1
311 #define URB_SF_ENTRY_SIZE 2
313 #define URB_CS_ENTRIES 4
314 #define URB_CS_ENTRY_SIZE 4
317 i965_render_vs_unit(VADriverContextP ctx)
319 struct i965_driver_data *i965 = i965_driver_data(ctx);
320 struct i965_render_state *render_state = &i965->render_state;
321 struct i965_vs_unit_state *vs_state;
323 dri_bo_map(render_state->vs.state, 1);
324 assert(render_state->vs.state->virtual);
325 vs_state = render_state->vs.state->virtual;
326 memset(vs_state, 0, sizeof(*vs_state));
328 if (IS_IRONLAKE(i965->intel.device_info))
329 vs_state->thread4.nr_urb_entries = URB_VS_ENTRIES >> 2;
331 vs_state->thread4.nr_urb_entries = URB_VS_ENTRIES;
333 vs_state->thread4.urb_entry_allocation_size = URB_VS_ENTRY_SIZE - 1;
334 vs_state->vs6.vs_enable = 0;
335 vs_state->vs6.vert_cache_disable = 1;
337 dri_bo_unmap(render_state->vs.state);
341 i965_render_sf_unit(VADriverContextP ctx)
343 struct i965_driver_data *i965 = i965_driver_data(ctx);
344 struct i965_render_state *render_state = &i965->render_state;
345 struct i965_sf_unit_state *sf_state;
347 dri_bo_map(render_state->sf.state, 1);
348 assert(render_state->sf.state->virtual);
349 sf_state = render_state->sf.state->virtual;
350 memset(sf_state, 0, sizeof(*sf_state));
352 sf_state->thread0.grf_reg_count = I965_GRF_BLOCKS(SF_KERNEL_NUM_GRF);
353 sf_state->thread0.kernel_start_pointer = render_state->render_kernels[SF_KERNEL].bo->offset >> 6;
355 sf_state->sf1.single_program_flow = 1; /* XXX */
356 sf_state->sf1.binding_table_entry_count = 0;
357 sf_state->sf1.thread_priority = 0;
358 sf_state->sf1.floating_point_mode = 0; /* Mesa does this */
359 sf_state->sf1.illegal_op_exception_enable = 1;
360 sf_state->sf1.mask_stack_exception_enable = 1;
361 sf_state->sf1.sw_exception_enable = 1;
363 /* scratch space is not used in our kernel */
364 sf_state->thread2.per_thread_scratch_space = 0;
365 sf_state->thread2.scratch_space_base_pointer = 0;
367 sf_state->thread3.const_urb_entry_read_length = 0; /* no const URBs */
368 sf_state->thread3.const_urb_entry_read_offset = 0; /* no const URBs */
369 sf_state->thread3.urb_entry_read_length = 1; /* 1 URB per vertex */
370 sf_state->thread3.urb_entry_read_offset = 0;
371 sf_state->thread3.dispatch_grf_start_reg = 3;
373 sf_state->thread4.max_threads = SF_MAX_THREADS - 1;
374 sf_state->thread4.urb_entry_allocation_size = URB_SF_ENTRY_SIZE - 1;
375 sf_state->thread4.nr_urb_entries = URB_SF_ENTRIES;
376 sf_state->thread4.stats_enable = 1;
378 sf_state->sf5.viewport_transform = 0; /* skip viewport */
380 sf_state->sf6.cull_mode = I965_CULLMODE_NONE;
381 sf_state->sf6.scissor = 0;
383 sf_state->sf7.trifan_pv = 2;
385 sf_state->sf6.dest_org_vbias = 0x8;
386 sf_state->sf6.dest_org_hbias = 0x8;
388 dri_bo_emit_reloc(render_state->sf.state,
389 I915_GEM_DOMAIN_INSTRUCTION, 0,
390 sf_state->thread0.grf_reg_count << 1,
391 offsetof(struct i965_sf_unit_state, thread0),
392 render_state->render_kernels[SF_KERNEL].bo);
394 dri_bo_unmap(render_state->sf.state);
398 i965_render_sampler(VADriverContextP ctx)
400 struct i965_driver_data *i965 = i965_driver_data(ctx);
401 struct i965_render_state *render_state = &i965->render_state;
402 struct i965_sampler_state *sampler_state;
405 assert(render_state->wm.sampler_count > 0);
406 assert(render_state->wm.sampler_count <= MAX_SAMPLERS);
408 dri_bo_map(render_state->wm.sampler, 1);
409 assert(render_state->wm.sampler->virtual);
410 sampler_state = render_state->wm.sampler->virtual;
411 for (i = 0; i < render_state->wm.sampler_count; i++) {
412 memset(sampler_state, 0, sizeof(*sampler_state));
413 sampler_state->ss0.min_filter = I965_MAPFILTER_LINEAR;
414 sampler_state->ss0.mag_filter = I965_MAPFILTER_LINEAR;
415 sampler_state->ss1.r_wrap_mode = I965_TEXCOORDMODE_CLAMP;
416 sampler_state->ss1.s_wrap_mode = I965_TEXCOORDMODE_CLAMP;
417 sampler_state->ss1.t_wrap_mode = I965_TEXCOORDMODE_CLAMP;
421 dri_bo_unmap(render_state->wm.sampler);
424 i965_subpic_render_wm_unit(VADriverContextP ctx)
426 struct i965_driver_data *i965 = i965_driver_data(ctx);
427 struct i965_render_state *render_state = &i965->render_state;
428 struct i965_wm_unit_state *wm_state;
430 assert(render_state->wm.sampler);
432 dri_bo_map(render_state->wm.state, 1);
433 assert(render_state->wm.state->virtual);
434 wm_state = render_state->wm.state->virtual;
435 memset(wm_state, 0, sizeof(*wm_state));
437 wm_state->thread0.grf_reg_count = I965_GRF_BLOCKS(PS_KERNEL_NUM_GRF);
438 wm_state->thread0.kernel_start_pointer = render_state->render_kernels[PS_SUBPIC_KERNEL].bo->offset >> 6;
440 wm_state->thread1.single_program_flow = 1; /* XXX */
442 if (IS_IRONLAKE(i965->intel.device_info))
443 wm_state->thread1.binding_table_entry_count = 0; /* hardware requirement */
445 wm_state->thread1.binding_table_entry_count = 7;
447 wm_state->thread2.scratch_space_base_pointer = 0;
448 wm_state->thread2.per_thread_scratch_space = 0; /* 1024 bytes */
450 wm_state->thread3.dispatch_grf_start_reg = 2; /* XXX */
451 wm_state->thread3.const_urb_entry_read_length = 4;
452 wm_state->thread3.const_urb_entry_read_offset = 0;
453 wm_state->thread3.urb_entry_read_length = 1; /* XXX */
454 wm_state->thread3.urb_entry_read_offset = 0; /* XXX */
456 wm_state->wm4.stats_enable = 0;
457 wm_state->wm4.sampler_state_pointer = render_state->wm.sampler->offset >> 5;
459 if (IS_IRONLAKE(i965->intel.device_info)) {
460 wm_state->wm4.sampler_count = 0; /* hardware requirement */
462 wm_state->wm4.sampler_count = (render_state->wm.sampler_count + 3) / 4;
465 wm_state->wm5.max_threads = i965->intel.device_info->max_wm_threads - 1;
466 wm_state->wm5.thread_dispatch_enable = 1;
467 wm_state->wm5.enable_16_pix = 1;
468 wm_state->wm5.enable_8_pix = 0;
469 wm_state->wm5.early_depth_test = 1;
471 dri_bo_emit_reloc(render_state->wm.state,
472 I915_GEM_DOMAIN_INSTRUCTION, 0,
473 wm_state->thread0.grf_reg_count << 1,
474 offsetof(struct i965_wm_unit_state, thread0),
475 render_state->render_kernels[PS_SUBPIC_KERNEL].bo);
477 dri_bo_emit_reloc(render_state->wm.state,
478 I915_GEM_DOMAIN_INSTRUCTION, 0,
479 wm_state->wm4.sampler_count << 2,
480 offsetof(struct i965_wm_unit_state, wm4),
481 render_state->wm.sampler);
483 dri_bo_unmap(render_state->wm.state);
488 i965_render_wm_unit(VADriverContextP ctx)
490 struct i965_driver_data *i965 = i965_driver_data(ctx);
491 struct i965_render_state *render_state = &i965->render_state;
492 struct i965_wm_unit_state *wm_state;
494 assert(render_state->wm.sampler);
496 dri_bo_map(render_state->wm.state, 1);
497 assert(render_state->wm.state->virtual);
498 wm_state = render_state->wm.state->virtual;
499 memset(wm_state, 0, sizeof(*wm_state));
501 wm_state->thread0.grf_reg_count = I965_GRF_BLOCKS(PS_KERNEL_NUM_GRF);
502 wm_state->thread0.kernel_start_pointer = render_state->render_kernels[PS_KERNEL].bo->offset >> 6;
504 wm_state->thread1.single_program_flow = 1; /* XXX */
506 if (IS_IRONLAKE(i965->intel.device_info))
507 wm_state->thread1.binding_table_entry_count = 0; /* hardware requirement */
509 wm_state->thread1.binding_table_entry_count = 7;
511 wm_state->thread2.scratch_space_base_pointer = 0;
512 wm_state->thread2.per_thread_scratch_space = 0; /* 1024 bytes */
514 wm_state->thread3.dispatch_grf_start_reg = 2; /* XXX */
515 wm_state->thread3.const_urb_entry_read_length = 4;
516 wm_state->thread3.const_urb_entry_read_offset = 0;
517 wm_state->thread3.urb_entry_read_length = 1; /* XXX */
518 wm_state->thread3.urb_entry_read_offset = 0; /* XXX */
520 wm_state->wm4.stats_enable = 0;
521 wm_state->wm4.sampler_state_pointer = render_state->wm.sampler->offset >> 5;
523 if (IS_IRONLAKE(i965->intel.device_info)) {
524 wm_state->wm4.sampler_count = 0; /* hardware requirement */
526 wm_state->wm4.sampler_count = (render_state->wm.sampler_count + 3) / 4;
529 wm_state->wm5.max_threads = i965->intel.device_info->max_wm_threads - 1;
530 wm_state->wm5.thread_dispatch_enable = 1;
531 wm_state->wm5.enable_16_pix = 1;
532 wm_state->wm5.enable_8_pix = 0;
533 wm_state->wm5.early_depth_test = 1;
535 dri_bo_emit_reloc(render_state->wm.state,
536 I915_GEM_DOMAIN_INSTRUCTION, 0,
537 wm_state->thread0.grf_reg_count << 1,
538 offsetof(struct i965_wm_unit_state, thread0),
539 render_state->render_kernels[PS_KERNEL].bo);
541 dri_bo_emit_reloc(render_state->wm.state,
542 I915_GEM_DOMAIN_INSTRUCTION, 0,
543 wm_state->wm4.sampler_count << 2,
544 offsetof(struct i965_wm_unit_state, wm4),
545 render_state->wm.sampler);
547 dri_bo_unmap(render_state->wm.state);
551 i965_render_cc_viewport(VADriverContextP ctx)
553 struct i965_driver_data *i965 = i965_driver_data(ctx);
554 struct i965_render_state *render_state = &i965->render_state;
555 struct i965_cc_viewport *cc_viewport;
557 dri_bo_map(render_state->cc.viewport, 1);
558 assert(render_state->cc.viewport->virtual);
559 cc_viewport = render_state->cc.viewport->virtual;
560 memset(cc_viewport, 0, sizeof(*cc_viewport));
562 cc_viewport->min_depth = -1.e35;
563 cc_viewport->max_depth = 1.e35;
565 dri_bo_unmap(render_state->cc.viewport);
569 i965_subpic_render_cc_unit(VADriverContextP ctx)
571 struct i965_driver_data *i965 = i965_driver_data(ctx);
572 struct i965_render_state *render_state = &i965->render_state;
573 struct i965_cc_unit_state *cc_state;
575 assert(render_state->cc.viewport);
577 dri_bo_map(render_state->cc.state, 1);
578 assert(render_state->cc.state->virtual);
579 cc_state = render_state->cc.state->virtual;
580 memset(cc_state, 0, sizeof(*cc_state));
582 cc_state->cc0.stencil_enable = 0; /* disable stencil */
583 cc_state->cc2.depth_test = 0; /* disable depth test */
584 cc_state->cc2.logicop_enable = 0; /* disable logic op */
585 cc_state->cc3.ia_blend_enable = 0 ; /* blend alpha just like colors */
586 cc_state->cc3.blend_enable = 1; /* enable color blend */
587 cc_state->cc3.alpha_test = 0; /* disable alpha test */
588 cc_state->cc3.alpha_test_format = 0;//0:ALPHATEST_UNORM8; /*store alpha value with UNORM8 */
589 cc_state->cc3.alpha_test_func = 5;//COMPAREFUNCTION_LESS; /*pass if less than the reference */
590 cc_state->cc4.cc_viewport_state_offset = render_state->cc.viewport->offset >> 5;
592 cc_state->cc5.dither_enable = 0; /* disable dither */
593 cc_state->cc5.logicop_func = 0xc; /* WHITE */
594 cc_state->cc5.statistics_enable = 1;
595 cc_state->cc5.ia_blend_function = I965_BLENDFUNCTION_ADD;
596 cc_state->cc5.ia_src_blend_factor = I965_BLENDFACTOR_DST_ALPHA;
597 cc_state->cc5.ia_dest_blend_factor = I965_BLENDFACTOR_DST_ALPHA;
599 cc_state->cc6.clamp_post_alpha_blend = 0;
600 cc_state->cc6.clamp_pre_alpha_blend =0;
602 /*final color = src_color*src_blend_factor +/- dst_color*dest_color_blend_factor*/
603 cc_state->cc6.blend_function = I965_BLENDFUNCTION_ADD;
604 cc_state->cc6.src_blend_factor = I965_BLENDFACTOR_SRC_ALPHA;
605 cc_state->cc6.dest_blend_factor = I965_BLENDFACTOR_INV_SRC_ALPHA;
607 /*alpha test reference*/
608 cc_state->cc7.alpha_ref.f =0.0 ;
611 dri_bo_emit_reloc(render_state->cc.state,
612 I915_GEM_DOMAIN_INSTRUCTION, 0,
614 offsetof(struct i965_cc_unit_state, cc4),
615 render_state->cc.viewport);
617 dri_bo_unmap(render_state->cc.state);
622 i965_render_cc_unit(VADriverContextP ctx)
624 struct i965_driver_data *i965 = i965_driver_data(ctx);
625 struct i965_render_state *render_state = &i965->render_state;
626 struct i965_cc_unit_state *cc_state;
628 assert(render_state->cc.viewport);
630 dri_bo_map(render_state->cc.state, 1);
631 assert(render_state->cc.state->virtual);
632 cc_state = render_state->cc.state->virtual;
633 memset(cc_state, 0, sizeof(*cc_state));
635 cc_state->cc0.stencil_enable = 0; /* disable stencil */
636 cc_state->cc2.depth_test = 0; /* disable depth test */
637 cc_state->cc2.logicop_enable = 1; /* enable logic op */
638 cc_state->cc3.ia_blend_enable = 0; /* blend alpha just like colors */
639 cc_state->cc3.blend_enable = 0; /* disable color blend */
640 cc_state->cc3.alpha_test = 0; /* disable alpha test */
641 cc_state->cc4.cc_viewport_state_offset = render_state->cc.viewport->offset >> 5;
643 cc_state->cc5.dither_enable = 0; /* disable dither */
644 cc_state->cc5.logicop_func = 0xc; /* WHITE */
645 cc_state->cc5.statistics_enable = 1;
646 cc_state->cc5.ia_blend_function = I965_BLENDFUNCTION_ADD;
647 cc_state->cc5.ia_src_blend_factor = I965_BLENDFACTOR_ONE;
648 cc_state->cc5.ia_dest_blend_factor = I965_BLENDFACTOR_ONE;
650 dri_bo_emit_reloc(render_state->cc.state,
651 I915_GEM_DOMAIN_INSTRUCTION, 0,
653 offsetof(struct i965_cc_unit_state, cc4),
654 render_state->cc.viewport);
656 dri_bo_unmap(render_state->cc.state);
660 i965_render_set_surface_tiling(struct i965_surface_state *ss, unsigned int tiling)
663 case I915_TILING_NONE:
664 ss->ss3.tiled_surface = 0;
665 ss->ss3.tile_walk = 0;
668 ss->ss3.tiled_surface = 1;
669 ss->ss3.tile_walk = I965_TILEWALK_XMAJOR;
672 ss->ss3.tiled_surface = 1;
673 ss->ss3.tile_walk = I965_TILEWALK_YMAJOR;
679 i965_render_set_surface_state(
680 struct i965_surface_state *ss,
682 unsigned long offset,
691 unsigned int swizzle;
693 memset(ss, 0, sizeof(*ss));
695 switch (flags & (VA_TOP_FIELD|VA_BOTTOM_FIELD)) {
696 case VA_BOTTOM_FIELD:
697 ss->ss0.vert_line_stride_ofs = 1;
700 ss->ss0.vert_line_stride = 1;
705 ss->ss0.surface_type = I965_SURFACE_2D;
706 ss->ss0.surface_format = format;
707 ss->ss0.color_blend = 1;
709 ss->ss1.base_addr = bo->offset + offset;
711 ss->ss2.width = width - 1;
712 ss->ss2.height = height - 1;
714 ss->ss3.pitch = pitch - 1;
716 dri_bo_get_tiling(bo, &tiling, &swizzle);
717 i965_render_set_surface_tiling(ss, tiling);
721 gen7_render_set_surface_tiling(struct gen7_surface_state *ss, uint32_t tiling)
724 case I915_TILING_NONE:
725 ss->ss0.tiled_surface = 0;
726 ss->ss0.tile_walk = 0;
729 ss->ss0.tiled_surface = 1;
730 ss->ss0.tile_walk = I965_TILEWALK_XMAJOR;
733 ss->ss0.tiled_surface = 1;
734 ss->ss0.tile_walk = I965_TILEWALK_YMAJOR;
739 /* Set "Shader Channel Select" */
741 gen7_render_set_surface_scs(struct gen7_surface_state *ss)
743 ss->ss7.shader_chanel_select_r = HSW_SCS_RED;
744 ss->ss7.shader_chanel_select_g = HSW_SCS_GREEN;
745 ss->ss7.shader_chanel_select_b = HSW_SCS_BLUE;
746 ss->ss7.shader_chanel_select_a = HSW_SCS_ALPHA;
750 gen7_render_set_surface_state(
751 struct gen7_surface_state *ss,
753 unsigned long offset,
762 unsigned int swizzle;
764 memset(ss, 0, sizeof(*ss));
766 switch (flags & (VA_TOP_FIELD|VA_BOTTOM_FIELD)) {
767 case VA_BOTTOM_FIELD:
768 ss->ss0.vert_line_stride_ofs = 1;
771 ss->ss0.vert_line_stride = 1;
776 ss->ss0.surface_type = I965_SURFACE_2D;
777 ss->ss0.surface_format = format;
779 ss->ss1.base_addr = bo->offset + offset;
781 ss->ss2.width = width - 1;
782 ss->ss2.height = height - 1;
784 ss->ss3.pitch = pitch - 1;
786 dri_bo_get_tiling(bo, &tiling, &swizzle);
787 gen7_render_set_surface_tiling(ss, tiling);
792 i965_render_src_surface_state(
793 VADriverContextP ctx,
796 unsigned long offset,
804 struct i965_driver_data *i965 = i965_driver_data(ctx);
805 struct i965_render_state *render_state = &i965->render_state;
807 dri_bo *ss_bo = render_state->wm.surface_state_binding_table_bo;
809 assert(index < MAX_RENDER_SURFACES);
811 dri_bo_map(ss_bo, 1);
812 assert(ss_bo->virtual);
813 ss = (char *)ss_bo->virtual + SURFACE_STATE_OFFSET(index);
815 if (IS_GEN7(i965->intel.device_info)) {
816 gen7_render_set_surface_state(ss,
819 pitch, format, flags);
820 if (IS_HASWELL(i965->intel.device_info))
821 gen7_render_set_surface_scs(ss);
822 dri_bo_emit_reloc(ss_bo,
823 I915_GEM_DOMAIN_SAMPLER, 0,
825 SURFACE_STATE_OFFSET(index) + offsetof(struct gen7_surface_state, ss1),
828 i965_render_set_surface_state(ss,
831 pitch, format, flags);
832 dri_bo_emit_reloc(ss_bo,
833 I915_GEM_DOMAIN_SAMPLER, 0,
835 SURFACE_STATE_OFFSET(index) + offsetof(struct i965_surface_state, ss1),
839 ((unsigned int *)((char *)ss_bo->virtual + BINDING_TABLE_OFFSET))[index] = SURFACE_STATE_OFFSET(index);
841 render_state->wm.sampler_count++;
845 i965_render_src_surfaces_state(
846 VADriverContextP ctx,
847 struct object_surface *obj_surface,
855 region_pitch = obj_surface->width;
856 rw = obj_surface->orig_width;
857 rh = obj_surface->orig_height;
858 region = obj_surface->bo;
860 i965_render_src_surface_state(ctx, 1, region, 0, rw, rh, region_pitch, I965_SURFACEFORMAT_R8_UNORM, flags); /* Y */
861 i965_render_src_surface_state(ctx, 2, region, 0, rw, rh, region_pitch, I965_SURFACEFORMAT_R8_UNORM, flags);
863 if (obj_surface->fourcc == VA_FOURCC_Y800) /* single plane for grayscale */
866 if (obj_surface->fourcc == VA_FOURCC_NV12) {
867 i965_render_src_surface_state(ctx, 3, region,
868 region_pitch * obj_surface->y_cb_offset,
869 obj_surface->cb_cr_width, obj_surface->cb_cr_height, obj_surface->cb_cr_pitch,
870 I965_SURFACEFORMAT_R8G8_UNORM, flags); /* UV */
871 i965_render_src_surface_state(ctx, 4, region,
872 region_pitch * obj_surface->y_cb_offset,
873 obj_surface->cb_cr_width, obj_surface->cb_cr_height, obj_surface->cb_cr_pitch,
874 I965_SURFACEFORMAT_R8G8_UNORM, flags);
876 i965_render_src_surface_state(ctx, 3, region,
877 region_pitch * obj_surface->y_cb_offset,
878 obj_surface->cb_cr_width, obj_surface->cb_cr_height, obj_surface->cb_cr_pitch,
879 I965_SURFACEFORMAT_R8_UNORM, flags); /* U */
880 i965_render_src_surface_state(ctx, 4, region,
881 region_pitch * obj_surface->y_cb_offset,
882 obj_surface->cb_cr_width, obj_surface->cb_cr_height, obj_surface->cb_cr_pitch,
883 I965_SURFACEFORMAT_R8_UNORM, flags);
884 i965_render_src_surface_state(ctx, 5, region,
885 region_pitch * obj_surface->y_cr_offset,
886 obj_surface->cb_cr_width, obj_surface->cb_cr_height, obj_surface->cb_cr_pitch,
887 I965_SURFACEFORMAT_R8_UNORM, flags); /* V */
888 i965_render_src_surface_state(ctx, 6, region,
889 region_pitch * obj_surface->y_cr_offset,
890 obj_surface->cb_cr_width, obj_surface->cb_cr_height, obj_surface->cb_cr_pitch,
891 I965_SURFACEFORMAT_R8_UNORM, flags);
896 i965_subpic_render_src_surfaces_state(VADriverContextP ctx,
897 struct object_surface *obj_surface)
899 dri_bo *subpic_region;
900 unsigned int index = obj_surface->subpic_render_idx;
901 struct object_subpic *obj_subpic = obj_surface->obj_subpic[index];
902 struct object_image *obj_image = obj_subpic->obj_image;
905 assert(obj_surface->bo);
906 subpic_region = obj_image->bo;
907 /*subpicture surface*/
908 i965_render_src_surface_state(ctx, 1, subpic_region, 0, obj_subpic->width, obj_subpic->height, obj_subpic->pitch, obj_subpic->format, 0);
909 i965_render_src_surface_state(ctx, 2, subpic_region, 0, obj_subpic->width, obj_subpic->height, obj_subpic->pitch, obj_subpic->format, 0);
913 i965_render_dest_surface_state(VADriverContextP ctx, int index)
915 struct i965_driver_data *i965 = i965_driver_data(ctx);
916 struct i965_render_state *render_state = &i965->render_state;
917 struct intel_region *dest_region = render_state->draw_region;
919 dri_bo *ss_bo = render_state->wm.surface_state_binding_table_bo;
921 assert(index < MAX_RENDER_SURFACES);
923 if (dest_region->cpp == 2) {
924 format = I965_SURFACEFORMAT_B5G6R5_UNORM;
926 format = I965_SURFACEFORMAT_B8G8R8A8_UNORM;
929 dri_bo_map(ss_bo, 1);
930 assert(ss_bo->virtual);
931 ss = (char *)ss_bo->virtual + SURFACE_STATE_OFFSET(index);
933 if (IS_GEN7(i965->intel.device_info)) {
934 gen7_render_set_surface_state(ss,
936 dest_region->width, dest_region->height,
937 dest_region->pitch, format, 0);
938 if (IS_HASWELL(i965->intel.device_info))
939 gen7_render_set_surface_scs(ss);
940 dri_bo_emit_reloc(ss_bo,
941 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
943 SURFACE_STATE_OFFSET(index) + offsetof(struct gen7_surface_state, ss1),
946 i965_render_set_surface_state(ss,
948 dest_region->width, dest_region->height,
949 dest_region->pitch, format, 0);
950 dri_bo_emit_reloc(ss_bo,
951 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
953 SURFACE_STATE_OFFSET(index) + offsetof(struct i965_surface_state, ss1),
957 ((unsigned int *)((char *)ss_bo->virtual + BINDING_TABLE_OFFSET))[index] = SURFACE_STATE_OFFSET(index);
962 i965_fill_vertex_buffer(
963 VADriverContextP ctx,
964 float tex_coords[4], /* [(u1,v1);(u2,v2)] */
965 float vid_coords[4] /* [(x1,y1);(x2,y2)] */
968 struct i965_driver_data * const i965 = i965_driver_data(ctx);
971 enum { X1, Y1, X2, Y2 };
973 static const unsigned int g_rotation_indices[][6] = {
974 [VA_ROTATION_NONE] = { X2, Y2, X1, Y2, X1, Y1 },
975 [VA_ROTATION_90] = { X2, Y1, X2, Y2, X1, Y2 },
976 [VA_ROTATION_180] = { X1, Y1, X2, Y1, X2, Y2 },
977 [VA_ROTATION_270] = { X1, Y2, X1, Y1, X2, Y1 },
980 const unsigned int * const rotation_indices =
981 g_rotation_indices[i965->rotation_attrib->value];
983 vb[0] = tex_coords[rotation_indices[0]]; /* bottom-right corner */
984 vb[1] = tex_coords[rotation_indices[1]];
985 vb[2] = vid_coords[X2];
986 vb[3] = vid_coords[Y2];
988 vb[4] = tex_coords[rotation_indices[2]]; /* bottom-left corner */
989 vb[5] = tex_coords[rotation_indices[3]];
990 vb[6] = vid_coords[X1];
991 vb[7] = vid_coords[Y2];
993 vb[8] = tex_coords[rotation_indices[4]]; /* top-left corner */
994 vb[9] = tex_coords[rotation_indices[5]];
995 vb[10] = vid_coords[X1];
996 vb[11] = vid_coords[Y1];
998 dri_bo_subdata(i965->render_state.vb.vertex_buffer, 0, sizeof(vb), vb);
1002 i965_subpic_render_upload_vertex(VADriverContextP ctx,
1003 struct object_surface *obj_surface,
1004 const VARectangle *output_rect)
1006 unsigned int index = obj_surface->subpic_render_idx;
1007 struct object_subpic *obj_subpic = obj_surface->obj_subpic[index];
1008 float tex_coords[4], vid_coords[4];
1009 VARectangle dst_rect;
1011 if (obj_subpic->flags & VA_SUBPICTURE_DESTINATION_IS_SCREEN_COORD)
1012 dst_rect = obj_subpic->dst_rect;
1014 const float sx = (float)output_rect->width / obj_surface->orig_width;
1015 const float sy = (float)output_rect->height / obj_surface->orig_height;
1016 dst_rect.x = output_rect->x + sx * obj_subpic->dst_rect.x;
1017 dst_rect.y = output_rect->y + sy * obj_subpic->dst_rect.y;
1018 dst_rect.width = sx * obj_subpic->dst_rect.width;
1019 dst_rect.height = sy * obj_subpic->dst_rect.height;
1022 tex_coords[0] = (float)obj_subpic->src_rect.x / obj_subpic->width;
1023 tex_coords[1] = (float)obj_subpic->src_rect.y / obj_subpic->height;
1024 tex_coords[2] = (float)(obj_subpic->src_rect.x + obj_subpic->src_rect.width) / obj_subpic->width;
1025 tex_coords[3] = (float)(obj_subpic->src_rect.y + obj_subpic->src_rect.height) / obj_subpic->height;
1027 vid_coords[0] = dst_rect.x;
1028 vid_coords[1] = dst_rect.y;
1029 vid_coords[2] = (float)(dst_rect.x + dst_rect.width);
1030 vid_coords[3] = (float)(dst_rect.y + dst_rect.height);
1032 i965_fill_vertex_buffer(ctx, tex_coords, vid_coords);
1036 i965_render_upload_vertex(
1037 VADriverContextP ctx,
1038 struct object_surface *obj_surface,
1039 const VARectangle *src_rect,
1040 const VARectangle *dst_rect
1043 struct i965_driver_data *i965 = i965_driver_data(ctx);
1044 struct i965_render_state *render_state = &i965->render_state;
1045 struct intel_region *dest_region = render_state->draw_region;
1046 float tex_coords[4], vid_coords[4];
1049 width = obj_surface->orig_width;
1050 height = obj_surface->orig_height;
1052 tex_coords[0] = (float)src_rect->x / width;
1053 tex_coords[1] = (float)src_rect->y / height;
1054 tex_coords[2] = (float)(src_rect->x + src_rect->width) / width;
1055 tex_coords[3] = (float)(src_rect->y + src_rect->height) / height;
1057 vid_coords[0] = dest_region->x + dst_rect->x;
1058 vid_coords[1] = dest_region->y + dst_rect->y;
1059 vid_coords[2] = vid_coords[0] + dst_rect->width;
1060 vid_coords[3] = vid_coords[1] + dst_rect->height;
1062 i965_fill_vertex_buffer(ctx, tex_coords, vid_coords);
1065 #define PI 3.1415926
1068 i965_render_upload_constants(VADriverContextP ctx,
1069 struct object_surface *obj_surface,
1072 struct i965_driver_data *i965 = i965_driver_data(ctx);
1073 struct i965_render_state *render_state = &i965->render_state;
1074 unsigned short *constant_buffer;
1075 float *color_balance_base;
1076 float contrast = (float)i965->contrast_attrib->value / DEFAULT_CONTRAST;
1077 float brightness = (float)i965->brightness_attrib->value / 255; /* YUV is float in the shader */
1078 float hue = (float)i965->hue_attrib->value / 180 * PI;
1079 float saturation = (float)i965->saturation_attrib->value / DEFAULT_SATURATION;
1081 const float* yuv_coefs;
1082 size_t coefs_length;
1084 dri_bo_map(render_state->curbe.bo, 1);
1085 assert(render_state->curbe.bo->virtual);
1086 constant_buffer = render_state->curbe.bo->virtual;
1088 if (obj_surface->subsampling == SUBSAMPLE_YUV400) {
1089 assert(obj_surface->fourcc == VA_FOURCC_Y800);
1091 constant_buffer[0] = 2;
1093 if (obj_surface->fourcc == VA_FOURCC_NV12)
1094 constant_buffer[0] = 1;
1096 constant_buffer[0] = 0;
1099 if (i965->contrast_attrib->value == DEFAULT_CONTRAST &&
1100 i965->brightness_attrib->value == DEFAULT_BRIGHTNESS &&
1101 i965->hue_attrib->value == DEFAULT_HUE &&
1102 i965->saturation_attrib->value == DEFAULT_SATURATION)
1103 constant_buffer[1] = 1; /* skip color balance transformation */
1105 constant_buffer[1] = 0;
1107 color_balance_base = (float *)constant_buffer + 4;
1108 *color_balance_base++ = contrast;
1109 *color_balance_base++ = brightness;
1110 *color_balance_base++ = cos(hue) * contrast * saturation;
1111 *color_balance_base++ = sin(hue) * contrast * saturation;
1113 yuv_to_rgb = (float *)constant_buffer + 8;
1114 yuv_coefs = i915_color_standard_to_coefs(i915_filter_to_color_standard(flags & VA_SRC_COLOR_MASK),
1116 memcpy(yuv_to_rgb, yuv_coefs, coefs_length);
1118 dri_bo_unmap(render_state->curbe.bo);
1122 i965_subpic_render_upload_constants(VADriverContextP ctx,
1123 struct object_surface *obj_surface)
1125 struct i965_driver_data *i965 = i965_driver_data(ctx);
1126 struct i965_render_state *render_state = &i965->render_state;
1127 float *constant_buffer;
1128 float global_alpha = 1.0;
1129 unsigned int index = obj_surface->subpic_render_idx;
1130 struct object_subpic *obj_subpic = obj_surface->obj_subpic[index];
1132 if (obj_subpic->flags & VA_SUBPICTURE_GLOBAL_ALPHA) {
1133 global_alpha = obj_subpic->global_alpha;
1136 dri_bo_map(render_state->curbe.bo, 1);
1138 assert(render_state->curbe.bo->virtual);
1139 constant_buffer = render_state->curbe.bo->virtual;
1140 *constant_buffer = global_alpha;
1142 dri_bo_unmap(render_state->curbe.bo);
1146 i965_surface_render_state_setup(
1147 VADriverContextP ctx,
1148 struct object_surface *obj_surface,
1149 const VARectangle *src_rect,
1150 const VARectangle *dst_rect,
1154 i965_render_vs_unit(ctx);
1155 i965_render_sf_unit(ctx);
1156 i965_render_dest_surface_state(ctx, 0);
1157 i965_render_src_surfaces_state(ctx, obj_surface, flags);
1158 i965_render_sampler(ctx);
1159 i965_render_wm_unit(ctx);
1160 i965_render_cc_viewport(ctx);
1161 i965_render_cc_unit(ctx);
1162 i965_render_upload_vertex(ctx, obj_surface, src_rect, dst_rect);
1163 i965_render_upload_constants(ctx, obj_surface, flags);
1167 i965_subpic_render_state_setup(
1168 VADriverContextP ctx,
1169 struct object_surface *obj_surface,
1170 const VARectangle *src_rect,
1171 const VARectangle *dst_rect
1174 i965_render_vs_unit(ctx);
1175 i965_render_sf_unit(ctx);
1176 i965_render_dest_surface_state(ctx, 0);
1177 i965_subpic_render_src_surfaces_state(ctx, obj_surface);
1178 i965_render_sampler(ctx);
1179 i965_subpic_render_wm_unit(ctx);
1180 i965_render_cc_viewport(ctx);
1181 i965_subpic_render_cc_unit(ctx);
1182 i965_subpic_render_upload_constants(ctx, obj_surface);
1183 i965_subpic_render_upload_vertex(ctx, obj_surface, dst_rect);
1188 i965_render_pipeline_select(VADriverContextP ctx)
1190 struct i965_driver_data *i965 = i965_driver_data(ctx);
1191 struct intel_batchbuffer *batch = i965->batch;
1193 BEGIN_BATCH(batch, 1);
1194 OUT_BATCH(batch, CMD_PIPELINE_SELECT | PIPELINE_SELECT_3D);
1195 ADVANCE_BATCH(batch);
1199 i965_render_state_sip(VADriverContextP ctx)
1201 struct i965_driver_data *i965 = i965_driver_data(ctx);
1202 struct intel_batchbuffer *batch = i965->batch;
1204 BEGIN_BATCH(batch, 2);
1205 OUT_BATCH(batch, CMD_STATE_SIP | 0);
1206 OUT_BATCH(batch, 0);
1207 ADVANCE_BATCH(batch);
1211 i965_render_state_base_address(VADriverContextP ctx)
1213 struct i965_driver_data *i965 = i965_driver_data(ctx);
1214 struct intel_batchbuffer *batch = i965->batch;
1215 struct i965_render_state *render_state = &i965->render_state;
1217 if (IS_IRONLAKE(i965->intel.device_info)) {
1218 BEGIN_BATCH(batch, 8);
1219 OUT_BATCH(batch, CMD_STATE_BASE_ADDRESS | 6);
1220 OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
1221 OUT_RELOC(batch, render_state->wm.surface_state_binding_table_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, BASE_ADDRESS_MODIFY);
1222 OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
1223 OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
1224 OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
1225 OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
1226 OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
1227 ADVANCE_BATCH(batch);
1229 BEGIN_BATCH(batch, 6);
1230 OUT_BATCH(batch, CMD_STATE_BASE_ADDRESS | 4);
1231 OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
1232 OUT_RELOC(batch, render_state->wm.surface_state_binding_table_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, BASE_ADDRESS_MODIFY);
1233 OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
1234 OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
1235 OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
1236 ADVANCE_BATCH(batch);
1241 i965_render_binding_table_pointers(VADriverContextP ctx)
1243 struct i965_driver_data *i965 = i965_driver_data(ctx);
1244 struct intel_batchbuffer *batch = i965->batch;
1246 BEGIN_BATCH(batch, 6);
1247 OUT_BATCH(batch, CMD_BINDING_TABLE_POINTERS | 4);
1248 OUT_BATCH(batch, 0); /* vs */
1249 OUT_BATCH(batch, 0); /* gs */
1250 OUT_BATCH(batch, 0); /* clip */
1251 OUT_BATCH(batch, 0); /* sf */
1252 OUT_BATCH(batch, BINDING_TABLE_OFFSET);
1253 ADVANCE_BATCH(batch);
1257 i965_render_constant_color(VADriverContextP ctx)
1259 struct i965_driver_data *i965 = i965_driver_data(ctx);
1260 struct intel_batchbuffer *batch = i965->batch;
1262 BEGIN_BATCH(batch, 5);
1263 OUT_BATCH(batch, CMD_CONSTANT_COLOR | 3);
1264 OUT_BATCH(batch, float_to_uint(1.0));
1265 OUT_BATCH(batch, float_to_uint(0.0));
1266 OUT_BATCH(batch, float_to_uint(1.0));
1267 OUT_BATCH(batch, float_to_uint(1.0));
1268 ADVANCE_BATCH(batch);
1272 i965_render_pipelined_pointers(VADriverContextP ctx)
1274 struct i965_driver_data *i965 = i965_driver_data(ctx);
1275 struct intel_batchbuffer *batch = i965->batch;
1276 struct i965_render_state *render_state = &i965->render_state;
1278 BEGIN_BATCH(batch, 7);
1279 OUT_BATCH(batch, CMD_PIPELINED_POINTERS | 5);
1280 OUT_RELOC(batch, render_state->vs.state, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
1281 OUT_BATCH(batch, 0); /* disable GS */
1282 OUT_BATCH(batch, 0); /* disable CLIP */
1283 OUT_RELOC(batch, render_state->sf.state, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
1284 OUT_RELOC(batch, render_state->wm.state, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
1285 OUT_RELOC(batch, render_state->cc.state, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
1286 ADVANCE_BATCH(batch);
1290 i965_render_urb_layout(VADriverContextP ctx)
1292 struct i965_driver_data *i965 = i965_driver_data(ctx);
1293 struct intel_batchbuffer *batch = i965->batch;
1294 int urb_vs_start, urb_vs_size;
1295 int urb_gs_start, urb_gs_size;
1296 int urb_clip_start, urb_clip_size;
1297 int urb_sf_start, urb_sf_size;
1298 int urb_cs_start, urb_cs_size;
1301 urb_vs_size = URB_VS_ENTRIES * URB_VS_ENTRY_SIZE;
1302 urb_gs_start = urb_vs_start + urb_vs_size;
1303 urb_gs_size = URB_GS_ENTRIES * URB_GS_ENTRY_SIZE;
1304 urb_clip_start = urb_gs_start + urb_gs_size;
1305 urb_clip_size = URB_CLIP_ENTRIES * URB_CLIP_ENTRY_SIZE;
1306 urb_sf_start = urb_clip_start + urb_clip_size;
1307 urb_sf_size = URB_SF_ENTRIES * URB_SF_ENTRY_SIZE;
1308 urb_cs_start = urb_sf_start + urb_sf_size;
1309 urb_cs_size = URB_CS_ENTRIES * URB_CS_ENTRY_SIZE;
1311 BEGIN_BATCH(batch, 3);
1321 ((urb_clip_start + urb_clip_size) << UF1_CLIP_FENCE_SHIFT) |
1322 ((urb_gs_start + urb_gs_size) << UF1_GS_FENCE_SHIFT) |
1323 ((urb_vs_start + urb_vs_size) << UF1_VS_FENCE_SHIFT));
1325 ((urb_cs_start + urb_cs_size) << UF2_CS_FENCE_SHIFT) |
1326 ((urb_sf_start + urb_sf_size) << UF2_SF_FENCE_SHIFT));
1327 ADVANCE_BATCH(batch);
1331 i965_render_cs_urb_layout(VADriverContextP ctx)
1333 struct i965_driver_data *i965 = i965_driver_data(ctx);
1334 struct intel_batchbuffer *batch = i965->batch;
1336 BEGIN_BATCH(batch, 2);
1337 OUT_BATCH(batch, CMD_CS_URB_STATE | 0);
1339 ((URB_CS_ENTRY_SIZE - 1) << 4) | /* URB Entry Allocation Size */
1340 (URB_CS_ENTRIES << 0)); /* Number of URB Entries */
1341 ADVANCE_BATCH(batch);
1345 i965_render_constant_buffer(VADriverContextP ctx)
1347 struct i965_driver_data *i965 = i965_driver_data(ctx);
1348 struct intel_batchbuffer *batch = i965->batch;
1349 struct i965_render_state *render_state = &i965->render_state;
1351 BEGIN_BATCH(batch, 2);
1352 OUT_BATCH(batch, CMD_CONSTANT_BUFFER | (1 << 8) | (2 - 2));
1353 OUT_RELOC(batch, render_state->curbe.bo,
1354 I915_GEM_DOMAIN_INSTRUCTION, 0,
1355 URB_CS_ENTRY_SIZE - 1);
1356 ADVANCE_BATCH(batch);
1360 i965_render_drawing_rectangle(VADriverContextP ctx)
1362 struct i965_driver_data *i965 = i965_driver_data(ctx);
1363 struct intel_batchbuffer *batch = i965->batch;
1364 struct i965_render_state *render_state = &i965->render_state;
1365 struct intel_region *dest_region = render_state->draw_region;
1367 BEGIN_BATCH(batch, 4);
1368 OUT_BATCH(batch, CMD_DRAWING_RECTANGLE | 2);
1369 OUT_BATCH(batch, 0x00000000);
1370 OUT_BATCH(batch, (dest_region->width - 1) | (dest_region->height - 1) << 16);
1371 OUT_BATCH(batch, 0x00000000);
1372 ADVANCE_BATCH(batch);
1376 i965_render_vertex_elements(VADriverContextP ctx)
1378 struct i965_driver_data *i965 = i965_driver_data(ctx);
1379 struct intel_batchbuffer *batch = i965->batch;
1381 if (IS_IRONLAKE(i965->intel.device_info)) {
1382 BEGIN_BATCH(batch, 5);
1383 OUT_BATCH(batch, CMD_VERTEX_ELEMENTS | 3);
1384 /* offset 0: X,Y -> {X, Y, 1.0, 1.0} */
1385 OUT_BATCH(batch, (0 << VE0_VERTEX_BUFFER_INDEX_SHIFT) |
1387 (I965_SURFACEFORMAT_R32G32_FLOAT << VE0_FORMAT_SHIFT) |
1388 (0 << VE0_OFFSET_SHIFT));
1389 OUT_BATCH(batch, (I965_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT) |
1390 (I965_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT) |
1391 (I965_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_2_SHIFT) |
1392 (I965_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT));
1393 /* offset 8: S0, T0 -> {S0, T0, 1.0, 1.0} */
1394 OUT_BATCH(batch, (0 << VE0_VERTEX_BUFFER_INDEX_SHIFT) |
1396 (I965_SURFACEFORMAT_R32G32_FLOAT << VE0_FORMAT_SHIFT) |
1397 (8 << VE0_OFFSET_SHIFT));
1398 OUT_BATCH(batch, (I965_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT) |
1399 (I965_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT) |
1400 (I965_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_2_SHIFT) |
1401 (I965_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT));
1402 ADVANCE_BATCH(batch);
1404 BEGIN_BATCH(batch, 5);
1405 OUT_BATCH(batch, CMD_VERTEX_ELEMENTS | 3);
1406 /* offset 0: X,Y -> {X, Y, 1.0, 1.0} */
1407 OUT_BATCH(batch, (0 << VE0_VERTEX_BUFFER_INDEX_SHIFT) |
1409 (I965_SURFACEFORMAT_R32G32_FLOAT << VE0_FORMAT_SHIFT) |
1410 (0 << VE0_OFFSET_SHIFT));
1411 OUT_BATCH(batch, (I965_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT) |
1412 (I965_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT) |
1413 (I965_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_2_SHIFT) |
1414 (I965_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT) |
1415 (0 << VE1_DESTINATION_ELEMENT_OFFSET_SHIFT));
1416 /* offset 8: S0, T0 -> {S0, T0, 1.0, 1.0} */
1417 OUT_BATCH(batch, (0 << VE0_VERTEX_BUFFER_INDEX_SHIFT) |
1419 (I965_SURFACEFORMAT_R32G32_FLOAT << VE0_FORMAT_SHIFT) |
1420 (8 << VE0_OFFSET_SHIFT));
1421 OUT_BATCH(batch, (I965_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT) |
1422 (I965_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT) |
1423 (I965_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_2_SHIFT) |
1424 (I965_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT) |
1425 (4 << VE1_DESTINATION_ELEMENT_OFFSET_SHIFT));
1426 ADVANCE_BATCH(batch);
1431 i965_render_upload_image_palette(
1432 VADriverContextP ctx,
1433 struct object_image *obj_image,
1437 struct i965_driver_data *i965 = i965_driver_data(ctx);
1438 struct intel_batchbuffer *batch = i965->batch;
1446 if (obj_image->image.num_palette_entries == 0)
1449 BEGIN_BATCH(batch, 1 + obj_image->image.num_palette_entries);
1450 OUT_BATCH(batch, CMD_SAMPLER_PALETTE_LOAD | (obj_image->image.num_palette_entries - 1));
1452 //int32_t out[16]; //0-23:color 23-31:alpha
1453 for (i = 0; i < obj_image->image.num_palette_entries; i++)
1454 OUT_BATCH(batch, (alpha << 24) | obj_image->palette[i]);
1455 ADVANCE_BATCH(batch);
1459 i965_render_startup(VADriverContextP ctx)
1461 struct i965_driver_data *i965 = i965_driver_data(ctx);
1462 struct intel_batchbuffer *batch = i965->batch;
1463 struct i965_render_state *render_state = &i965->render_state;
1465 BEGIN_BATCH(batch, 11);
1466 OUT_BATCH(batch, CMD_VERTEX_BUFFERS | 3);
1468 (0 << VB0_BUFFER_INDEX_SHIFT) |
1470 ((4 * 4) << VB0_BUFFER_PITCH_SHIFT));
1471 OUT_RELOC(batch, render_state->vb.vertex_buffer, I915_GEM_DOMAIN_VERTEX, 0, 0);
1473 if (IS_IRONLAKE(i965->intel.device_info))
1474 OUT_RELOC(batch, render_state->vb.vertex_buffer, I915_GEM_DOMAIN_VERTEX, 0, 12 * 4);
1476 OUT_BATCH(batch, 3);
1478 OUT_BATCH(batch, 0);
1482 _3DPRIMITIVE_VERTEX_SEQUENTIAL |
1483 (_3DPRIM_RECTLIST << _3DPRIMITIVE_TOPOLOGY_SHIFT) |
1486 OUT_BATCH(batch, 3); /* vertex count per instance */
1487 OUT_BATCH(batch, 0); /* start vertex offset */
1488 OUT_BATCH(batch, 1); /* single instance */
1489 OUT_BATCH(batch, 0); /* start instance location */
1490 OUT_BATCH(batch, 0); /* index buffer offset, ignored */
1491 ADVANCE_BATCH(batch);
1495 i965_clear_dest_region(VADriverContextP ctx)
1497 struct i965_driver_data *i965 = i965_driver_data(ctx);
1498 struct intel_batchbuffer *batch = i965->batch;
1499 struct i965_render_state *render_state = &i965->render_state;
1500 struct intel_region *dest_region = render_state->draw_region;
1501 unsigned int blt_cmd, br13;
1504 blt_cmd = XY_COLOR_BLT_CMD;
1506 pitch = dest_region->pitch;
1508 if (dest_region->cpp == 4) {
1510 blt_cmd |= (XY_COLOR_BLT_WRITE_RGB | XY_COLOR_BLT_WRITE_ALPHA);
1512 assert(dest_region->cpp == 2);
1516 if (dest_region->tiling != I915_TILING_NONE) {
1517 blt_cmd |= XY_COLOR_BLT_DST_TILED;
1523 if (IS_GEN6(i965->intel.device_info) ||
1524 IS_GEN7(i965->intel.device_info)) {
1525 intel_batchbuffer_start_atomic_blt(batch, 24);
1526 BEGIN_BLT_BATCH(batch, 6);
1528 intel_batchbuffer_start_atomic(batch, 24);
1529 BEGIN_BATCH(batch, 6);
1532 OUT_BATCH(batch, blt_cmd);
1533 OUT_BATCH(batch, br13);
1534 OUT_BATCH(batch, (dest_region->y << 16) | (dest_region->x));
1535 OUT_BATCH(batch, ((dest_region->y + dest_region->height) << 16) |
1536 (dest_region->x + dest_region->width));
1537 OUT_RELOC(batch, dest_region->bo,
1538 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
1540 OUT_BATCH(batch, 0x0);
1541 ADVANCE_BATCH(batch);
1542 intel_batchbuffer_end_atomic(batch);
1546 i965_surface_render_pipeline_setup(VADriverContextP ctx)
1548 struct i965_driver_data *i965 = i965_driver_data(ctx);
1549 struct intel_batchbuffer *batch = i965->batch;
1551 i965_clear_dest_region(ctx);
1552 intel_batchbuffer_start_atomic(batch, 0x1000);
1553 intel_batchbuffer_emit_mi_flush(batch);
1554 i965_render_pipeline_select(ctx);
1555 i965_render_state_sip(ctx);
1556 i965_render_state_base_address(ctx);
1557 i965_render_binding_table_pointers(ctx);
1558 i965_render_constant_color(ctx);
1559 i965_render_pipelined_pointers(ctx);
1560 i965_render_urb_layout(ctx);
1561 i965_render_cs_urb_layout(ctx);
1562 i965_render_constant_buffer(ctx);
1563 i965_render_drawing_rectangle(ctx);
1564 i965_render_vertex_elements(ctx);
1565 i965_render_startup(ctx);
1566 intel_batchbuffer_end_atomic(batch);
1570 i965_subpic_render_pipeline_setup(VADriverContextP ctx)
1572 struct i965_driver_data *i965 = i965_driver_data(ctx);
1573 struct intel_batchbuffer *batch = i965->batch;
1575 intel_batchbuffer_start_atomic(batch, 0x1000);
1576 intel_batchbuffer_emit_mi_flush(batch);
1577 i965_render_pipeline_select(ctx);
1578 i965_render_state_sip(ctx);
1579 i965_render_state_base_address(ctx);
1580 i965_render_binding_table_pointers(ctx);
1581 i965_render_constant_color(ctx);
1582 i965_render_pipelined_pointers(ctx);
1583 i965_render_urb_layout(ctx);
1584 i965_render_cs_urb_layout(ctx);
1585 i965_render_constant_buffer(ctx);
1586 i965_render_drawing_rectangle(ctx);
1587 i965_render_vertex_elements(ctx);
1588 i965_render_startup(ctx);
1589 intel_batchbuffer_end_atomic(batch);
1594 i965_render_initialize(VADriverContextP ctx)
1596 struct i965_driver_data *i965 = i965_driver_data(ctx);
1597 struct i965_render_state *render_state = &i965->render_state;
1601 dri_bo_unreference(render_state->vb.vertex_buffer);
1602 bo = dri_bo_alloc(i965->intel.bufmgr,
1607 render_state->vb.vertex_buffer = bo;
1610 dri_bo_unreference(render_state->vs.state);
1611 bo = dri_bo_alloc(i965->intel.bufmgr,
1613 sizeof(struct i965_vs_unit_state),
1616 render_state->vs.state = bo;
1621 dri_bo_unreference(render_state->sf.state);
1622 bo = dri_bo_alloc(i965->intel.bufmgr,
1624 sizeof(struct i965_sf_unit_state),
1627 render_state->sf.state = bo;
1630 dri_bo_unreference(render_state->wm.surface_state_binding_table_bo);
1631 bo = dri_bo_alloc(i965->intel.bufmgr,
1632 "surface state & binding table",
1633 (SURFACE_STATE_PADDED_SIZE + sizeof(unsigned int)) * MAX_RENDER_SURFACES,
1636 render_state->wm.surface_state_binding_table_bo = bo;
1638 dri_bo_unreference(render_state->wm.sampler);
1639 bo = dri_bo_alloc(i965->intel.bufmgr,
1641 MAX_SAMPLERS * sizeof(struct i965_sampler_state),
1644 render_state->wm.sampler = bo;
1645 render_state->wm.sampler_count = 0;
1647 dri_bo_unreference(render_state->wm.state);
1648 bo = dri_bo_alloc(i965->intel.bufmgr,
1650 sizeof(struct i965_wm_unit_state),
1653 render_state->wm.state = bo;
1655 /* COLOR CALCULATOR */
1656 dri_bo_unreference(render_state->cc.state);
1657 bo = dri_bo_alloc(i965->intel.bufmgr,
1659 sizeof(struct i965_cc_unit_state),
1662 render_state->cc.state = bo;
1664 dri_bo_unreference(render_state->cc.viewport);
1665 bo = dri_bo_alloc(i965->intel.bufmgr,
1667 sizeof(struct i965_cc_viewport),
1670 render_state->cc.viewport = bo;
1674 i965_render_put_surface(
1675 VADriverContextP ctx,
1676 struct object_surface *obj_surface,
1677 const VARectangle *src_rect,
1678 const VARectangle *dst_rect,
1682 struct i965_driver_data *i965 = i965_driver_data(ctx);
1683 struct intel_batchbuffer *batch = i965->batch;
1685 i965_render_initialize(ctx);
1686 i965_surface_render_state_setup(ctx, obj_surface, src_rect, dst_rect, flags);
1687 i965_surface_render_pipeline_setup(ctx);
1688 intel_batchbuffer_flush(batch);
1692 i965_render_put_subpicture(
1693 VADriverContextP ctx,
1694 struct object_surface *obj_surface,
1695 const VARectangle *src_rect,
1696 const VARectangle *dst_rect
1699 struct i965_driver_data *i965 = i965_driver_data(ctx);
1700 struct intel_batchbuffer *batch = i965->batch;
1701 unsigned int index = obj_surface->subpic_render_idx;
1702 struct object_subpic *obj_subpic = obj_surface->obj_subpic[index];
1706 i965_render_initialize(ctx);
1707 i965_subpic_render_state_setup(ctx, obj_surface, src_rect, dst_rect);
1708 i965_subpic_render_pipeline_setup(ctx);
1709 i965_render_upload_image_palette(ctx, obj_subpic->obj_image, 0xff);
1710 intel_batchbuffer_flush(batch);
1717 gen6_render_initialize(VADriverContextP ctx)
1719 struct i965_driver_data *i965 = i965_driver_data(ctx);
1720 struct i965_render_state *render_state = &i965->render_state;
1724 dri_bo_unreference(render_state->vb.vertex_buffer);
1725 bo = dri_bo_alloc(i965->intel.bufmgr,
1730 render_state->vb.vertex_buffer = bo;
1733 dri_bo_unreference(render_state->wm.surface_state_binding_table_bo);
1734 bo = dri_bo_alloc(i965->intel.bufmgr,
1735 "surface state & binding table",
1736 (SURFACE_STATE_PADDED_SIZE + sizeof(unsigned int)) * MAX_RENDER_SURFACES,
1739 render_state->wm.surface_state_binding_table_bo = bo;
1741 dri_bo_unreference(render_state->wm.sampler);
1742 bo = dri_bo_alloc(i965->intel.bufmgr,
1744 MAX_SAMPLERS * sizeof(struct i965_sampler_state),
1747 render_state->wm.sampler = bo;
1748 render_state->wm.sampler_count = 0;
1750 /* COLOR CALCULATOR */
1751 dri_bo_unreference(render_state->cc.state);
1752 bo = dri_bo_alloc(i965->intel.bufmgr,
1754 sizeof(struct gen6_color_calc_state),
1757 render_state->cc.state = bo;
1760 dri_bo_unreference(render_state->cc.viewport);
1761 bo = dri_bo_alloc(i965->intel.bufmgr,
1763 sizeof(struct i965_cc_viewport),
1766 render_state->cc.viewport = bo;
1769 dri_bo_unreference(render_state->cc.blend);
1770 bo = dri_bo_alloc(i965->intel.bufmgr,
1772 sizeof(struct gen6_blend_state),
1775 render_state->cc.blend = bo;
1777 /* DEPTH & STENCIL STATE */
1778 dri_bo_unreference(render_state->cc.depth_stencil);
1779 bo = dri_bo_alloc(i965->intel.bufmgr,
1780 "depth & stencil state",
1781 sizeof(struct gen6_depth_stencil_state),
1784 render_state->cc.depth_stencil = bo;
1788 gen6_render_color_calc_state(VADriverContextP ctx)
1790 struct i965_driver_data *i965 = i965_driver_data(ctx);
1791 struct i965_render_state *render_state = &i965->render_state;
1792 struct gen6_color_calc_state *color_calc_state;
1794 dri_bo_map(render_state->cc.state, 1);
1795 assert(render_state->cc.state->virtual);
1796 color_calc_state = render_state->cc.state->virtual;
1797 memset(color_calc_state, 0, sizeof(*color_calc_state));
1798 color_calc_state->constant_r = 1.0;
1799 color_calc_state->constant_g = 0.0;
1800 color_calc_state->constant_b = 1.0;
1801 color_calc_state->constant_a = 1.0;
1802 dri_bo_unmap(render_state->cc.state);
1806 gen6_render_blend_state(VADriverContextP ctx)
1808 struct i965_driver_data *i965 = i965_driver_data(ctx);
1809 struct i965_render_state *render_state = &i965->render_state;
1810 struct gen6_blend_state *blend_state;
1812 dri_bo_map(render_state->cc.blend, 1);
1813 assert(render_state->cc.blend->virtual);
1814 blend_state = render_state->cc.blend->virtual;
1815 memset(blend_state, 0, sizeof(*blend_state));
1816 blend_state->blend1.logic_op_enable = 1;
1817 blend_state->blend1.logic_op_func = 0xc;
1818 dri_bo_unmap(render_state->cc.blend);
1822 gen6_render_depth_stencil_state(VADriverContextP ctx)
1824 struct i965_driver_data *i965 = i965_driver_data(ctx);
1825 struct i965_render_state *render_state = &i965->render_state;
1826 struct gen6_depth_stencil_state *depth_stencil_state;
1828 dri_bo_map(render_state->cc.depth_stencil, 1);
1829 assert(render_state->cc.depth_stencil->virtual);
1830 depth_stencil_state = render_state->cc.depth_stencil->virtual;
1831 memset(depth_stencil_state, 0, sizeof(*depth_stencil_state));
1832 dri_bo_unmap(render_state->cc.depth_stencil);
1836 gen6_render_setup_states(
1837 VADriverContextP ctx,
1838 struct object_surface *obj_surface,
1839 const VARectangle *src_rect,
1840 const VARectangle *dst_rect,
1844 i965_render_dest_surface_state(ctx, 0);
1845 i965_render_src_surfaces_state(ctx, obj_surface, flags);
1846 i965_render_sampler(ctx);
1847 i965_render_cc_viewport(ctx);
1848 gen6_render_color_calc_state(ctx);
1849 gen6_render_blend_state(ctx);
1850 gen6_render_depth_stencil_state(ctx);
1851 i965_render_upload_constants(ctx, obj_surface, flags);
1852 i965_render_upload_vertex(ctx, obj_surface, src_rect, dst_rect);
1856 gen6_emit_invarient_states(VADriverContextP ctx)
1858 struct i965_driver_data *i965 = i965_driver_data(ctx);
1859 struct intel_batchbuffer *batch = i965->batch;
1861 OUT_BATCH(batch, CMD_PIPELINE_SELECT | PIPELINE_SELECT_3D);
1863 OUT_BATCH(batch, GEN6_3DSTATE_MULTISAMPLE | (3 - 2));
1864 OUT_BATCH(batch, GEN6_3DSTATE_MULTISAMPLE_PIXEL_LOCATION_CENTER |
1865 GEN6_3DSTATE_MULTISAMPLE_NUMSAMPLES_1); /* 1 sample/pixel */
1866 OUT_BATCH(batch, 0);
1868 OUT_BATCH(batch, GEN6_3DSTATE_SAMPLE_MASK | (2 - 2));
1869 OUT_BATCH(batch, 1);
1871 /* Set system instruction pointer */
1872 OUT_BATCH(batch, CMD_STATE_SIP | 0);
1873 OUT_BATCH(batch, 0);
1877 gen6_emit_state_base_address(VADriverContextP ctx)
1879 struct i965_driver_data *i965 = i965_driver_data(ctx);
1880 struct intel_batchbuffer *batch = i965->batch;
1881 struct i965_render_state *render_state = &i965->render_state;
1883 OUT_BATCH(batch, CMD_STATE_BASE_ADDRESS | (10 - 2));
1884 OUT_BATCH(batch, BASE_ADDRESS_MODIFY); /* General state base address */
1885 OUT_RELOC(batch, render_state->wm.surface_state_binding_table_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, BASE_ADDRESS_MODIFY); /* Surface state base address */
1886 OUT_BATCH(batch, BASE_ADDRESS_MODIFY); /* Dynamic state base address */
1887 OUT_BATCH(batch, BASE_ADDRESS_MODIFY); /* Indirect object base address */
1888 OUT_BATCH(batch, BASE_ADDRESS_MODIFY); /* Instruction base address */
1889 OUT_BATCH(batch, BASE_ADDRESS_MODIFY); /* General state upper bound */
1890 OUT_BATCH(batch, BASE_ADDRESS_MODIFY); /* Dynamic state upper bound */
1891 OUT_BATCH(batch, BASE_ADDRESS_MODIFY); /* Indirect object upper bound */
1892 OUT_BATCH(batch, BASE_ADDRESS_MODIFY); /* Instruction access upper bound */
1896 gen6_emit_viewport_state_pointers(VADriverContextP ctx)
1898 struct i965_driver_data *i965 = i965_driver_data(ctx);
1899 struct intel_batchbuffer *batch = i965->batch;
1900 struct i965_render_state *render_state = &i965->render_state;
1902 OUT_BATCH(batch, GEN6_3DSTATE_VIEWPORT_STATE_POINTERS |
1903 GEN6_3DSTATE_VIEWPORT_STATE_MODIFY_CC |
1905 OUT_BATCH(batch, 0);
1906 OUT_BATCH(batch, 0);
1907 OUT_RELOC(batch, render_state->cc.viewport, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
1911 gen6_emit_urb(VADriverContextP ctx)
1913 struct i965_driver_data *i965 = i965_driver_data(ctx);
1914 struct intel_batchbuffer *batch = i965->batch;
1916 OUT_BATCH(batch, GEN6_3DSTATE_URB | (3 - 2));
1917 OUT_BATCH(batch, ((1 - 1) << GEN6_3DSTATE_URB_VS_SIZE_SHIFT) |
1918 (24 << GEN6_3DSTATE_URB_VS_ENTRIES_SHIFT)); /* at least 24 on GEN6 */
1919 OUT_BATCH(batch, (0 << GEN6_3DSTATE_URB_GS_SIZE_SHIFT) |
1920 (0 << GEN6_3DSTATE_URB_GS_ENTRIES_SHIFT)); /* no GS thread */
1924 gen6_emit_cc_state_pointers(VADriverContextP ctx)
1926 struct i965_driver_data *i965 = i965_driver_data(ctx);
1927 struct intel_batchbuffer *batch = i965->batch;
1928 struct i965_render_state *render_state = &i965->render_state;
1930 OUT_BATCH(batch, GEN6_3DSTATE_CC_STATE_POINTERS | (4 - 2));
1931 OUT_RELOC(batch, render_state->cc.blend, I915_GEM_DOMAIN_INSTRUCTION, 0, 1);
1932 OUT_RELOC(batch, render_state->cc.depth_stencil, I915_GEM_DOMAIN_INSTRUCTION, 0, 1);
1933 OUT_RELOC(batch, render_state->cc.state, I915_GEM_DOMAIN_INSTRUCTION, 0, 1);
1937 gen6_emit_sampler_state_pointers(VADriverContextP ctx)
1939 struct i965_driver_data *i965 = i965_driver_data(ctx);
1940 struct intel_batchbuffer *batch = i965->batch;
1941 struct i965_render_state *render_state = &i965->render_state;
1943 OUT_BATCH(batch, GEN6_3DSTATE_SAMPLER_STATE_POINTERS |
1944 GEN6_3DSTATE_SAMPLER_STATE_MODIFY_PS |
1946 OUT_BATCH(batch, 0); /* VS */
1947 OUT_BATCH(batch, 0); /* GS */
1948 OUT_RELOC(batch,render_state->wm.sampler, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
1952 gen6_emit_binding_table(VADriverContextP ctx)
1954 struct i965_driver_data *i965 = i965_driver_data(ctx);
1955 struct intel_batchbuffer *batch = i965->batch;
1957 /* Binding table pointers */
1958 OUT_BATCH(batch, CMD_BINDING_TABLE_POINTERS |
1959 GEN6_BINDING_TABLE_MODIFY_PS |
1961 OUT_BATCH(batch, 0); /* vs */
1962 OUT_BATCH(batch, 0); /* gs */
1963 /* Only the PS uses the binding table */
1964 OUT_BATCH(batch, BINDING_TABLE_OFFSET);
1968 gen6_emit_depth_buffer_state(VADriverContextP ctx)
1970 struct i965_driver_data *i965 = i965_driver_data(ctx);
1971 struct intel_batchbuffer *batch = i965->batch;
1973 OUT_BATCH(batch, CMD_DEPTH_BUFFER | (7 - 2));
1974 OUT_BATCH(batch, (I965_SURFACE_NULL << CMD_DEPTH_BUFFER_TYPE_SHIFT) |
1975 (I965_DEPTHFORMAT_D32_FLOAT << CMD_DEPTH_BUFFER_FORMAT_SHIFT));
1976 OUT_BATCH(batch, 0);
1977 OUT_BATCH(batch, 0);
1978 OUT_BATCH(batch, 0);
1979 OUT_BATCH(batch, 0);
1980 OUT_BATCH(batch, 0);
1982 OUT_BATCH(batch, CMD_CLEAR_PARAMS | (2 - 2));
1983 OUT_BATCH(batch, 0);
1987 gen6_emit_drawing_rectangle(VADriverContextP ctx)
1989 i965_render_drawing_rectangle(ctx);
1993 gen6_emit_vs_state(VADriverContextP ctx)
1995 struct i965_driver_data *i965 = i965_driver_data(ctx);
1996 struct intel_batchbuffer *batch = i965->batch;
1998 /* disable VS constant buffer */
1999 OUT_BATCH(batch, GEN6_3DSTATE_CONSTANT_VS | (5 - 2));
2000 OUT_BATCH(batch, 0);
2001 OUT_BATCH(batch, 0);
2002 OUT_BATCH(batch, 0);
2003 OUT_BATCH(batch, 0);
2005 OUT_BATCH(batch, GEN6_3DSTATE_VS | (6 - 2));
2006 OUT_BATCH(batch, 0); /* without VS kernel */
2007 OUT_BATCH(batch, 0);
2008 OUT_BATCH(batch, 0);
2009 OUT_BATCH(batch, 0);
2010 OUT_BATCH(batch, 0); /* pass-through */
2014 gen6_emit_gs_state(VADriverContextP ctx)
2016 struct i965_driver_data *i965 = i965_driver_data(ctx);
2017 struct intel_batchbuffer *batch = i965->batch;
2019 /* disable GS constant buffer */
2020 OUT_BATCH(batch, GEN6_3DSTATE_CONSTANT_GS | (5 - 2));
2021 OUT_BATCH(batch, 0);
2022 OUT_BATCH(batch, 0);
2023 OUT_BATCH(batch, 0);
2024 OUT_BATCH(batch, 0);
2026 OUT_BATCH(batch, GEN6_3DSTATE_GS | (7 - 2));
2027 OUT_BATCH(batch, 0); /* without GS kernel */
2028 OUT_BATCH(batch, 0);
2029 OUT_BATCH(batch, 0);
2030 OUT_BATCH(batch, 0);
2031 OUT_BATCH(batch, 0);
2032 OUT_BATCH(batch, 0); /* pass-through */
2036 gen6_emit_clip_state(VADriverContextP ctx)
2038 struct i965_driver_data *i965 = i965_driver_data(ctx);
2039 struct intel_batchbuffer *batch = i965->batch;
2041 OUT_BATCH(batch, GEN6_3DSTATE_CLIP | (4 - 2));
2042 OUT_BATCH(batch, 0);
2043 OUT_BATCH(batch, 0); /* pass-through */
2044 OUT_BATCH(batch, 0);
2048 gen6_emit_sf_state(VADriverContextP ctx)
2050 struct i965_driver_data *i965 = i965_driver_data(ctx);
2051 struct intel_batchbuffer *batch = i965->batch;
2053 OUT_BATCH(batch, GEN6_3DSTATE_SF | (20 - 2));
2054 OUT_BATCH(batch, (1 << GEN6_3DSTATE_SF_NUM_OUTPUTS_SHIFT) |
2055 (1 << GEN6_3DSTATE_SF_URB_ENTRY_READ_LENGTH_SHIFT) |
2056 (0 << GEN6_3DSTATE_SF_URB_ENTRY_READ_OFFSET_SHIFT));
2057 OUT_BATCH(batch, 0);
2058 OUT_BATCH(batch, GEN6_3DSTATE_SF_CULL_NONE);
2059 OUT_BATCH(batch, 2 << GEN6_3DSTATE_SF_TRIFAN_PROVOKE_SHIFT); /* DW4 */
2060 OUT_BATCH(batch, 0);
2061 OUT_BATCH(batch, 0);
2062 OUT_BATCH(batch, 0);
2063 OUT_BATCH(batch, 0);
2064 OUT_BATCH(batch, 0); /* DW9 */
2065 OUT_BATCH(batch, 0);
2066 OUT_BATCH(batch, 0);
2067 OUT_BATCH(batch, 0);
2068 OUT_BATCH(batch, 0);
2069 OUT_BATCH(batch, 0); /* DW14 */
2070 OUT_BATCH(batch, 0);
2071 OUT_BATCH(batch, 0);
2072 OUT_BATCH(batch, 0);
2073 OUT_BATCH(batch, 0);
2074 OUT_BATCH(batch, 0); /* DW19 */
2078 gen6_emit_wm_state(VADriverContextP ctx, int kernel)
2080 struct i965_driver_data *i965 = i965_driver_data(ctx);
2081 struct intel_batchbuffer *batch = i965->batch;
2082 struct i965_render_state *render_state = &i965->render_state;
2084 OUT_BATCH(batch, GEN6_3DSTATE_CONSTANT_PS |
2085 GEN6_3DSTATE_CONSTANT_BUFFER_0_ENABLE |
2088 render_state->curbe.bo,
2089 I915_GEM_DOMAIN_INSTRUCTION, 0,
2090 (URB_CS_ENTRY_SIZE-1));
2091 OUT_BATCH(batch, 0);
2092 OUT_BATCH(batch, 0);
2093 OUT_BATCH(batch, 0);
2095 OUT_BATCH(batch, GEN6_3DSTATE_WM | (9 - 2));
2096 OUT_RELOC(batch, render_state->render_kernels[kernel].bo,
2097 I915_GEM_DOMAIN_INSTRUCTION, 0,
2099 OUT_BATCH(batch, (1 << GEN6_3DSTATE_WM_SAMPLER_COUNT_SHITF) |
2100 (5 << GEN6_3DSTATE_WM_BINDING_TABLE_ENTRY_COUNT_SHIFT));
2101 OUT_BATCH(batch, 0);
2102 OUT_BATCH(batch, (6 << GEN6_3DSTATE_WM_DISPATCH_START_GRF_0_SHIFT)); /* DW4 */
2103 OUT_BATCH(batch, ((i965->intel.device_info->max_wm_threads - 1) << GEN6_3DSTATE_WM_MAX_THREADS_SHIFT) |
2104 GEN6_3DSTATE_WM_DISPATCH_ENABLE |
2105 GEN6_3DSTATE_WM_16_DISPATCH_ENABLE);
2106 OUT_BATCH(batch, (1 << GEN6_3DSTATE_WM_NUM_SF_OUTPUTS_SHIFT) |
2107 GEN6_3DSTATE_WM_PERSPECTIVE_PIXEL_BARYCENTRIC);
2108 OUT_BATCH(batch, 0);
2109 OUT_BATCH(batch, 0);
2113 gen6_emit_vertex_element_state(VADriverContextP ctx)
2115 struct i965_driver_data *i965 = i965_driver_data(ctx);
2116 struct intel_batchbuffer *batch = i965->batch;
2118 /* Set up our vertex elements, sourced from the single vertex buffer. */
2119 OUT_BATCH(batch, CMD_VERTEX_ELEMENTS | (5 - 2));
2120 /* offset 0: X,Y -> {X, Y, 1.0, 1.0} */
2121 OUT_BATCH(batch, (0 << GEN6_VE0_VERTEX_BUFFER_INDEX_SHIFT) |
2123 (I965_SURFACEFORMAT_R32G32_FLOAT << VE0_FORMAT_SHIFT) |
2124 (0 << VE0_OFFSET_SHIFT));
2125 OUT_BATCH(batch, (I965_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT) |
2126 (I965_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT) |
2127 (I965_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_2_SHIFT) |
2128 (I965_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT));
2129 /* offset 8: S0, T0 -> {S0, T0, 1.0, 1.0} */
2130 OUT_BATCH(batch, (0 << GEN6_VE0_VERTEX_BUFFER_INDEX_SHIFT) |
2132 (I965_SURFACEFORMAT_R32G32_FLOAT << VE0_FORMAT_SHIFT) |
2133 (8 << VE0_OFFSET_SHIFT));
2134 OUT_BATCH(batch, (I965_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT) |
2135 (I965_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT) |
2136 (I965_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_2_SHIFT) |
2137 (I965_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT));
2141 gen6_emit_vertices(VADriverContextP ctx)
2143 struct i965_driver_data *i965 = i965_driver_data(ctx);
2144 struct intel_batchbuffer *batch = i965->batch;
2145 struct i965_render_state *render_state = &i965->render_state;
2147 BEGIN_BATCH(batch, 11);
2148 OUT_BATCH(batch, CMD_VERTEX_BUFFERS | 3);
2150 (0 << GEN6_VB0_BUFFER_INDEX_SHIFT) |
2151 GEN6_VB0_VERTEXDATA |
2152 ((4 * 4) << VB0_BUFFER_PITCH_SHIFT));
2153 OUT_RELOC(batch, render_state->vb.vertex_buffer, I915_GEM_DOMAIN_VERTEX, 0, 0);
2154 OUT_RELOC(batch, render_state->vb.vertex_buffer, I915_GEM_DOMAIN_VERTEX, 0, 12 * 4);
2155 OUT_BATCH(batch, 0);
2159 _3DPRIMITIVE_VERTEX_SEQUENTIAL |
2160 (_3DPRIM_RECTLIST << _3DPRIMITIVE_TOPOLOGY_SHIFT) |
2163 OUT_BATCH(batch, 3); /* vertex count per instance */
2164 OUT_BATCH(batch, 0); /* start vertex offset */
2165 OUT_BATCH(batch, 1); /* single instance */
2166 OUT_BATCH(batch, 0); /* start instance location */
2167 OUT_BATCH(batch, 0); /* index buffer offset, ignored */
2168 ADVANCE_BATCH(batch);
2172 gen6_render_emit_states(VADriverContextP ctx, int kernel)
2174 struct i965_driver_data *i965 = i965_driver_data(ctx);
2175 struct intel_batchbuffer *batch = i965->batch;
2177 intel_batchbuffer_start_atomic(batch, 0x1000);
2178 intel_batchbuffer_emit_mi_flush(batch);
2179 gen6_emit_invarient_states(ctx);
2180 gen6_emit_state_base_address(ctx);
2181 gen6_emit_viewport_state_pointers(ctx);
2183 gen6_emit_cc_state_pointers(ctx);
2184 gen6_emit_sampler_state_pointers(ctx);
2185 gen6_emit_vs_state(ctx);
2186 gen6_emit_gs_state(ctx);
2187 gen6_emit_clip_state(ctx);
2188 gen6_emit_sf_state(ctx);
2189 gen6_emit_wm_state(ctx, kernel);
2190 gen6_emit_binding_table(ctx);
2191 gen6_emit_depth_buffer_state(ctx);
2192 gen6_emit_drawing_rectangle(ctx);
2193 gen6_emit_vertex_element_state(ctx);
2194 gen6_emit_vertices(ctx);
2195 intel_batchbuffer_end_atomic(batch);
2199 gen6_render_put_surface(
2200 VADriverContextP ctx,
2201 struct object_surface *obj_surface,
2202 const VARectangle *src_rect,
2203 const VARectangle *dst_rect,
2207 struct i965_driver_data *i965 = i965_driver_data(ctx);
2208 struct intel_batchbuffer *batch = i965->batch;
2210 gen6_render_initialize(ctx);
2211 gen6_render_setup_states(ctx, obj_surface, src_rect, dst_rect, flags);
2212 i965_clear_dest_region(ctx);
2213 gen6_render_emit_states(ctx, PS_KERNEL);
2214 intel_batchbuffer_flush(batch);
2218 gen6_subpicture_render_blend_state(VADriverContextP ctx)
2220 struct i965_driver_data *i965 = i965_driver_data(ctx);
2221 struct i965_render_state *render_state = &i965->render_state;
2222 struct gen6_blend_state *blend_state;
2224 dri_bo_unmap(render_state->cc.state);
2225 dri_bo_map(render_state->cc.blend, 1);
2226 assert(render_state->cc.blend->virtual);
2227 blend_state = render_state->cc.blend->virtual;
2228 memset(blend_state, 0, sizeof(*blend_state));
2229 blend_state->blend0.dest_blend_factor = I965_BLENDFACTOR_INV_SRC_ALPHA;
2230 blend_state->blend0.source_blend_factor = I965_BLENDFACTOR_SRC_ALPHA;
2231 blend_state->blend0.blend_func = I965_BLENDFUNCTION_ADD;
2232 blend_state->blend0.blend_enable = 1;
2233 blend_state->blend1.post_blend_clamp_enable = 1;
2234 blend_state->blend1.pre_blend_clamp_enable = 1;
2235 blend_state->blend1.clamp_range = 0; /* clamp range [0, 1] */
2236 dri_bo_unmap(render_state->cc.blend);
2240 gen6_subpicture_render_setup_states(
2241 VADriverContextP ctx,
2242 struct object_surface *obj_surface,
2243 const VARectangle *src_rect,
2244 const VARectangle *dst_rect
2247 i965_render_dest_surface_state(ctx, 0);
2248 i965_subpic_render_src_surfaces_state(ctx, obj_surface);
2249 i965_render_sampler(ctx);
2250 i965_render_cc_viewport(ctx);
2251 gen6_render_color_calc_state(ctx);
2252 gen6_subpicture_render_blend_state(ctx);
2253 gen6_render_depth_stencil_state(ctx);
2254 i965_subpic_render_upload_constants(ctx, obj_surface);
2255 i965_subpic_render_upload_vertex(ctx, obj_surface, dst_rect);
2259 gen6_render_put_subpicture(
2260 VADriverContextP ctx,
2261 struct object_surface *obj_surface,
2262 const VARectangle *src_rect,
2263 const VARectangle *dst_rect
2266 struct i965_driver_data *i965 = i965_driver_data(ctx);
2267 struct intel_batchbuffer *batch = i965->batch;
2268 unsigned int index = obj_surface->subpic_render_idx;
2269 struct object_subpic *obj_subpic = obj_surface->obj_subpic[index];
2272 gen6_render_initialize(ctx);
2273 gen6_subpicture_render_setup_states(ctx, obj_surface, src_rect, dst_rect);
2274 gen6_render_emit_states(ctx, PS_SUBPIC_KERNEL);
2275 i965_render_upload_image_palette(ctx, obj_subpic->obj_image, 0xff);
2276 intel_batchbuffer_flush(batch);
2283 gen7_render_initialize(VADriverContextP ctx)
2285 struct i965_driver_data *i965 = i965_driver_data(ctx);
2286 struct i965_render_state *render_state = &i965->render_state;
2290 dri_bo_unreference(render_state->vb.vertex_buffer);
2291 bo = dri_bo_alloc(i965->intel.bufmgr,
2296 render_state->vb.vertex_buffer = bo;
2299 dri_bo_unreference(render_state->wm.surface_state_binding_table_bo);
2300 bo = dri_bo_alloc(i965->intel.bufmgr,
2301 "surface state & binding table",
2302 (SURFACE_STATE_PADDED_SIZE + sizeof(unsigned int)) * MAX_RENDER_SURFACES,
2305 render_state->wm.surface_state_binding_table_bo = bo;
2307 dri_bo_unreference(render_state->wm.sampler);
2308 bo = dri_bo_alloc(i965->intel.bufmgr,
2310 MAX_SAMPLERS * sizeof(struct gen7_sampler_state),
2313 render_state->wm.sampler = bo;
2314 render_state->wm.sampler_count = 0;
2316 /* COLOR CALCULATOR */
2317 dri_bo_unreference(render_state->cc.state);
2318 bo = dri_bo_alloc(i965->intel.bufmgr,
2320 sizeof(struct gen6_color_calc_state),
2323 render_state->cc.state = bo;
2326 dri_bo_unreference(render_state->cc.viewport);
2327 bo = dri_bo_alloc(i965->intel.bufmgr,
2329 sizeof(struct i965_cc_viewport),
2332 render_state->cc.viewport = bo;
2335 dri_bo_unreference(render_state->cc.blend);
2336 bo = dri_bo_alloc(i965->intel.bufmgr,
2338 sizeof(struct gen6_blend_state),
2341 render_state->cc.blend = bo;
2343 /* DEPTH & STENCIL STATE */
2344 dri_bo_unreference(render_state->cc.depth_stencil);
2345 bo = dri_bo_alloc(i965->intel.bufmgr,
2346 "depth & stencil state",
2347 sizeof(struct gen6_depth_stencil_state),
2350 render_state->cc.depth_stencil = bo;
2356 #define ALIGNMENT 64
2359 gen7_render_color_calc_state(VADriverContextP ctx)
2361 struct i965_driver_data *i965 = i965_driver_data(ctx);
2362 struct i965_render_state *render_state = &i965->render_state;
2363 struct gen6_color_calc_state *color_calc_state;
2365 dri_bo_map(render_state->cc.state, 1);
2366 assert(render_state->cc.state->virtual);
2367 color_calc_state = render_state->cc.state->virtual;
2368 memset(color_calc_state, 0, sizeof(*color_calc_state));
2369 color_calc_state->constant_r = 1.0;
2370 color_calc_state->constant_g = 0.0;
2371 color_calc_state->constant_b = 1.0;
2372 color_calc_state->constant_a = 1.0;
2373 dri_bo_unmap(render_state->cc.state);
2377 gen7_render_blend_state(VADriverContextP ctx)
2379 struct i965_driver_data *i965 = i965_driver_data(ctx);
2380 struct i965_render_state *render_state = &i965->render_state;
2381 struct gen6_blend_state *blend_state;
2383 dri_bo_map(render_state->cc.blend, 1);
2384 assert(render_state->cc.blend->virtual);
2385 blend_state = render_state->cc.blend->virtual;
2386 memset(blend_state, 0, sizeof(*blend_state));
2387 blend_state->blend1.logic_op_enable = 1;
2388 blend_state->blend1.logic_op_func = 0xc;
2389 blend_state->blend1.pre_blend_clamp_enable = 1;
2390 dri_bo_unmap(render_state->cc.blend);
2394 gen7_render_depth_stencil_state(VADriverContextP ctx)
2396 struct i965_driver_data *i965 = i965_driver_data(ctx);
2397 struct i965_render_state *render_state = &i965->render_state;
2398 struct gen6_depth_stencil_state *depth_stencil_state;
2400 dri_bo_map(render_state->cc.depth_stencil, 1);
2401 assert(render_state->cc.depth_stencil->virtual);
2402 depth_stencil_state = render_state->cc.depth_stencil->virtual;
2403 memset(depth_stencil_state, 0, sizeof(*depth_stencil_state));
2404 dri_bo_unmap(render_state->cc.depth_stencil);
2408 gen7_render_sampler(VADriverContextP ctx)
2410 struct i965_driver_data *i965 = i965_driver_data(ctx);
2411 struct i965_render_state *render_state = &i965->render_state;
2412 struct gen7_sampler_state *sampler_state;
2415 assert(render_state->wm.sampler_count > 0);
2416 assert(render_state->wm.sampler_count <= MAX_SAMPLERS);
2418 dri_bo_map(render_state->wm.sampler, 1);
2419 assert(render_state->wm.sampler->virtual);
2420 sampler_state = render_state->wm.sampler->virtual;
2421 for (i = 0; i < render_state->wm.sampler_count; i++) {
2422 memset(sampler_state, 0, sizeof(*sampler_state));
2423 sampler_state->ss0.min_filter = I965_MAPFILTER_LINEAR;
2424 sampler_state->ss0.mag_filter = I965_MAPFILTER_LINEAR;
2425 sampler_state->ss3.r_wrap_mode = I965_TEXCOORDMODE_CLAMP;
2426 sampler_state->ss3.s_wrap_mode = I965_TEXCOORDMODE_CLAMP;
2427 sampler_state->ss3.t_wrap_mode = I965_TEXCOORDMODE_CLAMP;
2431 dri_bo_unmap(render_state->wm.sampler);
2436 gen7_render_setup_states(
2437 VADriverContextP ctx,
2438 struct object_surface *obj_surface,
2439 const VARectangle *src_rect,
2440 const VARectangle *dst_rect,
2444 i965_render_dest_surface_state(ctx, 0);
2445 i965_render_src_surfaces_state(ctx, obj_surface, flags);
2446 gen7_render_sampler(ctx);
2447 i965_render_cc_viewport(ctx);
2448 gen7_render_color_calc_state(ctx);
2449 gen7_render_blend_state(ctx);
2450 gen7_render_depth_stencil_state(ctx);
2451 i965_render_upload_constants(ctx, obj_surface, flags);
2452 i965_render_upload_vertex(ctx, obj_surface, src_rect, dst_rect);
2457 gen7_emit_invarient_states(VADriverContextP ctx)
2459 struct i965_driver_data *i965 = i965_driver_data(ctx);
2460 struct intel_batchbuffer *batch = i965->batch;
2462 BEGIN_BATCH(batch, 1);
2463 OUT_BATCH(batch, CMD_PIPELINE_SELECT | PIPELINE_SELECT_3D);
2464 ADVANCE_BATCH(batch);
2466 BEGIN_BATCH(batch, 4);
2467 OUT_BATCH(batch, GEN6_3DSTATE_MULTISAMPLE | (4 - 2));
2468 OUT_BATCH(batch, GEN6_3DSTATE_MULTISAMPLE_PIXEL_LOCATION_CENTER |
2469 GEN6_3DSTATE_MULTISAMPLE_NUMSAMPLES_1); /* 1 sample/pixel */
2470 OUT_BATCH(batch, 0);
2471 OUT_BATCH(batch, 0);
2472 ADVANCE_BATCH(batch);
2474 BEGIN_BATCH(batch, 2);
2475 OUT_BATCH(batch, GEN6_3DSTATE_SAMPLE_MASK | (2 - 2));
2476 OUT_BATCH(batch, 1);
2477 ADVANCE_BATCH(batch);
2479 /* Set system instruction pointer */
2480 BEGIN_BATCH(batch, 2);
2481 OUT_BATCH(batch, CMD_STATE_SIP | 0);
2482 OUT_BATCH(batch, 0);
2483 ADVANCE_BATCH(batch);
2487 gen7_emit_state_base_address(VADriverContextP ctx)
2489 struct i965_driver_data *i965 = i965_driver_data(ctx);
2490 struct intel_batchbuffer *batch = i965->batch;
2491 struct i965_render_state *render_state = &i965->render_state;
2493 OUT_BATCH(batch, CMD_STATE_BASE_ADDRESS | (10 - 2));
2494 OUT_BATCH(batch, BASE_ADDRESS_MODIFY); /* General state base address */
2495 OUT_RELOC(batch, render_state->wm.surface_state_binding_table_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, BASE_ADDRESS_MODIFY); /* Surface state base address */
2496 OUT_BATCH(batch, BASE_ADDRESS_MODIFY); /* Dynamic state base address */
2497 OUT_BATCH(batch, BASE_ADDRESS_MODIFY); /* Indirect object base address */
2498 OUT_BATCH(batch, BASE_ADDRESS_MODIFY); /* Instruction base address */
2499 OUT_BATCH(batch, BASE_ADDRESS_MODIFY); /* General state upper bound */
2500 OUT_BATCH(batch, BASE_ADDRESS_MODIFY); /* Dynamic state upper bound */
2501 OUT_BATCH(batch, BASE_ADDRESS_MODIFY); /* Indirect object upper bound */
2502 OUT_BATCH(batch, BASE_ADDRESS_MODIFY); /* Instruction access upper bound */
2506 gen7_emit_viewport_state_pointers(VADriverContextP ctx)
2508 struct i965_driver_data *i965 = i965_driver_data(ctx);
2509 struct intel_batchbuffer *batch = i965->batch;
2510 struct i965_render_state *render_state = &i965->render_state;
2512 BEGIN_BATCH(batch, 2);
2513 OUT_BATCH(batch, GEN7_3DSTATE_VIEWPORT_STATE_POINTERS_CC | (2 - 2));
2515 render_state->cc.viewport,
2516 I915_GEM_DOMAIN_INSTRUCTION, 0,
2518 ADVANCE_BATCH(batch);
2520 BEGIN_BATCH(batch, 2);
2521 OUT_BATCH(batch, GEN7_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CL | (2 - 2));
2522 OUT_BATCH(batch, 0);
2523 ADVANCE_BATCH(batch);
2527 * URB layout on GEN7
2528 * ----------------------------------------
2529 * | PS Push Constants (8KB) | VS entries |
2530 * ----------------------------------------
2533 gen7_emit_urb(VADriverContextP ctx)
2535 struct i965_driver_data *i965 = i965_driver_data(ctx);
2536 struct intel_batchbuffer *batch = i965->batch;
2537 unsigned int num_urb_entries = 32;
2539 if (IS_HASWELL(i965->intel.device_info))
2540 num_urb_entries = 64;
2542 BEGIN_BATCH(batch, 2);
2543 OUT_BATCH(batch, GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_PS | (2 - 2));
2544 OUT_BATCH(batch, 8); /* in 1KBs */
2545 ADVANCE_BATCH(batch);
2547 BEGIN_BATCH(batch, 2);
2548 OUT_BATCH(batch, GEN7_3DSTATE_URB_VS | (2 - 2));
2550 (num_urb_entries << GEN7_URB_ENTRY_NUMBER_SHIFT) |
2551 (2 - 1) << GEN7_URB_ENTRY_SIZE_SHIFT |
2552 (1 << GEN7_URB_STARTING_ADDRESS_SHIFT));
2553 ADVANCE_BATCH(batch);
2555 BEGIN_BATCH(batch, 2);
2556 OUT_BATCH(batch, GEN7_3DSTATE_URB_GS | (2 - 2));
2558 (0 << GEN7_URB_ENTRY_SIZE_SHIFT) |
2559 (1 << GEN7_URB_STARTING_ADDRESS_SHIFT));
2560 ADVANCE_BATCH(batch);
2562 BEGIN_BATCH(batch, 2);
2563 OUT_BATCH(batch, GEN7_3DSTATE_URB_HS | (2 - 2));
2565 (0 << GEN7_URB_ENTRY_SIZE_SHIFT) |
2566 (2 << GEN7_URB_STARTING_ADDRESS_SHIFT));
2567 ADVANCE_BATCH(batch);
2569 BEGIN_BATCH(batch, 2);
2570 OUT_BATCH(batch, GEN7_3DSTATE_URB_DS | (2 - 2));
2572 (0 << GEN7_URB_ENTRY_SIZE_SHIFT) |
2573 (2 << GEN7_URB_STARTING_ADDRESS_SHIFT));
2574 ADVANCE_BATCH(batch);
2578 gen7_emit_cc_state_pointers(VADriverContextP ctx)
2580 struct i965_driver_data *i965 = i965_driver_data(ctx);
2581 struct intel_batchbuffer *batch = i965->batch;
2582 struct i965_render_state *render_state = &i965->render_state;
2584 BEGIN_BATCH(batch, 2);
2585 OUT_BATCH(batch, GEN6_3DSTATE_CC_STATE_POINTERS | (2 - 2));
2587 render_state->cc.state,
2588 I915_GEM_DOMAIN_INSTRUCTION, 0,
2590 ADVANCE_BATCH(batch);
2592 BEGIN_BATCH(batch, 2);
2593 OUT_BATCH(batch, GEN7_3DSTATE_BLEND_STATE_POINTERS | (2 - 2));
2595 render_state->cc.blend,
2596 I915_GEM_DOMAIN_INSTRUCTION, 0,
2598 ADVANCE_BATCH(batch);
2600 BEGIN_BATCH(batch, 2);
2601 OUT_BATCH(batch, GEN7_3DSTATE_DEPTH_STENCIL_STATE_POINTERS | (2 - 2));
2603 render_state->cc.depth_stencil,
2604 I915_GEM_DOMAIN_INSTRUCTION, 0,
2606 ADVANCE_BATCH(batch);
2610 gen7_emit_sampler_state_pointers(VADriverContextP ctx)
2612 struct i965_driver_data *i965 = i965_driver_data(ctx);
2613 struct intel_batchbuffer *batch = i965->batch;
2614 struct i965_render_state *render_state = &i965->render_state;
2616 BEGIN_BATCH(batch, 2);
2617 OUT_BATCH(batch, GEN7_3DSTATE_SAMPLER_STATE_POINTERS_PS | (2 - 2));
2619 render_state->wm.sampler,
2620 I915_GEM_DOMAIN_INSTRUCTION, 0,
2622 ADVANCE_BATCH(batch);
2626 gen7_emit_binding_table(VADriverContextP ctx)
2628 struct i965_driver_data *i965 = i965_driver_data(ctx);
2629 struct intel_batchbuffer *batch = i965->batch;
2631 BEGIN_BATCH(batch, 2);
2632 OUT_BATCH(batch, GEN7_3DSTATE_BINDING_TABLE_POINTERS_PS | (2 - 2));
2633 OUT_BATCH(batch, BINDING_TABLE_OFFSET);
2634 ADVANCE_BATCH(batch);
2638 gen7_emit_depth_buffer_state(VADriverContextP ctx)
2640 struct i965_driver_data *i965 = i965_driver_data(ctx);
2641 struct intel_batchbuffer *batch = i965->batch;
2643 BEGIN_BATCH(batch, 7);
2644 OUT_BATCH(batch, GEN7_3DSTATE_DEPTH_BUFFER | (7 - 2));
2646 (I965_DEPTHFORMAT_D32_FLOAT << 18) |
2647 (I965_SURFACE_NULL << 29));
2648 OUT_BATCH(batch, 0);
2649 OUT_BATCH(batch, 0);
2650 OUT_BATCH(batch, 0);
2651 OUT_BATCH(batch, 0);
2652 OUT_BATCH(batch, 0);
2653 ADVANCE_BATCH(batch);
2655 BEGIN_BATCH(batch, 3);
2656 OUT_BATCH(batch, GEN7_3DSTATE_CLEAR_PARAMS | (3 - 2));
2657 OUT_BATCH(batch, 0);
2658 OUT_BATCH(batch, 0);
2659 ADVANCE_BATCH(batch);
2663 gen7_emit_drawing_rectangle(VADriverContextP ctx)
2665 i965_render_drawing_rectangle(ctx);
2669 gen7_emit_vs_state(VADriverContextP ctx)
2671 struct i965_driver_data *i965 = i965_driver_data(ctx);
2672 struct intel_batchbuffer *batch = i965->batch;
2674 /* disable VS constant buffer */
2675 OUT_BATCH(batch, GEN6_3DSTATE_CONSTANT_VS | (7 - 2));
2676 OUT_BATCH(batch, 0);
2677 OUT_BATCH(batch, 0);
2678 OUT_BATCH(batch, 0);
2679 OUT_BATCH(batch, 0);
2680 OUT_BATCH(batch, 0);
2681 OUT_BATCH(batch, 0);
2683 OUT_BATCH(batch, GEN6_3DSTATE_VS | (6 - 2));
2684 OUT_BATCH(batch, 0); /* without VS kernel */
2685 OUT_BATCH(batch, 0);
2686 OUT_BATCH(batch, 0);
2687 OUT_BATCH(batch, 0);
2688 OUT_BATCH(batch, 0); /* pass-through */
2692 gen7_emit_bypass_state(VADriverContextP ctx)
2694 struct i965_driver_data *i965 = i965_driver_data(ctx);
2695 struct intel_batchbuffer *batch = i965->batch;
2698 BEGIN_BATCH(batch, 7);
2699 OUT_BATCH(batch, GEN6_3DSTATE_CONSTANT_GS | (7 - 2));
2700 OUT_BATCH(batch, 0);
2701 OUT_BATCH(batch, 0);
2702 OUT_BATCH(batch, 0);
2703 OUT_BATCH(batch, 0);
2704 OUT_BATCH(batch, 0);
2705 OUT_BATCH(batch, 0);
2706 ADVANCE_BATCH(batch);
2708 BEGIN_BATCH(batch, 7);
2709 OUT_BATCH(batch, GEN6_3DSTATE_GS | (7 - 2));
2710 OUT_BATCH(batch, 0); /* without GS kernel */
2711 OUT_BATCH(batch, 0);
2712 OUT_BATCH(batch, 0);
2713 OUT_BATCH(batch, 0);
2714 OUT_BATCH(batch, 0);
2715 OUT_BATCH(batch, 0); /* pass-through */
2716 ADVANCE_BATCH(batch);
2718 BEGIN_BATCH(batch, 2);
2719 OUT_BATCH(batch, GEN7_3DSTATE_BINDING_TABLE_POINTERS_GS | (2 - 2));
2720 OUT_BATCH(batch, 0);
2721 ADVANCE_BATCH(batch);
2724 BEGIN_BATCH(batch, 7);
2725 OUT_BATCH(batch, GEN7_3DSTATE_CONSTANT_HS | (7 - 2));
2726 OUT_BATCH(batch, 0);
2727 OUT_BATCH(batch, 0);
2728 OUT_BATCH(batch, 0);
2729 OUT_BATCH(batch, 0);
2730 OUT_BATCH(batch, 0);
2731 OUT_BATCH(batch, 0);
2732 ADVANCE_BATCH(batch);
2734 BEGIN_BATCH(batch, 7);
2735 OUT_BATCH(batch, GEN7_3DSTATE_HS | (7 - 2));
2736 OUT_BATCH(batch, 0);
2737 OUT_BATCH(batch, 0);
2738 OUT_BATCH(batch, 0);
2739 OUT_BATCH(batch, 0);
2740 OUT_BATCH(batch, 0);
2741 OUT_BATCH(batch, 0);
2742 ADVANCE_BATCH(batch);
2744 BEGIN_BATCH(batch, 2);
2745 OUT_BATCH(batch, GEN7_3DSTATE_BINDING_TABLE_POINTERS_HS | (2 - 2));
2746 OUT_BATCH(batch, 0);
2747 ADVANCE_BATCH(batch);
2750 BEGIN_BATCH(batch, 4);
2751 OUT_BATCH(batch, GEN7_3DSTATE_TE | (4 - 2));
2752 OUT_BATCH(batch, 0);
2753 OUT_BATCH(batch, 0);
2754 OUT_BATCH(batch, 0);
2755 ADVANCE_BATCH(batch);
2758 BEGIN_BATCH(batch, 7);
2759 OUT_BATCH(batch, GEN7_3DSTATE_CONSTANT_DS | (7 - 2));
2760 OUT_BATCH(batch, 0);
2761 OUT_BATCH(batch, 0);
2762 OUT_BATCH(batch, 0);
2763 OUT_BATCH(batch, 0);
2764 OUT_BATCH(batch, 0);
2765 OUT_BATCH(batch, 0);
2766 ADVANCE_BATCH(batch);
2768 BEGIN_BATCH(batch, 6);
2769 OUT_BATCH(batch, GEN7_3DSTATE_DS | (6 - 2));
2770 OUT_BATCH(batch, 0);
2771 OUT_BATCH(batch, 0);
2772 OUT_BATCH(batch, 0);
2773 OUT_BATCH(batch, 0);
2774 OUT_BATCH(batch, 0);
2775 ADVANCE_BATCH(batch);
2777 BEGIN_BATCH(batch, 2);
2778 OUT_BATCH(batch, GEN7_3DSTATE_BINDING_TABLE_POINTERS_DS | (2 - 2));
2779 OUT_BATCH(batch, 0);
2780 ADVANCE_BATCH(batch);
2782 /* Disable STREAMOUT */
2783 BEGIN_BATCH(batch, 3);
2784 OUT_BATCH(batch, GEN7_3DSTATE_STREAMOUT | (3 - 2));
2785 OUT_BATCH(batch, 0);
2786 OUT_BATCH(batch, 0);
2787 ADVANCE_BATCH(batch);
2791 gen7_emit_clip_state(VADriverContextP ctx)
2793 struct i965_driver_data *i965 = i965_driver_data(ctx);
2794 struct intel_batchbuffer *batch = i965->batch;
2796 OUT_BATCH(batch, GEN6_3DSTATE_CLIP | (4 - 2));
2797 OUT_BATCH(batch, 0);
2798 OUT_BATCH(batch, 0); /* pass-through */
2799 OUT_BATCH(batch, 0);
2803 gen7_emit_sf_state(VADriverContextP ctx)
2805 struct i965_driver_data *i965 = i965_driver_data(ctx);
2806 struct intel_batchbuffer *batch = i965->batch;
2808 BEGIN_BATCH(batch, 14);
2809 OUT_BATCH(batch, GEN7_3DSTATE_SBE | (14 - 2));
2811 (1 << GEN7_SBE_NUM_OUTPUTS_SHIFT) |
2812 (1 << GEN7_SBE_URB_ENTRY_READ_LENGTH_SHIFT) |
2813 (0 << GEN7_SBE_URB_ENTRY_READ_OFFSET_SHIFT));
2814 OUT_BATCH(batch, 0);
2815 OUT_BATCH(batch, 0);
2816 OUT_BATCH(batch, 0); /* DW4 */
2817 OUT_BATCH(batch, 0);
2818 OUT_BATCH(batch, 0);
2819 OUT_BATCH(batch, 0);
2820 OUT_BATCH(batch, 0);
2821 OUT_BATCH(batch, 0); /* DW9 */
2822 OUT_BATCH(batch, 0);
2823 OUT_BATCH(batch, 0);
2824 OUT_BATCH(batch, 0);
2825 OUT_BATCH(batch, 0);
2826 ADVANCE_BATCH(batch);
2828 BEGIN_BATCH(batch, 7);
2829 OUT_BATCH(batch, GEN6_3DSTATE_SF | (7 - 2));
2830 OUT_BATCH(batch, 0);
2831 OUT_BATCH(batch, GEN6_3DSTATE_SF_CULL_NONE);
2832 OUT_BATCH(batch, 2 << GEN6_3DSTATE_SF_TRIFAN_PROVOKE_SHIFT);
2833 OUT_BATCH(batch, 0);
2834 OUT_BATCH(batch, 0);
2835 OUT_BATCH(batch, 0);
2836 ADVANCE_BATCH(batch);
2840 gen7_emit_wm_state(VADriverContextP ctx, int kernel)
2842 struct i965_driver_data *i965 = i965_driver_data(ctx);
2843 struct intel_batchbuffer *batch = i965->batch;
2844 struct i965_render_state *render_state = &i965->render_state;
2845 unsigned int max_threads_shift = GEN7_PS_MAX_THREADS_SHIFT_IVB;
2846 unsigned int num_samples = 0;
2848 if (IS_HASWELL(i965->intel.device_info)) {
2849 max_threads_shift = GEN7_PS_MAX_THREADS_SHIFT_HSW;
2850 num_samples = 1 << GEN7_PS_SAMPLE_MASK_SHIFT_HSW;
2853 BEGIN_BATCH(batch, 3);
2854 OUT_BATCH(batch, GEN6_3DSTATE_WM | (3 - 2));
2856 GEN7_WM_DISPATCH_ENABLE |
2857 GEN7_WM_PERSPECTIVE_PIXEL_BARYCENTRIC);
2858 OUT_BATCH(batch, 0);
2859 ADVANCE_BATCH(batch);
2861 BEGIN_BATCH(batch, 7);
2862 OUT_BATCH(batch, GEN6_3DSTATE_CONSTANT_PS | (7 - 2));
2863 OUT_BATCH(batch, URB_CS_ENTRY_SIZE);
2864 OUT_BATCH(batch, 0);
2866 render_state->curbe.bo,
2867 I915_GEM_DOMAIN_INSTRUCTION, 0,
2869 OUT_BATCH(batch, 0);
2870 OUT_BATCH(batch, 0);
2871 OUT_BATCH(batch, 0);
2872 ADVANCE_BATCH(batch);
2874 BEGIN_BATCH(batch, 8);
2875 OUT_BATCH(batch, GEN7_3DSTATE_PS | (8 - 2));
2877 render_state->render_kernels[kernel].bo,
2878 I915_GEM_DOMAIN_INSTRUCTION, 0,
2881 (1 << GEN7_PS_SAMPLER_COUNT_SHIFT) |
2882 (5 << GEN7_PS_BINDING_TABLE_ENTRY_COUNT_SHIFT));
2883 OUT_BATCH(batch, 0); /* scratch space base offset */
2885 ((i965->intel.device_info->max_wm_threads - 1) << max_threads_shift) | num_samples |
2886 GEN7_PS_PUSH_CONSTANT_ENABLE |
2887 GEN7_PS_ATTRIBUTE_ENABLE |
2888 GEN7_PS_16_DISPATCH_ENABLE);
2890 (6 << GEN7_PS_DISPATCH_START_GRF_SHIFT_0));
2891 OUT_BATCH(batch, 0); /* kernel 1 pointer */
2892 OUT_BATCH(batch, 0); /* kernel 2 pointer */
2893 ADVANCE_BATCH(batch);
2897 gen7_emit_vertex_element_state(VADriverContextP ctx)
2899 struct i965_driver_data *i965 = i965_driver_data(ctx);
2900 struct intel_batchbuffer *batch = i965->batch;
2902 /* Set up our vertex elements, sourced from the single vertex buffer. */
2903 OUT_BATCH(batch, CMD_VERTEX_ELEMENTS | (5 - 2));
2904 /* offset 0: X,Y -> {X, Y, 1.0, 1.0} */
2905 OUT_BATCH(batch, (0 << GEN6_VE0_VERTEX_BUFFER_INDEX_SHIFT) |
2907 (I965_SURFACEFORMAT_R32G32_FLOAT << VE0_FORMAT_SHIFT) |
2908 (0 << VE0_OFFSET_SHIFT));
2909 OUT_BATCH(batch, (I965_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT) |
2910 (I965_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT) |
2911 (I965_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_2_SHIFT) |
2912 (I965_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT));
2913 /* offset 8: S0, T0 -> {S0, T0, 1.0, 1.0} */
2914 OUT_BATCH(batch, (0 << GEN6_VE0_VERTEX_BUFFER_INDEX_SHIFT) |
2916 (I965_SURFACEFORMAT_R32G32_FLOAT << VE0_FORMAT_SHIFT) |
2917 (8 << VE0_OFFSET_SHIFT));
2918 OUT_BATCH(batch, (I965_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT) |
2919 (I965_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT) |
2920 (I965_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_2_SHIFT) |
2921 (I965_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT));
2925 gen7_emit_vertices(VADriverContextP ctx)
2927 struct i965_driver_data *i965 = i965_driver_data(ctx);
2928 struct intel_batchbuffer *batch = i965->batch;
2929 struct i965_render_state *render_state = &i965->render_state;
2931 BEGIN_BATCH(batch, 5);
2932 OUT_BATCH(batch, CMD_VERTEX_BUFFERS | (5 - 2));
2934 (0 << GEN6_VB0_BUFFER_INDEX_SHIFT) |
2935 GEN6_VB0_VERTEXDATA |
2936 GEN7_VB0_ADDRESS_MODIFYENABLE |
2937 ((4 * 4) << VB0_BUFFER_PITCH_SHIFT));
2938 OUT_RELOC(batch, render_state->vb.vertex_buffer, I915_GEM_DOMAIN_VERTEX, 0, 0);
2939 OUT_RELOC(batch, render_state->vb.vertex_buffer, I915_GEM_DOMAIN_VERTEX, 0, 12 * 4);
2940 OUT_BATCH(batch, 0);
2941 ADVANCE_BATCH(batch);
2943 BEGIN_BATCH(batch, 7);
2944 OUT_BATCH(batch, CMD_3DPRIMITIVE | (7 - 2));
2947 GEN7_3DPRIM_VERTEXBUFFER_ACCESS_SEQUENTIAL);
2948 OUT_BATCH(batch, 3); /* vertex count per instance */
2949 OUT_BATCH(batch, 0); /* start vertex offset */
2950 OUT_BATCH(batch, 1); /* single instance */
2951 OUT_BATCH(batch, 0); /* start instance location */
2952 OUT_BATCH(batch, 0);
2953 ADVANCE_BATCH(batch);
2957 gen7_render_emit_states(VADriverContextP ctx, int kernel)
2959 struct i965_driver_data *i965 = i965_driver_data(ctx);
2960 struct intel_batchbuffer *batch = i965->batch;
2962 intel_batchbuffer_start_atomic(batch, 0x1000);
2963 intel_batchbuffer_emit_mi_flush(batch);
2964 gen7_emit_invarient_states(ctx);
2965 gen7_emit_state_base_address(ctx);
2966 gen7_emit_viewport_state_pointers(ctx);
2968 gen7_emit_cc_state_pointers(ctx);
2969 gen7_emit_sampler_state_pointers(ctx);
2970 gen7_emit_bypass_state(ctx);
2971 gen7_emit_vs_state(ctx);
2972 gen7_emit_clip_state(ctx);
2973 gen7_emit_sf_state(ctx);
2974 gen7_emit_wm_state(ctx, kernel);
2975 gen7_emit_binding_table(ctx);
2976 gen7_emit_depth_buffer_state(ctx);
2977 gen7_emit_drawing_rectangle(ctx);
2978 gen7_emit_vertex_element_state(ctx);
2979 gen7_emit_vertices(ctx);
2980 intel_batchbuffer_end_atomic(batch);
2985 gen7_render_put_surface(
2986 VADriverContextP ctx,
2987 struct object_surface *obj_surface,
2988 const VARectangle *src_rect,
2989 const VARectangle *dst_rect,
2993 struct i965_driver_data *i965 = i965_driver_data(ctx);
2994 struct intel_batchbuffer *batch = i965->batch;
2996 gen7_render_initialize(ctx);
2997 gen7_render_setup_states(ctx, obj_surface, src_rect, dst_rect, flags);
2998 i965_clear_dest_region(ctx);
2999 gen7_render_emit_states(ctx, PS_KERNEL);
3000 intel_batchbuffer_flush(batch);
3005 gen7_subpicture_render_blend_state(VADriverContextP ctx)
3007 struct i965_driver_data *i965 = i965_driver_data(ctx);
3008 struct i965_render_state *render_state = &i965->render_state;
3009 struct gen6_blend_state *blend_state;
3011 dri_bo_unmap(render_state->cc.state);
3012 dri_bo_map(render_state->cc.blend, 1);
3013 assert(render_state->cc.blend->virtual);
3014 blend_state = render_state->cc.blend->virtual;
3015 memset(blend_state, 0, sizeof(*blend_state));
3016 blend_state->blend0.dest_blend_factor = I965_BLENDFACTOR_INV_SRC_ALPHA;
3017 blend_state->blend0.source_blend_factor = I965_BLENDFACTOR_SRC_ALPHA;
3018 blend_state->blend0.blend_func = I965_BLENDFUNCTION_ADD;
3019 blend_state->blend0.blend_enable = 1;
3020 blend_state->blend1.post_blend_clamp_enable = 1;
3021 blend_state->blend1.pre_blend_clamp_enable = 1;
3022 blend_state->blend1.clamp_range = 0; /* clamp range [0, 1] */
3023 dri_bo_unmap(render_state->cc.blend);
3027 gen7_subpicture_render_setup_states(
3028 VADriverContextP ctx,
3029 struct object_surface *obj_surface,
3030 const VARectangle *src_rect,
3031 const VARectangle *dst_rect
3034 i965_render_dest_surface_state(ctx, 0);
3035 i965_subpic_render_src_surfaces_state(ctx, obj_surface);
3036 i965_render_sampler(ctx);
3037 i965_render_cc_viewport(ctx);
3038 gen7_render_color_calc_state(ctx);
3039 gen7_subpicture_render_blend_state(ctx);
3040 gen7_render_depth_stencil_state(ctx);
3041 i965_subpic_render_upload_constants(ctx, obj_surface);
3042 i965_subpic_render_upload_vertex(ctx, obj_surface, dst_rect);
3046 gen7_render_put_subpicture(
3047 VADriverContextP ctx,
3048 struct object_surface *obj_surface,
3049 const VARectangle *src_rect,
3050 const VARectangle *dst_rect
3053 struct i965_driver_data *i965 = i965_driver_data(ctx);
3054 struct intel_batchbuffer *batch = i965->batch;
3055 unsigned int index = obj_surface->subpic_render_idx;
3056 struct object_subpic *obj_subpic = obj_surface->obj_subpic[index];
3059 gen7_render_initialize(ctx);
3060 gen7_subpicture_render_setup_states(ctx, obj_surface, src_rect, dst_rect);
3061 gen7_render_emit_states(ctx, PS_SUBPIC_KERNEL);
3062 i965_render_upload_image_palette(ctx, obj_subpic->obj_image, 0xff);
3063 intel_batchbuffer_flush(batch);
3068 intel_render_put_surface(
3069 VADriverContextP ctx,
3070 struct object_surface *obj_surface,
3071 const VARectangle *src_rect,
3072 const VARectangle *dst_rect,
3076 struct i965_driver_data *i965 = i965_driver_data(ctx);
3077 struct i965_render_state *render_state = &i965->render_state;
3078 int has_done_scaling = 0;
3079 VARectangle calibrated_rect;
3080 VASurfaceID out_surface_id = i965_post_processing(ctx,
3088 assert((!has_done_scaling) || (out_surface_id != VA_INVALID_ID));
3090 if (out_surface_id != VA_INVALID_ID) {
3091 struct object_surface *new_obj_surface = SURFACE(out_surface_id);
3093 if (new_obj_surface && new_obj_surface->bo)
3094 obj_surface = new_obj_surface;
3096 if (has_done_scaling)
3097 src_rect = &calibrated_rect;
3100 render_state->render_put_surface(ctx, obj_surface, src_rect, dst_rect, flags);
3102 if (out_surface_id != VA_INVALID_ID)
3103 i965_DestroySurfaces(ctx, &out_surface_id, 1);
3107 intel_render_put_subpicture(
3108 VADriverContextP ctx,
3109 struct object_surface *obj_surface,
3110 const VARectangle *src_rect,
3111 const VARectangle *dst_rect
3114 struct i965_driver_data *i965 = i965_driver_data(ctx);
3115 struct i965_render_state *render_state = &i965->render_state;
3117 render_state->render_put_subpicture(ctx, obj_surface, src_rect, dst_rect);
3121 genx_render_terminate(VADriverContextP ctx)
3124 struct i965_driver_data *i965 = i965_driver_data(ctx);
3125 struct i965_render_state *render_state = &i965->render_state;
3127 dri_bo_unreference(render_state->curbe.bo);
3128 render_state->curbe.bo = NULL;
3130 for (i = 0; i < NUM_RENDER_KERNEL; i++) {
3131 struct i965_kernel *kernel = &render_state->render_kernels[i];
3133 dri_bo_unreference(kernel->bo);
3137 dri_bo_unreference(render_state->vb.vertex_buffer);
3138 render_state->vb.vertex_buffer = NULL;
3139 dri_bo_unreference(render_state->vs.state);
3140 render_state->vs.state = NULL;
3141 dri_bo_unreference(render_state->sf.state);
3142 render_state->sf.state = NULL;
3143 dri_bo_unreference(render_state->wm.sampler);
3144 render_state->wm.sampler = NULL;
3145 dri_bo_unreference(render_state->wm.state);
3146 render_state->wm.state = NULL;
3147 dri_bo_unreference(render_state->wm.surface_state_binding_table_bo);
3148 dri_bo_unreference(render_state->cc.viewport);
3149 render_state->cc.viewport = NULL;
3150 dri_bo_unreference(render_state->cc.state);
3151 render_state->cc.state = NULL;
3152 dri_bo_unreference(render_state->cc.blend);
3153 render_state->cc.blend = NULL;
3154 dri_bo_unreference(render_state->cc.depth_stencil);
3155 render_state->cc.depth_stencil = NULL;
3157 if (render_state->draw_region) {
3158 dri_bo_unreference(render_state->draw_region->bo);
3159 free(render_state->draw_region);
3160 render_state->draw_region = NULL;
3165 genx_render_init(VADriverContextP ctx)
3167 struct i965_driver_data *i965 = i965_driver_data(ctx);
3168 struct i965_render_state *render_state = &i965->render_state;
3172 assert(NUM_RENDER_KERNEL == (sizeof(render_kernels_gen5) /
3173 sizeof(render_kernels_gen5[0])));
3174 assert(NUM_RENDER_KERNEL == (sizeof(render_kernels_gen6) /
3175 sizeof(render_kernels_gen6[0])));
3177 if (IS_GEN7(i965->intel.device_info)) {
3178 memcpy(render_state->render_kernels,
3179 (IS_HASWELL(i965->intel.device_info) ? render_kernels_gen7_haswell : render_kernels_gen7),
3180 sizeof(render_state->render_kernels));
3181 render_state->render_put_surface = gen7_render_put_surface;
3182 render_state->render_put_subpicture = gen7_render_put_subpicture;
3183 } else if (IS_GEN6(i965->intel.device_info)) {
3184 memcpy(render_state->render_kernels, render_kernels_gen6, sizeof(render_state->render_kernels));
3185 render_state->render_put_surface = gen6_render_put_surface;
3186 render_state->render_put_subpicture = gen6_render_put_subpicture;
3187 } else if (IS_IRONLAKE(i965->intel.device_info)) {
3188 memcpy(render_state->render_kernels, render_kernels_gen5, sizeof(render_state->render_kernels));
3189 render_state->render_put_surface = i965_render_put_surface;
3190 render_state->render_put_subpicture = i965_render_put_subpicture;
3192 memcpy(render_state->render_kernels, render_kernels_gen4, sizeof(render_state->render_kernels));
3193 render_state->render_put_surface = i965_render_put_surface;
3194 render_state->render_put_subpicture = i965_render_put_subpicture;
3197 render_state->render_terminate = genx_render_terminate;
3199 for (i = 0; i < NUM_RENDER_KERNEL; i++) {
3200 struct i965_kernel *kernel = &render_state->render_kernels[i];
3205 kernel->bo = dri_bo_alloc(i965->intel.bufmgr,
3207 kernel->size, 0x1000);
3209 dri_bo_subdata(kernel->bo, 0, kernel->size, kernel->bin);
3212 /* constant buffer */
3213 render_state->curbe.bo = dri_bo_alloc(i965->intel.bufmgr,
3216 assert(render_state->curbe.bo);
3222 i965_render_init(VADriverContextP ctx)
3224 struct i965_driver_data *i965 = i965_driver_data(ctx);
3226 return i965->codec_info->render_init(ctx);
3230 i965_render_terminate(VADriverContextP ctx)
3232 struct i965_driver_data *i965 = i965_driver_data(ctx);
3233 struct i965_render_state *render_state = &i965->render_state;
3235 render_state->render_terminate(ctx);