2 * Copyright © 2006 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Eric Anholt <eric@anholt.net>
25 * Keith Packard <keithp@keithp.com>
26 * Xiang Haihao <haihao.xiang@intel.com>
31 * Most of rendering codes are ported from xf86-video-intel/src/i965_video.c
40 #include <va/va_drmcommon.h>
42 #include "intel_batchbuffer.h"
43 #include "intel_driver.h"
44 #include "i965_defines.h"
45 #include "i965_drv_video.h"
46 #include "i965_structs.h"
48 #include "i965_render.h"
50 #define SF_KERNEL_NUM_GRF 16
51 #define SF_MAX_THREADS 1
53 static const uint32_t sf_kernel_static[][4] =
55 #include "shaders/render/exa_sf.g4b"
58 #define PS_KERNEL_NUM_GRF 48
59 #define PS_MAX_THREADS 32
61 #define I965_GRF_BLOCKS(nreg) ((nreg + 15) / 16 - 1)
63 static const uint32_t ps_kernel_static[][4] =
65 #include "shaders/render/exa_wm_xy.g4b"
66 #include "shaders/render/exa_wm_src_affine.g4b"
67 #include "shaders/render/exa_wm_src_sample_planar.g4b"
68 #include "shaders/render/exa_wm_yuv_color_balance.g4b"
69 #include "shaders/render/exa_wm_yuv_rgb.g4b"
70 #include "shaders/render/exa_wm_write.g4b"
72 static const uint32_t ps_subpic_kernel_static[][4] =
74 #include "shaders/render/exa_wm_xy.g4b"
75 #include "shaders/render/exa_wm_src_affine.g4b"
76 #include "shaders/render/exa_wm_src_sample_argb.g4b"
77 #include "shaders/render/exa_wm_write.g4b"
81 static const uint32_t sf_kernel_static_gen5[][4] =
83 #include "shaders/render/exa_sf.g4b.gen5"
86 static const uint32_t ps_kernel_static_gen5[][4] =
88 #include "shaders/render/exa_wm_xy.g4b.gen5"
89 #include "shaders/render/exa_wm_src_affine.g4b.gen5"
90 #include "shaders/render/exa_wm_src_sample_planar.g4b.gen5"
91 #include "shaders/render/exa_wm_yuv_color_balance.g4b.gen5"
92 #include "shaders/render/exa_wm_yuv_rgb.g4b.gen5"
93 #include "shaders/render/exa_wm_write.g4b.gen5"
95 static const uint32_t ps_subpic_kernel_static_gen5[][4] =
97 #include "shaders/render/exa_wm_xy.g4b.gen5"
98 #include "shaders/render/exa_wm_src_affine.g4b.gen5"
99 #include "shaders/render/exa_wm_src_sample_argb.g4b.gen5"
100 #include "shaders/render/exa_wm_write.g4b.gen5"
103 /* programs for Sandybridge */
104 static const uint32_t sf_kernel_static_gen6[][4] =
108 static const uint32_t ps_kernel_static_gen6[][4] = {
109 #include "shaders/render/exa_wm_src_affine.g6b"
110 #include "shaders/render/exa_wm_src_sample_planar.g6b"
111 #include "shaders/render/exa_wm_yuv_color_balance.g6b"
112 #include "shaders/render/exa_wm_yuv_rgb.g6b"
113 #include "shaders/render/exa_wm_write.g6b"
116 static const uint32_t ps_subpic_kernel_static_gen6[][4] = {
117 #include "shaders/render/exa_wm_src_affine.g6b"
118 #include "shaders/render/exa_wm_src_sample_argb.g6b"
119 #include "shaders/render/exa_wm_write.g6b"
122 /* programs for Ivybridge */
123 static const uint32_t sf_kernel_static_gen7[][4] =
127 static const uint32_t ps_kernel_static_gen7[][4] = {
128 #include "shaders/render/exa_wm_src_affine.g7b"
129 #include "shaders/render/exa_wm_src_sample_planar.g7b"
130 #include "shaders/render/exa_wm_yuv_color_balance.g7b"
131 #include "shaders/render/exa_wm_yuv_rgb.g7b"
132 #include "shaders/render/exa_wm_write.g7b"
135 static const uint32_t ps_subpic_kernel_static_gen7[][4] = {
136 #include "shaders/render/exa_wm_src_affine.g7b"
137 #include "shaders/render/exa_wm_src_sample_argb.g7b"
138 #include "shaders/render/exa_wm_write.g7b"
141 /* Programs for Haswell */
142 static const uint32_t ps_kernel_static_gen7_haswell[][4] = {
143 #include "shaders/render/exa_wm_src_affine.g7b"
144 #include "shaders/render/exa_wm_src_sample_planar.g7b.haswell"
145 #include "shaders/render/exa_wm_yuv_color_balance.g7b.haswell"
146 #include "shaders/render/exa_wm_yuv_rgb.g7b"
147 #include "shaders/render/exa_wm_write.g7b"
150 /*TODO: Modify the shader for GEN8.
151 * Now it only uses the shader for gen7/haswell
153 /* Programs for Gen8 */
154 static const uint32_t sf_kernel_static_gen8[][4] =
157 static const uint32_t ps_kernel_static_gen8[][4] = {
158 #include "shaders/render/exa_wm_src_affine.g8b"
159 #include "shaders/render/exa_wm_src_sample_planar.g8b"
160 #include "shaders/render/exa_wm_yuv_color_balance.g8b"
161 #include "shaders/render/exa_wm_yuv_rgb.g8b"
162 #include "shaders/render/exa_wm_write.g8b"
165 static const uint32_t ps_subpic_kernel_static_gen8[][4] = {
166 #include "shaders/render/exa_wm_src_affine.g8b"
167 #include "shaders/render/exa_wm_src_sample_argb.g8b"
168 #include "shaders/render/exa_wm_write.g8b"
172 #define SURFACE_STATE_PADDED_SIZE MAX(SURFACE_STATE_PADDED_SIZE_GEN8, \
173 MAX(SURFACE_STATE_PADDED_SIZE_GEN6, SURFACE_STATE_PADDED_SIZE_GEN7))
175 #define SURFACE_STATE_OFFSET(index) (SURFACE_STATE_PADDED_SIZE * index)
176 #define BINDING_TABLE_OFFSET SURFACE_STATE_OFFSET(MAX_RENDER_SURFACES)
178 static uint32_t float_to_uint (float f)
196 static struct i965_kernel render_kernels_gen4[] = {
201 sizeof(sf_kernel_static),
208 sizeof(ps_kernel_static),
215 ps_subpic_kernel_static,
216 sizeof(ps_subpic_kernel_static),
221 static struct i965_kernel render_kernels_gen5[] = {
225 sf_kernel_static_gen5,
226 sizeof(sf_kernel_static_gen5),
232 ps_kernel_static_gen5,
233 sizeof(ps_kernel_static_gen5),
240 ps_subpic_kernel_static_gen5,
241 sizeof(ps_subpic_kernel_static_gen5),
246 static struct i965_kernel render_kernels_gen6[] = {
250 sf_kernel_static_gen6,
251 sizeof(sf_kernel_static_gen6),
257 ps_kernel_static_gen6,
258 sizeof(ps_kernel_static_gen6),
265 ps_subpic_kernel_static_gen6,
266 sizeof(ps_subpic_kernel_static_gen6),
271 static struct i965_kernel render_kernels_gen7[] = {
275 sf_kernel_static_gen7,
276 sizeof(sf_kernel_static_gen7),
282 ps_kernel_static_gen7,
283 sizeof(ps_kernel_static_gen7),
290 ps_subpic_kernel_static_gen7,
291 sizeof(ps_subpic_kernel_static_gen7),
296 static struct i965_kernel render_kernels_gen7_haswell[] = {
300 sf_kernel_static_gen7,
301 sizeof(sf_kernel_static_gen7),
307 ps_kernel_static_gen7_haswell,
308 sizeof(ps_kernel_static_gen7_haswell),
315 ps_subpic_kernel_static_gen7,
316 sizeof(ps_subpic_kernel_static_gen7),
321 static struct i965_kernel render_kernels_gen8[] = {
325 sf_kernel_static_gen8,
326 sizeof(sf_kernel_static_gen8),
332 ps_kernel_static_gen8,
333 sizeof(ps_kernel_static_gen8),
340 ps_subpic_kernel_static_gen8,
341 sizeof(ps_subpic_kernel_static_gen8),
346 #define URB_VS_ENTRIES 8
347 #define URB_VS_ENTRY_SIZE 1
349 #define URB_GS_ENTRIES 0
350 #define URB_GS_ENTRY_SIZE 0
352 #define URB_CLIP_ENTRIES 0
353 #define URB_CLIP_ENTRY_SIZE 0
355 #define URB_SF_ENTRIES 1
356 #define URB_SF_ENTRY_SIZE 2
358 #define URB_CS_ENTRIES 4
359 #define URB_CS_ENTRY_SIZE 4
361 static float yuv_to_rgb_bt601[3][4] = {
362 {1.164, 0, 1.596, -0.06275,},
363 {1.164, -0.392, -0.813, -0.50196,},
364 {1.164, 2.017, 0, -0.50196,},
367 static float yuv_to_rgb_bt709[3][4] = {
368 {1.164, 0, 1.793, -0.06275,},
369 {1.164, -0.213, -0.533, -0.50196,},
370 {1.164, 2.112, 0, -0.50196,},
373 static float yuv_to_rgb_smpte_240[3][4] = {
374 {1.164, 0, 1.794, -0.06275,},
375 {1.164, -0.258, -0.5425, -0.50196,},
376 {1.164, 2.078, 0, -0.50196,},
380 i965_render_vs_unit(VADriverContextP ctx)
382 struct i965_driver_data *i965 = i965_driver_data(ctx);
383 struct i965_render_state *render_state = &i965->render_state;
384 struct i965_vs_unit_state *vs_state;
386 dri_bo_map(render_state->vs.state, 1);
387 assert(render_state->vs.state->virtual);
388 vs_state = render_state->vs.state->virtual;
389 memset(vs_state, 0, sizeof(*vs_state));
391 if (IS_IRONLAKE(i965->intel.device_id))
392 vs_state->thread4.nr_urb_entries = URB_VS_ENTRIES >> 2;
394 vs_state->thread4.nr_urb_entries = URB_VS_ENTRIES;
396 vs_state->thread4.urb_entry_allocation_size = URB_VS_ENTRY_SIZE - 1;
397 vs_state->vs6.vs_enable = 0;
398 vs_state->vs6.vert_cache_disable = 1;
400 dri_bo_unmap(render_state->vs.state);
404 i965_render_sf_unit(VADriverContextP ctx)
406 struct i965_driver_data *i965 = i965_driver_data(ctx);
407 struct i965_render_state *render_state = &i965->render_state;
408 struct i965_sf_unit_state *sf_state;
410 dri_bo_map(render_state->sf.state, 1);
411 assert(render_state->sf.state->virtual);
412 sf_state = render_state->sf.state->virtual;
413 memset(sf_state, 0, sizeof(*sf_state));
415 sf_state->thread0.grf_reg_count = I965_GRF_BLOCKS(SF_KERNEL_NUM_GRF);
416 sf_state->thread0.kernel_start_pointer = render_state->render_kernels[SF_KERNEL].bo->offset >> 6;
418 sf_state->sf1.single_program_flow = 1; /* XXX */
419 sf_state->sf1.binding_table_entry_count = 0;
420 sf_state->sf1.thread_priority = 0;
421 sf_state->sf1.floating_point_mode = 0; /* Mesa does this */
422 sf_state->sf1.illegal_op_exception_enable = 1;
423 sf_state->sf1.mask_stack_exception_enable = 1;
424 sf_state->sf1.sw_exception_enable = 1;
426 /* scratch space is not used in our kernel */
427 sf_state->thread2.per_thread_scratch_space = 0;
428 sf_state->thread2.scratch_space_base_pointer = 0;
430 sf_state->thread3.const_urb_entry_read_length = 0; /* no const URBs */
431 sf_state->thread3.const_urb_entry_read_offset = 0; /* no const URBs */
432 sf_state->thread3.urb_entry_read_length = 1; /* 1 URB per vertex */
433 sf_state->thread3.urb_entry_read_offset = 0;
434 sf_state->thread3.dispatch_grf_start_reg = 3;
436 sf_state->thread4.max_threads = SF_MAX_THREADS - 1;
437 sf_state->thread4.urb_entry_allocation_size = URB_SF_ENTRY_SIZE - 1;
438 sf_state->thread4.nr_urb_entries = URB_SF_ENTRIES;
439 sf_state->thread4.stats_enable = 1;
441 sf_state->sf5.viewport_transform = 0; /* skip viewport */
443 sf_state->sf6.cull_mode = I965_CULLMODE_NONE;
444 sf_state->sf6.scissor = 0;
446 sf_state->sf7.trifan_pv = 2;
448 sf_state->sf6.dest_org_vbias = 0x8;
449 sf_state->sf6.dest_org_hbias = 0x8;
451 dri_bo_emit_reloc(render_state->sf.state,
452 I915_GEM_DOMAIN_INSTRUCTION, 0,
453 sf_state->thread0.grf_reg_count << 1,
454 offsetof(struct i965_sf_unit_state, thread0),
455 render_state->render_kernels[SF_KERNEL].bo);
457 dri_bo_unmap(render_state->sf.state);
461 i965_render_sampler(VADriverContextP ctx)
463 struct i965_driver_data *i965 = i965_driver_data(ctx);
464 struct i965_render_state *render_state = &i965->render_state;
465 struct i965_sampler_state *sampler_state;
468 assert(render_state->wm.sampler_count > 0);
469 assert(render_state->wm.sampler_count <= MAX_SAMPLERS);
471 dri_bo_map(render_state->wm.sampler, 1);
472 assert(render_state->wm.sampler->virtual);
473 sampler_state = render_state->wm.sampler->virtual;
474 for (i = 0; i < render_state->wm.sampler_count; i++) {
475 memset(sampler_state, 0, sizeof(*sampler_state));
476 sampler_state->ss0.min_filter = I965_MAPFILTER_LINEAR;
477 sampler_state->ss0.mag_filter = I965_MAPFILTER_LINEAR;
478 sampler_state->ss1.r_wrap_mode = I965_TEXCOORDMODE_CLAMP;
479 sampler_state->ss1.s_wrap_mode = I965_TEXCOORDMODE_CLAMP;
480 sampler_state->ss1.t_wrap_mode = I965_TEXCOORDMODE_CLAMP;
484 dri_bo_unmap(render_state->wm.sampler);
487 i965_subpic_render_wm_unit(VADriverContextP ctx)
489 struct i965_driver_data *i965 = i965_driver_data(ctx);
490 struct i965_render_state *render_state = &i965->render_state;
491 struct i965_wm_unit_state *wm_state;
493 assert(render_state->wm.sampler);
495 dri_bo_map(render_state->wm.state, 1);
496 assert(render_state->wm.state->virtual);
497 wm_state = render_state->wm.state->virtual;
498 memset(wm_state, 0, sizeof(*wm_state));
500 wm_state->thread0.grf_reg_count = I965_GRF_BLOCKS(PS_KERNEL_NUM_GRF);
501 wm_state->thread0.kernel_start_pointer = render_state->render_kernels[PS_SUBPIC_KERNEL].bo->offset >> 6;
503 wm_state->thread1.single_program_flow = 1; /* XXX */
505 if (IS_IRONLAKE(i965->intel.device_id))
506 wm_state->thread1.binding_table_entry_count = 0; /* hardware requirement */
508 wm_state->thread1.binding_table_entry_count = 7;
510 wm_state->thread2.scratch_space_base_pointer = 0;
511 wm_state->thread2.per_thread_scratch_space = 0; /* 1024 bytes */
513 wm_state->thread3.dispatch_grf_start_reg = 2; /* XXX */
514 wm_state->thread3.const_urb_entry_read_length = 4;
515 wm_state->thread3.const_urb_entry_read_offset = 0;
516 wm_state->thread3.urb_entry_read_length = 1; /* XXX */
517 wm_state->thread3.urb_entry_read_offset = 0; /* XXX */
519 wm_state->wm4.stats_enable = 0;
520 wm_state->wm4.sampler_state_pointer = render_state->wm.sampler->offset >> 5;
522 if (IS_IRONLAKE(i965->intel.device_id)) {
523 wm_state->wm4.sampler_count = 0; /* hardware requirement */
525 wm_state->wm4.sampler_count = (render_state->wm.sampler_count + 3) / 4;
528 wm_state->wm5.max_threads = render_state->max_wm_threads - 1;
529 wm_state->wm5.thread_dispatch_enable = 1;
530 wm_state->wm5.enable_16_pix = 1;
531 wm_state->wm5.enable_8_pix = 0;
532 wm_state->wm5.early_depth_test = 1;
534 dri_bo_emit_reloc(render_state->wm.state,
535 I915_GEM_DOMAIN_INSTRUCTION, 0,
536 wm_state->thread0.grf_reg_count << 1,
537 offsetof(struct i965_wm_unit_state, thread0),
538 render_state->render_kernels[PS_SUBPIC_KERNEL].bo);
540 dri_bo_emit_reloc(render_state->wm.state,
541 I915_GEM_DOMAIN_INSTRUCTION, 0,
542 wm_state->wm4.sampler_count << 2,
543 offsetof(struct i965_wm_unit_state, wm4),
544 render_state->wm.sampler);
546 dri_bo_unmap(render_state->wm.state);
551 i965_render_wm_unit(VADriverContextP ctx)
553 struct i965_driver_data *i965 = i965_driver_data(ctx);
554 struct i965_render_state *render_state = &i965->render_state;
555 struct i965_wm_unit_state *wm_state;
557 assert(render_state->wm.sampler);
559 dri_bo_map(render_state->wm.state, 1);
560 assert(render_state->wm.state->virtual);
561 wm_state = render_state->wm.state->virtual;
562 memset(wm_state, 0, sizeof(*wm_state));
564 wm_state->thread0.grf_reg_count = I965_GRF_BLOCKS(PS_KERNEL_NUM_GRF);
565 wm_state->thread0.kernel_start_pointer = render_state->render_kernels[PS_KERNEL].bo->offset >> 6;
567 wm_state->thread1.single_program_flow = 1; /* XXX */
569 if (IS_IRONLAKE(i965->intel.device_id))
570 wm_state->thread1.binding_table_entry_count = 0; /* hardware requirement */
572 wm_state->thread1.binding_table_entry_count = 7;
574 wm_state->thread2.scratch_space_base_pointer = 0;
575 wm_state->thread2.per_thread_scratch_space = 0; /* 1024 bytes */
577 wm_state->thread3.dispatch_grf_start_reg = 2; /* XXX */
578 wm_state->thread3.const_urb_entry_read_length = 4;
579 wm_state->thread3.const_urb_entry_read_offset = 0;
580 wm_state->thread3.urb_entry_read_length = 1; /* XXX */
581 wm_state->thread3.urb_entry_read_offset = 0; /* XXX */
583 wm_state->wm4.stats_enable = 0;
584 wm_state->wm4.sampler_state_pointer = render_state->wm.sampler->offset >> 5;
586 if (IS_IRONLAKE(i965->intel.device_id)) {
587 wm_state->wm4.sampler_count = 0; /* hardware requirement */
589 wm_state->wm4.sampler_count = (render_state->wm.sampler_count + 3) / 4;
592 wm_state->wm5.max_threads = render_state->max_wm_threads - 1;
593 wm_state->wm5.thread_dispatch_enable = 1;
594 wm_state->wm5.enable_16_pix = 1;
595 wm_state->wm5.enable_8_pix = 0;
596 wm_state->wm5.early_depth_test = 1;
598 dri_bo_emit_reloc(render_state->wm.state,
599 I915_GEM_DOMAIN_INSTRUCTION, 0,
600 wm_state->thread0.grf_reg_count << 1,
601 offsetof(struct i965_wm_unit_state, thread0),
602 render_state->render_kernels[PS_KERNEL].bo);
604 dri_bo_emit_reloc(render_state->wm.state,
605 I915_GEM_DOMAIN_INSTRUCTION, 0,
606 wm_state->wm4.sampler_count << 2,
607 offsetof(struct i965_wm_unit_state, wm4),
608 render_state->wm.sampler);
610 dri_bo_unmap(render_state->wm.state);
614 i965_render_cc_viewport(VADriverContextP ctx)
616 struct i965_driver_data *i965 = i965_driver_data(ctx);
617 struct i965_render_state *render_state = &i965->render_state;
618 struct i965_cc_viewport *cc_viewport;
620 dri_bo_map(render_state->cc.viewport, 1);
621 assert(render_state->cc.viewport->virtual);
622 cc_viewport = render_state->cc.viewport->virtual;
623 memset(cc_viewport, 0, sizeof(*cc_viewport));
625 cc_viewport->min_depth = -1.e35;
626 cc_viewport->max_depth = 1.e35;
628 dri_bo_unmap(render_state->cc.viewport);
632 i965_subpic_render_cc_unit(VADriverContextP ctx)
634 struct i965_driver_data *i965 = i965_driver_data(ctx);
635 struct i965_render_state *render_state = &i965->render_state;
636 struct i965_cc_unit_state *cc_state;
638 assert(render_state->cc.viewport);
640 dri_bo_map(render_state->cc.state, 1);
641 assert(render_state->cc.state->virtual);
642 cc_state = render_state->cc.state->virtual;
643 memset(cc_state, 0, sizeof(*cc_state));
645 cc_state->cc0.stencil_enable = 0; /* disable stencil */
646 cc_state->cc2.depth_test = 0; /* disable depth test */
647 cc_state->cc2.logicop_enable = 0; /* disable logic op */
648 cc_state->cc3.ia_blend_enable = 0 ; /* blend alpha just like colors */
649 cc_state->cc3.blend_enable = 1; /* enable color blend */
650 cc_state->cc3.alpha_test = 0; /* disable alpha test */
651 cc_state->cc3.alpha_test_format = 0;//0:ALPHATEST_UNORM8; /*store alpha value with UNORM8 */
652 cc_state->cc3.alpha_test_func = 5;//COMPAREFUNCTION_LESS; /*pass if less than the reference */
653 cc_state->cc4.cc_viewport_state_offset = render_state->cc.viewport->offset >> 5;
655 cc_state->cc5.dither_enable = 0; /* disable dither */
656 cc_state->cc5.logicop_func = 0xc; /* WHITE */
657 cc_state->cc5.statistics_enable = 1;
658 cc_state->cc5.ia_blend_function = I965_BLENDFUNCTION_ADD;
659 cc_state->cc5.ia_src_blend_factor = I965_BLENDFACTOR_DST_ALPHA;
660 cc_state->cc5.ia_dest_blend_factor = I965_BLENDFACTOR_DST_ALPHA;
662 cc_state->cc6.clamp_post_alpha_blend = 0;
663 cc_state->cc6.clamp_pre_alpha_blend =0;
665 /*final color = src_color*src_blend_factor +/- dst_color*dest_color_blend_factor*/
666 cc_state->cc6.blend_function = I965_BLENDFUNCTION_ADD;
667 cc_state->cc6.src_blend_factor = I965_BLENDFACTOR_SRC_ALPHA;
668 cc_state->cc6.dest_blend_factor = I965_BLENDFACTOR_INV_SRC_ALPHA;
670 /*alpha test reference*/
671 cc_state->cc7.alpha_ref.f =0.0 ;
674 dri_bo_emit_reloc(render_state->cc.state,
675 I915_GEM_DOMAIN_INSTRUCTION, 0,
677 offsetof(struct i965_cc_unit_state, cc4),
678 render_state->cc.viewport);
680 dri_bo_unmap(render_state->cc.state);
685 i965_render_cc_unit(VADriverContextP ctx)
687 struct i965_driver_data *i965 = i965_driver_data(ctx);
688 struct i965_render_state *render_state = &i965->render_state;
689 struct i965_cc_unit_state *cc_state;
691 assert(render_state->cc.viewport);
693 dri_bo_map(render_state->cc.state, 1);
694 assert(render_state->cc.state->virtual);
695 cc_state = render_state->cc.state->virtual;
696 memset(cc_state, 0, sizeof(*cc_state));
698 cc_state->cc0.stencil_enable = 0; /* disable stencil */
699 cc_state->cc2.depth_test = 0; /* disable depth test */
700 cc_state->cc2.logicop_enable = 1; /* enable logic op */
701 cc_state->cc3.ia_blend_enable = 0; /* blend alpha just like colors */
702 cc_state->cc3.blend_enable = 0; /* disable color blend */
703 cc_state->cc3.alpha_test = 0; /* disable alpha test */
704 cc_state->cc4.cc_viewport_state_offset = render_state->cc.viewport->offset >> 5;
706 cc_state->cc5.dither_enable = 0; /* disable dither */
707 cc_state->cc5.logicop_func = 0xc; /* WHITE */
708 cc_state->cc5.statistics_enable = 1;
709 cc_state->cc5.ia_blend_function = I965_BLENDFUNCTION_ADD;
710 cc_state->cc5.ia_src_blend_factor = I965_BLENDFACTOR_ONE;
711 cc_state->cc5.ia_dest_blend_factor = I965_BLENDFACTOR_ONE;
713 dri_bo_emit_reloc(render_state->cc.state,
714 I915_GEM_DOMAIN_INSTRUCTION, 0,
716 offsetof(struct i965_cc_unit_state, cc4),
717 render_state->cc.viewport);
719 dri_bo_unmap(render_state->cc.state);
723 i965_render_set_surface_tiling(struct i965_surface_state *ss, unsigned int tiling)
726 case I915_TILING_NONE:
727 ss->ss3.tiled_surface = 0;
728 ss->ss3.tile_walk = 0;
731 ss->ss3.tiled_surface = 1;
732 ss->ss3.tile_walk = I965_TILEWALK_XMAJOR;
735 ss->ss3.tiled_surface = 1;
736 ss->ss3.tile_walk = I965_TILEWALK_YMAJOR;
742 i965_render_set_surface_state(
743 struct i965_surface_state *ss,
745 unsigned long offset,
754 unsigned int swizzle;
756 memset(ss, 0, sizeof(*ss));
758 switch (flags & (I965_PP_FLAG_TOP_FIELD|I965_PP_FLAG_BOTTOM_FIELD)) {
759 case I965_PP_FLAG_BOTTOM_FIELD:
760 ss->ss0.vert_line_stride_ofs = 1;
762 case I965_PP_FLAG_TOP_FIELD:
763 ss->ss0.vert_line_stride = 1;
768 ss->ss0.surface_type = I965_SURFACE_2D;
769 ss->ss0.surface_format = format;
770 ss->ss0.color_blend = 1;
772 ss->ss1.base_addr = bo->offset + offset;
774 ss->ss2.width = width - 1;
775 ss->ss2.height = height - 1;
777 ss->ss3.pitch = pitch - 1;
779 dri_bo_get_tiling(bo, &tiling, &swizzle);
780 i965_render_set_surface_tiling(ss, tiling);
784 gen7_render_set_surface_tiling(struct gen7_surface_state *ss, uint32_t tiling)
787 case I915_TILING_NONE:
788 ss->ss0.tiled_surface = 0;
789 ss->ss0.tile_walk = 0;
792 ss->ss0.tiled_surface = 1;
793 ss->ss0.tile_walk = I965_TILEWALK_XMAJOR;
796 ss->ss0.tiled_surface = 1;
797 ss->ss0.tile_walk = I965_TILEWALK_YMAJOR;
803 gen8_render_set_surface_tiling(struct gen8_surface_state *ss, uint32_t tiling)
806 case I915_TILING_NONE:
807 ss->ss0.tiled_surface = 0;
808 ss->ss0.tile_walk = 0;
811 ss->ss0.tiled_surface = 1;
812 ss->ss0.tile_walk = I965_TILEWALK_XMAJOR;
815 ss->ss0.tiled_surface = 1;
816 ss->ss0.tile_walk = I965_TILEWALK_YMAJOR;
821 /* Set "Shader Channel Select" */
823 gen7_render_set_surface_scs(struct gen7_surface_state *ss)
825 ss->ss7.shader_chanel_select_r = HSW_SCS_RED;
826 ss->ss7.shader_chanel_select_g = HSW_SCS_GREEN;
827 ss->ss7.shader_chanel_select_b = HSW_SCS_BLUE;
828 ss->ss7.shader_chanel_select_a = HSW_SCS_ALPHA;
831 /* Set "Shader Channel Select" for GEN8+ */
833 gen8_render_set_surface_scs(struct gen8_surface_state *ss)
835 ss->ss7.shader_chanel_select_r = HSW_SCS_RED;
836 ss->ss7.shader_chanel_select_g = HSW_SCS_GREEN;
837 ss->ss7.shader_chanel_select_b = HSW_SCS_BLUE;
838 ss->ss7.shader_chanel_select_a = HSW_SCS_ALPHA;
842 gen7_render_set_surface_state(
843 struct gen7_surface_state *ss,
845 unsigned long offset,
854 unsigned int swizzle;
856 memset(ss, 0, sizeof(*ss));
858 switch (flags & (I965_PP_FLAG_TOP_FIELD|I965_PP_FLAG_BOTTOM_FIELD)) {
859 case I965_PP_FLAG_BOTTOM_FIELD:
860 ss->ss0.vert_line_stride_ofs = 1;
862 case I965_PP_FLAG_TOP_FIELD:
863 ss->ss0.vert_line_stride = 1;
868 ss->ss0.surface_type = I965_SURFACE_2D;
869 ss->ss0.surface_format = format;
871 ss->ss1.base_addr = bo->offset + offset;
873 ss->ss2.width = width - 1;
874 ss->ss2.height = height - 1;
876 ss->ss3.pitch = pitch - 1;
878 dri_bo_get_tiling(bo, &tiling, &swizzle);
879 gen7_render_set_surface_tiling(ss, tiling);
884 gen8_render_set_surface_state(
885 struct gen8_surface_state *ss,
887 unsigned long offset,
896 unsigned int swizzle;
898 memset(ss, 0, sizeof(*ss));
900 switch (flags & (I965_PP_FLAG_TOP_FIELD|I965_PP_FLAG_BOTTOM_FIELD)) {
901 case I965_PP_FLAG_BOTTOM_FIELD:
902 ss->ss0.vert_line_stride_ofs = 1;
904 case I965_PP_FLAG_TOP_FIELD:
905 ss->ss0.vert_line_stride = 1;
910 ss->ss0.surface_type = I965_SURFACE_2D;
911 ss->ss0.surface_format = format;
913 ss->ss8.base_addr = bo->offset + offset;
915 ss->ss2.width = width - 1;
916 ss->ss2.height = height - 1;
918 ss->ss3.pitch = pitch - 1;
920 /* Always set 1(align 4 mode) per B-spec */
921 ss->ss0.vertical_alignment = 1;
922 ss->ss0.horizontal_alignment = 1;
924 dri_bo_get_tiling(bo, &tiling, &swizzle);
925 gen8_render_set_surface_tiling(ss, tiling);
929 i965_render_src_surface_state(
930 VADriverContextP ctx,
933 unsigned long offset,
941 struct i965_driver_data *i965 = i965_driver_data(ctx);
942 struct i965_render_state *render_state = &i965->render_state;
944 dri_bo *ss_bo = render_state->wm.surface_state_binding_table_bo;
946 assert(index < MAX_RENDER_SURFACES);
948 dri_bo_map(ss_bo, 1);
949 assert(ss_bo->virtual);
950 ss = (char *)ss_bo->virtual + SURFACE_STATE_OFFSET(index);
952 if (IS_GEN8(i965->intel.device_id)) {
953 gen8_render_set_surface_state(ss,
956 pitch, format, flags);
957 gen8_render_set_surface_scs(ss);
958 dri_bo_emit_reloc(ss_bo,
959 I915_GEM_DOMAIN_SAMPLER, 0,
961 SURFACE_STATE_OFFSET(index) + offsetof(struct gen8_surface_state, ss8),
963 } else if (IS_GEN7(i965->intel.device_id)) {
964 gen7_render_set_surface_state(ss,
967 pitch, format, flags);
968 if (IS_HASWELL(i965->intel.device_id))
969 gen7_render_set_surface_scs(ss);
970 dri_bo_emit_reloc(ss_bo,
971 I915_GEM_DOMAIN_SAMPLER, 0,
973 SURFACE_STATE_OFFSET(index) + offsetof(struct gen7_surface_state, ss1),
976 i965_render_set_surface_state(ss,
979 pitch, format, flags);
980 dri_bo_emit_reloc(ss_bo,
981 I915_GEM_DOMAIN_SAMPLER, 0,
983 SURFACE_STATE_OFFSET(index) + offsetof(struct i965_surface_state, ss1),
987 ((unsigned int *)((char *)ss_bo->virtual + BINDING_TABLE_OFFSET))[index] = SURFACE_STATE_OFFSET(index);
989 render_state->wm.sampler_count++;
993 i965_render_src_surfaces_state(
994 VADriverContextP ctx,
995 struct object_surface *obj_surface,
1003 region_pitch = obj_surface->width;
1004 rw = obj_surface->orig_width;
1005 rh = obj_surface->orig_height;
1006 region = obj_surface->bo;
1008 i965_render_src_surface_state(ctx, 1, region, 0, rw, rh, region_pitch, I965_SURFACEFORMAT_R8_UNORM, flags); /* Y */
1009 i965_render_src_surface_state(ctx, 2, region, 0, rw, rh, region_pitch, I965_SURFACEFORMAT_R8_UNORM, flags);
1011 if (obj_surface->fourcc == VA_FOURCC('N', 'V', '1', '2')) {
1012 i965_render_src_surface_state(ctx, 3, region,
1013 region_pitch * obj_surface->y_cb_offset,
1014 obj_surface->cb_cr_width, obj_surface->cb_cr_height, obj_surface->cb_cr_pitch,
1015 I965_SURFACEFORMAT_R8G8_UNORM, flags); /* UV */
1016 i965_render_src_surface_state(ctx, 4, region,
1017 region_pitch * obj_surface->y_cb_offset,
1018 obj_surface->cb_cr_width, obj_surface->cb_cr_height, obj_surface->cb_cr_pitch,
1019 I965_SURFACEFORMAT_R8G8_UNORM, flags);
1021 i965_render_src_surface_state(ctx, 3, region,
1022 region_pitch * obj_surface->y_cb_offset,
1023 obj_surface->cb_cr_width, obj_surface->cb_cr_height, obj_surface->cb_cr_pitch,
1024 I965_SURFACEFORMAT_R8_UNORM, flags); /* U */
1025 i965_render_src_surface_state(ctx, 4, region,
1026 region_pitch * obj_surface->y_cb_offset,
1027 obj_surface->cb_cr_width, obj_surface->cb_cr_height, obj_surface->cb_cr_pitch,
1028 I965_SURFACEFORMAT_R8_UNORM, flags);
1029 i965_render_src_surface_state(ctx, 5, region,
1030 region_pitch * obj_surface->y_cr_offset,
1031 obj_surface->cb_cr_width, obj_surface->cb_cr_height, obj_surface->cb_cr_pitch,
1032 I965_SURFACEFORMAT_R8_UNORM, flags); /* V */
1033 i965_render_src_surface_state(ctx, 6, region,
1034 region_pitch * obj_surface->y_cr_offset,
1035 obj_surface->cb_cr_width, obj_surface->cb_cr_height, obj_surface->cb_cr_pitch,
1036 I965_SURFACEFORMAT_R8_UNORM, flags);
1041 i965_subpic_render_src_surfaces_state(VADriverContextP ctx,
1042 struct object_surface *obj_surface)
1044 dri_bo *subpic_region;
1045 unsigned int index = obj_surface->subpic_render_idx;
1046 struct object_subpic *obj_subpic = obj_surface->obj_subpic[index];
1047 struct object_image *obj_image = obj_subpic->obj_image;
1049 assert(obj_surface);
1050 assert(obj_surface->bo);
1051 subpic_region = obj_image->bo;
1052 /*subpicture surface*/
1053 i965_render_src_surface_state(ctx, 1, subpic_region, 0, obj_subpic->width, obj_subpic->height, obj_subpic->pitch, obj_subpic->format, 0);
1054 i965_render_src_surface_state(ctx, 2, subpic_region, 0, obj_subpic->width, obj_subpic->height, obj_subpic->pitch, obj_subpic->format, 0);
1058 i965_render_dest_surface_state(VADriverContextP ctx, int index)
1060 struct i965_driver_data *i965 = i965_driver_data(ctx);
1061 struct i965_render_state *render_state = &i965->render_state;
1062 struct intel_region *dest_region = render_state->draw_region;
1064 dri_bo *ss_bo = render_state->wm.surface_state_binding_table_bo;
1066 assert(index < MAX_RENDER_SURFACES);
1068 if (dest_region->cpp == 2) {
1069 format = I965_SURFACEFORMAT_B5G6R5_UNORM;
1071 format = I965_SURFACEFORMAT_B8G8R8A8_UNORM;
1074 dri_bo_map(ss_bo, 1);
1075 assert(ss_bo->virtual);
1076 ss = (char *)ss_bo->virtual + SURFACE_STATE_OFFSET(index);
1078 if (IS_GEN8(i965->intel.device_id)) {
1079 gen8_render_set_surface_state(ss,
1081 dest_region->width, dest_region->height,
1082 dest_region->pitch, format, 0);
1083 gen8_render_set_surface_scs(ss);
1084 dri_bo_emit_reloc(ss_bo,
1085 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
1087 SURFACE_STATE_OFFSET(index) + offsetof(struct gen8_surface_state, ss8),
1089 } else if (IS_GEN7(i965->intel.device_id)) {
1090 gen7_render_set_surface_state(ss,
1092 dest_region->width, dest_region->height,
1093 dest_region->pitch, format, 0);
1094 if (IS_HASWELL(i965->intel.device_id))
1095 gen7_render_set_surface_scs(ss);
1096 dri_bo_emit_reloc(ss_bo,
1097 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
1099 SURFACE_STATE_OFFSET(index) + offsetof(struct gen7_surface_state, ss1),
1102 i965_render_set_surface_state(ss,
1104 dest_region->width, dest_region->height,
1105 dest_region->pitch, format, 0);
1106 dri_bo_emit_reloc(ss_bo,
1107 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
1109 SURFACE_STATE_OFFSET(index) + offsetof(struct i965_surface_state, ss1),
1113 ((unsigned int *)((char *)ss_bo->virtual + BINDING_TABLE_OFFSET))[index] = SURFACE_STATE_OFFSET(index);
1114 dri_bo_unmap(ss_bo);
1118 i965_fill_vertex_buffer(
1119 VADriverContextP ctx,
1120 float tex_coords[4], /* [(u1,v1);(u2,v2)] */
1121 float vid_coords[4] /* [(x1,y1);(x2,y2)] */
1124 struct i965_driver_data * const i965 = i965_driver_data(ctx);
1127 enum { X1, Y1, X2, Y2 };
1129 static const unsigned int g_rotation_indices[][6] = {
1130 [VA_ROTATION_NONE] = { X2, Y2, X1, Y2, X1, Y1 },
1131 [VA_ROTATION_90] = { X2, Y1, X2, Y2, X1, Y2 },
1132 [VA_ROTATION_180] = { X1, Y1, X2, Y1, X2, Y2 },
1133 [VA_ROTATION_270] = { X1, Y2, X1, Y1, X2, Y1 },
1136 const unsigned int * const rotation_indices =
1137 g_rotation_indices[i965->rotation_attrib->value];
1139 vb[0] = tex_coords[rotation_indices[0]]; /* bottom-right corner */
1140 vb[1] = tex_coords[rotation_indices[1]];
1141 vb[2] = vid_coords[X2];
1142 vb[3] = vid_coords[Y2];
1144 vb[4] = tex_coords[rotation_indices[2]]; /* bottom-left corner */
1145 vb[5] = tex_coords[rotation_indices[3]];
1146 vb[6] = vid_coords[X1];
1147 vb[7] = vid_coords[Y2];
1149 vb[8] = tex_coords[rotation_indices[4]]; /* top-left corner */
1150 vb[9] = tex_coords[rotation_indices[5]];
1151 vb[10] = vid_coords[X1];
1152 vb[11] = vid_coords[Y1];
1154 dri_bo_subdata(i965->render_state.vb.vertex_buffer, 0, sizeof(vb), vb);
1158 i965_subpic_render_upload_vertex(VADriverContextP ctx,
1159 struct object_surface *obj_surface,
1160 const VARectangle *output_rect)
1162 unsigned int index = obj_surface->subpic_render_idx;
1163 struct object_subpic *obj_subpic = obj_surface->obj_subpic[index];
1164 float tex_coords[4], vid_coords[4];
1165 VARectangle dst_rect;
1167 if (obj_subpic->flags & VA_SUBPICTURE_DESTINATION_IS_SCREEN_COORD)
1168 dst_rect = obj_subpic->dst_rect;
1170 const float sx = (float)output_rect->width / obj_surface->orig_width;
1171 const float sy = (float)output_rect->height / obj_surface->orig_height;
1172 dst_rect.x = output_rect->x + sx * obj_subpic->dst_rect.x;
1173 dst_rect.y = output_rect->y + sy * obj_subpic->dst_rect.y;
1174 dst_rect.width = sx * obj_subpic->dst_rect.width;
1175 dst_rect.height = sy * obj_subpic->dst_rect.height;
1178 tex_coords[0] = (float)obj_subpic->src_rect.x / obj_subpic->width;
1179 tex_coords[1] = (float)obj_subpic->src_rect.y / obj_subpic->height;
1180 tex_coords[2] = (float)(obj_subpic->src_rect.x + obj_subpic->src_rect.width) / obj_subpic->width;
1181 tex_coords[3] = (float)(obj_subpic->src_rect.y + obj_subpic->src_rect.height) / obj_subpic->height;
1183 vid_coords[0] = dst_rect.x;
1184 vid_coords[1] = dst_rect.y;
1185 vid_coords[2] = (float)(dst_rect.x + dst_rect.width);
1186 vid_coords[3] = (float)(dst_rect.y + dst_rect.height);
1188 i965_fill_vertex_buffer(ctx, tex_coords, vid_coords);
1192 i965_render_upload_vertex(
1193 VADriverContextP ctx,
1194 struct object_surface *obj_surface,
1195 const VARectangle *src_rect,
1196 const VARectangle *dst_rect
1199 struct i965_driver_data *i965 = i965_driver_data(ctx);
1200 struct i965_render_state *render_state = &i965->render_state;
1201 struct intel_region *dest_region = render_state->draw_region;
1202 float tex_coords[4], vid_coords[4];
1205 width = obj_surface->orig_width;
1206 height = obj_surface->orig_height;
1208 tex_coords[0] = (float)src_rect->x / width;
1209 tex_coords[1] = (float)src_rect->y / height;
1210 tex_coords[2] = (float)(src_rect->x + src_rect->width) / width;
1211 tex_coords[3] = (float)(src_rect->y + src_rect->height) / height;
1213 vid_coords[0] = dest_region->x + dst_rect->x;
1214 vid_coords[1] = dest_region->y + dst_rect->y;
1215 vid_coords[2] = vid_coords[0] + dst_rect->width;
1216 vid_coords[3] = vid_coords[1] + dst_rect->height;
1218 i965_fill_vertex_buffer(ctx, tex_coords, vid_coords);
1221 #define PI 3.1415926
1224 i965_render_upload_constants(VADriverContextP ctx,
1225 struct object_surface *obj_surface,
1228 struct i965_driver_data *i965 = i965_driver_data(ctx);
1229 struct i965_render_state *render_state = &i965->render_state;
1230 unsigned short *constant_buffer;
1231 float *color_balance_base;
1232 float contrast = (float)i965->contrast_attrib->value / DEFAULT_CONTRAST;
1233 float brightness = (float)i965->brightness_attrib->value / 255; /* YUV is float in the shader */
1234 float hue = (float)i965->hue_attrib->value / 180 * PI;
1235 float saturation = (float)i965->saturation_attrib->value / DEFAULT_SATURATION;
1237 unsigned int color_flag;
1239 dri_bo_map(render_state->curbe.bo, 1);
1240 assert(render_state->curbe.bo->virtual);
1241 constant_buffer = render_state->curbe.bo->virtual;
1243 if (obj_surface->subsampling == SUBSAMPLE_YUV400) {
1244 assert(obj_surface->fourcc == VA_FOURCC('Y', '8', '0', '0'));
1246 constant_buffer[0] = 2;
1248 if (obj_surface->fourcc == VA_FOURCC('N', 'V', '1', '2'))
1249 constant_buffer[0] = 1;
1251 constant_buffer[0] = 0;
1254 if (i965->contrast_attrib->value == DEFAULT_CONTRAST &&
1255 i965->brightness_attrib->value == DEFAULT_BRIGHTNESS &&
1256 i965->hue_attrib->value == DEFAULT_HUE &&
1257 i965->saturation_attrib->value == DEFAULT_SATURATION)
1258 constant_buffer[1] = 1; /* skip color balance transformation */
1260 constant_buffer[1] = 0;
1262 color_balance_base = (float *)constant_buffer + 4;
1263 *color_balance_base++ = contrast;
1264 *color_balance_base++ = brightness;
1265 *color_balance_base++ = cos(hue) * contrast * saturation;
1266 *color_balance_base++ = sin(hue) * contrast * saturation;
1268 color_flag = flags & VA_SRC_COLOR_MASK;
1269 yuv_to_rgb = (float *)constant_buffer + 8;
1270 if (color_flag == VA_SRC_BT709)
1271 memcpy(yuv_to_rgb, yuv_to_rgb_bt709, sizeof(yuv_to_rgb_bt709));
1272 else if (color_flag == VA_SRC_SMPTE_240)
1273 memcpy(yuv_to_rgb, yuv_to_rgb_smpte_240, sizeof(yuv_to_rgb_smpte_240));
1275 memcpy(yuv_to_rgb, yuv_to_rgb_bt601, sizeof(yuv_to_rgb_bt601));
1277 dri_bo_unmap(render_state->curbe.bo);
1281 i965_subpic_render_upload_constants(VADriverContextP ctx,
1282 struct object_surface *obj_surface)
1284 struct i965_driver_data *i965 = i965_driver_data(ctx);
1285 struct i965_render_state *render_state = &i965->render_state;
1286 float *constant_buffer;
1287 float global_alpha = 1.0;
1288 unsigned int index = obj_surface->subpic_render_idx;
1289 struct object_subpic *obj_subpic = obj_surface->obj_subpic[index];
1291 if (obj_subpic->flags & VA_SUBPICTURE_GLOBAL_ALPHA) {
1292 global_alpha = obj_subpic->global_alpha;
1295 dri_bo_map(render_state->curbe.bo, 1);
1297 assert(render_state->curbe.bo->virtual);
1298 constant_buffer = render_state->curbe.bo->virtual;
1299 *constant_buffer = global_alpha;
1301 dri_bo_unmap(render_state->curbe.bo);
1305 i965_surface_render_state_setup(
1306 VADriverContextP ctx,
1307 struct object_surface *obj_surface,
1308 const VARectangle *src_rect,
1309 const VARectangle *dst_rect,
1313 i965_render_vs_unit(ctx);
1314 i965_render_sf_unit(ctx);
1315 i965_render_dest_surface_state(ctx, 0);
1316 i965_render_src_surfaces_state(ctx, obj_surface, flags);
1317 i965_render_sampler(ctx);
1318 i965_render_wm_unit(ctx);
1319 i965_render_cc_viewport(ctx);
1320 i965_render_cc_unit(ctx);
1321 i965_render_upload_vertex(ctx, obj_surface, src_rect, dst_rect);
1322 i965_render_upload_constants(ctx, obj_surface, flags);
1326 i965_subpic_render_state_setup(
1327 VADriverContextP ctx,
1328 struct object_surface *obj_surface,
1329 const VARectangle *src_rect,
1330 const VARectangle *dst_rect
1333 i965_render_vs_unit(ctx);
1334 i965_render_sf_unit(ctx);
1335 i965_render_dest_surface_state(ctx, 0);
1336 i965_subpic_render_src_surfaces_state(ctx, obj_surface);
1337 i965_render_sampler(ctx);
1338 i965_subpic_render_wm_unit(ctx);
1339 i965_render_cc_viewport(ctx);
1340 i965_subpic_render_cc_unit(ctx);
1341 i965_subpic_render_upload_constants(ctx, obj_surface);
1342 i965_subpic_render_upload_vertex(ctx, obj_surface, dst_rect);
1347 i965_render_pipeline_select(VADriverContextP ctx)
1349 struct i965_driver_data *i965 = i965_driver_data(ctx);
1350 struct intel_batchbuffer *batch = i965->batch;
1352 BEGIN_BATCH(batch, 1);
1353 OUT_BATCH(batch, CMD_PIPELINE_SELECT | PIPELINE_SELECT_3D);
1354 ADVANCE_BATCH(batch);
1358 i965_render_state_sip(VADriverContextP ctx)
1360 struct i965_driver_data *i965 = i965_driver_data(ctx);
1361 struct intel_batchbuffer *batch = i965->batch;
1363 BEGIN_BATCH(batch, 2);
1364 OUT_BATCH(batch, CMD_STATE_SIP | 0);
1365 OUT_BATCH(batch, 0);
1366 ADVANCE_BATCH(batch);
1370 i965_render_state_base_address(VADriverContextP ctx)
1372 struct i965_driver_data *i965 = i965_driver_data(ctx);
1373 struct intel_batchbuffer *batch = i965->batch;
1374 struct i965_render_state *render_state = &i965->render_state;
1376 if (IS_IRONLAKE(i965->intel.device_id)) {
1377 BEGIN_BATCH(batch, 8);
1378 OUT_BATCH(batch, CMD_STATE_BASE_ADDRESS | 6);
1379 OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
1380 OUT_RELOC(batch, render_state->wm.surface_state_binding_table_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, BASE_ADDRESS_MODIFY);
1381 OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
1382 OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
1383 OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
1384 OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
1385 OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
1386 ADVANCE_BATCH(batch);
1388 BEGIN_BATCH(batch, 6);
1389 OUT_BATCH(batch, CMD_STATE_BASE_ADDRESS | 4);
1390 OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
1391 OUT_RELOC(batch, render_state->wm.surface_state_binding_table_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, BASE_ADDRESS_MODIFY);
1392 OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
1393 OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
1394 OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
1395 ADVANCE_BATCH(batch);
1400 i965_render_binding_table_pointers(VADriverContextP ctx)
1402 struct i965_driver_data *i965 = i965_driver_data(ctx);
1403 struct intel_batchbuffer *batch = i965->batch;
1405 BEGIN_BATCH(batch, 6);
1406 OUT_BATCH(batch, CMD_BINDING_TABLE_POINTERS | 4);
1407 OUT_BATCH(batch, 0); /* vs */
1408 OUT_BATCH(batch, 0); /* gs */
1409 OUT_BATCH(batch, 0); /* clip */
1410 OUT_BATCH(batch, 0); /* sf */
1411 OUT_BATCH(batch, BINDING_TABLE_OFFSET);
1412 ADVANCE_BATCH(batch);
1416 i965_render_constant_color(VADriverContextP ctx)
1418 struct i965_driver_data *i965 = i965_driver_data(ctx);
1419 struct intel_batchbuffer *batch = i965->batch;
1421 BEGIN_BATCH(batch, 5);
1422 OUT_BATCH(batch, CMD_CONSTANT_COLOR | 3);
1423 OUT_BATCH(batch, float_to_uint(1.0));
1424 OUT_BATCH(batch, float_to_uint(0.0));
1425 OUT_BATCH(batch, float_to_uint(1.0));
1426 OUT_BATCH(batch, float_to_uint(1.0));
1427 ADVANCE_BATCH(batch);
1431 i965_render_pipelined_pointers(VADriverContextP ctx)
1433 struct i965_driver_data *i965 = i965_driver_data(ctx);
1434 struct intel_batchbuffer *batch = i965->batch;
1435 struct i965_render_state *render_state = &i965->render_state;
1437 BEGIN_BATCH(batch, 7);
1438 OUT_BATCH(batch, CMD_PIPELINED_POINTERS | 5);
1439 OUT_RELOC(batch, render_state->vs.state, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
1440 OUT_BATCH(batch, 0); /* disable GS */
1441 OUT_BATCH(batch, 0); /* disable CLIP */
1442 OUT_RELOC(batch, render_state->sf.state, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
1443 OUT_RELOC(batch, render_state->wm.state, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
1444 OUT_RELOC(batch, render_state->cc.state, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
1445 ADVANCE_BATCH(batch);
1449 i965_render_urb_layout(VADriverContextP ctx)
1451 struct i965_driver_data *i965 = i965_driver_data(ctx);
1452 struct intel_batchbuffer *batch = i965->batch;
1453 int urb_vs_start, urb_vs_size;
1454 int urb_gs_start, urb_gs_size;
1455 int urb_clip_start, urb_clip_size;
1456 int urb_sf_start, urb_sf_size;
1457 int urb_cs_start, urb_cs_size;
1460 urb_vs_size = URB_VS_ENTRIES * URB_VS_ENTRY_SIZE;
1461 urb_gs_start = urb_vs_start + urb_vs_size;
1462 urb_gs_size = URB_GS_ENTRIES * URB_GS_ENTRY_SIZE;
1463 urb_clip_start = urb_gs_start + urb_gs_size;
1464 urb_clip_size = URB_CLIP_ENTRIES * URB_CLIP_ENTRY_SIZE;
1465 urb_sf_start = urb_clip_start + urb_clip_size;
1466 urb_sf_size = URB_SF_ENTRIES * URB_SF_ENTRY_SIZE;
1467 urb_cs_start = urb_sf_start + urb_sf_size;
1468 urb_cs_size = URB_CS_ENTRIES * URB_CS_ENTRY_SIZE;
1470 BEGIN_BATCH(batch, 3);
1480 ((urb_clip_start + urb_clip_size) << UF1_CLIP_FENCE_SHIFT) |
1481 ((urb_gs_start + urb_gs_size) << UF1_GS_FENCE_SHIFT) |
1482 ((urb_vs_start + urb_vs_size) << UF1_VS_FENCE_SHIFT));
1484 ((urb_cs_start + urb_cs_size) << UF2_CS_FENCE_SHIFT) |
1485 ((urb_sf_start + urb_sf_size) << UF2_SF_FENCE_SHIFT));
1486 ADVANCE_BATCH(batch);
1490 i965_render_cs_urb_layout(VADriverContextP ctx)
1492 struct i965_driver_data *i965 = i965_driver_data(ctx);
1493 struct intel_batchbuffer *batch = i965->batch;
1495 BEGIN_BATCH(batch, 2);
1496 OUT_BATCH(batch, CMD_CS_URB_STATE | 0);
1498 ((URB_CS_ENTRY_SIZE - 1) << 4) | /* URB Entry Allocation Size */
1499 (URB_CS_ENTRIES << 0)); /* Number of URB Entries */
1500 ADVANCE_BATCH(batch);
1504 i965_render_constant_buffer(VADriverContextP ctx)
1506 struct i965_driver_data *i965 = i965_driver_data(ctx);
1507 struct intel_batchbuffer *batch = i965->batch;
1508 struct i965_render_state *render_state = &i965->render_state;
1510 BEGIN_BATCH(batch, 2);
1511 OUT_BATCH(batch, CMD_CONSTANT_BUFFER | (1 << 8) | (2 - 2));
1512 OUT_RELOC(batch, render_state->curbe.bo,
1513 I915_GEM_DOMAIN_INSTRUCTION, 0,
1514 URB_CS_ENTRY_SIZE - 1);
1515 ADVANCE_BATCH(batch);
1519 i965_render_drawing_rectangle(VADriverContextP ctx)
1521 struct i965_driver_data *i965 = i965_driver_data(ctx);
1522 struct intel_batchbuffer *batch = i965->batch;
1523 struct i965_render_state *render_state = &i965->render_state;
1524 struct intel_region *dest_region = render_state->draw_region;
1526 BEGIN_BATCH(batch, 4);
1527 OUT_BATCH(batch, CMD_DRAWING_RECTANGLE | 2);
1528 OUT_BATCH(batch, 0x00000000);
1529 OUT_BATCH(batch, (dest_region->width - 1) | (dest_region->height - 1) << 16);
1530 OUT_BATCH(batch, 0x00000000);
1531 ADVANCE_BATCH(batch);
1535 i965_render_vertex_elements(VADriverContextP ctx)
1537 struct i965_driver_data *i965 = i965_driver_data(ctx);
1538 struct intel_batchbuffer *batch = i965->batch;
1540 if (IS_IRONLAKE(i965->intel.device_id)) {
1541 BEGIN_BATCH(batch, 5);
1542 OUT_BATCH(batch, CMD_VERTEX_ELEMENTS | 3);
1543 /* offset 0: X,Y -> {X, Y, 1.0, 1.0} */
1544 OUT_BATCH(batch, (0 << VE0_VERTEX_BUFFER_INDEX_SHIFT) |
1546 (I965_SURFACEFORMAT_R32G32_FLOAT << VE0_FORMAT_SHIFT) |
1547 (0 << VE0_OFFSET_SHIFT));
1548 OUT_BATCH(batch, (I965_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT) |
1549 (I965_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT) |
1550 (I965_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_2_SHIFT) |
1551 (I965_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT));
1552 /* offset 8: S0, T0 -> {S0, T0, 1.0, 1.0} */
1553 OUT_BATCH(batch, (0 << VE0_VERTEX_BUFFER_INDEX_SHIFT) |
1555 (I965_SURFACEFORMAT_R32G32_FLOAT << VE0_FORMAT_SHIFT) |
1556 (8 << VE0_OFFSET_SHIFT));
1557 OUT_BATCH(batch, (I965_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT) |
1558 (I965_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT) |
1559 (I965_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_2_SHIFT) |
1560 (I965_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT));
1561 ADVANCE_BATCH(batch);
1563 BEGIN_BATCH(batch, 5);
1564 OUT_BATCH(batch, CMD_VERTEX_ELEMENTS | 3);
1565 /* offset 0: X,Y -> {X, Y, 1.0, 1.0} */
1566 OUT_BATCH(batch, (0 << VE0_VERTEX_BUFFER_INDEX_SHIFT) |
1568 (I965_SURFACEFORMAT_R32G32_FLOAT << VE0_FORMAT_SHIFT) |
1569 (0 << VE0_OFFSET_SHIFT));
1570 OUT_BATCH(batch, (I965_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT) |
1571 (I965_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT) |
1572 (I965_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_2_SHIFT) |
1573 (I965_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT) |
1574 (0 << VE1_DESTINATION_ELEMENT_OFFSET_SHIFT));
1575 /* offset 8: S0, T0 -> {S0, T0, 1.0, 1.0} */
1576 OUT_BATCH(batch, (0 << VE0_VERTEX_BUFFER_INDEX_SHIFT) |
1578 (I965_SURFACEFORMAT_R32G32_FLOAT << VE0_FORMAT_SHIFT) |
1579 (8 << VE0_OFFSET_SHIFT));
1580 OUT_BATCH(batch, (I965_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT) |
1581 (I965_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT) |
1582 (I965_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_2_SHIFT) |
1583 (I965_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT) |
1584 (4 << VE1_DESTINATION_ELEMENT_OFFSET_SHIFT));
1585 ADVANCE_BATCH(batch);
1590 i965_render_upload_image_palette(
1591 VADriverContextP ctx,
1592 struct object_image *obj_image,
1596 struct i965_driver_data *i965 = i965_driver_data(ctx);
1597 struct intel_batchbuffer *batch = i965->batch;
1605 if (obj_image->image.num_palette_entries == 0)
1608 BEGIN_BATCH(batch, 1 + obj_image->image.num_palette_entries);
1609 OUT_BATCH(batch, CMD_SAMPLER_PALETTE_LOAD | (obj_image->image.num_palette_entries - 1));
1611 //int32_t out[16]; //0-23:color 23-31:alpha
1612 for (i = 0; i < obj_image->image.num_palette_entries; i++)
1613 OUT_BATCH(batch, (alpha << 24) | obj_image->palette[i]);
1614 ADVANCE_BATCH(batch);
1618 i965_render_startup(VADriverContextP ctx)
1620 struct i965_driver_data *i965 = i965_driver_data(ctx);
1621 struct intel_batchbuffer *batch = i965->batch;
1622 struct i965_render_state *render_state = &i965->render_state;
1624 BEGIN_BATCH(batch, 11);
1625 OUT_BATCH(batch, CMD_VERTEX_BUFFERS | 3);
1627 (0 << VB0_BUFFER_INDEX_SHIFT) |
1629 ((4 * 4) << VB0_BUFFER_PITCH_SHIFT));
1630 OUT_RELOC(batch, render_state->vb.vertex_buffer, I915_GEM_DOMAIN_VERTEX, 0, 0);
1632 if (IS_IRONLAKE(i965->intel.device_id))
1633 OUT_RELOC(batch, render_state->vb.vertex_buffer, I915_GEM_DOMAIN_VERTEX, 0, 12 * 4);
1635 OUT_BATCH(batch, 3);
1637 OUT_BATCH(batch, 0);
1641 _3DPRIMITIVE_VERTEX_SEQUENTIAL |
1642 (_3DPRIM_RECTLIST << _3DPRIMITIVE_TOPOLOGY_SHIFT) |
1645 OUT_BATCH(batch, 3); /* vertex count per instance */
1646 OUT_BATCH(batch, 0); /* start vertex offset */
1647 OUT_BATCH(batch, 1); /* single instance */
1648 OUT_BATCH(batch, 0); /* start instance location */
1649 OUT_BATCH(batch, 0); /* index buffer offset, ignored */
1650 ADVANCE_BATCH(batch);
1654 i965_clear_dest_region(VADriverContextP ctx)
1656 struct i965_driver_data *i965 = i965_driver_data(ctx);
1657 struct intel_batchbuffer *batch = i965->batch;
1658 struct i965_render_state *render_state = &i965->render_state;
1659 struct intel_region *dest_region = render_state->draw_region;
1660 unsigned int blt_cmd, br13;
1663 blt_cmd = XY_COLOR_BLT_CMD;
1665 pitch = dest_region->pitch;
1667 if (dest_region->cpp == 4) {
1669 blt_cmd |= (XY_COLOR_BLT_WRITE_RGB | XY_COLOR_BLT_WRITE_ALPHA);
1671 assert(dest_region->cpp == 2);
1675 if (dest_region->tiling != I915_TILING_NONE) {
1676 blt_cmd |= XY_COLOR_BLT_DST_TILED;
1682 if (IS_GEN6(i965->intel.device_id) ||
1683 IS_GEN7(i965->intel.device_id) ||
1684 IS_GEN8(i965->intel.device_id)) {
1685 intel_batchbuffer_start_atomic_blt(batch, 24);
1686 BEGIN_BLT_BATCH(batch, 6);
1688 intel_batchbuffer_start_atomic(batch, 24);
1689 BEGIN_BATCH(batch, 6);
1692 OUT_BATCH(batch, blt_cmd);
1693 OUT_BATCH(batch, br13);
1694 OUT_BATCH(batch, (dest_region->y << 16) | (dest_region->x));
1695 OUT_BATCH(batch, ((dest_region->y + dest_region->height) << 16) |
1696 (dest_region->x + dest_region->width));
1697 OUT_RELOC(batch, dest_region->bo,
1698 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
1700 OUT_BATCH(batch, 0x0);
1701 ADVANCE_BATCH(batch);
1702 intel_batchbuffer_end_atomic(batch);
1706 gen8_clear_dest_region(VADriverContextP ctx)
1708 struct i965_driver_data *i965 = i965_driver_data(ctx);
1709 struct intel_batchbuffer *batch = i965->batch;
1710 struct i965_render_state *render_state = &i965->render_state;
1711 struct intel_region *dest_region = render_state->draw_region;
1712 unsigned int blt_cmd, br13;
1715 blt_cmd = GEN8_XY_COLOR_BLT_CMD;
1717 pitch = dest_region->pitch;
1719 if (dest_region->cpp == 4) {
1721 blt_cmd |= (XY_COLOR_BLT_WRITE_RGB | XY_COLOR_BLT_WRITE_ALPHA);
1723 assert(dest_region->cpp == 2);
1727 if (dest_region->tiling != I915_TILING_NONE) {
1728 blt_cmd |= XY_COLOR_BLT_DST_TILED;
1734 intel_batchbuffer_start_atomic_blt(batch, 24);
1735 BEGIN_BLT_BATCH(batch, 7);
1737 OUT_BATCH(batch, blt_cmd);
1738 OUT_BATCH(batch, br13);
1739 OUT_BATCH(batch, (dest_region->y << 16) | (dest_region->x));
1740 OUT_BATCH(batch, ((dest_region->y + dest_region->height) << 16) |
1741 (dest_region->x + dest_region->width));
1742 OUT_RELOC(batch, dest_region->bo,
1743 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
1745 OUT_BATCH(batch, 0x0);
1746 OUT_BATCH(batch, 0x0);
1747 ADVANCE_BATCH(batch);
1748 intel_batchbuffer_end_atomic(batch);
1752 i965_surface_render_pipeline_setup(VADriverContextP ctx)
1754 struct i965_driver_data *i965 = i965_driver_data(ctx);
1755 struct intel_batchbuffer *batch = i965->batch;
1757 i965_clear_dest_region(ctx);
1758 intel_batchbuffer_start_atomic(batch, 0x1000);
1759 intel_batchbuffer_emit_mi_flush(batch);
1760 i965_render_pipeline_select(ctx);
1761 i965_render_state_sip(ctx);
1762 i965_render_state_base_address(ctx);
1763 i965_render_binding_table_pointers(ctx);
1764 i965_render_constant_color(ctx);
1765 i965_render_pipelined_pointers(ctx);
1766 i965_render_urb_layout(ctx);
1767 i965_render_cs_urb_layout(ctx);
1768 i965_render_constant_buffer(ctx);
1769 i965_render_drawing_rectangle(ctx);
1770 i965_render_vertex_elements(ctx);
1771 i965_render_startup(ctx);
1772 intel_batchbuffer_end_atomic(batch);
1776 i965_subpic_render_pipeline_setup(VADriverContextP ctx)
1778 struct i965_driver_data *i965 = i965_driver_data(ctx);
1779 struct intel_batchbuffer *batch = i965->batch;
1781 intel_batchbuffer_start_atomic(batch, 0x1000);
1782 intel_batchbuffer_emit_mi_flush(batch);
1783 i965_render_pipeline_select(ctx);
1784 i965_render_state_sip(ctx);
1785 i965_render_state_base_address(ctx);
1786 i965_render_binding_table_pointers(ctx);
1787 i965_render_constant_color(ctx);
1788 i965_render_pipelined_pointers(ctx);
1789 i965_render_urb_layout(ctx);
1790 i965_render_cs_urb_layout(ctx);
1791 i965_render_constant_buffer(ctx);
1792 i965_render_drawing_rectangle(ctx);
1793 i965_render_vertex_elements(ctx);
1794 i965_render_startup(ctx);
1795 intel_batchbuffer_end_atomic(batch);
1800 i965_render_initialize(VADriverContextP ctx)
1802 struct i965_driver_data *i965 = i965_driver_data(ctx);
1803 struct i965_render_state *render_state = &i965->render_state;
1807 dri_bo_unreference(render_state->vb.vertex_buffer);
1808 bo = dri_bo_alloc(i965->intel.bufmgr,
1813 render_state->vb.vertex_buffer = bo;
1816 dri_bo_unreference(render_state->vs.state);
1817 bo = dri_bo_alloc(i965->intel.bufmgr,
1819 sizeof(struct i965_vs_unit_state),
1822 render_state->vs.state = bo;
1827 dri_bo_unreference(render_state->sf.state);
1828 bo = dri_bo_alloc(i965->intel.bufmgr,
1830 sizeof(struct i965_sf_unit_state),
1833 render_state->sf.state = bo;
1836 dri_bo_unreference(render_state->wm.surface_state_binding_table_bo);
1837 bo = dri_bo_alloc(i965->intel.bufmgr,
1838 "surface state & binding table",
1839 (SURFACE_STATE_PADDED_SIZE + sizeof(unsigned int)) * MAX_RENDER_SURFACES,
1842 render_state->wm.surface_state_binding_table_bo = bo;
1844 dri_bo_unreference(render_state->wm.sampler);
1845 bo = dri_bo_alloc(i965->intel.bufmgr,
1847 MAX_SAMPLERS * sizeof(struct i965_sampler_state),
1850 render_state->wm.sampler = bo;
1851 render_state->wm.sampler_count = 0;
1853 dri_bo_unreference(render_state->wm.state);
1854 bo = dri_bo_alloc(i965->intel.bufmgr,
1856 sizeof(struct i965_wm_unit_state),
1859 render_state->wm.state = bo;
1861 /* COLOR CALCULATOR */
1862 dri_bo_unreference(render_state->cc.state);
1863 bo = dri_bo_alloc(i965->intel.bufmgr,
1865 sizeof(struct i965_cc_unit_state),
1868 render_state->cc.state = bo;
1870 dri_bo_unreference(render_state->cc.viewport);
1871 bo = dri_bo_alloc(i965->intel.bufmgr,
1873 sizeof(struct i965_cc_viewport),
1876 render_state->cc.viewport = bo;
1880 i965_render_put_surface(
1881 VADriverContextP ctx,
1882 struct object_surface *obj_surface,
1883 const VARectangle *src_rect,
1884 const VARectangle *dst_rect,
1888 struct i965_driver_data *i965 = i965_driver_data(ctx);
1889 struct intel_batchbuffer *batch = i965->batch;
1891 i965_render_initialize(ctx);
1892 i965_surface_render_state_setup(ctx, obj_surface, src_rect, dst_rect, flags);
1893 i965_surface_render_pipeline_setup(ctx);
1894 intel_batchbuffer_flush(batch);
1898 i965_render_put_subpicture(
1899 VADriverContextP ctx,
1900 struct object_surface *obj_surface,
1901 const VARectangle *src_rect,
1902 const VARectangle *dst_rect
1905 struct i965_driver_data *i965 = i965_driver_data(ctx);
1906 struct intel_batchbuffer *batch = i965->batch;
1907 unsigned int index = obj_surface->subpic_render_idx;
1908 struct object_subpic *obj_subpic = obj_surface->obj_subpic[index];
1912 i965_render_initialize(ctx);
1913 i965_subpic_render_state_setup(ctx, obj_surface, src_rect, dst_rect);
1914 i965_subpic_render_pipeline_setup(ctx);
1915 i965_render_upload_image_palette(ctx, obj_subpic->obj_image, 0xff);
1916 intel_batchbuffer_flush(batch);
1923 gen6_render_initialize(VADriverContextP ctx)
1925 struct i965_driver_data *i965 = i965_driver_data(ctx);
1926 struct i965_render_state *render_state = &i965->render_state;
1930 dri_bo_unreference(render_state->vb.vertex_buffer);
1931 bo = dri_bo_alloc(i965->intel.bufmgr,
1936 render_state->vb.vertex_buffer = bo;
1939 dri_bo_unreference(render_state->wm.surface_state_binding_table_bo);
1940 bo = dri_bo_alloc(i965->intel.bufmgr,
1941 "surface state & binding table",
1942 (SURFACE_STATE_PADDED_SIZE + sizeof(unsigned int)) * MAX_RENDER_SURFACES,
1945 render_state->wm.surface_state_binding_table_bo = bo;
1947 dri_bo_unreference(render_state->wm.sampler);
1948 bo = dri_bo_alloc(i965->intel.bufmgr,
1950 MAX_SAMPLERS * sizeof(struct i965_sampler_state),
1953 render_state->wm.sampler = bo;
1954 render_state->wm.sampler_count = 0;
1956 /* COLOR CALCULATOR */
1957 dri_bo_unreference(render_state->cc.state);
1958 bo = dri_bo_alloc(i965->intel.bufmgr,
1960 sizeof(struct gen6_color_calc_state),
1963 render_state->cc.state = bo;
1966 dri_bo_unreference(render_state->cc.viewport);
1967 bo = dri_bo_alloc(i965->intel.bufmgr,
1969 sizeof(struct i965_cc_viewport),
1972 render_state->cc.viewport = bo;
1975 dri_bo_unreference(render_state->cc.blend);
1976 bo = dri_bo_alloc(i965->intel.bufmgr,
1978 sizeof(struct gen6_blend_state),
1981 render_state->cc.blend = bo;
1983 /* DEPTH & STENCIL STATE */
1984 dri_bo_unreference(render_state->cc.depth_stencil);
1985 bo = dri_bo_alloc(i965->intel.bufmgr,
1986 "depth & stencil state",
1987 sizeof(struct gen6_depth_stencil_state),
1990 render_state->cc.depth_stencil = bo;
1994 gen6_render_color_calc_state(VADriverContextP ctx)
1996 struct i965_driver_data *i965 = i965_driver_data(ctx);
1997 struct i965_render_state *render_state = &i965->render_state;
1998 struct gen6_color_calc_state *color_calc_state;
2000 dri_bo_map(render_state->cc.state, 1);
2001 assert(render_state->cc.state->virtual);
2002 color_calc_state = render_state->cc.state->virtual;
2003 memset(color_calc_state, 0, sizeof(*color_calc_state));
2004 color_calc_state->constant_r = 1.0;
2005 color_calc_state->constant_g = 0.0;
2006 color_calc_state->constant_b = 1.0;
2007 color_calc_state->constant_a = 1.0;
2008 dri_bo_unmap(render_state->cc.state);
2012 gen6_render_blend_state(VADriverContextP ctx)
2014 struct i965_driver_data *i965 = i965_driver_data(ctx);
2015 struct i965_render_state *render_state = &i965->render_state;
2016 struct gen6_blend_state *blend_state;
2018 dri_bo_map(render_state->cc.blend, 1);
2019 assert(render_state->cc.blend->virtual);
2020 blend_state = render_state->cc.blend->virtual;
2021 memset(blend_state, 0, sizeof(*blend_state));
2022 blend_state->blend1.logic_op_enable = 1;
2023 blend_state->blend1.logic_op_func = 0xc;
2024 dri_bo_unmap(render_state->cc.blend);
2028 gen6_render_depth_stencil_state(VADriverContextP ctx)
2030 struct i965_driver_data *i965 = i965_driver_data(ctx);
2031 struct i965_render_state *render_state = &i965->render_state;
2032 struct gen6_depth_stencil_state *depth_stencil_state;
2034 dri_bo_map(render_state->cc.depth_stencil, 1);
2035 assert(render_state->cc.depth_stencil->virtual);
2036 depth_stencil_state = render_state->cc.depth_stencil->virtual;
2037 memset(depth_stencil_state, 0, sizeof(*depth_stencil_state));
2038 dri_bo_unmap(render_state->cc.depth_stencil);
2042 gen6_render_setup_states(
2043 VADriverContextP ctx,
2044 struct object_surface *obj_surface,
2045 const VARectangle *src_rect,
2046 const VARectangle *dst_rect,
2050 i965_render_dest_surface_state(ctx, 0);
2051 i965_render_src_surfaces_state(ctx, obj_surface, flags);
2052 i965_render_sampler(ctx);
2053 i965_render_cc_viewport(ctx);
2054 gen6_render_color_calc_state(ctx);
2055 gen6_render_blend_state(ctx);
2056 gen6_render_depth_stencil_state(ctx);
2057 i965_render_upload_constants(ctx, obj_surface, flags);
2058 i965_render_upload_vertex(ctx, obj_surface, src_rect, dst_rect);
2062 gen6_emit_invarient_states(VADriverContextP ctx)
2064 struct i965_driver_data *i965 = i965_driver_data(ctx);
2065 struct intel_batchbuffer *batch = i965->batch;
2067 OUT_BATCH(batch, CMD_PIPELINE_SELECT | PIPELINE_SELECT_3D);
2069 OUT_BATCH(batch, GEN6_3DSTATE_MULTISAMPLE | (3 - 2));
2070 OUT_BATCH(batch, GEN6_3DSTATE_MULTISAMPLE_PIXEL_LOCATION_CENTER |
2071 GEN6_3DSTATE_MULTISAMPLE_NUMSAMPLES_1); /* 1 sample/pixel */
2072 OUT_BATCH(batch, 0);
2074 OUT_BATCH(batch, GEN6_3DSTATE_SAMPLE_MASK | (2 - 2));
2075 OUT_BATCH(batch, 1);
2077 /* Set system instruction pointer */
2078 OUT_BATCH(batch, CMD_STATE_SIP | 0);
2079 OUT_BATCH(batch, 0);
2083 gen6_emit_state_base_address(VADriverContextP ctx)
2085 struct i965_driver_data *i965 = i965_driver_data(ctx);
2086 struct intel_batchbuffer *batch = i965->batch;
2087 struct i965_render_state *render_state = &i965->render_state;
2089 OUT_BATCH(batch, CMD_STATE_BASE_ADDRESS | (10 - 2));
2090 OUT_BATCH(batch, BASE_ADDRESS_MODIFY); /* General state base address */
2091 OUT_RELOC(batch, render_state->wm.surface_state_binding_table_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, BASE_ADDRESS_MODIFY); /* Surface state base address */
2092 OUT_BATCH(batch, BASE_ADDRESS_MODIFY); /* Dynamic state base address */
2093 OUT_BATCH(batch, BASE_ADDRESS_MODIFY); /* Indirect object base address */
2094 OUT_BATCH(batch, BASE_ADDRESS_MODIFY); /* Instruction base address */
2095 OUT_BATCH(batch, BASE_ADDRESS_MODIFY); /* General state upper bound */
2096 OUT_BATCH(batch, BASE_ADDRESS_MODIFY); /* Dynamic state upper bound */
2097 OUT_BATCH(batch, BASE_ADDRESS_MODIFY); /* Indirect object upper bound */
2098 OUT_BATCH(batch, BASE_ADDRESS_MODIFY); /* Instruction access upper bound */
2102 gen6_emit_viewport_state_pointers(VADriverContextP ctx)
2104 struct i965_driver_data *i965 = i965_driver_data(ctx);
2105 struct intel_batchbuffer *batch = i965->batch;
2106 struct i965_render_state *render_state = &i965->render_state;
2108 OUT_BATCH(batch, GEN6_3DSTATE_VIEWPORT_STATE_POINTERS |
2109 GEN6_3DSTATE_VIEWPORT_STATE_MODIFY_CC |
2111 OUT_BATCH(batch, 0);
2112 OUT_BATCH(batch, 0);
2113 OUT_RELOC(batch, render_state->cc.viewport, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
2117 gen6_emit_urb(VADriverContextP ctx)
2119 struct i965_driver_data *i965 = i965_driver_data(ctx);
2120 struct intel_batchbuffer *batch = i965->batch;
2122 OUT_BATCH(batch, GEN6_3DSTATE_URB | (3 - 2));
2123 OUT_BATCH(batch, ((1 - 1) << GEN6_3DSTATE_URB_VS_SIZE_SHIFT) |
2124 (24 << GEN6_3DSTATE_URB_VS_ENTRIES_SHIFT)); /* at least 24 on GEN6 */
2125 OUT_BATCH(batch, (0 << GEN6_3DSTATE_URB_GS_SIZE_SHIFT) |
2126 (0 << GEN6_3DSTATE_URB_GS_ENTRIES_SHIFT)); /* no GS thread */
2130 gen6_emit_cc_state_pointers(VADriverContextP ctx)
2132 struct i965_driver_data *i965 = i965_driver_data(ctx);
2133 struct intel_batchbuffer *batch = i965->batch;
2134 struct i965_render_state *render_state = &i965->render_state;
2136 OUT_BATCH(batch, GEN6_3DSTATE_CC_STATE_POINTERS | (4 - 2));
2137 OUT_RELOC(batch, render_state->cc.blend, I915_GEM_DOMAIN_INSTRUCTION, 0, 1);
2138 OUT_RELOC(batch, render_state->cc.depth_stencil, I915_GEM_DOMAIN_INSTRUCTION, 0, 1);
2139 OUT_RELOC(batch, render_state->cc.state, I915_GEM_DOMAIN_INSTRUCTION, 0, 1);
2143 gen6_emit_sampler_state_pointers(VADriverContextP ctx)
2145 struct i965_driver_data *i965 = i965_driver_data(ctx);
2146 struct intel_batchbuffer *batch = i965->batch;
2147 struct i965_render_state *render_state = &i965->render_state;
2149 OUT_BATCH(batch, GEN6_3DSTATE_SAMPLER_STATE_POINTERS |
2150 GEN6_3DSTATE_SAMPLER_STATE_MODIFY_PS |
2152 OUT_BATCH(batch, 0); /* VS */
2153 OUT_BATCH(batch, 0); /* GS */
2154 OUT_RELOC(batch,render_state->wm.sampler, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
2158 gen6_emit_binding_table(VADriverContextP ctx)
2160 struct i965_driver_data *i965 = i965_driver_data(ctx);
2161 struct intel_batchbuffer *batch = i965->batch;
2163 /* Binding table pointers */
2164 OUT_BATCH(batch, CMD_BINDING_TABLE_POINTERS |
2165 GEN6_BINDING_TABLE_MODIFY_PS |
2167 OUT_BATCH(batch, 0); /* vs */
2168 OUT_BATCH(batch, 0); /* gs */
2169 /* Only the PS uses the binding table */
2170 OUT_BATCH(batch, BINDING_TABLE_OFFSET);
2174 gen6_emit_depth_buffer_state(VADriverContextP ctx)
2176 struct i965_driver_data *i965 = i965_driver_data(ctx);
2177 struct intel_batchbuffer *batch = i965->batch;
2179 OUT_BATCH(batch, CMD_DEPTH_BUFFER | (7 - 2));
2180 OUT_BATCH(batch, (I965_SURFACE_NULL << CMD_DEPTH_BUFFER_TYPE_SHIFT) |
2181 (I965_DEPTHFORMAT_D32_FLOAT << CMD_DEPTH_BUFFER_FORMAT_SHIFT));
2182 OUT_BATCH(batch, 0);
2183 OUT_BATCH(batch, 0);
2184 OUT_BATCH(batch, 0);
2185 OUT_BATCH(batch, 0);
2186 OUT_BATCH(batch, 0);
2188 OUT_BATCH(batch, CMD_CLEAR_PARAMS | (2 - 2));
2189 OUT_BATCH(batch, 0);
2193 gen6_emit_drawing_rectangle(VADriverContextP ctx)
2195 i965_render_drawing_rectangle(ctx);
2199 gen6_emit_vs_state(VADriverContextP ctx)
2201 struct i965_driver_data *i965 = i965_driver_data(ctx);
2202 struct intel_batchbuffer *batch = i965->batch;
2204 /* disable VS constant buffer */
2205 OUT_BATCH(batch, GEN6_3DSTATE_CONSTANT_VS | (5 - 2));
2206 OUT_BATCH(batch, 0);
2207 OUT_BATCH(batch, 0);
2208 OUT_BATCH(batch, 0);
2209 OUT_BATCH(batch, 0);
2211 OUT_BATCH(batch, GEN6_3DSTATE_VS | (6 - 2));
2212 OUT_BATCH(batch, 0); /* without VS kernel */
2213 OUT_BATCH(batch, 0);
2214 OUT_BATCH(batch, 0);
2215 OUT_BATCH(batch, 0);
2216 OUT_BATCH(batch, 0); /* pass-through */
2220 gen6_emit_gs_state(VADriverContextP ctx)
2222 struct i965_driver_data *i965 = i965_driver_data(ctx);
2223 struct intel_batchbuffer *batch = i965->batch;
2225 /* disable GS constant buffer */
2226 OUT_BATCH(batch, GEN6_3DSTATE_CONSTANT_GS | (5 - 2));
2227 OUT_BATCH(batch, 0);
2228 OUT_BATCH(batch, 0);
2229 OUT_BATCH(batch, 0);
2230 OUT_BATCH(batch, 0);
2232 OUT_BATCH(batch, GEN6_3DSTATE_GS | (7 - 2));
2233 OUT_BATCH(batch, 0); /* without GS kernel */
2234 OUT_BATCH(batch, 0);
2235 OUT_BATCH(batch, 0);
2236 OUT_BATCH(batch, 0);
2237 OUT_BATCH(batch, 0);
2238 OUT_BATCH(batch, 0); /* pass-through */
2242 gen6_emit_clip_state(VADriverContextP ctx)
2244 struct i965_driver_data *i965 = i965_driver_data(ctx);
2245 struct intel_batchbuffer *batch = i965->batch;
2247 OUT_BATCH(batch, GEN6_3DSTATE_CLIP | (4 - 2));
2248 OUT_BATCH(batch, 0);
2249 OUT_BATCH(batch, 0); /* pass-through */
2250 OUT_BATCH(batch, 0);
2254 gen6_emit_sf_state(VADriverContextP ctx)
2256 struct i965_driver_data *i965 = i965_driver_data(ctx);
2257 struct intel_batchbuffer *batch = i965->batch;
2259 OUT_BATCH(batch, GEN6_3DSTATE_SF | (20 - 2));
2260 OUT_BATCH(batch, (1 << GEN6_3DSTATE_SF_NUM_OUTPUTS_SHIFT) |
2261 (1 << GEN6_3DSTATE_SF_URB_ENTRY_READ_LENGTH_SHIFT) |
2262 (0 << GEN6_3DSTATE_SF_URB_ENTRY_READ_OFFSET_SHIFT));
2263 OUT_BATCH(batch, 0);
2264 OUT_BATCH(batch, GEN6_3DSTATE_SF_CULL_NONE);
2265 OUT_BATCH(batch, 2 << GEN6_3DSTATE_SF_TRIFAN_PROVOKE_SHIFT); /* DW4 */
2266 OUT_BATCH(batch, 0);
2267 OUT_BATCH(batch, 0);
2268 OUT_BATCH(batch, 0);
2269 OUT_BATCH(batch, 0);
2270 OUT_BATCH(batch, 0); /* DW9 */
2271 OUT_BATCH(batch, 0);
2272 OUT_BATCH(batch, 0);
2273 OUT_BATCH(batch, 0);
2274 OUT_BATCH(batch, 0);
2275 OUT_BATCH(batch, 0); /* DW14 */
2276 OUT_BATCH(batch, 0);
2277 OUT_BATCH(batch, 0);
2278 OUT_BATCH(batch, 0);
2279 OUT_BATCH(batch, 0);
2280 OUT_BATCH(batch, 0); /* DW19 */
2284 gen6_emit_wm_state(VADriverContextP ctx, int kernel)
2286 struct i965_driver_data *i965 = i965_driver_data(ctx);
2287 struct intel_batchbuffer *batch = i965->batch;
2288 struct i965_render_state *render_state = &i965->render_state;
2290 OUT_BATCH(batch, GEN6_3DSTATE_CONSTANT_PS |
2291 GEN6_3DSTATE_CONSTANT_BUFFER_0_ENABLE |
2294 render_state->curbe.bo,
2295 I915_GEM_DOMAIN_INSTRUCTION, 0,
2296 (URB_CS_ENTRY_SIZE-1));
2297 OUT_BATCH(batch, 0);
2298 OUT_BATCH(batch, 0);
2299 OUT_BATCH(batch, 0);
2301 OUT_BATCH(batch, GEN6_3DSTATE_WM | (9 - 2));
2302 OUT_RELOC(batch, render_state->render_kernels[kernel].bo,
2303 I915_GEM_DOMAIN_INSTRUCTION, 0,
2305 OUT_BATCH(batch, (1 << GEN6_3DSTATE_WM_SAMPLER_COUNT_SHITF) |
2306 (5 << GEN6_3DSTATE_WM_BINDING_TABLE_ENTRY_COUNT_SHIFT));
2307 OUT_BATCH(batch, 0);
2308 OUT_BATCH(batch, (6 << GEN6_3DSTATE_WM_DISPATCH_START_GRF_0_SHIFT)); /* DW4 */
2309 OUT_BATCH(batch, ((render_state->max_wm_threads - 1) << GEN6_3DSTATE_WM_MAX_THREADS_SHIFT) |
2310 GEN6_3DSTATE_WM_DISPATCH_ENABLE |
2311 GEN6_3DSTATE_WM_16_DISPATCH_ENABLE);
2312 OUT_BATCH(batch, (1 << GEN6_3DSTATE_WM_NUM_SF_OUTPUTS_SHIFT) |
2313 GEN6_3DSTATE_WM_PERSPECTIVE_PIXEL_BARYCENTRIC);
2314 OUT_BATCH(batch, 0);
2315 OUT_BATCH(batch, 0);
2319 gen6_emit_vertex_element_state(VADriverContextP ctx)
2321 struct i965_driver_data *i965 = i965_driver_data(ctx);
2322 struct intel_batchbuffer *batch = i965->batch;
2324 /* Set up our vertex elements, sourced from the single vertex buffer. */
2325 OUT_BATCH(batch, CMD_VERTEX_ELEMENTS | (5 - 2));
2326 /* offset 0: X,Y -> {X, Y, 1.0, 1.0} */
2327 OUT_BATCH(batch, (0 << GEN6_VE0_VERTEX_BUFFER_INDEX_SHIFT) |
2329 (I965_SURFACEFORMAT_R32G32_FLOAT << VE0_FORMAT_SHIFT) |
2330 (0 << VE0_OFFSET_SHIFT));
2331 OUT_BATCH(batch, (I965_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT) |
2332 (I965_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT) |
2333 (I965_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_2_SHIFT) |
2334 (I965_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT));
2335 /* offset 8: S0, T0 -> {S0, T0, 1.0, 1.0} */
2336 OUT_BATCH(batch, (0 << GEN6_VE0_VERTEX_BUFFER_INDEX_SHIFT) |
2338 (I965_SURFACEFORMAT_R32G32_FLOAT << VE0_FORMAT_SHIFT) |
2339 (8 << VE0_OFFSET_SHIFT));
2340 OUT_BATCH(batch, (I965_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT) |
2341 (I965_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT) |
2342 (I965_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_2_SHIFT) |
2343 (I965_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT));
2347 gen6_emit_vertices(VADriverContextP ctx)
2349 struct i965_driver_data *i965 = i965_driver_data(ctx);
2350 struct intel_batchbuffer *batch = i965->batch;
2351 struct i965_render_state *render_state = &i965->render_state;
2353 BEGIN_BATCH(batch, 11);
2354 OUT_BATCH(batch, CMD_VERTEX_BUFFERS | 3);
2356 (0 << GEN6_VB0_BUFFER_INDEX_SHIFT) |
2357 GEN6_VB0_VERTEXDATA |
2358 ((4 * 4) << VB0_BUFFER_PITCH_SHIFT));
2359 OUT_RELOC(batch, render_state->vb.vertex_buffer, I915_GEM_DOMAIN_VERTEX, 0, 0);
2360 OUT_RELOC(batch, render_state->vb.vertex_buffer, I915_GEM_DOMAIN_VERTEX, 0, 12 * 4);
2361 OUT_BATCH(batch, 0);
2365 _3DPRIMITIVE_VERTEX_SEQUENTIAL |
2366 (_3DPRIM_RECTLIST << _3DPRIMITIVE_TOPOLOGY_SHIFT) |
2369 OUT_BATCH(batch, 3); /* vertex count per instance */
2370 OUT_BATCH(batch, 0); /* start vertex offset */
2371 OUT_BATCH(batch, 1); /* single instance */
2372 OUT_BATCH(batch, 0); /* start instance location */
2373 OUT_BATCH(batch, 0); /* index buffer offset, ignored */
2374 ADVANCE_BATCH(batch);
2378 gen6_render_emit_states(VADriverContextP ctx, int kernel)
2380 struct i965_driver_data *i965 = i965_driver_data(ctx);
2381 struct intel_batchbuffer *batch = i965->batch;
2383 intel_batchbuffer_start_atomic(batch, 0x1000);
2384 intel_batchbuffer_emit_mi_flush(batch);
2385 gen6_emit_invarient_states(ctx);
2386 gen6_emit_state_base_address(ctx);
2387 gen6_emit_viewport_state_pointers(ctx);
2389 gen6_emit_cc_state_pointers(ctx);
2390 gen6_emit_sampler_state_pointers(ctx);
2391 gen6_emit_vs_state(ctx);
2392 gen6_emit_gs_state(ctx);
2393 gen6_emit_clip_state(ctx);
2394 gen6_emit_sf_state(ctx);
2395 gen6_emit_wm_state(ctx, kernel);
2396 gen6_emit_binding_table(ctx);
2397 gen6_emit_depth_buffer_state(ctx);
2398 gen6_emit_drawing_rectangle(ctx);
2399 gen6_emit_vertex_element_state(ctx);
2400 gen6_emit_vertices(ctx);
2401 intel_batchbuffer_end_atomic(batch);
2405 gen6_render_put_surface(
2406 VADriverContextP ctx,
2407 struct object_surface *obj_surface,
2408 const VARectangle *src_rect,
2409 const VARectangle *dst_rect,
2413 struct i965_driver_data *i965 = i965_driver_data(ctx);
2414 struct intel_batchbuffer *batch = i965->batch;
2416 gen6_render_initialize(ctx);
2417 gen6_render_setup_states(ctx, obj_surface, src_rect, dst_rect, flags);
2418 i965_clear_dest_region(ctx);
2419 gen6_render_emit_states(ctx, PS_KERNEL);
2420 intel_batchbuffer_flush(batch);
2424 gen6_subpicture_render_blend_state(VADriverContextP ctx)
2426 struct i965_driver_data *i965 = i965_driver_data(ctx);
2427 struct i965_render_state *render_state = &i965->render_state;
2428 struct gen6_blend_state *blend_state;
2430 dri_bo_unmap(render_state->cc.state);
2431 dri_bo_map(render_state->cc.blend, 1);
2432 assert(render_state->cc.blend->virtual);
2433 blend_state = render_state->cc.blend->virtual;
2434 memset(blend_state, 0, sizeof(*blend_state));
2435 blend_state->blend0.dest_blend_factor = I965_BLENDFACTOR_INV_SRC_ALPHA;
2436 blend_state->blend0.source_blend_factor = I965_BLENDFACTOR_SRC_ALPHA;
2437 blend_state->blend0.blend_func = I965_BLENDFUNCTION_ADD;
2438 blend_state->blend0.blend_enable = 1;
2439 blend_state->blend1.post_blend_clamp_enable = 1;
2440 blend_state->blend1.pre_blend_clamp_enable = 1;
2441 blend_state->blend1.clamp_range = 0; /* clamp range [0, 1] */
2442 dri_bo_unmap(render_state->cc.blend);
2446 gen6_subpicture_render_setup_states(
2447 VADriverContextP ctx,
2448 struct object_surface *obj_surface,
2449 const VARectangle *src_rect,
2450 const VARectangle *dst_rect
2453 i965_render_dest_surface_state(ctx, 0);
2454 i965_subpic_render_src_surfaces_state(ctx, obj_surface);
2455 i965_render_sampler(ctx);
2456 i965_render_cc_viewport(ctx);
2457 gen6_render_color_calc_state(ctx);
2458 gen6_subpicture_render_blend_state(ctx);
2459 gen6_render_depth_stencil_state(ctx);
2460 i965_subpic_render_upload_constants(ctx, obj_surface);
2461 i965_subpic_render_upload_vertex(ctx, obj_surface, dst_rect);
2465 gen6_render_put_subpicture(
2466 VADriverContextP ctx,
2467 struct object_surface *obj_surface,
2468 const VARectangle *src_rect,
2469 const VARectangle *dst_rect
2472 struct i965_driver_data *i965 = i965_driver_data(ctx);
2473 struct intel_batchbuffer *batch = i965->batch;
2474 unsigned int index = obj_surface->subpic_render_idx;
2475 struct object_subpic *obj_subpic = obj_surface->obj_subpic[index];
2478 gen6_render_initialize(ctx);
2479 gen6_subpicture_render_setup_states(ctx, obj_surface, src_rect, dst_rect);
2480 gen6_render_emit_states(ctx, PS_SUBPIC_KERNEL);
2481 i965_render_upload_image_palette(ctx, obj_subpic->obj_image, 0xff);
2482 intel_batchbuffer_flush(batch);
2489 gen7_render_initialize(VADriverContextP ctx)
2491 struct i965_driver_data *i965 = i965_driver_data(ctx);
2492 struct i965_render_state *render_state = &i965->render_state;
2497 dri_bo_unreference(render_state->vb.vertex_buffer);
2498 bo = dri_bo_alloc(i965->intel.bufmgr,
2503 render_state->vb.vertex_buffer = bo;
2506 dri_bo_unreference(render_state->wm.surface_state_binding_table_bo);
2507 bo = dri_bo_alloc(i965->intel.bufmgr,
2508 "surface state & binding table",
2509 (SURFACE_STATE_PADDED_SIZE + sizeof(unsigned int)) * MAX_RENDER_SURFACES,
2512 render_state->wm.surface_state_binding_table_bo = bo;
2514 dri_bo_unreference(render_state->wm.sampler);
2515 bo = dri_bo_alloc(i965->intel.bufmgr,
2517 MAX_SAMPLERS * sizeof(struct gen7_sampler_state),
2520 render_state->wm.sampler = bo;
2521 render_state->wm.sampler_count = 0;
2523 /* COLOR CALCULATOR */
2524 dri_bo_unreference(render_state->cc.state);
2525 bo = dri_bo_alloc(i965->intel.bufmgr,
2527 sizeof(struct gen6_color_calc_state),
2530 render_state->cc.state = bo;
2533 dri_bo_unreference(render_state->cc.viewport);
2534 bo = dri_bo_alloc(i965->intel.bufmgr,
2536 sizeof(struct i965_cc_viewport),
2539 render_state->cc.viewport = bo;
2542 dri_bo_unreference(render_state->cc.blend);
2543 size = sizeof(struct gen8_global_blend_state) + 2 * sizeof(struct gen8_blend_state_rt);
2544 bo = dri_bo_alloc(i965->intel.bufmgr,
2549 render_state->cc.blend = bo;
2551 /* DEPTH & STENCIL STATE */
2552 dri_bo_unreference(render_state->cc.depth_stencil);
2553 bo = dri_bo_alloc(i965->intel.bufmgr,
2554 "depth & stencil state",
2555 sizeof(struct gen6_depth_stencil_state),
2558 render_state->cc.depth_stencil = bo;
2565 gen8_render_initialize(VADriverContextP ctx)
2567 struct i965_driver_data *i965 = i965_driver_data(ctx);
2568 struct i965_render_state *render_state = &i965->render_state;
2571 unsigned int end_offset;
2574 dri_bo_unreference(render_state->vb.vertex_buffer);
2575 bo = dri_bo_alloc(i965->intel.bufmgr,
2580 render_state->vb.vertex_buffer = bo;
2583 dri_bo_unreference(render_state->wm.surface_state_binding_table_bo);
2584 bo = dri_bo_alloc(i965->intel.bufmgr,
2585 "surface state & binding table",
2586 (SURFACE_STATE_PADDED_SIZE + sizeof(unsigned int)) * MAX_RENDER_SURFACES,
2589 render_state->wm.surface_state_binding_table_bo = bo;
2591 render_state->curbe_size = 256;
2593 render_state->wm.sampler_count = 0;
2595 render_state->sampler_size = MAX_SAMPLERS * sizeof(struct gen8_sampler_state);
2597 render_state->cc_state_size = sizeof(struct gen6_color_calc_state);
2599 render_state->cc_viewport_size = sizeof(struct i965_cc_viewport);
2601 render_state->blend_state_size = sizeof(struct gen8_global_blend_state) +
2602 16 * sizeof(struct gen8_blend_state_rt);
2604 render_state->sf_clip_size = 1024;
2606 render_state->scissor_size = 1024;
2608 size = 4096 + render_state->curbe_size + render_state->sampler_size +
2609 render_state->cc_state_size + render_state->cc_viewport_size +
2610 render_state->blend_state_size + render_state->sf_clip_size +
2611 render_state->scissor_size;
2613 dri_bo_unreference(render_state->dynamic_state.bo);
2614 bo = dri_bo_alloc(i965->intel.bufmgr,
2619 render_state->dynamic_state.bo = bo;
2622 render_state->dynamic_state.end_offset = 0;
2624 /* Constant buffer offset */
2625 render_state->curbe_offset = ALIGN(end_offset, 64);
2626 end_offset += render_state->curbe_size;
2629 render_state->sampler_offset = ALIGN(end_offset, 64);
2630 end_offset += render_state->sampler_size;
2632 /* CC_VIEWPORT_state */
2633 render_state->cc_viewport_offset = ALIGN(end_offset, 64);
2634 end_offset += render_state->cc_viewport_size;
2636 /* CC_STATE_state */
2637 render_state->cc_state_offset = ALIGN(end_offset, 64);
2638 end_offset += render_state->cc_state_size;
2641 render_state->blend_state_offset = ALIGN(end_offset, 64);
2642 end_offset += render_state->blend_state_size;
2645 render_state->sf_clip_offset = ALIGN(end_offset, 64);
2646 end_offset += render_state->sf_clip_size;
2649 render_state->scissor_offset = ALIGN(end_offset, 64);
2650 end_offset += render_state->scissor_size;
2652 /* update the end offset of dynamic_state */
2653 render_state->dynamic_state.end_offset = ALIGN(end_offset, 64);
2658 gen7_render_color_calc_state(VADriverContextP ctx)
2660 struct i965_driver_data *i965 = i965_driver_data(ctx);
2661 struct i965_render_state *render_state = &i965->render_state;
2662 struct gen6_color_calc_state *color_calc_state;
2664 dri_bo_map(render_state->cc.state, 1);
2665 assert(render_state->cc.state->virtual);
2666 color_calc_state = render_state->cc.state->virtual;
2667 memset(color_calc_state, 0, sizeof(*color_calc_state));
2668 color_calc_state->constant_r = 1.0;
2669 color_calc_state->constant_g = 0.0;
2670 color_calc_state->constant_b = 1.0;
2671 color_calc_state->constant_a = 1.0;
2672 dri_bo_unmap(render_state->cc.state);
2676 gen7_render_blend_state(VADriverContextP ctx)
2678 struct i965_driver_data *i965 = i965_driver_data(ctx);
2679 struct i965_render_state *render_state = &i965->render_state;
2680 struct gen6_blend_state *blend_state;
2682 dri_bo_map(render_state->cc.blend, 1);
2683 assert(render_state->cc.blend->virtual);
2684 blend_state = render_state->cc.blend->virtual;
2685 memset(blend_state, 0, sizeof(*blend_state));
2686 blend_state->blend1.logic_op_enable = 1;
2687 blend_state->blend1.logic_op_func = 0xc;
2688 blend_state->blend1.pre_blend_clamp_enable = 1;
2689 dri_bo_unmap(render_state->cc.blend);
2693 gen7_render_depth_stencil_state(VADriverContextP ctx)
2695 struct i965_driver_data *i965 = i965_driver_data(ctx);
2696 struct i965_render_state *render_state = &i965->render_state;
2697 struct gen6_depth_stencil_state *depth_stencil_state;
2699 dri_bo_map(render_state->cc.depth_stencil, 1);
2700 assert(render_state->cc.depth_stencil->virtual);
2701 depth_stencil_state = render_state->cc.depth_stencil->virtual;
2702 memset(depth_stencil_state, 0, sizeof(*depth_stencil_state));
2703 dri_bo_unmap(render_state->cc.depth_stencil);
2707 gen7_render_sampler(VADriverContextP ctx)
2709 struct i965_driver_data *i965 = i965_driver_data(ctx);
2710 struct i965_render_state *render_state = &i965->render_state;
2711 struct gen7_sampler_state *sampler_state;
2714 assert(render_state->wm.sampler_count > 0);
2715 assert(render_state->wm.sampler_count <= MAX_SAMPLERS);
2717 dri_bo_map(render_state->wm.sampler, 1);
2718 assert(render_state->wm.sampler->virtual);
2719 sampler_state = render_state->wm.sampler->virtual;
2720 for (i = 0; i < render_state->wm.sampler_count; i++) {
2721 memset(sampler_state, 0, sizeof(*sampler_state));
2722 sampler_state->ss0.min_filter = I965_MAPFILTER_LINEAR;
2723 sampler_state->ss0.mag_filter = I965_MAPFILTER_LINEAR;
2724 sampler_state->ss3.r_wrap_mode = I965_TEXCOORDMODE_CLAMP;
2725 sampler_state->ss3.s_wrap_mode = I965_TEXCOORDMODE_CLAMP;
2726 sampler_state->ss3.t_wrap_mode = I965_TEXCOORDMODE_CLAMP;
2730 dri_bo_unmap(render_state->wm.sampler);
2734 gen8_render_sampler(VADriverContextP ctx)
2736 struct i965_driver_data *i965 = i965_driver_data(ctx);
2737 struct i965_render_state *render_state = &i965->render_state;
2738 struct gen8_sampler_state *sampler_state;
2740 unsigned char *cc_ptr;
2742 assert(render_state->wm.sampler_count > 0);
2743 assert(render_state->wm.sampler_count <= MAX_SAMPLERS);
2745 dri_bo_map(render_state->dynamic_state.bo, 1);
2746 assert(render_state->dynamic_state.bo->virtual);
2748 cc_ptr = (unsigned char *) render_state->dynamic_state.bo->virtual +
2749 render_state->sampler_offset;
2751 sampler_state = (struct gen8_sampler_state *) cc_ptr;
2753 for (i = 0; i < render_state->wm.sampler_count; i++) {
2754 memset(sampler_state, 0, sizeof(*sampler_state));
2755 sampler_state->ss0.min_filter = I965_MAPFILTER_LINEAR;
2756 sampler_state->ss0.mag_filter = I965_MAPFILTER_LINEAR;
2757 sampler_state->ss3.r_wrap_mode = I965_TEXCOORDMODE_CLAMP;
2758 sampler_state->ss3.s_wrap_mode = I965_TEXCOORDMODE_CLAMP;
2759 sampler_state->ss3.t_wrap_mode = I965_TEXCOORDMODE_CLAMP;
2763 dri_bo_unmap(render_state->dynamic_state.bo);
2768 gen7_render_setup_states(
2769 VADriverContextP ctx,
2770 struct object_surface *obj_surface,
2771 const VARectangle *src_rect,
2772 const VARectangle *dst_rect,
2776 i965_render_dest_surface_state(ctx, 0);
2777 i965_render_src_surfaces_state(ctx, obj_surface, flags);
2778 gen7_render_sampler(ctx);
2779 i965_render_cc_viewport(ctx);
2780 gen7_render_color_calc_state(ctx);
2781 gen7_render_blend_state(ctx);
2782 gen7_render_depth_stencil_state(ctx);
2783 i965_render_upload_constants(ctx, obj_surface, flags);
2784 i965_render_upload_vertex(ctx, obj_surface, src_rect, dst_rect);
2788 gen8_render_blend_state(VADriverContextP ctx)
2790 struct i965_driver_data *i965 = i965_driver_data(ctx);
2791 struct i965_render_state *render_state = &i965->render_state;
2792 struct gen8_global_blend_state *global_blend_state;
2793 struct gen8_blend_state_rt *blend_state;
2794 unsigned char *cc_ptr;
2796 dri_bo_map(render_state->dynamic_state.bo, 1);
2797 assert(render_state->dynamic_state.bo->virtual);
2799 cc_ptr = (unsigned char *) render_state->dynamic_state.bo->virtual +
2800 render_state->blend_state_offset;
2802 global_blend_state = (struct gen8_global_blend_state*) cc_ptr;
2804 memset(global_blend_state, 0, sizeof(*global_blend_state));
2805 /* Global blend state + blend_state for Render Target */
2806 blend_state = (struct gen8_blend_state_rt *)(global_blend_state + 1);
2807 blend_state->blend1.logic_op_enable = 1;
2808 blend_state->blend1.logic_op_func = 0xc;
2809 blend_state->blend1.pre_blend_clamp_enable = 1;
2811 dri_bo_unmap(render_state->dynamic_state.bo);
2816 gen8_render_cc_viewport(VADriverContextP ctx)
2818 struct i965_driver_data *i965 = i965_driver_data(ctx);
2819 struct i965_render_state *render_state = &i965->render_state;
2820 struct i965_cc_viewport *cc_viewport;
2821 unsigned char *cc_ptr;
2823 dri_bo_map(render_state->dynamic_state.bo, 1);
2824 assert(render_state->dynamic_state.bo->virtual);
2826 cc_ptr = (unsigned char *) render_state->dynamic_state.bo->virtual +
2827 render_state->cc_viewport_offset;
2829 cc_viewport = (struct i965_cc_viewport *) cc_ptr;
2831 memset(cc_viewport, 0, sizeof(*cc_viewport));
2833 cc_viewport->min_depth = -1.e35;
2834 cc_viewport->max_depth = 1.e35;
2836 dri_bo_unmap(render_state->dynamic_state.bo);
2840 gen8_render_color_calc_state(VADriverContextP ctx)
2842 struct i965_driver_data *i965 = i965_driver_data(ctx);
2843 struct i965_render_state *render_state = &i965->render_state;
2844 struct gen6_color_calc_state *color_calc_state;
2845 unsigned char *cc_ptr;
2847 dri_bo_map(render_state->dynamic_state.bo, 1);
2848 assert(render_state->dynamic_state.bo->virtual);
2850 cc_ptr = (unsigned char *) render_state->dynamic_state.bo->virtual +
2851 render_state->cc_state_offset;
2853 color_calc_state = (struct gen6_color_calc_state *) cc_ptr;
2855 memset(color_calc_state, 0, sizeof(*color_calc_state));
2856 color_calc_state->constant_r = 1.0;
2857 color_calc_state->constant_g = 0.0;
2858 color_calc_state->constant_b = 1.0;
2859 color_calc_state->constant_a = 1.0;
2860 dri_bo_unmap(render_state->dynamic_state.bo);
2864 gen8_render_upload_constants(VADriverContextP ctx,
2865 struct object_surface *obj_surface,
2868 struct i965_driver_data *i965 = i965_driver_data(ctx);
2869 struct i965_render_state *render_state = &i965->render_state;
2870 unsigned short *constant_buffer;
2871 unsigned char *cc_ptr;
2872 float *color_balance_base;
2873 float contrast = (float)i965->contrast_attrib->value / DEFAULT_CONTRAST;
2874 float brightness = (float)i965->brightness_attrib->value / 255; /* YUV is float in the shader */
2875 float hue = (float)i965->hue_attrib->value / 180 * PI;
2876 float saturation = (float)i965->saturation_attrib->value / DEFAULT_SATURATION;
2878 unsigned int color_flag;
2880 dri_bo_map(render_state->dynamic_state.bo, 1);
2881 assert(render_state->dynamic_state.bo->virtual);
2883 cc_ptr = (unsigned char *) render_state->dynamic_state.bo->virtual +
2884 render_state->curbe_offset;
2886 constant_buffer = (unsigned short *) cc_ptr;
2888 if (obj_surface->subsampling == SUBSAMPLE_YUV400) {
2889 assert(obj_surface->fourcc == VA_FOURCC('Y', '8', '0', '0'));
2891 *constant_buffer = 2;
2893 if (obj_surface->fourcc == VA_FOURCC('N', 'V', '1', '2'))
2894 *constant_buffer = 1;
2896 *constant_buffer = 0;
2899 if (i965->contrast_attrib->value == DEFAULT_CONTRAST &&
2900 i965->brightness_attrib->value == DEFAULT_BRIGHTNESS &&
2901 i965->hue_attrib->value == DEFAULT_HUE &&
2902 i965->saturation_attrib->value == DEFAULT_SATURATION)
2903 constant_buffer[1] = 1; /* skip color balance transformation */
2905 constant_buffer[1] = 0;
2907 color_balance_base = (float *)constant_buffer + 4;
2908 *color_balance_base++ = contrast;
2909 *color_balance_base++ = brightness;
2910 *color_balance_base++ = cos(hue) * contrast * saturation;
2911 *color_balance_base++ = sin(hue) * contrast * saturation;
2913 color_flag = flags & VA_SRC_COLOR_MASK;
2914 yuv_to_rgb = (float *)constant_buffer + 8;
2915 if (color_flag == VA_SRC_BT709)
2916 memcpy(yuv_to_rgb, yuv_to_rgb_bt709, sizeof(yuv_to_rgb_bt709));
2917 else if (color_flag == VA_SRC_SMPTE_240)
2918 memcpy(yuv_to_rgb, yuv_to_rgb_smpte_240, sizeof(yuv_to_rgb_smpte_240));
2920 memcpy(yuv_to_rgb, yuv_to_rgb_bt601, sizeof(yuv_to_rgb_bt601));
2922 dri_bo_unmap(render_state->dynamic_state.bo);
2926 gen8_render_setup_states(
2927 VADriverContextP ctx,
2928 struct object_surface *obj_surface,
2929 const VARectangle *src_rect,
2930 const VARectangle *dst_rect,
2934 i965_render_dest_surface_state(ctx, 0);
2935 i965_render_src_surfaces_state(ctx, obj_surface, flags);
2936 gen8_render_sampler(ctx);
2937 gen8_render_cc_viewport(ctx);
2938 gen8_render_color_calc_state(ctx);
2939 gen8_render_blend_state(ctx);
2940 gen8_render_upload_constants(ctx, obj_surface, flags);
2941 i965_render_upload_vertex(ctx, obj_surface, src_rect, dst_rect);
2945 gen7_emit_invarient_states(VADriverContextP ctx)
2947 struct i965_driver_data *i965 = i965_driver_data(ctx);
2948 struct intel_batchbuffer *batch = i965->batch;
2950 BEGIN_BATCH(batch, 1);
2951 OUT_BATCH(batch, CMD_PIPELINE_SELECT | PIPELINE_SELECT_3D);
2952 ADVANCE_BATCH(batch);
2954 BEGIN_BATCH(batch, 4);
2955 OUT_BATCH(batch, GEN6_3DSTATE_MULTISAMPLE | (4 - 2));
2956 OUT_BATCH(batch, GEN6_3DSTATE_MULTISAMPLE_PIXEL_LOCATION_CENTER |
2957 GEN6_3DSTATE_MULTISAMPLE_NUMSAMPLES_1); /* 1 sample/pixel */
2958 OUT_BATCH(batch, 0);
2959 OUT_BATCH(batch, 0);
2960 ADVANCE_BATCH(batch);
2962 BEGIN_BATCH(batch, 2);
2963 OUT_BATCH(batch, GEN6_3DSTATE_SAMPLE_MASK | (2 - 2));
2964 OUT_BATCH(batch, 1);
2965 ADVANCE_BATCH(batch);
2967 /* Set system instruction pointer */
2968 BEGIN_BATCH(batch, 2);
2969 OUT_BATCH(batch, CMD_STATE_SIP | 0);
2970 OUT_BATCH(batch, 0);
2971 ADVANCE_BATCH(batch);
2975 gen7_emit_state_base_address(VADriverContextP ctx)
2977 struct i965_driver_data *i965 = i965_driver_data(ctx);
2978 struct intel_batchbuffer *batch = i965->batch;
2979 struct i965_render_state *render_state = &i965->render_state;
2981 OUT_BATCH(batch, CMD_STATE_BASE_ADDRESS | (10 - 2));
2982 OUT_BATCH(batch, BASE_ADDRESS_MODIFY); /* General state base address */
2983 OUT_RELOC(batch, render_state->wm.surface_state_binding_table_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, BASE_ADDRESS_MODIFY); /* Surface state base address */
2984 OUT_BATCH(batch, BASE_ADDRESS_MODIFY); /* Dynamic state base address */
2985 OUT_BATCH(batch, BASE_ADDRESS_MODIFY); /* Indirect object base address */
2986 OUT_BATCH(batch, BASE_ADDRESS_MODIFY); /* Instruction base address */
2987 OUT_BATCH(batch, BASE_ADDRESS_MODIFY); /* General state upper bound */
2988 OUT_BATCH(batch, BASE_ADDRESS_MODIFY); /* Dynamic state upper bound */
2989 OUT_BATCH(batch, BASE_ADDRESS_MODIFY); /* Indirect object upper bound */
2990 OUT_BATCH(batch, BASE_ADDRESS_MODIFY); /* Instruction access upper bound */
2994 gen8_emit_state_base_address(VADriverContextP ctx)
2996 struct i965_driver_data *i965 = i965_driver_data(ctx);
2997 struct intel_batchbuffer *batch = i965->batch;
2998 struct i965_render_state *render_state = &i965->render_state;
3000 BEGIN_BATCH(batch, 16);
3001 OUT_BATCH(batch, CMD_STATE_BASE_ADDRESS | (16 - 2));
3002 OUT_BATCH(batch, BASE_ADDRESS_MODIFY); /* General state base address */
3003 OUT_BATCH(batch, 0);
3004 OUT_BATCH(batch, 0);
3006 OUT_RELOC(batch, render_state->wm.surface_state_binding_table_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, BASE_ADDRESS_MODIFY); /* Surface state base address */
3007 OUT_BATCH(batch, 0);
3010 /* Dynamic state base address */
3011 OUT_RELOC(batch, render_state->dynamic_state.bo, I915_GEM_DOMAIN_RENDER | I915_GEM_DOMAIN_SAMPLER,
3012 0, BASE_ADDRESS_MODIFY);
3013 OUT_BATCH(batch, 0);
3016 OUT_BATCH(batch, BASE_ADDRESS_MODIFY); /* Indirect object base address */
3017 OUT_BATCH(batch, 0);
3020 /* Instruction base address */
3021 OUT_RELOC(batch, render_state->instruction_state.bo, I915_GEM_DOMAIN_INSTRUCTION, 0, BASE_ADDRESS_MODIFY);
3022 OUT_BATCH(batch, 0);
3025 OUT_BATCH(batch, 0xFFFF0000 | BASE_ADDRESS_MODIFY); /* General state upper bound */
3026 OUT_BATCH(batch, 0xFFFF0000 | BASE_ADDRESS_MODIFY); /* Dynamic state upper bound */
3027 OUT_BATCH(batch, 0xFFFF0000 | BASE_ADDRESS_MODIFY); /* Indirect object upper bound */
3028 OUT_BATCH(batch, 0xFFFF0000 | BASE_ADDRESS_MODIFY); /* Instruction access upper bound */
3029 ADVANCE_BATCH(batch);
3033 gen7_emit_viewport_state_pointers(VADriverContextP ctx)
3035 struct i965_driver_data *i965 = i965_driver_data(ctx);
3036 struct intel_batchbuffer *batch = i965->batch;
3037 struct i965_render_state *render_state = &i965->render_state;
3039 BEGIN_BATCH(batch, 2);
3040 OUT_BATCH(batch, GEN7_3DSTATE_VIEWPORT_STATE_POINTERS_CC | (2 - 2));
3042 render_state->cc.viewport,
3043 I915_GEM_DOMAIN_INSTRUCTION, 0,
3045 ADVANCE_BATCH(batch);
3047 BEGIN_BATCH(batch, 2);
3048 OUT_BATCH(batch, GEN7_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CL | (2 - 2));
3049 OUT_BATCH(batch, 0);
3050 ADVANCE_BATCH(batch);
3054 * URB layout on GEN7
3055 * ----------------------------------------
3056 * | PS Push Constants (8KB) | VS entries |
3057 * ----------------------------------------
3060 gen7_emit_urb(VADriverContextP ctx)
3062 struct i965_driver_data *i965 = i965_driver_data(ctx);
3063 struct intel_batchbuffer *batch = i965->batch;
3064 unsigned int num_urb_entries = 32;
3066 if (IS_HASWELL(i965->intel.device_id))
3067 num_urb_entries = 64;
3069 BEGIN_BATCH(batch, 2);
3070 OUT_BATCH(batch, GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_PS | (2 - 2));
3071 OUT_BATCH(batch, 8); /* in 1KBs */
3072 ADVANCE_BATCH(batch);
3074 BEGIN_BATCH(batch, 2);
3075 OUT_BATCH(batch, GEN7_3DSTATE_URB_VS | (2 - 2));
3077 (num_urb_entries << GEN7_URB_ENTRY_NUMBER_SHIFT) |
3078 (2 - 1) << GEN7_URB_ENTRY_SIZE_SHIFT |
3079 (1 << GEN7_URB_STARTING_ADDRESS_SHIFT));
3080 ADVANCE_BATCH(batch);
3082 BEGIN_BATCH(batch, 2);
3083 OUT_BATCH(batch, GEN7_3DSTATE_URB_GS | (2 - 2));
3085 (0 << GEN7_URB_ENTRY_SIZE_SHIFT) |
3086 (1 << GEN7_URB_STARTING_ADDRESS_SHIFT));
3087 ADVANCE_BATCH(batch);
3089 BEGIN_BATCH(batch, 2);
3090 OUT_BATCH(batch, GEN7_3DSTATE_URB_HS | (2 - 2));
3092 (0 << GEN7_URB_ENTRY_SIZE_SHIFT) |
3093 (2 << GEN7_URB_STARTING_ADDRESS_SHIFT));
3094 ADVANCE_BATCH(batch);
3096 BEGIN_BATCH(batch, 2);
3097 OUT_BATCH(batch, GEN7_3DSTATE_URB_DS | (2 - 2));
3099 (0 << GEN7_URB_ENTRY_SIZE_SHIFT) |
3100 (2 << GEN7_URB_STARTING_ADDRESS_SHIFT));
3101 ADVANCE_BATCH(batch);
3105 gen7_emit_cc_state_pointers(VADriverContextP ctx)
3107 struct i965_driver_data *i965 = i965_driver_data(ctx);
3108 struct intel_batchbuffer *batch = i965->batch;
3109 struct i965_render_state *render_state = &i965->render_state;
3111 BEGIN_BATCH(batch, 2);
3112 OUT_BATCH(batch, GEN6_3DSTATE_CC_STATE_POINTERS | (2 - 2));
3114 render_state->cc.state,
3115 I915_GEM_DOMAIN_INSTRUCTION, 0,
3117 ADVANCE_BATCH(batch);
3119 BEGIN_BATCH(batch, 2);
3120 OUT_BATCH(batch, GEN7_3DSTATE_BLEND_STATE_POINTERS | (2 - 2));
3122 render_state->cc.blend,
3123 I915_GEM_DOMAIN_INSTRUCTION, 0,
3125 ADVANCE_BATCH(batch);
3127 BEGIN_BATCH(batch, 2);
3128 OUT_BATCH(batch, GEN7_3DSTATE_DEPTH_STENCIL_STATE_POINTERS | (2 - 2));
3130 render_state->cc.depth_stencil,
3131 I915_GEM_DOMAIN_INSTRUCTION, 0,
3133 ADVANCE_BATCH(batch);
3137 gen8_emit_cc_state_pointers(VADriverContextP ctx)
3139 struct i965_driver_data *i965 = i965_driver_data(ctx);
3140 struct intel_batchbuffer *batch = i965->batch;
3141 struct i965_render_state *render_state = &i965->render_state;
3143 BEGIN_BATCH(batch, 2);
3144 OUT_BATCH(batch, GEN6_3DSTATE_CC_STATE_POINTERS | (2 - 2));
3145 OUT_BATCH(batch, (render_state->cc_state_offset + 1));
3146 ADVANCE_BATCH(batch);
3148 BEGIN_BATCH(batch, 2);
3149 OUT_BATCH(batch, GEN7_3DSTATE_BLEND_STATE_POINTERS | (2 - 2));
3150 OUT_BATCH(batch, (render_state->blend_state_offset + 1));
3151 ADVANCE_BATCH(batch);
3156 gen7_emit_sampler_state_pointers(VADriverContextP ctx)
3158 struct i965_driver_data *i965 = i965_driver_data(ctx);
3159 struct intel_batchbuffer *batch = i965->batch;
3160 struct i965_render_state *render_state = &i965->render_state;
3162 BEGIN_BATCH(batch, 2);
3163 OUT_BATCH(batch, GEN7_3DSTATE_SAMPLER_STATE_POINTERS_PS | (2 - 2));
3165 render_state->wm.sampler,
3166 I915_GEM_DOMAIN_INSTRUCTION, 0,
3168 ADVANCE_BATCH(batch);
3172 gen7_emit_binding_table(VADriverContextP ctx)
3174 struct i965_driver_data *i965 = i965_driver_data(ctx);
3175 struct intel_batchbuffer *batch = i965->batch;
3177 BEGIN_BATCH(batch, 2);
3178 OUT_BATCH(batch, GEN7_3DSTATE_BINDING_TABLE_POINTERS_PS | (2 - 2));
3179 OUT_BATCH(batch, BINDING_TABLE_OFFSET);
3180 ADVANCE_BATCH(batch);
3184 gen7_emit_depth_buffer_state(VADriverContextP ctx)
3186 struct i965_driver_data *i965 = i965_driver_data(ctx);
3187 struct intel_batchbuffer *batch = i965->batch;
3189 BEGIN_BATCH(batch, 7);
3190 OUT_BATCH(batch, GEN7_3DSTATE_DEPTH_BUFFER | (7 - 2));
3192 (I965_DEPTHFORMAT_D32_FLOAT << 18) |
3193 (I965_SURFACE_NULL << 29));
3194 OUT_BATCH(batch, 0);
3195 OUT_BATCH(batch, 0);
3196 OUT_BATCH(batch, 0);
3197 OUT_BATCH(batch, 0);
3198 OUT_BATCH(batch, 0);
3199 ADVANCE_BATCH(batch);
3201 BEGIN_BATCH(batch, 3);
3202 OUT_BATCH(batch, GEN7_3DSTATE_CLEAR_PARAMS | (3 - 2));
3203 OUT_BATCH(batch, 0);
3204 OUT_BATCH(batch, 0);
3205 ADVANCE_BATCH(batch);
3209 gen7_emit_drawing_rectangle(VADriverContextP ctx)
3211 i965_render_drawing_rectangle(ctx);
3215 gen7_emit_vs_state(VADriverContextP ctx)
3217 struct i965_driver_data *i965 = i965_driver_data(ctx);
3218 struct intel_batchbuffer *batch = i965->batch;
3220 /* disable VS constant buffer */
3221 OUT_BATCH(batch, GEN6_3DSTATE_CONSTANT_VS | (7 - 2));
3222 OUT_BATCH(batch, 0);
3223 OUT_BATCH(batch, 0);
3224 OUT_BATCH(batch, 0);
3225 OUT_BATCH(batch, 0);
3226 OUT_BATCH(batch, 0);
3227 OUT_BATCH(batch, 0);
3229 OUT_BATCH(batch, GEN6_3DSTATE_VS | (6 - 2));
3230 OUT_BATCH(batch, 0); /* without VS kernel */
3231 OUT_BATCH(batch, 0);
3232 OUT_BATCH(batch, 0);
3233 OUT_BATCH(batch, 0);
3234 OUT_BATCH(batch, 0); /* pass-through */
3238 gen7_emit_bypass_state(VADriverContextP ctx)
3240 struct i965_driver_data *i965 = i965_driver_data(ctx);
3241 struct intel_batchbuffer *batch = i965->batch;
3244 BEGIN_BATCH(batch, 7);
3245 OUT_BATCH(batch, GEN6_3DSTATE_CONSTANT_GS | (7 - 2));
3246 OUT_BATCH(batch, 0);
3247 OUT_BATCH(batch, 0);
3248 OUT_BATCH(batch, 0);
3249 OUT_BATCH(batch, 0);
3250 OUT_BATCH(batch, 0);
3251 OUT_BATCH(batch, 0);
3252 ADVANCE_BATCH(batch);
3254 BEGIN_BATCH(batch, 7);
3255 OUT_BATCH(batch, GEN6_3DSTATE_GS | (7 - 2));
3256 OUT_BATCH(batch, 0); /* without GS kernel */
3257 OUT_BATCH(batch, 0);
3258 OUT_BATCH(batch, 0);
3259 OUT_BATCH(batch, 0);
3260 OUT_BATCH(batch, 0);
3261 OUT_BATCH(batch, 0); /* pass-through */
3262 ADVANCE_BATCH(batch);
3264 BEGIN_BATCH(batch, 2);
3265 OUT_BATCH(batch, GEN7_3DSTATE_BINDING_TABLE_POINTERS_GS | (2 - 2));
3266 OUT_BATCH(batch, 0);
3267 ADVANCE_BATCH(batch);
3270 BEGIN_BATCH(batch, 7);
3271 OUT_BATCH(batch, GEN7_3DSTATE_CONSTANT_HS | (7 - 2));
3272 OUT_BATCH(batch, 0);
3273 OUT_BATCH(batch, 0);
3274 OUT_BATCH(batch, 0);
3275 OUT_BATCH(batch, 0);
3276 OUT_BATCH(batch, 0);
3277 OUT_BATCH(batch, 0);
3278 ADVANCE_BATCH(batch);
3280 BEGIN_BATCH(batch, 7);
3281 OUT_BATCH(batch, GEN7_3DSTATE_HS | (7 - 2));
3282 OUT_BATCH(batch, 0);
3283 OUT_BATCH(batch, 0);
3284 OUT_BATCH(batch, 0);
3285 OUT_BATCH(batch, 0);
3286 OUT_BATCH(batch, 0);
3287 OUT_BATCH(batch, 0);
3288 ADVANCE_BATCH(batch);
3290 BEGIN_BATCH(batch, 2);
3291 OUT_BATCH(batch, GEN7_3DSTATE_BINDING_TABLE_POINTERS_HS | (2 - 2));
3292 OUT_BATCH(batch, 0);
3293 ADVANCE_BATCH(batch);
3296 BEGIN_BATCH(batch, 4);
3297 OUT_BATCH(batch, GEN7_3DSTATE_TE | (4 - 2));
3298 OUT_BATCH(batch, 0);
3299 OUT_BATCH(batch, 0);
3300 OUT_BATCH(batch, 0);
3301 ADVANCE_BATCH(batch);
3304 BEGIN_BATCH(batch, 7);
3305 OUT_BATCH(batch, GEN7_3DSTATE_CONSTANT_DS | (7 - 2));
3306 OUT_BATCH(batch, 0);
3307 OUT_BATCH(batch, 0);
3308 OUT_BATCH(batch, 0);
3309 OUT_BATCH(batch, 0);
3310 OUT_BATCH(batch, 0);
3311 OUT_BATCH(batch, 0);
3312 ADVANCE_BATCH(batch);
3314 BEGIN_BATCH(batch, 6);
3315 OUT_BATCH(batch, GEN7_3DSTATE_DS | (6 - 2));
3316 OUT_BATCH(batch, 0);
3317 OUT_BATCH(batch, 0);
3318 OUT_BATCH(batch, 0);
3319 OUT_BATCH(batch, 0);
3320 OUT_BATCH(batch, 0);
3321 ADVANCE_BATCH(batch);
3323 BEGIN_BATCH(batch, 2);
3324 OUT_BATCH(batch, GEN7_3DSTATE_BINDING_TABLE_POINTERS_DS | (2 - 2));
3325 OUT_BATCH(batch, 0);
3326 ADVANCE_BATCH(batch);
3328 /* Disable STREAMOUT */
3329 BEGIN_BATCH(batch, 3);
3330 OUT_BATCH(batch, GEN7_3DSTATE_STREAMOUT | (3 - 2));
3331 OUT_BATCH(batch, 0);
3332 OUT_BATCH(batch, 0);
3333 ADVANCE_BATCH(batch);
3337 gen7_emit_clip_state(VADriverContextP ctx)
3339 struct i965_driver_data *i965 = i965_driver_data(ctx);
3340 struct intel_batchbuffer *batch = i965->batch;
3342 OUT_BATCH(batch, GEN6_3DSTATE_CLIP | (4 - 2));
3343 OUT_BATCH(batch, 0);
3344 OUT_BATCH(batch, 0); /* pass-through */
3345 OUT_BATCH(batch, 0);
3349 gen7_emit_sf_state(VADriverContextP ctx)
3351 struct i965_driver_data *i965 = i965_driver_data(ctx);
3352 struct intel_batchbuffer *batch = i965->batch;
3354 BEGIN_BATCH(batch, 14);
3355 OUT_BATCH(batch, GEN7_3DSTATE_SBE | (14 - 2));
3357 (1 << GEN7_SBE_NUM_OUTPUTS_SHIFT) |
3358 (1 << GEN7_SBE_URB_ENTRY_READ_LENGTH_SHIFT) |
3359 (0 << GEN7_SBE_URB_ENTRY_READ_OFFSET_SHIFT));
3360 OUT_BATCH(batch, 0);
3361 OUT_BATCH(batch, 0);
3362 OUT_BATCH(batch, 0); /* DW4 */
3363 OUT_BATCH(batch, 0);
3364 OUT_BATCH(batch, 0);
3365 OUT_BATCH(batch, 0);
3366 OUT_BATCH(batch, 0);
3367 OUT_BATCH(batch, 0); /* DW9 */
3368 OUT_BATCH(batch, 0);
3369 OUT_BATCH(batch, 0);
3370 OUT_BATCH(batch, 0);
3371 OUT_BATCH(batch, 0);
3372 ADVANCE_BATCH(batch);
3374 BEGIN_BATCH(batch, 7);
3375 OUT_BATCH(batch, GEN6_3DSTATE_SF | (7 - 2));
3376 OUT_BATCH(batch, 0);
3377 OUT_BATCH(batch, GEN6_3DSTATE_SF_CULL_NONE);
3378 OUT_BATCH(batch, 2 << GEN6_3DSTATE_SF_TRIFAN_PROVOKE_SHIFT);
3379 OUT_BATCH(batch, 0);
3380 OUT_BATCH(batch, 0);
3381 OUT_BATCH(batch, 0);
3382 ADVANCE_BATCH(batch);
3386 gen7_emit_wm_state(VADriverContextP ctx, int kernel)
3388 struct i965_driver_data *i965 = i965_driver_data(ctx);
3389 struct intel_batchbuffer *batch = i965->batch;
3390 struct i965_render_state *render_state = &i965->render_state;
3391 unsigned int max_threads_shift = GEN7_PS_MAX_THREADS_SHIFT_IVB;
3392 unsigned int num_samples = 0;
3394 if (IS_HASWELL(i965->intel.device_id)) {
3395 max_threads_shift = GEN7_PS_MAX_THREADS_SHIFT_HSW;
3396 num_samples = 1 << GEN7_PS_SAMPLE_MASK_SHIFT_HSW;
3399 BEGIN_BATCH(batch, 3);
3400 OUT_BATCH(batch, GEN6_3DSTATE_WM | (3 - 2));
3402 GEN7_WM_DISPATCH_ENABLE |
3403 GEN7_WM_PERSPECTIVE_PIXEL_BARYCENTRIC);
3404 OUT_BATCH(batch, 0);
3405 ADVANCE_BATCH(batch);
3407 BEGIN_BATCH(batch, 7);
3408 OUT_BATCH(batch, GEN6_3DSTATE_CONSTANT_PS | (7 - 2));
3409 OUT_BATCH(batch, URB_CS_ENTRY_SIZE);
3410 OUT_BATCH(batch, 0);
3412 render_state->curbe.bo,
3413 I915_GEM_DOMAIN_INSTRUCTION, 0,
3415 OUT_BATCH(batch, 0);
3416 OUT_BATCH(batch, 0);
3417 OUT_BATCH(batch, 0);
3418 ADVANCE_BATCH(batch);
3420 BEGIN_BATCH(batch, 8);
3421 OUT_BATCH(batch, GEN7_3DSTATE_PS | (8 - 2));
3423 render_state->render_kernels[kernel].bo,
3424 I915_GEM_DOMAIN_INSTRUCTION, 0,
3427 (1 << GEN7_PS_SAMPLER_COUNT_SHIFT) |
3428 (5 << GEN7_PS_BINDING_TABLE_ENTRY_COUNT_SHIFT));
3429 OUT_BATCH(batch, 0); /* scratch space base offset */
3431 ((render_state->max_wm_threads - 1) << max_threads_shift) | num_samples |
3432 GEN7_PS_PUSH_CONSTANT_ENABLE |
3433 GEN7_PS_ATTRIBUTE_ENABLE |
3434 GEN7_PS_16_DISPATCH_ENABLE);
3436 (6 << GEN7_PS_DISPATCH_START_GRF_SHIFT_0));
3437 OUT_BATCH(batch, 0); /* kernel 1 pointer */
3438 OUT_BATCH(batch, 0); /* kernel 2 pointer */
3439 ADVANCE_BATCH(batch);
3443 gen7_emit_vertex_element_state(VADriverContextP ctx)
3445 struct i965_driver_data *i965 = i965_driver_data(ctx);
3446 struct intel_batchbuffer *batch = i965->batch;
3448 /* Set up our vertex elements, sourced from the single vertex buffer. */
3449 OUT_BATCH(batch, CMD_VERTEX_ELEMENTS | (5 - 2));
3450 /* offset 0: X,Y -> {X, Y, 1.0, 1.0} */
3451 OUT_BATCH(batch, (0 << GEN6_VE0_VERTEX_BUFFER_INDEX_SHIFT) |
3453 (I965_SURFACEFORMAT_R32G32_FLOAT << VE0_FORMAT_SHIFT) |
3454 (0 << VE0_OFFSET_SHIFT));
3455 OUT_BATCH(batch, (I965_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT) |
3456 (I965_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT) |
3457 (I965_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_2_SHIFT) |
3458 (I965_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT));
3459 /* offset 8: S0, T0 -> {S0, T0, 1.0, 1.0} */
3460 OUT_BATCH(batch, (0 << GEN6_VE0_VERTEX_BUFFER_INDEX_SHIFT) |
3462 (I965_SURFACEFORMAT_R32G32_FLOAT << VE0_FORMAT_SHIFT) |
3463 (8 << VE0_OFFSET_SHIFT));
3464 OUT_BATCH(batch, (I965_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT) |
3465 (I965_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT) |
3466 (I965_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_2_SHIFT) |
3467 (I965_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT));
3471 gen7_emit_vertices(VADriverContextP ctx)
3473 struct i965_driver_data *i965 = i965_driver_data(ctx);
3474 struct intel_batchbuffer *batch = i965->batch;
3475 struct i965_render_state *render_state = &i965->render_state;
3477 BEGIN_BATCH(batch, 5);
3478 OUT_BATCH(batch, CMD_VERTEX_BUFFERS | (5 - 2));
3480 (0 << GEN6_VB0_BUFFER_INDEX_SHIFT) |
3481 GEN6_VB0_VERTEXDATA |
3482 GEN7_VB0_ADDRESS_MODIFYENABLE |
3483 ((4 * 4) << VB0_BUFFER_PITCH_SHIFT));
3484 OUT_RELOC(batch, render_state->vb.vertex_buffer, I915_GEM_DOMAIN_VERTEX, 0, 0);
3485 OUT_RELOC(batch, render_state->vb.vertex_buffer, I915_GEM_DOMAIN_VERTEX, 0, 12 * 4);
3486 OUT_BATCH(batch, 0);
3487 ADVANCE_BATCH(batch);
3489 BEGIN_BATCH(batch, 7);
3490 OUT_BATCH(batch, CMD_3DPRIMITIVE | (7 - 2));
3493 GEN7_3DPRIM_VERTEXBUFFER_ACCESS_SEQUENTIAL);
3494 OUT_BATCH(batch, 3); /* vertex count per instance */
3495 OUT_BATCH(batch, 0); /* start vertex offset */
3496 OUT_BATCH(batch, 1); /* single instance */
3497 OUT_BATCH(batch, 0); /* start instance location */
3498 OUT_BATCH(batch, 0);
3499 ADVANCE_BATCH(batch);
3503 gen7_render_emit_states(VADriverContextP ctx, int kernel)
3505 struct i965_driver_data *i965 = i965_driver_data(ctx);
3506 struct intel_batchbuffer *batch = i965->batch;
3508 intel_batchbuffer_start_atomic(batch, 0x1000);
3509 intel_batchbuffer_emit_mi_flush(batch);
3510 gen7_emit_invarient_states(ctx);
3511 gen7_emit_state_base_address(ctx);
3512 gen7_emit_viewport_state_pointers(ctx);
3514 gen7_emit_cc_state_pointers(ctx);
3515 gen7_emit_sampler_state_pointers(ctx);
3516 gen7_emit_bypass_state(ctx);
3517 gen7_emit_vs_state(ctx);
3518 gen7_emit_clip_state(ctx);
3519 gen7_emit_sf_state(ctx);
3520 gen7_emit_wm_state(ctx, kernel);
3521 gen7_emit_binding_table(ctx);
3522 gen7_emit_depth_buffer_state(ctx);
3523 gen7_emit_drawing_rectangle(ctx);
3524 gen7_emit_vertex_element_state(ctx);
3525 gen7_emit_vertices(ctx);
3526 intel_batchbuffer_end_atomic(batch);
3530 gen8_emit_vertices(VADriverContextP ctx)
3532 struct i965_driver_data *i965 = i965_driver_data(ctx);
3533 struct intel_batchbuffer *batch = i965->batch;
3534 struct i965_render_state *render_state = &i965->render_state;
3536 BEGIN_BATCH(batch, 5);
3537 OUT_BATCH(batch, CMD_VERTEX_BUFFERS | (5 - 2));
3539 (0 << GEN8_VB0_BUFFER_INDEX_SHIFT) |
3540 (0 << GEN8_VB0_MOCS_SHIFT) |
3541 GEN7_VB0_ADDRESS_MODIFYENABLE |
3542 ((4 * 4) << VB0_BUFFER_PITCH_SHIFT));
3543 OUT_RELOC(batch, render_state->vb.vertex_buffer, I915_GEM_DOMAIN_VERTEX, 0, 0);
3544 OUT_BATCH(batch, 0);
3545 OUT_BATCH(batch, 12 * 4);
3546 ADVANCE_BATCH(batch);
3548 /* Topology in 3D primitive is overrided by VF_TOPOLOGY command */
3549 BEGIN_BATCH(batch, 2);
3550 OUT_BATCH(batch, GEN8_3DSTATE_VF_TOPOLOGY | (2 - 2));
3553 ADVANCE_BATCH(batch);
3556 BEGIN_BATCH(batch, 7);
3557 OUT_BATCH(batch, CMD_3DPRIMITIVE | (7 - 2));
3559 GEN7_3DPRIM_VERTEXBUFFER_ACCESS_SEQUENTIAL);
3560 OUT_BATCH(batch, 3); /* vertex count per instance */
3561 OUT_BATCH(batch, 0); /* start vertex offset */
3562 OUT_BATCH(batch, 1); /* single instance */
3563 OUT_BATCH(batch, 0); /* start instance location */
3564 OUT_BATCH(batch, 0);
3565 ADVANCE_BATCH(batch);
3569 gen8_emit_vertex_element_state(VADriverContextP ctx)
3571 struct i965_driver_data *i965 = i965_driver_data(ctx);
3572 struct intel_batchbuffer *batch = i965->batch;
3576 * dword 0-3: pad (0, 0, 0. 0)
3577 * dword 4-7: position (x, y, 1.0, 1.0),
3578 * dword 8-11: texture coordinate 0 (u0, v0, 1.0, 1.0)
3581 /* Set up our vertex elements, sourced from the single vertex buffer. */
3582 OUT_BATCH(batch, CMD_VERTEX_ELEMENTS | (7 - 2));
3584 /* Element state 0. These are 4 dwords of 0 required for the VUE format.
3585 * We don't really know or care what they do.
3588 OUT_BATCH(batch, (0 << GEN8_VE0_VERTEX_BUFFER_INDEX_SHIFT) |
3590 (I965_SURFACEFORMAT_R32G32_FLOAT << VE0_FORMAT_SHIFT) |
3591 (0 << VE0_OFFSET_SHIFT));
3592 OUT_BATCH(batch, (I965_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_0_SHIFT) |
3593 (I965_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_1_SHIFT) |
3594 (I965_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_2_SHIFT) |
3595 (I965_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_3_SHIFT));
3597 /* offset 8: X, Y -> {x, y, 1.0, 1.0} */
3598 OUT_BATCH(batch, (0 << GEN8_VE0_VERTEX_BUFFER_INDEX_SHIFT) |
3600 (I965_SURFACEFORMAT_R32G32_FLOAT << VE0_FORMAT_SHIFT) |
3601 (8 << VE0_OFFSET_SHIFT));
3602 OUT_BATCH(batch, (I965_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT) |
3603 (I965_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT) |
3604 (I965_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_2_SHIFT) |
3605 (I965_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT));
3607 /* offset 0: u,v -> {U, V, 1.0, 1.0} */
3608 OUT_BATCH(batch, (0 << GEN8_VE0_VERTEX_BUFFER_INDEX_SHIFT) |
3610 (I965_SURFACEFORMAT_R32G32_FLOAT << VE0_FORMAT_SHIFT) |
3611 (0 << VE0_OFFSET_SHIFT));
3612 OUT_BATCH(batch, (I965_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT) |
3613 (I965_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT) |
3614 (I965_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_2_SHIFT) |
3615 (I965_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT));
3619 gen8_emit_vs_state(VADriverContextP ctx)
3621 struct i965_driver_data *i965 = i965_driver_data(ctx);
3622 struct intel_batchbuffer *batch = i965->batch;
3624 /* disable VS constant buffer */
3625 BEGIN_BATCH(batch, 11);
3626 OUT_BATCH(batch, GEN6_3DSTATE_CONSTANT_VS | (11 - 2));
3627 OUT_BATCH(batch, 0);
3628 OUT_BATCH(batch, 0);
3630 OUT_BATCH(batch, 0);
3631 OUT_BATCH(batch, 0);
3633 OUT_BATCH(batch, 0);
3634 OUT_BATCH(batch, 0);
3636 OUT_BATCH(batch, 0);
3637 OUT_BATCH(batch, 0);
3639 OUT_BATCH(batch, 0);
3640 OUT_BATCH(batch, 0);
3641 ADVANCE_BATCH(batch);
3643 BEGIN_BATCH(batch, 9);
3644 OUT_BATCH(batch, GEN6_3DSTATE_VS | (9 - 2));
3645 OUT_BATCH(batch, 0); /* without VS kernel */
3646 OUT_BATCH(batch, 0);
3647 /* VS shader dispatch flag */
3648 OUT_BATCH(batch, 0);
3649 OUT_BATCH(batch, 0);
3650 OUT_BATCH(batch, 0);
3651 /* DW6. VS shader GRF and URB buffer definition */
3652 OUT_BATCH(batch, 0);
3653 OUT_BATCH(batch, 0); /* pass-through */
3654 OUT_BATCH(batch, 0);
3655 ADVANCE_BATCH(batch);
3657 BEGIN_BATCH(batch, 2);
3658 OUT_BATCH(batch, GEN7_3DSTATE_BINDING_TABLE_POINTERS_VS | (2 - 2));
3659 OUT_BATCH(batch, 0);
3660 ADVANCE_BATCH(batch);
3662 BEGIN_BATCH(batch, 2);
3663 OUT_BATCH(batch, GEN7_3DSTATE_SAMPLER_STATE_POINTERS_VS | (2 - 2));
3664 OUT_BATCH(batch, 0);
3665 ADVANCE_BATCH(batch);
3670 * URB layout on GEN8
3671 * ----------------------------------------
3672 * | PS Push Constants (8KB) | VS entries |
3673 * ----------------------------------------
3676 gen8_emit_urb(VADriverContextP ctx)
3678 struct i965_driver_data *i965 = i965_driver_data(ctx);
3679 struct intel_batchbuffer *batch = i965->batch;
3680 unsigned int num_urb_entries = 64;
3682 /* The minimum urb entries is 64 */
3684 BEGIN_BATCH(batch, 2);
3685 OUT_BATCH(batch, GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_VS | (2 - 2));
3686 OUT_BATCH(batch, 0);
3687 ADVANCE_BATCH(batch);
3689 BEGIN_BATCH(batch, 2);
3690 OUT_BATCH(batch, GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_DS | (2 - 2));
3691 OUT_BATCH(batch, 0);
3692 ADVANCE_BATCH(batch);
3694 BEGIN_BATCH(batch, 2);
3695 OUT_BATCH(batch, GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_HS | (2 - 2));
3696 OUT_BATCH(batch, 0);
3697 ADVANCE_BATCH(batch);
3699 BEGIN_BATCH(batch, 2);
3700 OUT_BATCH(batch, GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_GS | (2 - 2));
3701 OUT_BATCH(batch, 0);
3702 ADVANCE_BATCH(batch);
3704 /* Size is 8Kbs and base address is 0Kb */
3705 BEGIN_BATCH(batch, 2);
3706 OUT_BATCH(batch, GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_PS | (2 - 2));
3707 /* Size is 8Kbs and base address is 0Kb */
3709 (0 << GEN8_PUSH_CONSTANT_BUFFER_OFFSET_SHIFT) |
3710 (8 << GEN8_PUSH_CONSTANT_BUFFER_SIZE_SHIFT));
3711 ADVANCE_BATCH(batch);
3713 BEGIN_BATCH(batch, 2);
3714 OUT_BATCH(batch, GEN7_3DSTATE_URB_VS | (2 - 2));
3716 (num_urb_entries << GEN7_URB_ENTRY_NUMBER_SHIFT) |
3717 (4 - 1) << GEN7_URB_ENTRY_SIZE_SHIFT |
3718 (1 << GEN7_URB_STARTING_ADDRESS_SHIFT));
3719 ADVANCE_BATCH(batch);
3721 BEGIN_BATCH(batch, 2);
3722 OUT_BATCH(batch, GEN7_3DSTATE_URB_GS | (2 - 2));
3724 (0 << GEN7_URB_ENTRY_SIZE_SHIFT) |
3725 (5 << GEN7_URB_STARTING_ADDRESS_SHIFT));
3726 ADVANCE_BATCH(batch);
3728 BEGIN_BATCH(batch, 2);
3729 OUT_BATCH(batch, GEN7_3DSTATE_URB_HS | (2 - 2));
3731 (0 << GEN7_URB_ENTRY_SIZE_SHIFT) |
3732 (6 << GEN7_URB_STARTING_ADDRESS_SHIFT));
3733 ADVANCE_BATCH(batch);
3735 BEGIN_BATCH(batch, 2);
3736 OUT_BATCH(batch, GEN7_3DSTATE_URB_DS | (2 - 2));
3738 (0 << GEN7_URB_ENTRY_SIZE_SHIFT) |
3739 (7 << GEN7_URB_STARTING_ADDRESS_SHIFT));
3740 ADVANCE_BATCH(batch);
3744 gen8_emit_bypass_state(VADriverContextP ctx)
3746 struct i965_driver_data *i965 = i965_driver_data(ctx);
3747 struct intel_batchbuffer *batch = i965->batch;
3750 BEGIN_BATCH(batch, 11);
3751 OUT_BATCH(batch, GEN6_3DSTATE_CONSTANT_GS | (11 - 2));
3752 OUT_BATCH(batch, 0);
3753 OUT_BATCH(batch, 0);
3754 OUT_BATCH(batch, 0);
3755 OUT_BATCH(batch, 0);
3756 OUT_BATCH(batch, 0);
3757 OUT_BATCH(batch, 0);
3758 OUT_BATCH(batch, 0);
3759 OUT_BATCH(batch, 0);
3760 OUT_BATCH(batch, 0);
3761 OUT_BATCH(batch, 0);
3762 ADVANCE_BATCH(batch);
3764 BEGIN_BATCH(batch, 10);
3765 OUT_BATCH(batch, GEN6_3DSTATE_GS | (10 - 2));
3766 /* GS shader address */
3767 OUT_BATCH(batch, 0); /* without GS kernel */
3768 OUT_BATCH(batch, 0);
3769 /* DW3. GS shader dispatch flag */
3770 OUT_BATCH(batch, 0);
3771 OUT_BATCH(batch, 0);
3772 OUT_BATCH(batch, 0);
3773 /* DW6. GS shader GRF and URB offset/length */
3774 OUT_BATCH(batch, 0);
3775 OUT_BATCH(batch, 0); /* pass-through */
3776 OUT_BATCH(batch, 0);
3777 OUT_BATCH(batch, 0);
3778 ADVANCE_BATCH(batch);
3780 BEGIN_BATCH(batch, 2);
3781 OUT_BATCH(batch, GEN7_3DSTATE_BINDING_TABLE_POINTERS_GS | (2 - 2));
3782 OUT_BATCH(batch, 0);
3783 ADVANCE_BATCH(batch);
3785 BEGIN_BATCH(batch, 2);
3786 OUT_BATCH(batch, GEN7_3DSTATE_SAMPLER_STATE_POINTERS_GS | (2 - 2));
3787 OUT_BATCH(batch, 0);
3788 ADVANCE_BATCH(batch);
3791 BEGIN_BATCH(batch, 11);
3792 OUT_BATCH(batch, GEN7_3DSTATE_CONSTANT_HS | (11 - 2));
3793 OUT_BATCH(batch, 0);
3794 OUT_BATCH(batch, 0);
3795 OUT_BATCH(batch, 0);
3796 OUT_BATCH(batch, 0);
3797 OUT_BATCH(batch, 0);
3798 OUT_BATCH(batch, 0);
3799 OUT_BATCH(batch, 0);
3800 OUT_BATCH(batch, 0);
3801 OUT_BATCH(batch, 0);
3802 OUT_BATCH(batch, 0);
3803 ADVANCE_BATCH(batch);
3805 BEGIN_BATCH(batch, 9);
3806 OUT_BATCH(batch, GEN7_3DSTATE_HS | (9 - 2));
3807 OUT_BATCH(batch, 0);
3808 /*DW2. HS pass-through */
3809 OUT_BATCH(batch, 0);
3810 /*DW3. HS shader address */
3811 OUT_BATCH(batch, 0);
3812 OUT_BATCH(batch, 0);
3813 /*DW5. HS shader flag. URB offset/length and so on */
3814 OUT_BATCH(batch, 0);
3815 OUT_BATCH(batch, 0);
3816 OUT_BATCH(batch, 0);
3817 OUT_BATCH(batch, 0);
3818 ADVANCE_BATCH(batch);
3820 BEGIN_BATCH(batch, 2);
3821 OUT_BATCH(batch, GEN7_3DSTATE_BINDING_TABLE_POINTERS_HS | (2 - 2));
3822 OUT_BATCH(batch, 0);
3823 ADVANCE_BATCH(batch);
3825 BEGIN_BATCH(batch, 2);
3826 OUT_BATCH(batch, GEN7_3DSTATE_SAMPLER_STATE_POINTERS_HS | (2 - 2));
3827 OUT_BATCH(batch, 0);
3828 ADVANCE_BATCH(batch);
3831 BEGIN_BATCH(batch, 4);
3832 OUT_BATCH(batch, GEN7_3DSTATE_TE | (4 - 2));
3833 OUT_BATCH(batch, 0);
3834 OUT_BATCH(batch, 0);
3835 OUT_BATCH(batch, 0);
3836 ADVANCE_BATCH(batch);
3839 BEGIN_BATCH(batch, 11);
3840 OUT_BATCH(batch, GEN7_3DSTATE_CONSTANT_DS | (11 - 2));
3841 OUT_BATCH(batch, 0);
3842 OUT_BATCH(batch, 0);
3843 OUT_BATCH(batch, 0);
3844 OUT_BATCH(batch, 0);
3845 OUT_BATCH(batch, 0);
3846 OUT_BATCH(batch, 0);
3847 OUT_BATCH(batch, 0);
3848 OUT_BATCH(batch, 0);
3849 OUT_BATCH(batch, 0);
3850 OUT_BATCH(batch, 0);
3851 ADVANCE_BATCH(batch);
3853 BEGIN_BATCH(batch, 9);
3854 OUT_BATCH(batch, GEN7_3DSTATE_DS | (9 - 2));
3855 /* DW1. DS shader pointer */
3856 OUT_BATCH(batch, 0);
3857 OUT_BATCH(batch, 0);
3858 /* DW3-5. DS shader dispatch flag.*/
3859 OUT_BATCH(batch, 0);
3860 OUT_BATCH(batch, 0);
3861 OUT_BATCH(batch, 0);
3862 /* DW6-7. DS shader pass-through, GRF,URB offset/Length,Thread Number*/
3863 OUT_BATCH(batch, 0);
3864 OUT_BATCH(batch, 0);
3865 /* DW8. DS shader output URB */
3866 OUT_BATCH(batch, 0);
3867 ADVANCE_BATCH(batch);
3869 BEGIN_BATCH(batch, 2);
3870 OUT_BATCH(batch, GEN7_3DSTATE_BINDING_TABLE_POINTERS_DS | (2 - 2));
3871 OUT_BATCH(batch, 0);
3872 ADVANCE_BATCH(batch);
3874 BEGIN_BATCH(batch, 2);
3875 OUT_BATCH(batch, GEN7_3DSTATE_SAMPLER_STATE_POINTERS_DS | (2 - 2));
3876 OUT_BATCH(batch, 0);
3877 ADVANCE_BATCH(batch);
3879 /* Disable STREAMOUT */
3880 BEGIN_BATCH(batch, 5);
3881 OUT_BATCH(batch, GEN7_3DSTATE_STREAMOUT | (5 - 2));
3882 OUT_BATCH(batch, 0);
3883 OUT_BATCH(batch, 0);
3884 OUT_BATCH(batch, 0);
3885 OUT_BATCH(batch, 0);
3886 ADVANCE_BATCH(batch);
3890 gen8_emit_invarient_states(VADriverContextP ctx)
3892 struct i965_driver_data *i965 = i965_driver_data(ctx);
3893 struct intel_batchbuffer *batch = i965->batch;
3895 BEGIN_BATCH(batch, 1);
3896 OUT_BATCH(batch, CMD_PIPELINE_SELECT | PIPELINE_SELECT_3D);
3897 ADVANCE_BATCH(batch);
3899 BEGIN_BATCH(batch, 2);
3900 OUT_BATCH(batch, GEN8_3DSTATE_MULTISAMPLE | (2 - 2));
3901 OUT_BATCH(batch, GEN6_3DSTATE_MULTISAMPLE_PIXEL_LOCATION_CENTER |
3902 GEN6_3DSTATE_MULTISAMPLE_NUMSAMPLES_1); /* 1 sample/pixel */
3903 ADVANCE_BATCH(batch);
3905 /* Update 3D Multisample pattern */
3906 BEGIN_BATCH(batch, 9);
3907 OUT_BATCH(batch, GEN8_3DSTATE_SAMPLE_PATTERN | (9 - 2));
3908 OUT_BATCH(batch, 0);
3909 OUT_BATCH(batch, 0);
3910 OUT_BATCH(batch, 0);
3911 OUT_BATCH(batch, 0);
3912 OUT_BATCH(batch, 0);
3913 OUT_BATCH(batch, 0);
3914 OUT_BATCH(batch, 0);
3915 OUT_BATCH(batch, 0);
3916 ADVANCE_BATCH(batch);
3919 BEGIN_BATCH(batch, 2);
3920 OUT_BATCH(batch, GEN6_3DSTATE_SAMPLE_MASK | (2 - 2));
3921 OUT_BATCH(batch, 1);
3922 ADVANCE_BATCH(batch);
3924 /* Set system instruction pointer */
3925 BEGIN_BATCH(batch, 3);
3926 OUT_BATCH(batch, CMD_STATE_SIP | 0);
3927 OUT_BATCH(batch, 0);
3928 OUT_BATCH(batch, 0);
3929 ADVANCE_BATCH(batch);
3933 gen8_emit_clip_state(VADriverContextP ctx)
3935 struct i965_driver_data *i965 = i965_driver_data(ctx);
3936 struct intel_batchbuffer *batch = i965->batch;
3938 OUT_BATCH(batch, GEN6_3DSTATE_CLIP | (4 - 2));
3939 OUT_BATCH(batch, 0);
3940 OUT_BATCH(batch, 0); /* pass-through */
3941 OUT_BATCH(batch, 0);
3945 gen8_emit_sf_state(VADriverContextP ctx)
3947 struct i965_driver_data *i965 = i965_driver_data(ctx);
3948 struct intel_batchbuffer *batch = i965->batch;
3950 BEGIN_BATCH(batch, 5);
3951 OUT_BATCH(batch, GEN8_3DSTATE_RASTER | (5 - 2));
3952 OUT_BATCH(batch, GEN8_3DSTATE_RASTER_CULL_NONE);
3953 OUT_BATCH(batch, 0);
3954 OUT_BATCH(batch, 0);
3955 OUT_BATCH(batch, 0);
3956 ADVANCE_BATCH(batch);
3959 BEGIN_BATCH(batch, 4);
3960 OUT_BATCH(batch, GEN7_3DSTATE_SBE | (4 - 2));
3962 (GEN8_SBE_FORCE_URB_ENTRY_READ_LENGTH) |
3963 (GEN8_SBE_FORCE_URB_ENTRY_READ_OFFSET) |
3964 (1 << GEN7_SBE_NUM_OUTPUTS_SHIFT) |
3965 (1 << GEN7_SBE_URB_ENTRY_READ_LENGTH_SHIFT) |
3966 (1 << GEN8_SBE_URB_ENTRY_READ_OFFSET_SHIFT));
3967 OUT_BATCH(batch, 0);
3968 OUT_BATCH(batch, 0);
3969 ADVANCE_BATCH(batch);
3971 /* SBE for backend setup */
3972 BEGIN_BATCH(batch, 11);
3973 OUT_BATCH(batch, GEN8_3DSTATE_SBE_SWIZ | (11 - 2));
3974 OUT_BATCH(batch, 0);
3975 OUT_BATCH(batch, 0);
3976 OUT_BATCH(batch, 0);
3977 OUT_BATCH(batch, 0);
3978 OUT_BATCH(batch, 0);
3979 OUT_BATCH(batch, 0);
3980 OUT_BATCH(batch, 0);
3981 OUT_BATCH(batch, 0);
3982 OUT_BATCH(batch, 0);
3983 OUT_BATCH(batch, 0);
3984 ADVANCE_BATCH(batch);
3986 BEGIN_BATCH(batch, 4);
3987 OUT_BATCH(batch, GEN6_3DSTATE_SF | (4 - 2));
3988 OUT_BATCH(batch, 0);
3989 OUT_BATCH(batch, 0);
3990 OUT_BATCH(batch, 2 << GEN6_3DSTATE_SF_TRIFAN_PROVOKE_SHIFT);
3991 ADVANCE_BATCH(batch);
3995 gen8_emit_wm_state(VADriverContextP ctx, int kernel)
3997 struct i965_driver_data *i965 = i965_driver_data(ctx);
3998 struct intel_batchbuffer *batch = i965->batch;
3999 struct i965_render_state *render_state = &i965->render_state;
4000 unsigned int num_samples = 0;
4001 unsigned int max_threads;
4003 max_threads = render_state->max_wm_threads - 2;
4005 BEGIN_BATCH(batch, 2);
4006 OUT_BATCH(batch, GEN8_3DSTATE_PSEXTRA | (2 - 2));
4008 (GEN8_PSX_PIXEL_SHADER_VALID | GEN8_PSX_ATTRIBUTE_ENABLE));
4009 ADVANCE_BATCH(batch);
4012 if (kernel == PS_KERNEL) {
4013 BEGIN_BATCH(batch, 2);
4014 OUT_BATCH(batch, GEN8_3DSTATE_PSBLEND | (2 - 2));
4016 GEN8_PS_BLEND_HAS_WRITEABLE_RT);
4017 ADVANCE_BATCH(batch);
4018 } else if (kernel == PS_SUBPIC_KERNEL) {
4019 BEGIN_BATCH(batch, 2);
4020 OUT_BATCH(batch, GEN8_3DSTATE_PSBLEND | (2 - 2));
4022 (GEN8_PS_BLEND_HAS_WRITEABLE_RT |
4023 GEN8_PS_BLEND_COLOR_BUFFER_BLEND_ENABLE |
4024 (I965_BLENDFACTOR_SRC_ALPHA << GEN8_PS_BLEND_SRC_ALPHA_BLEND_FACTOR_SHIFT) |
4025 (I965_BLENDFACTOR_INV_SRC_ALPHA << GEN8_PS_BLEND_DST_ALPHA_BLEND_FACTOR_SHIFT) |
4026 (I965_BLENDFACTOR_SRC_ALPHA << GEN8_PS_BLEND_SRC_BLEND_FACTOR_SHIFT) |
4027 (I965_BLENDFACTOR_INV_SRC_ALPHA << GEN8_PS_BLEND_DST_BLEND_FACTOR_SHIFT)));
4028 ADVANCE_BATCH(batch);
4031 BEGIN_BATCH(batch, 2);
4032 OUT_BATCH(batch, GEN6_3DSTATE_WM | (2 - 2));
4034 GEN7_WM_PERSPECTIVE_PIXEL_BARYCENTRIC);
4035 ADVANCE_BATCH(batch);
4037 BEGIN_BATCH(batch, 11);
4038 OUT_BATCH(batch, GEN6_3DSTATE_CONSTANT_PS | (11 - 2));
4039 OUT_BATCH(batch, URB_CS_ENTRY_SIZE);
4040 OUT_BATCH(batch, 0);
4041 /*DW3-4. Constant buffer 0 */
4042 OUT_BATCH(batch, render_state->curbe_offset);
4043 OUT_BATCH(batch, 0);
4045 /*DW5-10. Constant buffer 1-3 */
4046 OUT_BATCH(batch, 0);
4047 OUT_BATCH(batch, 0);
4048 OUT_BATCH(batch, 0);
4049 OUT_BATCH(batch, 0);
4050 OUT_BATCH(batch, 0);
4051 OUT_BATCH(batch, 0);
4052 ADVANCE_BATCH(batch);
4054 BEGIN_BATCH(batch, 12);
4055 OUT_BATCH(batch, GEN7_3DSTATE_PS | (12 - 2));
4056 /* PS shader address */
4057 OUT_BATCH(batch, render_state->render_kernels[kernel].kernel_offset);
4059 OUT_BATCH(batch, 0);
4060 /* DW3. PS shader flag .Binding table cnt/sample cnt */
4062 (1 << GEN7_PS_SAMPLER_COUNT_SHIFT) |
4063 (5 << GEN7_PS_BINDING_TABLE_ENTRY_COUNT_SHIFT));
4064 /* DW4-5. Scatch space */
4065 OUT_BATCH(batch, 0); /* scratch space base offset */
4066 OUT_BATCH(batch, 0);
4067 /* DW6. PS shader threads. */
4069 ((max_threads - 1) << GEN8_PS_MAX_THREADS_SHIFT) | num_samples |
4070 GEN7_PS_PUSH_CONSTANT_ENABLE |
4071 GEN7_PS_16_DISPATCH_ENABLE);
4072 /* DW7. PS shader GRF */
4074 (6 << GEN7_PS_DISPATCH_START_GRF_SHIFT_0));
4075 OUT_BATCH(batch, 0); /* kernel 1 pointer */
4076 OUT_BATCH(batch, 0);
4077 OUT_BATCH(batch, 0); /* kernel 2 pointer */
4078 OUT_BATCH(batch, 0);
4079 ADVANCE_BATCH(batch);
4081 BEGIN_BATCH(batch, 2);
4082 OUT_BATCH(batch, GEN7_3DSTATE_BINDING_TABLE_POINTERS_PS | (2 - 2));
4083 OUT_BATCH(batch, BINDING_TABLE_OFFSET);
4084 ADVANCE_BATCH(batch);
4088 gen8_emit_depth_buffer_state(VADriverContextP ctx)
4090 struct i965_driver_data *i965 = i965_driver_data(ctx);
4091 struct intel_batchbuffer *batch = i965->batch;
4093 BEGIN_BATCH(batch, 8);
4094 OUT_BATCH(batch, GEN7_3DSTATE_DEPTH_BUFFER | (8 - 2));
4096 (I965_DEPTHFORMAT_D32_FLOAT << 18) |
4097 (I965_SURFACE_NULL << 29));
4098 /* DW2-3. Depth Buffer Address */
4099 OUT_BATCH(batch, 0);
4100 OUT_BATCH(batch, 0);
4101 /* DW4-7. Surface structure */
4102 OUT_BATCH(batch, 0);
4103 OUT_BATCH(batch, 0);
4104 OUT_BATCH(batch, 0);
4105 OUT_BATCH(batch, 0);
4106 ADVANCE_BATCH(batch);
4108 /* Update the Hier Depth buffer */
4109 BEGIN_BATCH(batch, 5);
4110 OUT_BATCH(batch, GEN7_3DSTATE_HIER_DEPTH_BUFFER | (5 - 2));
4111 OUT_BATCH(batch, 0);
4112 OUT_BATCH(batch, 0);
4113 OUT_BATCH(batch, 0);
4114 OUT_BATCH(batch, 0);
4115 ADVANCE_BATCH(batch);
4117 /* Update the stencil buffer */
4118 BEGIN_BATCH(batch, 5);
4119 OUT_BATCH(batch, GEN7_3DSTATE_STENCIL_BUFFER | (5 - 2));
4120 OUT_BATCH(batch, 0);
4121 OUT_BATCH(batch, 0);
4122 OUT_BATCH(batch, 0);
4123 OUT_BATCH(batch, 0);
4124 ADVANCE_BATCH(batch);
4126 BEGIN_BATCH(batch, 3);
4127 OUT_BATCH(batch, GEN7_3DSTATE_CLEAR_PARAMS | (3 - 2));
4128 OUT_BATCH(batch, 0);
4129 OUT_BATCH(batch, 0);
4130 ADVANCE_BATCH(batch);
4134 gen8_emit_depth_stencil_state(VADriverContextP ctx)
4136 struct i965_driver_data *i965 = i965_driver_data(ctx);
4137 struct intel_batchbuffer *batch = i965->batch;
4139 BEGIN_BATCH(batch, 3);
4140 OUT_BATCH(batch, GEN8_3DSTATE_WM_DEPTH_STENCIL | (3 - 2));
4141 OUT_BATCH(batch, 0);
4142 OUT_BATCH(batch, 0);
4143 ADVANCE_BATCH(batch);
4147 gen8_emit_wm_hz_op(VADriverContextP ctx)
4149 struct i965_driver_data *i965 = i965_driver_data(ctx);
4150 struct intel_batchbuffer *batch = i965->batch;
4152 BEGIN_BATCH(batch, 5);
4153 OUT_BATCH(batch, GEN8_3DSTATE_WM_HZ_OP | (5 - 2));
4154 OUT_BATCH(batch, 0);
4155 OUT_BATCH(batch, 0);
4156 OUT_BATCH(batch, 0);
4157 OUT_BATCH(batch, 0);
4158 ADVANCE_BATCH(batch);
4162 gen8_emit_viewport_state_pointers(VADriverContextP ctx)
4164 struct i965_driver_data *i965 = i965_driver_data(ctx);
4165 struct intel_batchbuffer *batch = i965->batch;
4166 struct i965_render_state *render_state = &i965->render_state;
4168 BEGIN_BATCH(batch, 2);
4169 OUT_BATCH(batch, GEN7_3DSTATE_VIEWPORT_STATE_POINTERS_CC | (2 - 2));
4170 OUT_BATCH(batch, render_state->cc_viewport_offset);
4171 ADVANCE_BATCH(batch);
4173 BEGIN_BATCH(batch, 2);
4174 OUT_BATCH(batch, GEN7_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CL | (2 - 2));
4175 OUT_BATCH(batch, 0);
4176 ADVANCE_BATCH(batch);
4180 gen8_emit_sampler_state_pointers(VADriverContextP ctx)
4182 struct i965_driver_data *i965 = i965_driver_data(ctx);
4183 struct intel_batchbuffer *batch = i965->batch;
4184 struct i965_render_state *render_state = &i965->render_state;
4186 BEGIN_BATCH(batch, 2);
4187 OUT_BATCH(batch, GEN7_3DSTATE_SAMPLER_STATE_POINTERS_PS | (2 - 2));
4188 OUT_BATCH(batch, render_state->sampler_offset);
4189 ADVANCE_BATCH(batch);
4194 gen8_render_emit_states(VADriverContextP ctx, int kernel)
4196 struct i965_driver_data *i965 = i965_driver_data(ctx);
4197 struct intel_batchbuffer *batch = i965->batch;
4199 intel_batchbuffer_start_atomic(batch, 0x1000);
4200 intel_batchbuffer_emit_mi_flush(batch);
4201 gen8_emit_invarient_states(ctx);
4202 gen8_emit_state_base_address(ctx);
4203 gen8_emit_viewport_state_pointers(ctx);
4205 gen8_emit_cc_state_pointers(ctx);
4206 gen8_emit_sampler_state_pointers(ctx);
4207 gen8_emit_wm_hz_op(ctx);
4208 gen8_emit_bypass_state(ctx);
4209 gen8_emit_vs_state(ctx);
4210 gen8_emit_clip_state(ctx);
4211 gen8_emit_sf_state(ctx);
4212 gen8_emit_depth_stencil_state(ctx);
4213 gen8_emit_wm_state(ctx, kernel);
4214 gen8_emit_depth_buffer_state(ctx);
4215 gen7_emit_drawing_rectangle(ctx);
4216 gen8_emit_vertex_element_state(ctx);
4217 gen8_emit_vertices(ctx);
4218 intel_batchbuffer_end_atomic(batch);
4222 gen7_render_put_surface(
4223 VADriverContextP ctx,
4224 struct object_surface *obj_surface,
4225 const VARectangle *src_rect,
4226 const VARectangle *dst_rect,
4230 struct i965_driver_data *i965 = i965_driver_data(ctx);
4231 struct intel_batchbuffer *batch = i965->batch;
4233 gen7_render_initialize(ctx);
4234 gen7_render_setup_states(ctx, obj_surface, src_rect, dst_rect, flags);
4235 i965_clear_dest_region(ctx);
4236 gen7_render_emit_states(ctx, PS_KERNEL);
4237 intel_batchbuffer_flush(batch);
4241 gen8_render_put_surface(
4242 VADriverContextP ctx,
4243 struct object_surface *obj_surface,
4244 const VARectangle *src_rect,
4245 const VARectangle *dst_rect,
4249 struct i965_driver_data *i965 = i965_driver_data(ctx);
4250 struct intel_batchbuffer *batch = i965->batch;
4252 gen8_render_initialize(ctx);
4253 gen8_render_setup_states(ctx, obj_surface, src_rect, dst_rect, flags);
4254 gen8_clear_dest_region(ctx);
4255 gen8_render_emit_states(ctx, PS_KERNEL);
4256 intel_batchbuffer_flush(batch);
4260 gen7_subpicture_render_blend_state(VADriverContextP ctx)
4262 struct i965_driver_data *i965 = i965_driver_data(ctx);
4263 struct i965_render_state *render_state = &i965->render_state;
4264 struct gen6_blend_state *blend_state;
4266 dri_bo_unmap(render_state->cc.state);
4267 dri_bo_map(render_state->cc.blend, 1);
4268 assert(render_state->cc.blend->virtual);
4269 blend_state = render_state->cc.blend->virtual;
4270 memset(blend_state, 0, sizeof(*blend_state));
4271 blend_state->blend0.dest_blend_factor = I965_BLENDFACTOR_INV_SRC_ALPHA;
4272 blend_state->blend0.source_blend_factor = I965_BLENDFACTOR_SRC_ALPHA;
4273 blend_state->blend0.blend_func = I965_BLENDFUNCTION_ADD;
4274 blend_state->blend0.blend_enable = 1;
4275 blend_state->blend1.post_blend_clamp_enable = 1;
4276 blend_state->blend1.pre_blend_clamp_enable = 1;
4277 blend_state->blend1.clamp_range = 0; /* clamp range [0, 1] */
4278 dri_bo_unmap(render_state->cc.blend);
4282 gen8_subpicture_render_blend_state(VADriverContextP ctx)
4284 struct i965_driver_data *i965 = i965_driver_data(ctx);
4285 struct i965_render_state *render_state = &i965->render_state;
4286 struct gen8_global_blend_state *global_blend_state;
4287 struct gen8_blend_state_rt *blend_state;
4288 unsigned char *cc_ptr;
4290 dri_bo_map(render_state->dynamic_state.bo, 1);
4291 assert(render_state->dynamic_state.bo->virtual);
4293 cc_ptr = (unsigned char *) render_state->dynamic_state.bo->virtual +
4294 render_state->blend_state_offset;
4296 global_blend_state = (struct gen8_global_blend_state*) cc_ptr;
4298 memset(global_blend_state, 0, sizeof(*global_blend_state));
4299 /* Global blend state + blend_state for Render Target */
4300 blend_state = (struct gen8_blend_state_rt *)(global_blend_state + 1);
4301 blend_state->blend0.color_blend_func = I965_BLENDFUNCTION_ADD;
4302 blend_state->blend0.dest_blend_factor = I965_BLENDFACTOR_INV_SRC_ALPHA;
4303 blend_state->blend0.src_blend_factor = I965_BLENDFACTOR_SRC_ALPHA;
4304 blend_state->blend0.alpha_blend_func = I965_BLENDFUNCTION_ADD;
4305 blend_state->blend0.ia_dest_blend_factor = I965_BLENDFACTOR_INV_SRC_ALPHA;
4306 blend_state->blend0.ia_src_blend_factor = I965_BLENDFACTOR_SRC_ALPHA;
4307 blend_state->blend0.colorbuf_blend = 1;
4308 blend_state->blend1.post_blend_clamp_enable = 1;
4309 blend_state->blend1.pre_blend_clamp_enable = 1;
4310 blend_state->blend1.clamp_range = 0; /* clamp range [0, 1] */
4312 dri_bo_unmap(render_state->dynamic_state.bo);
4316 gen7_subpicture_render_setup_states(
4317 VADriverContextP ctx,
4318 struct object_surface *obj_surface,
4319 const VARectangle *src_rect,
4320 const VARectangle *dst_rect
4323 i965_render_dest_surface_state(ctx, 0);
4324 i965_subpic_render_src_surfaces_state(ctx, obj_surface);
4325 i965_render_sampler(ctx);
4326 i965_render_cc_viewport(ctx);
4327 gen7_render_color_calc_state(ctx);
4328 gen7_subpicture_render_blend_state(ctx);
4329 gen7_render_depth_stencil_state(ctx);
4330 i965_subpic_render_upload_constants(ctx, obj_surface);
4331 i965_subpic_render_upload_vertex(ctx, obj_surface, dst_rect);
4335 gen8_subpic_render_upload_constants(VADriverContextP ctx,
4336 struct object_surface *obj_surface)
4338 struct i965_driver_data *i965 = i965_driver_data(ctx);
4339 struct i965_render_state *render_state = &i965->render_state;
4340 float *constant_buffer;
4341 float global_alpha = 1.0;
4342 unsigned int index = obj_surface->subpic_render_idx;
4343 struct object_subpic *obj_subpic = obj_surface->obj_subpic[index];
4344 unsigned char *cc_ptr;
4346 if (obj_subpic->flags & VA_SUBPICTURE_GLOBAL_ALPHA) {
4347 global_alpha = obj_subpic->global_alpha;
4351 dri_bo_map(render_state->dynamic_state.bo, 1);
4352 assert(render_state->dynamic_state.bo->virtual);
4354 cc_ptr = (unsigned char *) render_state->dynamic_state.bo->virtual +
4355 render_state->curbe_offset;
4357 constant_buffer = (float *) cc_ptr;
4358 *constant_buffer = global_alpha;
4360 dri_bo_unmap(render_state->dynamic_state.bo);
4364 gen8_subpicture_render_setup_states(
4365 VADriverContextP ctx,
4366 struct object_surface *obj_surface,
4367 const VARectangle *src_rect,
4368 const VARectangle *dst_rect
4371 i965_render_dest_surface_state(ctx, 0);
4372 i965_subpic_render_src_surfaces_state(ctx, obj_surface);
4373 gen8_render_sampler(ctx);
4374 gen8_render_cc_viewport(ctx);
4375 gen8_render_color_calc_state(ctx);
4376 gen8_subpicture_render_blend_state(ctx);
4377 gen8_subpic_render_upload_constants(ctx, obj_surface);
4378 i965_subpic_render_upload_vertex(ctx, obj_surface, dst_rect);
4382 gen7_render_put_subpicture(
4383 VADriverContextP ctx,
4384 struct object_surface *obj_surface,
4385 const VARectangle *src_rect,
4386 const VARectangle *dst_rect
4389 struct i965_driver_data *i965 = i965_driver_data(ctx);
4390 struct intel_batchbuffer *batch = i965->batch;
4391 unsigned int index = obj_surface->subpic_render_idx;
4392 struct object_subpic *obj_subpic = obj_surface->obj_subpic[index];
4395 gen7_render_initialize(ctx);
4396 gen7_subpicture_render_setup_states(ctx, obj_surface, src_rect, dst_rect);
4397 gen7_render_emit_states(ctx, PS_SUBPIC_KERNEL);
4398 i965_render_upload_image_palette(ctx, obj_subpic->obj_image, 0xff);
4399 intel_batchbuffer_flush(batch);
4403 gen8_render_put_subpicture(
4404 VADriverContextP ctx,
4405 struct object_surface *obj_surface,
4406 const VARectangle *src_rect,
4407 const VARectangle *dst_rect
4410 struct i965_driver_data *i965 = i965_driver_data(ctx);
4411 struct intel_batchbuffer *batch = i965->batch;
4412 unsigned int index = obj_surface->subpic_render_idx;
4413 struct object_subpic *obj_subpic = obj_surface->obj_subpic[index];
4416 gen8_render_initialize(ctx);
4417 gen8_subpicture_render_setup_states(ctx, obj_surface, src_rect, dst_rect);
4418 gen8_render_emit_states(ctx, PS_SUBPIC_KERNEL);
4419 i965_render_upload_image_palette(ctx, obj_subpic->obj_image, 0xff);
4420 intel_batchbuffer_flush(batch);
4427 i965_DestroySurfaces(VADriverContextP ctx,
4428 VASurfaceID *surface_list,
4431 intel_render_put_surface(
4432 VADriverContextP ctx,
4433 struct object_surface *obj_surface,
4434 const VARectangle *src_rect,
4435 const VARectangle *dst_rect,
4439 struct i965_driver_data *i965 = i965_driver_data(ctx);
4440 int has_done_scaling = 0;
4441 VASurfaceID out_surface_id = i965_post_processing(ctx,
4448 assert((!has_done_scaling) || (out_surface_id != VA_INVALID_ID));
4450 if (out_surface_id != VA_INVALID_ID) {
4451 struct object_surface *new_obj_surface = SURFACE(out_surface_id);
4453 if (new_obj_surface && new_obj_surface->bo)
4454 obj_surface = new_obj_surface;
4456 if (has_done_scaling)
4457 src_rect = dst_rect;
4460 if (IS_GEN8(i965->intel.device_id))
4461 gen8_render_put_surface(ctx, obj_surface, src_rect, dst_rect, flags);
4462 else if (IS_GEN7(i965->intel.device_id))
4463 gen7_render_put_surface(ctx, obj_surface, src_rect, dst_rect, flags);
4464 else if (IS_GEN6(i965->intel.device_id))
4465 gen6_render_put_surface(ctx, obj_surface, src_rect, dst_rect, flags);
4467 i965_render_put_surface(ctx, obj_surface, src_rect, dst_rect, flags);
4469 if (out_surface_id != VA_INVALID_ID)
4470 i965_DestroySurfaces(ctx, &out_surface_id, 1);
4474 intel_render_put_subpicture(
4475 VADriverContextP ctx,
4476 struct object_surface *obj_surface,
4477 const VARectangle *src_rect,
4478 const VARectangle *dst_rect
4481 struct i965_driver_data *i965 = i965_driver_data(ctx);
4483 if (IS_GEN8(i965->intel.device_id))
4484 gen8_render_put_subpicture(ctx, obj_surface, src_rect, dst_rect);
4485 else if (IS_GEN7(i965->intel.device_id))
4486 gen7_render_put_subpicture(ctx, obj_surface, src_rect, dst_rect);
4487 else if (IS_GEN6(i965->intel.device_id))
4488 gen6_render_put_subpicture(ctx, obj_surface, src_rect, dst_rect);
4490 i965_render_put_subpicture(ctx, obj_surface, src_rect, dst_rect);
4494 gen8_render_init(VADriverContextP ctx)
4496 struct i965_driver_data *i965 = i965_driver_data(ctx);
4497 struct i965_render_state *render_state = &i965->render_state;
4499 unsigned int kernel_offset, end_offset;
4500 unsigned char *kernel_ptr;
4501 struct i965_kernel *kernel;
4504 if (IS_GEN8(i965->intel.device_id)) {
4505 memcpy(render_state->render_kernels, render_kernels_gen8,
4506 sizeof(render_state->render_kernels));
4511 for (i = 0; i < NUM_RENDER_KERNEL; i++) {
4512 kernel = &render_state->render_kernels[i];
4517 kernel_size += kernel->size;
4520 render_state->instruction_state.bo = dri_bo_alloc(i965->intel.bufmgr,
4524 if (render_state->instruction_state.bo == NULL) {
4525 WARN_ONCE("failure to allocate the buffer space for kernel shader\n");
4529 assert(render_state->instruction_state.bo);
4531 render_state->instruction_state.bo_size = kernel_size;
4532 render_state->instruction_state.end_offset = 0;
4535 dri_bo_map(render_state->instruction_state.bo, 1);
4536 kernel_ptr = (unsigned char *)(render_state->instruction_state.bo->virtual);
4537 for (i = 0; i < NUM_RENDER_KERNEL; i++) {
4538 kernel = &render_state->render_kernels[i];
4539 kernel_offset = ALIGN(end_offset, 64);
4540 kernel->kernel_offset = kernel_offset;
4545 memcpy(kernel_ptr + kernel_offset, kernel->bin, kernel->size);
4547 end_offset += kernel->size;
4550 render_state->instruction_state.end_offset = end_offset;
4552 dri_bo_unmap(render_state->instruction_state.bo);
4555 if (IS_GEN8(i965->intel.device_id)) {
4556 render_state->max_wm_threads = 64;
4558 /* should never get here !!! */
4567 i965_render_init(VADriverContextP ctx)
4569 struct i965_driver_data *i965 = i965_driver_data(ctx);
4570 struct i965_render_state *render_state = &i965->render_state;
4574 assert(NUM_RENDER_KERNEL == (sizeof(render_kernels_gen5) /
4575 sizeof(render_kernels_gen5[0])));
4576 assert(NUM_RENDER_KERNEL == (sizeof(render_kernels_gen6) /
4577 sizeof(render_kernels_gen6[0])));
4579 if (IS_GEN8(i965->intel.device_id)) {
4580 return gen8_render_init(ctx);
4581 } else if (IS_GEN7(i965->intel.device_id))
4582 memcpy(render_state->render_kernels,
4583 (IS_HASWELL(i965->intel.device_id) ? render_kernels_gen7_haswell : render_kernels_gen7),
4584 sizeof(render_state->render_kernels));
4585 else if (IS_GEN6(i965->intel.device_id))
4586 memcpy(render_state->render_kernels, render_kernels_gen6, sizeof(render_state->render_kernels));
4587 else if (IS_IRONLAKE(i965->intel.device_id))
4588 memcpy(render_state->render_kernels, render_kernels_gen5, sizeof(render_state->render_kernels));
4590 memcpy(render_state->render_kernels, render_kernels_gen4, sizeof(render_state->render_kernels));
4592 for (i = 0; i < NUM_RENDER_KERNEL; i++) {
4593 struct i965_kernel *kernel = &render_state->render_kernels[i];
4598 kernel->bo = dri_bo_alloc(i965->intel.bufmgr,
4600 kernel->size, 0x1000);
4602 dri_bo_subdata(kernel->bo, 0, kernel->size, kernel->bin);
4605 /* constant buffer */
4606 render_state->curbe.bo = dri_bo_alloc(i965->intel.bufmgr,
4609 assert(render_state->curbe.bo);
4611 if (IS_HSW_GT1(i965->intel.device_id)) {
4612 render_state->max_wm_threads = 102;
4613 } else if (IS_HSW_GT2(i965->intel.device_id)) {
4614 render_state->max_wm_threads = 204;
4615 } else if (IS_HSW_GT3(i965->intel.device_id)) {
4616 render_state->max_wm_threads = 408;
4617 } else if (IS_IVB_GT1(i965->intel.device_id) || IS_BAYTRAIL(i965->intel.device_id)) {
4618 render_state->max_wm_threads = 48;
4619 } else if (IS_IVB_GT2(i965->intel.device_id)) {
4620 render_state->max_wm_threads = 172;
4621 } else if (IS_SNB_GT1(i965->intel.device_id)) {
4622 render_state->max_wm_threads = 40;
4623 } else if (IS_SNB_GT2(i965->intel.device_id)) {
4624 render_state->max_wm_threads = 80;
4625 } else if (IS_IRONLAKE(i965->intel.device_id)) {
4626 render_state->max_wm_threads = 72; /* 12 * 6 */
4627 } else if (IS_G4X(i965->intel.device_id)) {
4628 render_state->max_wm_threads = 50; /* 12 * 5 */
4630 /* should never get here !!! */
4638 gen8_render_terminate(VADriverContextP ctx)
4641 struct i965_driver_data *i965 = i965_driver_data(ctx);
4642 struct i965_render_state *render_state = &i965->render_state;
4644 dri_bo_unreference(render_state->vb.vertex_buffer);
4645 render_state->vb.vertex_buffer = NULL;
4647 dri_bo_unreference(render_state->wm.surface_state_binding_table_bo);
4648 render_state->wm.surface_state_binding_table_bo = NULL;
4650 if (render_state->instruction_state.bo) {
4651 dri_bo_unreference(render_state->instruction_state.bo);
4652 render_state->instruction_state.bo = NULL;
4655 if (render_state->dynamic_state.bo) {
4656 dri_bo_unreference(render_state->dynamic_state.bo);
4657 render_state->dynamic_state.bo = NULL;
4660 if (render_state->indirect_state.bo) {
4661 dri_bo_unreference(render_state->indirect_state.bo);
4662 render_state->indirect_state.bo = NULL;
4665 if (render_state->draw_region) {
4666 dri_bo_unreference(render_state->draw_region->bo);
4667 free(render_state->draw_region);
4668 render_state->draw_region = NULL;
4673 i965_render_terminate(VADriverContextP ctx)
4676 struct i965_driver_data *i965 = i965_driver_data(ctx);
4677 struct i965_render_state *render_state = &i965->render_state;
4679 if (IS_GEN8(i965->intel.device_id)) {
4680 gen8_render_terminate(ctx);
4684 dri_bo_unreference(render_state->curbe.bo);
4685 render_state->curbe.bo = NULL;
4687 for (i = 0; i < NUM_RENDER_KERNEL; i++) {
4688 struct i965_kernel *kernel = &render_state->render_kernels[i];
4690 dri_bo_unreference(kernel->bo);
4694 dri_bo_unreference(render_state->vb.vertex_buffer);
4695 render_state->vb.vertex_buffer = NULL;
4696 dri_bo_unreference(render_state->vs.state);
4697 render_state->vs.state = NULL;
4698 dri_bo_unreference(render_state->sf.state);
4699 render_state->sf.state = NULL;
4700 dri_bo_unreference(render_state->wm.sampler);
4701 render_state->wm.sampler = NULL;
4702 dri_bo_unreference(render_state->wm.state);
4703 render_state->wm.state = NULL;
4704 dri_bo_unreference(render_state->wm.surface_state_binding_table_bo);
4705 dri_bo_unreference(render_state->cc.viewport);
4706 render_state->cc.viewport = NULL;
4707 dri_bo_unreference(render_state->cc.state);
4708 render_state->cc.state = NULL;
4709 dri_bo_unreference(render_state->cc.blend);
4710 render_state->cc.blend = NULL;
4711 dri_bo_unreference(render_state->cc.depth_stencil);
4712 render_state->cc.depth_stencil = NULL;
4714 if (render_state->draw_region) {
4715 dri_bo_unreference(render_state->draw_region->bo);
4716 free(render_state->draw_region);
4717 render_state->draw_region = NULL;