2 * Copyright © 2006 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Eric Anholt <eric@anholt.net>
25 * Keith Packard <keithp@keithp.com>
26 * Xiang Haihao <haihao.xiang@intel.com>
31 * Most of rendering codes are ported from xf86-video-intel/src/i965_video.c
39 #include "intel_batchbuffer.h"
40 #include "intel_driver.h"
41 #include "i965_defines.h"
42 #include "i965_drv_video.h"
43 #include "i965_structs.h"
45 #include "i965_render.h"
47 #define SF_KERNEL_NUM_GRF 16
48 #define SF_MAX_THREADS 1
50 static const uint32_t sf_kernel_static[][4] =
52 #include "shaders/render/exa_sf.g4b"
55 #define PS_KERNEL_NUM_GRF 32
56 #define PS_MAX_THREADS 32
58 #define I965_GRF_BLOCKS(nreg) ((nreg + 15) / 16 - 1)
60 static const uint32_t ps_kernel_static[][4] =
62 #include "shaders/render/exa_wm_xy.g4b"
63 #include "shaders/render/exa_wm_src_affine.g4b"
64 #include "shaders/render/exa_wm_src_sample_planar.g4b"
65 #include "shaders/render/exa_wm_yuv_rgb.g4b"
66 #include "shaders/render/exa_wm_write.g4b"
68 static const uint32_t ps_subpic_kernel_static[][4] =
70 #include "shaders/render/exa_wm_xy.g4b"
71 #include "shaders/render/exa_wm_src_affine.g4b"
72 #include "shaders/render/exa_wm_src_sample_argb.g4b"
73 #include "shaders/render/exa_wm_write.g4b"
77 static const uint32_t sf_kernel_static_gen5[][4] =
79 #include "shaders/render/exa_sf.g4b.gen5"
82 static const uint32_t ps_kernel_static_gen5[][4] =
84 #include "shaders/render/exa_wm_xy.g4b.gen5"
85 #include "shaders/render/exa_wm_src_affine.g4b.gen5"
86 #include "shaders/render/exa_wm_src_sample_planar.g4b.gen5"
87 #include "shaders/render/exa_wm_yuv_rgb.g4b.gen5"
88 #include "shaders/render/exa_wm_write.g4b.gen5"
90 static const uint32_t ps_subpic_kernel_static_gen5[][4] =
92 #include "shaders/render/exa_wm_xy.g4b.gen5"
93 #include "shaders/render/exa_wm_src_affine.g4b.gen5"
94 #include "shaders/render/exa_wm_src_sample_argb.g4b.gen5"
95 #include "shaders/render/exa_wm_write.g4b.gen5"
98 /* programs for Sandybridge */
99 static const uint32_t sf_kernel_static_gen6[][4] =
103 static const uint32_t ps_kernel_static_gen6[][4] = {
104 #include "shaders/render/exa_wm_src_affine.g6b"
105 #include "shaders/render/exa_wm_src_sample_planar.g6b"
106 #include "shaders/render/exa_wm_yuv_rgb.g6b"
107 #include "shaders/render/exa_wm_write.g6b"
110 static const uint32_t ps_subpic_kernel_static_gen6[][4] = {
111 #include "shaders/render/exa_wm_src_affine.g6b"
112 #include "shaders/render/exa_wm_src_sample_argb.g6b"
113 #include "shaders/render/exa_wm_write.g6b"
116 /* programs for Ivybridge */
117 static const uint32_t sf_kernel_static_gen7[][4] =
121 static const uint32_t ps_kernel_static_gen7[][4] = {
122 #include "shaders/render/exa_wm_src_affine.g7b"
123 #include "shaders/render/exa_wm_src_sample_planar.g7b"
124 #include "shaders/render/exa_wm_yuv_rgb.g7b"
125 #include "shaders/render/exa_wm_write.g7b"
128 static const uint32_t ps_subpic_kernel_static_gen7[][4] = {
129 #include "shaders/render/exa_wm_src_affine.g7b"
130 #include "shaders/render/exa_wm_src_sample_argb.g7b"
131 #include "shaders/render/exa_wm_write.g7b"
134 /* Programs for Haswell */
135 static const uint32_t ps_kernel_static_gen7_haswell[][4] = {
136 #include "shaders/render/exa_wm_src_affine.g7b"
137 #include "shaders/render/exa_wm_src_sample_planar.g7b.haswell"
138 #include "shaders/render/exa_wm_yuv_rgb.g7b"
139 #include "shaders/render/exa_wm_write.g7b"
142 #define SURFACE_STATE_PADDED_SIZE_I965 ALIGN(sizeof(struct i965_surface_state), 32)
143 #define SURFACE_STATE_PADDED_SIZE_GEN7 ALIGN(sizeof(struct gen7_surface_state), 32)
144 #define SURFACE_STATE_PADDED_SIZE MAX(SURFACE_STATE_PADDED_SIZE_I965, SURFACE_STATE_PADDED_SIZE_GEN7)
145 #define SURFACE_STATE_OFFSET(index) (SURFACE_STATE_PADDED_SIZE * index)
146 #define BINDING_TABLE_OFFSET SURFACE_STATE_OFFSET(MAX_RENDER_SURFACES)
148 static uint32_t float_to_uint (float f)
166 static struct i965_kernel render_kernels_gen4[] = {
171 sizeof(sf_kernel_static),
178 sizeof(ps_kernel_static),
185 ps_subpic_kernel_static,
186 sizeof(ps_subpic_kernel_static),
191 static struct i965_kernel render_kernels_gen5[] = {
195 sf_kernel_static_gen5,
196 sizeof(sf_kernel_static_gen5),
202 ps_kernel_static_gen5,
203 sizeof(ps_kernel_static_gen5),
210 ps_subpic_kernel_static_gen5,
211 sizeof(ps_subpic_kernel_static_gen5),
216 static struct i965_kernel render_kernels_gen6[] = {
220 sf_kernel_static_gen6,
221 sizeof(sf_kernel_static_gen6),
227 ps_kernel_static_gen6,
228 sizeof(ps_kernel_static_gen6),
235 ps_subpic_kernel_static_gen6,
236 sizeof(ps_subpic_kernel_static_gen6),
241 static struct i965_kernel render_kernels_gen7[] = {
245 sf_kernel_static_gen7,
246 sizeof(sf_kernel_static_gen7),
252 ps_kernel_static_gen7,
253 sizeof(ps_kernel_static_gen7),
260 ps_subpic_kernel_static_gen7,
261 sizeof(ps_subpic_kernel_static_gen7),
266 static struct i965_kernel render_kernels_gen7_haswell[] = {
270 sf_kernel_static_gen7,
271 sizeof(sf_kernel_static_gen7),
277 ps_kernel_static_gen7_haswell,
278 sizeof(ps_kernel_static_gen7_haswell),
285 ps_subpic_kernel_static_gen7,
286 sizeof(ps_subpic_kernel_static_gen7),
291 #define URB_VS_ENTRIES 8
292 #define URB_VS_ENTRY_SIZE 1
294 #define URB_GS_ENTRIES 0
295 #define URB_GS_ENTRY_SIZE 0
297 #define URB_CLIP_ENTRIES 0
298 #define URB_CLIP_ENTRY_SIZE 0
300 #define URB_SF_ENTRIES 1
301 #define URB_SF_ENTRY_SIZE 2
303 #define URB_CS_ENTRIES 1
304 #define URB_CS_ENTRY_SIZE 1
307 i965_render_vs_unit(VADriverContextP ctx)
309 struct i965_driver_data *i965 = i965_driver_data(ctx);
310 struct i965_render_state *render_state = &i965->render_state;
311 struct i965_vs_unit_state *vs_state;
313 dri_bo_map(render_state->vs.state, 1);
314 assert(render_state->vs.state->virtual);
315 vs_state = render_state->vs.state->virtual;
316 memset(vs_state, 0, sizeof(*vs_state));
318 if (IS_IRONLAKE(i965->intel.device_id))
319 vs_state->thread4.nr_urb_entries = URB_VS_ENTRIES >> 2;
321 vs_state->thread4.nr_urb_entries = URB_VS_ENTRIES;
323 vs_state->thread4.urb_entry_allocation_size = URB_VS_ENTRY_SIZE - 1;
324 vs_state->vs6.vs_enable = 0;
325 vs_state->vs6.vert_cache_disable = 1;
327 dri_bo_unmap(render_state->vs.state);
331 i965_render_sf_unit(VADriverContextP ctx)
333 struct i965_driver_data *i965 = i965_driver_data(ctx);
334 struct i965_render_state *render_state = &i965->render_state;
335 struct i965_sf_unit_state *sf_state;
337 dri_bo_map(render_state->sf.state, 1);
338 assert(render_state->sf.state->virtual);
339 sf_state = render_state->sf.state->virtual;
340 memset(sf_state, 0, sizeof(*sf_state));
342 sf_state->thread0.grf_reg_count = I965_GRF_BLOCKS(SF_KERNEL_NUM_GRF);
343 sf_state->thread0.kernel_start_pointer = render_state->render_kernels[SF_KERNEL].bo->offset >> 6;
345 sf_state->sf1.single_program_flow = 1; /* XXX */
346 sf_state->sf1.binding_table_entry_count = 0;
347 sf_state->sf1.thread_priority = 0;
348 sf_state->sf1.floating_point_mode = 0; /* Mesa does this */
349 sf_state->sf1.illegal_op_exception_enable = 1;
350 sf_state->sf1.mask_stack_exception_enable = 1;
351 sf_state->sf1.sw_exception_enable = 1;
353 /* scratch space is not used in our kernel */
354 sf_state->thread2.per_thread_scratch_space = 0;
355 sf_state->thread2.scratch_space_base_pointer = 0;
357 sf_state->thread3.const_urb_entry_read_length = 0; /* no const URBs */
358 sf_state->thread3.const_urb_entry_read_offset = 0; /* no const URBs */
359 sf_state->thread3.urb_entry_read_length = 1; /* 1 URB per vertex */
360 sf_state->thread3.urb_entry_read_offset = 0;
361 sf_state->thread3.dispatch_grf_start_reg = 3;
363 sf_state->thread4.max_threads = SF_MAX_THREADS - 1;
364 sf_state->thread4.urb_entry_allocation_size = URB_SF_ENTRY_SIZE - 1;
365 sf_state->thread4.nr_urb_entries = URB_SF_ENTRIES;
366 sf_state->thread4.stats_enable = 1;
368 sf_state->sf5.viewport_transform = 0; /* skip viewport */
370 sf_state->sf6.cull_mode = I965_CULLMODE_NONE;
371 sf_state->sf6.scissor = 0;
373 sf_state->sf7.trifan_pv = 2;
375 sf_state->sf6.dest_org_vbias = 0x8;
376 sf_state->sf6.dest_org_hbias = 0x8;
378 dri_bo_emit_reloc(render_state->sf.state,
379 I915_GEM_DOMAIN_INSTRUCTION, 0,
380 sf_state->thread0.grf_reg_count << 1,
381 offsetof(struct i965_sf_unit_state, thread0),
382 render_state->render_kernels[SF_KERNEL].bo);
384 dri_bo_unmap(render_state->sf.state);
388 i965_render_sampler(VADriverContextP ctx)
390 struct i965_driver_data *i965 = i965_driver_data(ctx);
391 struct i965_render_state *render_state = &i965->render_state;
392 struct i965_sampler_state *sampler_state;
395 assert(render_state->wm.sampler_count > 0);
396 assert(render_state->wm.sampler_count <= MAX_SAMPLERS);
398 dri_bo_map(render_state->wm.sampler, 1);
399 assert(render_state->wm.sampler->virtual);
400 sampler_state = render_state->wm.sampler->virtual;
401 for (i = 0; i < render_state->wm.sampler_count; i++) {
402 memset(sampler_state, 0, sizeof(*sampler_state));
403 sampler_state->ss0.min_filter = I965_MAPFILTER_LINEAR;
404 sampler_state->ss0.mag_filter = I965_MAPFILTER_LINEAR;
405 sampler_state->ss1.r_wrap_mode = I965_TEXCOORDMODE_CLAMP;
406 sampler_state->ss1.s_wrap_mode = I965_TEXCOORDMODE_CLAMP;
407 sampler_state->ss1.t_wrap_mode = I965_TEXCOORDMODE_CLAMP;
411 dri_bo_unmap(render_state->wm.sampler);
414 i965_subpic_render_wm_unit(VADriverContextP ctx)
416 struct i965_driver_data *i965 = i965_driver_data(ctx);
417 struct i965_render_state *render_state = &i965->render_state;
418 struct i965_wm_unit_state *wm_state;
420 assert(render_state->wm.sampler);
422 dri_bo_map(render_state->wm.state, 1);
423 assert(render_state->wm.state->virtual);
424 wm_state = render_state->wm.state->virtual;
425 memset(wm_state, 0, sizeof(*wm_state));
427 wm_state->thread0.grf_reg_count = I965_GRF_BLOCKS(PS_KERNEL_NUM_GRF);
428 wm_state->thread0.kernel_start_pointer = render_state->render_kernels[PS_SUBPIC_KERNEL].bo->offset >> 6;
430 wm_state->thread1.single_program_flow = 1; /* XXX */
432 if (IS_IRONLAKE(i965->intel.device_id))
433 wm_state->thread1.binding_table_entry_count = 0; /* hardware requirement */
435 wm_state->thread1.binding_table_entry_count = 7;
437 wm_state->thread2.scratch_space_base_pointer = 0;
438 wm_state->thread2.per_thread_scratch_space = 0; /* 1024 bytes */
440 wm_state->thread3.dispatch_grf_start_reg = 3; /* XXX */
441 wm_state->thread3.const_urb_entry_read_length = 0;
442 wm_state->thread3.const_urb_entry_read_offset = 0;
443 wm_state->thread3.urb_entry_read_length = 1; /* XXX */
444 wm_state->thread3.urb_entry_read_offset = 0; /* XXX */
446 wm_state->wm4.stats_enable = 0;
447 wm_state->wm4.sampler_state_pointer = render_state->wm.sampler->offset >> 5;
449 if (IS_IRONLAKE(i965->intel.device_id)) {
450 wm_state->wm4.sampler_count = 0; /* hardware requirement */
451 wm_state->wm5.max_threads = 12 * 6 - 1;
453 wm_state->wm4.sampler_count = (render_state->wm.sampler_count + 3) / 4;
454 wm_state->wm5.max_threads = 10 * 5 - 1;
457 wm_state->wm5.thread_dispatch_enable = 1;
458 wm_state->wm5.enable_16_pix = 1;
459 wm_state->wm5.enable_8_pix = 0;
460 wm_state->wm5.early_depth_test = 1;
462 dri_bo_emit_reloc(render_state->wm.state,
463 I915_GEM_DOMAIN_INSTRUCTION, 0,
464 wm_state->thread0.grf_reg_count << 1,
465 offsetof(struct i965_wm_unit_state, thread0),
466 render_state->render_kernels[PS_SUBPIC_KERNEL].bo);
468 dri_bo_emit_reloc(render_state->wm.state,
469 I915_GEM_DOMAIN_INSTRUCTION, 0,
470 wm_state->wm4.sampler_count << 2,
471 offsetof(struct i965_wm_unit_state, wm4),
472 render_state->wm.sampler);
474 dri_bo_unmap(render_state->wm.state);
479 i965_render_wm_unit(VADriverContextP ctx)
481 struct i965_driver_data *i965 = i965_driver_data(ctx);
482 struct i965_render_state *render_state = &i965->render_state;
483 struct i965_wm_unit_state *wm_state;
485 assert(render_state->wm.sampler);
487 dri_bo_map(render_state->wm.state, 1);
488 assert(render_state->wm.state->virtual);
489 wm_state = render_state->wm.state->virtual;
490 memset(wm_state, 0, sizeof(*wm_state));
492 wm_state->thread0.grf_reg_count = I965_GRF_BLOCKS(PS_KERNEL_NUM_GRF);
493 wm_state->thread0.kernel_start_pointer = render_state->render_kernels[PS_KERNEL].bo->offset >> 6;
495 wm_state->thread1.single_program_flow = 1; /* XXX */
497 if (IS_IRONLAKE(i965->intel.device_id))
498 wm_state->thread1.binding_table_entry_count = 0; /* hardware requirement */
500 wm_state->thread1.binding_table_entry_count = 7;
502 wm_state->thread2.scratch_space_base_pointer = 0;
503 wm_state->thread2.per_thread_scratch_space = 0; /* 1024 bytes */
505 wm_state->thread3.dispatch_grf_start_reg = 2; /* XXX */
506 wm_state->thread3.const_urb_entry_read_length = 1;
507 wm_state->thread3.const_urb_entry_read_offset = 0;
508 wm_state->thread3.urb_entry_read_length = 1; /* XXX */
509 wm_state->thread3.urb_entry_read_offset = 0; /* XXX */
511 wm_state->wm4.stats_enable = 0;
512 wm_state->wm4.sampler_state_pointer = render_state->wm.sampler->offset >> 5;
514 if (IS_IRONLAKE(i965->intel.device_id)) {
515 wm_state->wm4.sampler_count = 0; /* hardware requirement */
516 wm_state->wm5.max_threads = 12 * 6 - 1;
518 wm_state->wm4.sampler_count = (render_state->wm.sampler_count + 3) / 4;
519 wm_state->wm5.max_threads = 10 * 5 - 1;
522 wm_state->wm5.thread_dispatch_enable = 1;
523 wm_state->wm5.enable_16_pix = 1;
524 wm_state->wm5.enable_8_pix = 0;
525 wm_state->wm5.early_depth_test = 1;
527 dri_bo_emit_reloc(render_state->wm.state,
528 I915_GEM_DOMAIN_INSTRUCTION, 0,
529 wm_state->thread0.grf_reg_count << 1,
530 offsetof(struct i965_wm_unit_state, thread0),
531 render_state->render_kernels[PS_KERNEL].bo);
533 dri_bo_emit_reloc(render_state->wm.state,
534 I915_GEM_DOMAIN_INSTRUCTION, 0,
535 wm_state->wm4.sampler_count << 2,
536 offsetof(struct i965_wm_unit_state, wm4),
537 render_state->wm.sampler);
539 dri_bo_unmap(render_state->wm.state);
543 i965_render_cc_viewport(VADriverContextP ctx)
545 struct i965_driver_data *i965 = i965_driver_data(ctx);
546 struct i965_render_state *render_state = &i965->render_state;
547 struct i965_cc_viewport *cc_viewport;
549 dri_bo_map(render_state->cc.viewport, 1);
550 assert(render_state->cc.viewport->virtual);
551 cc_viewport = render_state->cc.viewport->virtual;
552 memset(cc_viewport, 0, sizeof(*cc_viewport));
554 cc_viewport->min_depth = -1.e35;
555 cc_viewport->max_depth = 1.e35;
557 dri_bo_unmap(render_state->cc.viewport);
561 i965_subpic_render_cc_unit(VADriverContextP ctx)
563 struct i965_driver_data *i965 = i965_driver_data(ctx);
564 struct i965_render_state *render_state = &i965->render_state;
565 struct i965_cc_unit_state *cc_state;
567 assert(render_state->cc.viewport);
569 dri_bo_map(render_state->cc.state, 1);
570 assert(render_state->cc.state->virtual);
571 cc_state = render_state->cc.state->virtual;
572 memset(cc_state, 0, sizeof(*cc_state));
574 cc_state->cc0.stencil_enable = 0; /* disable stencil */
575 cc_state->cc2.depth_test = 0; /* disable depth test */
576 cc_state->cc2.logicop_enable = 0; /* disable logic op */
577 cc_state->cc3.ia_blend_enable = 0 ; /* blend alpha just like colors */
578 cc_state->cc3.blend_enable = 1; /* enable color blend */
579 cc_state->cc3.alpha_test = 0; /* disable alpha test */
580 cc_state->cc3.alpha_test_format = 0;//0:ALPHATEST_UNORM8; /*store alpha value with UNORM8 */
581 cc_state->cc3.alpha_test_func = 5;//COMPAREFUNCTION_LESS; /*pass if less than the reference */
582 cc_state->cc4.cc_viewport_state_offset = render_state->cc.viewport->offset >> 5;
584 cc_state->cc5.dither_enable = 0; /* disable dither */
585 cc_state->cc5.logicop_func = 0xc; /* WHITE */
586 cc_state->cc5.statistics_enable = 1;
587 cc_state->cc5.ia_blend_function = I965_BLENDFUNCTION_ADD;
588 cc_state->cc5.ia_src_blend_factor = I965_BLENDFACTOR_DST_ALPHA;
589 cc_state->cc5.ia_dest_blend_factor = I965_BLENDFACTOR_DST_ALPHA;
591 cc_state->cc6.clamp_post_alpha_blend = 0;
592 cc_state->cc6.clamp_pre_alpha_blend =0;
594 /*final color = src_color*src_blend_factor +/- dst_color*dest_color_blend_factor*/
595 cc_state->cc6.blend_function = I965_BLENDFUNCTION_ADD;
596 cc_state->cc6.src_blend_factor = I965_BLENDFACTOR_SRC_ALPHA;
597 cc_state->cc6.dest_blend_factor = I965_BLENDFACTOR_INV_SRC_ALPHA;
599 /*alpha test reference*/
600 cc_state->cc7.alpha_ref.f =0.0 ;
603 dri_bo_emit_reloc(render_state->cc.state,
604 I915_GEM_DOMAIN_INSTRUCTION, 0,
606 offsetof(struct i965_cc_unit_state, cc4),
607 render_state->cc.viewport);
609 dri_bo_unmap(render_state->cc.state);
614 i965_render_cc_unit(VADriverContextP ctx)
616 struct i965_driver_data *i965 = i965_driver_data(ctx);
617 struct i965_render_state *render_state = &i965->render_state;
618 struct i965_cc_unit_state *cc_state;
620 assert(render_state->cc.viewport);
622 dri_bo_map(render_state->cc.state, 1);
623 assert(render_state->cc.state->virtual);
624 cc_state = render_state->cc.state->virtual;
625 memset(cc_state, 0, sizeof(*cc_state));
627 cc_state->cc0.stencil_enable = 0; /* disable stencil */
628 cc_state->cc2.depth_test = 0; /* disable depth test */
629 cc_state->cc2.logicop_enable = 1; /* enable logic op */
630 cc_state->cc3.ia_blend_enable = 0; /* blend alpha just like colors */
631 cc_state->cc3.blend_enable = 0; /* disable color blend */
632 cc_state->cc3.alpha_test = 0; /* disable alpha test */
633 cc_state->cc4.cc_viewport_state_offset = render_state->cc.viewport->offset >> 5;
635 cc_state->cc5.dither_enable = 0; /* disable dither */
636 cc_state->cc5.logicop_func = 0xc; /* WHITE */
637 cc_state->cc5.statistics_enable = 1;
638 cc_state->cc5.ia_blend_function = I965_BLENDFUNCTION_ADD;
639 cc_state->cc5.ia_src_blend_factor = I965_BLENDFACTOR_ONE;
640 cc_state->cc5.ia_dest_blend_factor = I965_BLENDFACTOR_ONE;
642 dri_bo_emit_reloc(render_state->cc.state,
643 I915_GEM_DOMAIN_INSTRUCTION, 0,
645 offsetof(struct i965_cc_unit_state, cc4),
646 render_state->cc.viewport);
648 dri_bo_unmap(render_state->cc.state);
652 i965_render_set_surface_tiling(struct i965_surface_state *ss, unsigned int tiling)
655 case I915_TILING_NONE:
656 ss->ss3.tiled_surface = 0;
657 ss->ss3.tile_walk = 0;
660 ss->ss3.tiled_surface = 1;
661 ss->ss3.tile_walk = I965_TILEWALK_XMAJOR;
664 ss->ss3.tiled_surface = 1;
665 ss->ss3.tile_walk = I965_TILEWALK_YMAJOR;
671 i965_render_set_surface_state(
672 struct i965_surface_state *ss,
674 unsigned long offset,
683 unsigned int swizzle;
685 memset(ss, 0, sizeof(*ss));
687 switch (flags & (I965_PP_FLAG_TOP_FIELD|I965_PP_FLAG_BOTTOM_FIELD)) {
688 case I965_PP_FLAG_BOTTOM_FIELD:
689 ss->ss0.vert_line_stride_ofs = 1;
691 case I965_PP_FLAG_TOP_FIELD:
692 ss->ss0.vert_line_stride = 1;
697 ss->ss0.surface_type = I965_SURFACE_2D;
698 ss->ss0.surface_format = format;
699 ss->ss0.color_blend = 1;
701 ss->ss1.base_addr = bo->offset + offset;
703 ss->ss2.width = width - 1;
704 ss->ss2.height = height - 1;
706 ss->ss3.pitch = pitch - 1;
708 dri_bo_get_tiling(bo, &tiling, &swizzle);
709 i965_render_set_surface_tiling(ss, tiling);
713 gen7_render_set_surface_tiling(struct gen7_surface_state *ss, uint32_t tiling)
716 case I915_TILING_NONE:
717 ss->ss0.tiled_surface = 0;
718 ss->ss0.tile_walk = 0;
721 ss->ss0.tiled_surface = 1;
722 ss->ss0.tile_walk = I965_TILEWALK_XMAJOR;
725 ss->ss0.tiled_surface = 1;
726 ss->ss0.tile_walk = I965_TILEWALK_YMAJOR;
731 /* Set "Shader Channel Select" */
733 gen7_render_set_surface_scs(struct gen7_surface_state *ss)
735 ss->ss7.shader_chanel_select_r = HSW_SCS_RED;
736 ss->ss7.shader_chanel_select_g = HSW_SCS_GREEN;
737 ss->ss7.shader_chanel_select_b = HSW_SCS_BLUE;
738 ss->ss7.shader_chanel_select_a = HSW_SCS_ALPHA;
742 gen7_render_set_surface_state(
743 struct gen7_surface_state *ss,
745 unsigned long offset,
754 unsigned int swizzle;
756 memset(ss, 0, sizeof(*ss));
758 switch (flags & (I965_PP_FLAG_TOP_FIELD|I965_PP_FLAG_BOTTOM_FIELD)) {
759 case I965_PP_FLAG_BOTTOM_FIELD:
760 ss->ss0.vert_line_stride_ofs = 1;
762 case I965_PP_FLAG_TOP_FIELD:
763 ss->ss0.vert_line_stride = 1;
768 ss->ss0.surface_type = I965_SURFACE_2D;
769 ss->ss0.surface_format = format;
771 ss->ss1.base_addr = bo->offset + offset;
773 ss->ss2.width = width - 1;
774 ss->ss2.height = height - 1;
776 ss->ss3.pitch = pitch - 1;
778 dri_bo_get_tiling(bo, &tiling, &swizzle);
779 gen7_render_set_surface_tiling(ss, tiling);
783 i965_render_src_surface_state(
784 VADriverContextP ctx,
787 unsigned long offset,
795 struct i965_driver_data *i965 = i965_driver_data(ctx);
796 struct i965_render_state *render_state = &i965->render_state;
798 dri_bo *ss_bo = render_state->wm.surface_state_binding_table_bo;
800 assert(index < MAX_RENDER_SURFACES);
802 dri_bo_map(ss_bo, 1);
803 assert(ss_bo->virtual);
804 ss = (char *)ss_bo->virtual + SURFACE_STATE_OFFSET(index);
806 if (IS_GEN7(i965->intel.device_id)) {
807 gen7_render_set_surface_state(ss,
810 pitch, format, flags);
811 if (IS_HASWELL(i965->intel.device_id))
812 gen7_render_set_surface_scs(ss);
813 dri_bo_emit_reloc(ss_bo,
814 I915_GEM_DOMAIN_SAMPLER, 0,
816 SURFACE_STATE_OFFSET(index) + offsetof(struct gen7_surface_state, ss1),
819 i965_render_set_surface_state(ss,
822 pitch, format, flags);
823 dri_bo_emit_reloc(ss_bo,
824 I915_GEM_DOMAIN_SAMPLER, 0,
826 SURFACE_STATE_OFFSET(index) + offsetof(struct i965_surface_state, ss1),
830 ((unsigned int *)((char *)ss_bo->virtual + BINDING_TABLE_OFFSET))[index] = SURFACE_STATE_OFFSET(index);
832 render_state->wm.sampler_count++;
836 i965_render_src_surfaces_state(
837 VADriverContextP ctx,
842 struct i965_driver_data *i965 = i965_driver_data(ctx);
843 struct object_surface *obj_surface;
848 obj_surface = SURFACE(surface);
851 region_pitch = obj_surface->width;
852 rw = obj_surface->orig_width;
853 rh = obj_surface->orig_height;
854 region = obj_surface->bo;
856 i965_render_src_surface_state(ctx, 1, region, 0, rw, rh, region_pitch, I965_SURFACEFORMAT_R8_UNORM, flags); /* Y */
857 i965_render_src_surface_state(ctx, 2, region, 0, rw, rh, region_pitch, I965_SURFACEFORMAT_R8_UNORM, flags);
859 if (obj_surface->fourcc == VA_FOURCC('N', 'V', '1', '2')) {
860 i965_render_src_surface_state(ctx, 3, region,
861 region_pitch * obj_surface->y_cb_offset,
862 obj_surface->cb_cr_width, obj_surface->cb_cr_height, obj_surface->cb_cr_pitch,
863 I965_SURFACEFORMAT_R8G8_UNORM, flags); /* UV */
864 i965_render_src_surface_state(ctx, 4, region,
865 region_pitch * obj_surface->y_cb_offset,
866 obj_surface->cb_cr_width, obj_surface->cb_cr_height, obj_surface->cb_cr_pitch,
867 I965_SURFACEFORMAT_R8G8_UNORM, flags);
869 i965_render_src_surface_state(ctx, 3, region,
870 region_pitch * obj_surface->y_cb_offset,
871 obj_surface->cb_cr_width, obj_surface->cb_cr_height, obj_surface->cb_cr_pitch,
872 I965_SURFACEFORMAT_R8_UNORM, flags); /* U */
873 i965_render_src_surface_state(ctx, 4, region,
874 region_pitch * obj_surface->y_cb_offset,
875 obj_surface->cb_cr_width, obj_surface->cb_cr_height, obj_surface->cb_cr_pitch,
876 I965_SURFACEFORMAT_R8_UNORM, flags);
877 i965_render_src_surface_state(ctx, 5, region,
878 region_pitch * obj_surface->y_cr_offset,
879 obj_surface->cb_cr_width, obj_surface->cb_cr_height, obj_surface->cb_cr_pitch,
880 I965_SURFACEFORMAT_R8_UNORM, flags); /* V */
881 i965_render_src_surface_state(ctx, 6, region,
882 region_pitch * obj_surface->y_cr_offset,
883 obj_surface->cb_cr_width, obj_surface->cb_cr_height, obj_surface->cb_cr_pitch,
884 I965_SURFACEFORMAT_R8_UNORM, flags);
889 i965_subpic_render_src_surfaces_state(VADriverContextP ctx,
892 struct i965_driver_data *i965 = i965_driver_data(ctx);
893 struct object_surface *obj_surface = SURFACE(surface);
894 dri_bo *subpic_region;
895 unsigned int index = obj_surface->subpic_render_idx;
896 struct object_subpic *obj_subpic = SUBPIC(obj_surface->subpic[index]);
897 struct object_image *obj_image = IMAGE(obj_subpic->image);
899 assert(obj_surface->bo);
900 subpic_region = obj_image->bo;
901 /*subpicture surface*/
902 i965_render_src_surface_state(ctx, 1, subpic_region, 0, obj_subpic->width, obj_subpic->height, obj_subpic->pitch, obj_subpic->format, 0);
903 i965_render_src_surface_state(ctx, 2, subpic_region, 0, obj_subpic->width, obj_subpic->height, obj_subpic->pitch, obj_subpic->format, 0);
907 i965_render_dest_surface_state(VADriverContextP ctx, int index)
909 struct i965_driver_data *i965 = i965_driver_data(ctx);
910 struct i965_render_state *render_state = &i965->render_state;
911 struct intel_region *dest_region = render_state->draw_region;
913 dri_bo *ss_bo = render_state->wm.surface_state_binding_table_bo;
915 assert(index < MAX_RENDER_SURFACES);
917 if (dest_region->cpp == 2) {
918 format = I965_SURFACEFORMAT_B5G6R5_UNORM;
920 format = I965_SURFACEFORMAT_B8G8R8A8_UNORM;
923 dri_bo_map(ss_bo, 1);
924 assert(ss_bo->virtual);
925 ss = (char *)ss_bo->virtual + SURFACE_STATE_OFFSET(index);
927 if (IS_GEN7(i965->intel.device_id)) {
928 gen7_render_set_surface_state(ss,
930 dest_region->width, dest_region->height,
931 dest_region->pitch, format, 0);
932 if (IS_HASWELL(i965->intel.device_id))
933 gen7_render_set_surface_scs(ss);
934 dri_bo_emit_reloc(ss_bo,
935 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
937 SURFACE_STATE_OFFSET(index) + offsetof(struct gen7_surface_state, ss1),
940 i965_render_set_surface_state(ss,
942 dest_region->width, dest_region->height,
943 dest_region->pitch, format, 0);
944 dri_bo_emit_reloc(ss_bo,
945 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
947 SURFACE_STATE_OFFSET(index) + offsetof(struct i965_surface_state, ss1),
951 ((unsigned int *)((char *)ss_bo->virtual + BINDING_TABLE_OFFSET))[index] = SURFACE_STATE_OFFSET(index);
956 i965_fill_vertex_buffer(
957 VADriverContextP ctx,
958 float tex_coords[4], /* [(u1,v1);(u2,v2)] */
959 float vid_coords[4] /* [(x1,y1);(x2,y2)] */
962 struct i965_driver_data * const i965 = i965_driver_data(ctx);
965 enum { X1, Y1, X2, Y2 };
967 static const unsigned int g_rotation_indices[][6] = {
968 [VA_ROTATION_NONE] = { X2, Y2, X1, Y2, X1, Y1 },
969 [VA_ROTATION_90] = { X2, Y1, X2, Y2, X1, Y2 },
970 [VA_ROTATION_180] = { X1, Y1, X2, Y1, X2, Y2 },
971 [VA_ROTATION_270] = { X1, Y2, X1, Y1, X2, Y1 },
974 const unsigned int * const rotation_indices =
975 g_rotation_indices[i965->rotation_attrib->value];
977 vb[0] = tex_coords[rotation_indices[0]]; /* bottom-right corner */
978 vb[1] = tex_coords[rotation_indices[1]];
979 vb[2] = vid_coords[X2];
980 vb[3] = vid_coords[Y2];
982 vb[4] = tex_coords[rotation_indices[2]]; /* bottom-left corner */
983 vb[5] = tex_coords[rotation_indices[3]];
984 vb[6] = vid_coords[X1];
985 vb[7] = vid_coords[Y2];
987 vb[8] = tex_coords[rotation_indices[4]]; /* top-left corner */
988 vb[9] = tex_coords[rotation_indices[5]];
989 vb[10] = vid_coords[X1];
990 vb[11] = vid_coords[Y1];
992 dri_bo_subdata(i965->render_state.vb.vertex_buffer, 0, sizeof(vb), vb);
996 i965_subpic_render_upload_vertex(VADriverContextP ctx,
998 const VARectangle *output_rect)
1000 struct i965_driver_data *i965 = i965_driver_data(ctx);
1001 struct object_surface *obj_surface = SURFACE(surface);
1002 unsigned int index = obj_surface->subpic_render_idx;
1003 struct object_subpic *obj_subpic = SUBPIC(obj_surface->subpic[index]);
1004 float tex_coords[4], vid_coords[4];
1005 VARectangle dst_rect;
1007 if (obj_subpic->flags & VA_SUBPICTURE_DESTINATION_IS_SCREEN_COORD)
1008 dst_rect = obj_subpic->dst_rect;
1010 const float sx = (float)output_rect->width / obj_surface->orig_width;
1011 const float sy = (float)output_rect->height / obj_surface->orig_height;
1012 dst_rect.x = output_rect->x + sx * obj_subpic->dst_rect.x;
1013 dst_rect.y = output_rect->y + sy * obj_subpic->dst_rect.y;
1014 dst_rect.width = sx * obj_subpic->dst_rect.width;
1015 dst_rect.height = sy * obj_subpic->dst_rect.height;
1018 tex_coords[0] = (float)obj_subpic->src_rect.x / obj_subpic->width;
1019 tex_coords[1] = (float)obj_subpic->src_rect.y / obj_subpic->height;
1020 tex_coords[2] = (float)(obj_subpic->src_rect.x + obj_subpic->src_rect.width) / obj_subpic->width;
1021 tex_coords[3] = (float)(obj_subpic->src_rect.y + obj_subpic->src_rect.height) / obj_subpic->height;
1023 vid_coords[0] = dst_rect.x;
1024 vid_coords[1] = dst_rect.y;
1025 vid_coords[2] = (float)(dst_rect.x + dst_rect.width);
1026 vid_coords[3] = (float)(dst_rect.y + dst_rect.height);
1028 i965_fill_vertex_buffer(ctx, tex_coords, vid_coords);
1032 i965_render_upload_vertex(
1033 VADriverContextP ctx,
1034 VASurfaceID surface,
1035 const VARectangle *src_rect,
1036 const VARectangle *dst_rect
1039 struct i965_driver_data *i965 = i965_driver_data(ctx);
1040 struct i965_render_state *render_state = &i965->render_state;
1041 struct intel_region *dest_region = render_state->draw_region;
1042 struct object_surface *obj_surface;
1043 float tex_coords[4], vid_coords[4];
1046 obj_surface = SURFACE(surface);
1049 width = obj_surface->orig_width;
1050 height = obj_surface->orig_height;
1052 tex_coords[0] = (float)src_rect->x / width;
1053 tex_coords[1] = (float)src_rect->y / height;
1054 tex_coords[2] = (float)(src_rect->x + src_rect->width) / width;
1055 tex_coords[3] = (float)(src_rect->y + src_rect->height) / height;
1057 vid_coords[0] = dest_region->x + dst_rect->x;
1058 vid_coords[1] = dest_region->y + dst_rect->y;
1059 vid_coords[2] = vid_coords[0] + dst_rect->width;
1060 vid_coords[3] = vid_coords[1] + dst_rect->height;
1062 i965_fill_vertex_buffer(ctx, tex_coords, vid_coords);
1066 i965_render_upload_constants(VADriverContextP ctx,
1067 VASurfaceID surface)
1069 struct i965_driver_data *i965 = i965_driver_data(ctx);
1070 struct i965_render_state *render_state = &i965->render_state;
1071 unsigned short *constant_buffer;
1072 struct object_surface *obj_surface = SURFACE(surface);
1074 dri_bo_map(render_state->curbe.bo, 1);
1075 assert(render_state->curbe.bo->virtual);
1076 constant_buffer = render_state->curbe.bo->virtual;
1078 if (obj_surface->subsampling == SUBSAMPLE_YUV400) {
1079 assert(obj_surface->fourcc == VA_FOURCC('I', 'M', 'C', '1') ||
1080 obj_surface->fourcc == VA_FOURCC('I', 'M', 'C', '3'));
1081 *constant_buffer = 2;
1083 if (obj_surface->fourcc == VA_FOURCC('N', 'V', '1', '2'))
1084 *constant_buffer = 1;
1086 *constant_buffer = 0;
1089 dri_bo_unmap(render_state->curbe.bo);
1093 i965_subpic_render_upload_constants(VADriverContextP ctx,
1094 VASurfaceID surface)
1096 struct i965_driver_data *i965 = i965_driver_data(ctx);
1097 struct i965_render_state *render_state = &i965->render_state;
1098 float *constant_buffer;
1099 float global_alpha = 1.0;
1100 struct object_surface *obj_surface = SURFACE(surface);
1101 unsigned int index = obj_surface->subpic_render_idx;
1103 if(obj_surface->subpic[index] != VA_INVALID_ID){
1104 struct object_subpic *obj_subpic= SUBPIC(obj_surface->subpic[index]);
1105 if(obj_subpic->flags & VA_SUBPICTURE_GLOBAL_ALPHA){
1106 global_alpha = obj_subpic->global_alpha;
1110 dri_bo_map(render_state->curbe.bo, 1);
1112 assert(render_state->curbe.bo->virtual);
1113 constant_buffer = render_state->curbe.bo->virtual;
1114 *constant_buffer = global_alpha;
1116 dri_bo_unmap(render_state->curbe.bo);
1120 i965_surface_render_state_setup(
1121 VADriverContextP ctx,
1122 VASurfaceID surface,
1123 const VARectangle *src_rect,
1124 const VARectangle *dst_rect,
1128 i965_render_vs_unit(ctx);
1129 i965_render_sf_unit(ctx);
1130 i965_render_dest_surface_state(ctx, 0);
1131 i965_render_src_surfaces_state(ctx, surface, flags);
1132 i965_render_sampler(ctx);
1133 i965_render_wm_unit(ctx);
1134 i965_render_cc_viewport(ctx);
1135 i965_render_cc_unit(ctx);
1136 i965_render_upload_vertex(ctx, surface, src_rect, dst_rect);
1137 i965_render_upload_constants(ctx, surface);
1141 i965_subpic_render_state_setup(
1142 VADriverContextP ctx,
1143 VASurfaceID surface,
1144 const VARectangle *src_rect,
1145 const VARectangle *dst_rect
1148 i965_render_vs_unit(ctx);
1149 i965_render_sf_unit(ctx);
1150 i965_render_dest_surface_state(ctx, 0);
1151 i965_subpic_render_src_surfaces_state(ctx, surface);
1152 i965_render_sampler(ctx);
1153 i965_subpic_render_wm_unit(ctx);
1154 i965_render_cc_viewport(ctx);
1155 i965_subpic_render_cc_unit(ctx);
1156 i965_subpic_render_upload_constants(ctx, surface);
1157 i965_subpic_render_upload_vertex(ctx, surface, dst_rect);
1162 i965_render_pipeline_select(VADriverContextP ctx)
1164 struct i965_driver_data *i965 = i965_driver_data(ctx);
1165 struct intel_batchbuffer *batch = i965->batch;
1167 BEGIN_BATCH(batch, 1);
1168 OUT_BATCH(batch, CMD_PIPELINE_SELECT | PIPELINE_SELECT_3D);
1169 ADVANCE_BATCH(batch);
1173 i965_render_state_sip(VADriverContextP ctx)
1175 struct i965_driver_data *i965 = i965_driver_data(ctx);
1176 struct intel_batchbuffer *batch = i965->batch;
1178 BEGIN_BATCH(batch, 2);
1179 OUT_BATCH(batch, CMD_STATE_SIP | 0);
1180 OUT_BATCH(batch, 0);
1181 ADVANCE_BATCH(batch);
1185 i965_render_state_base_address(VADriverContextP ctx)
1187 struct i965_driver_data *i965 = i965_driver_data(ctx);
1188 struct intel_batchbuffer *batch = i965->batch;
1189 struct i965_render_state *render_state = &i965->render_state;
1191 if (IS_IRONLAKE(i965->intel.device_id)) {
1192 BEGIN_BATCH(batch, 8);
1193 OUT_BATCH(batch, CMD_STATE_BASE_ADDRESS | 6);
1194 OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
1195 OUT_RELOC(batch, render_state->wm.surface_state_binding_table_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, BASE_ADDRESS_MODIFY);
1196 OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
1197 OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
1198 OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
1199 OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
1200 OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
1201 ADVANCE_BATCH(batch);
1203 BEGIN_BATCH(batch, 6);
1204 OUT_BATCH(batch, CMD_STATE_BASE_ADDRESS | 4);
1205 OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
1206 OUT_RELOC(batch, render_state->wm.surface_state_binding_table_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, BASE_ADDRESS_MODIFY);
1207 OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
1208 OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
1209 OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
1210 ADVANCE_BATCH(batch);
1215 i965_render_binding_table_pointers(VADriverContextP ctx)
1217 struct i965_driver_data *i965 = i965_driver_data(ctx);
1218 struct intel_batchbuffer *batch = i965->batch;
1220 BEGIN_BATCH(batch, 6);
1221 OUT_BATCH(batch, CMD_BINDING_TABLE_POINTERS | 4);
1222 OUT_BATCH(batch, 0); /* vs */
1223 OUT_BATCH(batch, 0); /* gs */
1224 OUT_BATCH(batch, 0); /* clip */
1225 OUT_BATCH(batch, 0); /* sf */
1226 OUT_BATCH(batch, BINDING_TABLE_OFFSET);
1227 ADVANCE_BATCH(batch);
1231 i965_render_constant_color(VADriverContextP ctx)
1233 struct i965_driver_data *i965 = i965_driver_data(ctx);
1234 struct intel_batchbuffer *batch = i965->batch;
1236 BEGIN_BATCH(batch, 5);
1237 OUT_BATCH(batch, CMD_CONSTANT_COLOR | 3);
1238 OUT_BATCH(batch, float_to_uint(1.0));
1239 OUT_BATCH(batch, float_to_uint(0.0));
1240 OUT_BATCH(batch, float_to_uint(1.0));
1241 OUT_BATCH(batch, float_to_uint(1.0));
1242 ADVANCE_BATCH(batch);
1246 i965_render_pipelined_pointers(VADriverContextP ctx)
1248 struct i965_driver_data *i965 = i965_driver_data(ctx);
1249 struct intel_batchbuffer *batch = i965->batch;
1250 struct i965_render_state *render_state = &i965->render_state;
1252 BEGIN_BATCH(batch, 7);
1253 OUT_BATCH(batch, CMD_PIPELINED_POINTERS | 5);
1254 OUT_RELOC(batch, render_state->vs.state, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
1255 OUT_BATCH(batch, 0); /* disable GS */
1256 OUT_BATCH(batch, 0); /* disable CLIP */
1257 OUT_RELOC(batch, render_state->sf.state, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
1258 OUT_RELOC(batch, render_state->wm.state, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
1259 OUT_RELOC(batch, render_state->cc.state, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
1260 ADVANCE_BATCH(batch);
1264 i965_render_urb_layout(VADriverContextP ctx)
1266 struct i965_driver_data *i965 = i965_driver_data(ctx);
1267 struct intel_batchbuffer *batch = i965->batch;
1268 int urb_vs_start, urb_vs_size;
1269 int urb_gs_start, urb_gs_size;
1270 int urb_clip_start, urb_clip_size;
1271 int urb_sf_start, urb_sf_size;
1272 int urb_cs_start, urb_cs_size;
1275 urb_vs_size = URB_VS_ENTRIES * URB_VS_ENTRY_SIZE;
1276 urb_gs_start = urb_vs_start + urb_vs_size;
1277 urb_gs_size = URB_GS_ENTRIES * URB_GS_ENTRY_SIZE;
1278 urb_clip_start = urb_gs_start + urb_gs_size;
1279 urb_clip_size = URB_CLIP_ENTRIES * URB_CLIP_ENTRY_SIZE;
1280 urb_sf_start = urb_clip_start + urb_clip_size;
1281 urb_sf_size = URB_SF_ENTRIES * URB_SF_ENTRY_SIZE;
1282 urb_cs_start = urb_sf_start + urb_sf_size;
1283 urb_cs_size = URB_CS_ENTRIES * URB_CS_ENTRY_SIZE;
1285 BEGIN_BATCH(batch, 3);
1295 ((urb_clip_start + urb_clip_size) << UF1_CLIP_FENCE_SHIFT) |
1296 ((urb_gs_start + urb_gs_size) << UF1_GS_FENCE_SHIFT) |
1297 ((urb_vs_start + urb_vs_size) << UF1_VS_FENCE_SHIFT));
1299 ((urb_cs_start + urb_cs_size) << UF2_CS_FENCE_SHIFT) |
1300 ((urb_sf_start + urb_sf_size) << UF2_SF_FENCE_SHIFT));
1301 ADVANCE_BATCH(batch);
1305 i965_render_cs_urb_layout(VADriverContextP ctx)
1307 struct i965_driver_data *i965 = i965_driver_data(ctx);
1308 struct intel_batchbuffer *batch = i965->batch;
1310 BEGIN_BATCH(batch, 2);
1311 OUT_BATCH(batch, CMD_CS_URB_STATE | 0);
1313 ((URB_CS_ENTRY_SIZE - 1) << 4) | /* URB Entry Allocation Size */
1314 (URB_CS_ENTRIES << 0)); /* Number of URB Entries */
1315 ADVANCE_BATCH(batch);
1319 i965_render_constant_buffer(VADriverContextP ctx)
1321 struct i965_driver_data *i965 = i965_driver_data(ctx);
1322 struct intel_batchbuffer *batch = i965->batch;
1323 struct i965_render_state *render_state = &i965->render_state;
1325 BEGIN_BATCH(batch, 2);
1326 OUT_BATCH(batch, CMD_CONSTANT_BUFFER | (1 << 8) | (2 - 2));
1327 OUT_RELOC(batch, render_state->curbe.bo,
1328 I915_GEM_DOMAIN_INSTRUCTION, 0,
1329 URB_CS_ENTRY_SIZE - 1);
1330 ADVANCE_BATCH(batch);
1334 i965_render_drawing_rectangle(VADriverContextP ctx)
1336 struct i965_driver_data *i965 = i965_driver_data(ctx);
1337 struct intel_batchbuffer *batch = i965->batch;
1338 struct i965_render_state *render_state = &i965->render_state;
1339 struct intel_region *dest_region = render_state->draw_region;
1341 BEGIN_BATCH(batch, 4);
1342 OUT_BATCH(batch, CMD_DRAWING_RECTANGLE | 2);
1343 OUT_BATCH(batch, 0x00000000);
1344 OUT_BATCH(batch, (dest_region->width - 1) | (dest_region->height - 1) << 16);
1345 OUT_BATCH(batch, 0x00000000);
1346 ADVANCE_BATCH(batch);
1350 i965_render_vertex_elements(VADriverContextP ctx)
1352 struct i965_driver_data *i965 = i965_driver_data(ctx);
1353 struct intel_batchbuffer *batch = i965->batch;
1355 if (IS_IRONLAKE(i965->intel.device_id)) {
1356 BEGIN_BATCH(batch, 5);
1357 OUT_BATCH(batch, CMD_VERTEX_ELEMENTS | 3);
1358 /* offset 0: X,Y -> {X, Y, 1.0, 1.0} */
1359 OUT_BATCH(batch, (0 << VE0_VERTEX_BUFFER_INDEX_SHIFT) |
1361 (I965_SURFACEFORMAT_R32G32_FLOAT << VE0_FORMAT_SHIFT) |
1362 (0 << VE0_OFFSET_SHIFT));
1363 OUT_BATCH(batch, (I965_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT) |
1364 (I965_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT) |
1365 (I965_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_2_SHIFT) |
1366 (I965_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT));
1367 /* offset 8: S0, T0 -> {S0, T0, 1.0, 1.0} */
1368 OUT_BATCH(batch, (0 << VE0_VERTEX_BUFFER_INDEX_SHIFT) |
1370 (I965_SURFACEFORMAT_R32G32_FLOAT << VE0_FORMAT_SHIFT) |
1371 (8 << VE0_OFFSET_SHIFT));
1372 OUT_BATCH(batch, (I965_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT) |
1373 (I965_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT) |
1374 (I965_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_2_SHIFT) |
1375 (I965_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT));
1376 ADVANCE_BATCH(batch);
1378 BEGIN_BATCH(batch, 5);
1379 OUT_BATCH(batch, CMD_VERTEX_ELEMENTS | 3);
1380 /* offset 0: X,Y -> {X, Y, 1.0, 1.0} */
1381 OUT_BATCH(batch, (0 << VE0_VERTEX_BUFFER_INDEX_SHIFT) |
1383 (I965_SURFACEFORMAT_R32G32_FLOAT << VE0_FORMAT_SHIFT) |
1384 (0 << VE0_OFFSET_SHIFT));
1385 OUT_BATCH(batch, (I965_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT) |
1386 (I965_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT) |
1387 (I965_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_2_SHIFT) |
1388 (I965_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT) |
1389 (0 << VE1_DESTINATION_ELEMENT_OFFSET_SHIFT));
1390 /* offset 8: S0, T0 -> {S0, T0, 1.0, 1.0} */
1391 OUT_BATCH(batch, (0 << VE0_VERTEX_BUFFER_INDEX_SHIFT) |
1393 (I965_SURFACEFORMAT_R32G32_FLOAT << VE0_FORMAT_SHIFT) |
1394 (8 << VE0_OFFSET_SHIFT));
1395 OUT_BATCH(batch, (I965_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT) |
1396 (I965_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT) |
1397 (I965_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_2_SHIFT) |
1398 (I965_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT) |
1399 (4 << VE1_DESTINATION_ELEMENT_OFFSET_SHIFT));
1400 ADVANCE_BATCH(batch);
1405 i965_render_upload_image_palette(
1406 VADriverContextP ctx,
1411 struct i965_driver_data *i965 = i965_driver_data(ctx);
1412 struct intel_batchbuffer *batch = i965->batch;
1415 struct object_image *obj_image = IMAGE(image_id);
1418 if (obj_image->image.num_palette_entries == 0)
1421 BEGIN_BATCH(batch, 1 + obj_image->image.num_palette_entries);
1422 OUT_BATCH(batch, CMD_SAMPLER_PALETTE_LOAD | (obj_image->image.num_palette_entries - 1));
1424 //int32_t out[16]; //0-23:color 23-31:alpha
1425 for (i = 0; i < obj_image->image.num_palette_entries; i++)
1426 OUT_BATCH(batch, (alpha << 24) | obj_image->palette[i]);
1427 ADVANCE_BATCH(batch);
1431 i965_render_startup(VADriverContextP ctx)
1433 struct i965_driver_data *i965 = i965_driver_data(ctx);
1434 struct intel_batchbuffer *batch = i965->batch;
1435 struct i965_render_state *render_state = &i965->render_state;
1437 BEGIN_BATCH(batch, 11);
1438 OUT_BATCH(batch, CMD_VERTEX_BUFFERS | 3);
1440 (0 << VB0_BUFFER_INDEX_SHIFT) |
1442 ((4 * 4) << VB0_BUFFER_PITCH_SHIFT));
1443 OUT_RELOC(batch, render_state->vb.vertex_buffer, I915_GEM_DOMAIN_VERTEX, 0, 0);
1445 if (IS_IRONLAKE(i965->intel.device_id))
1446 OUT_RELOC(batch, render_state->vb.vertex_buffer, I915_GEM_DOMAIN_VERTEX, 0, 12 * 4);
1448 OUT_BATCH(batch, 3);
1450 OUT_BATCH(batch, 0);
1454 _3DPRIMITIVE_VERTEX_SEQUENTIAL |
1455 (_3DPRIM_RECTLIST << _3DPRIMITIVE_TOPOLOGY_SHIFT) |
1458 OUT_BATCH(batch, 3); /* vertex count per instance */
1459 OUT_BATCH(batch, 0); /* start vertex offset */
1460 OUT_BATCH(batch, 1); /* single instance */
1461 OUT_BATCH(batch, 0); /* start instance location */
1462 OUT_BATCH(batch, 0); /* index buffer offset, ignored */
1463 ADVANCE_BATCH(batch);
1467 i965_clear_dest_region(VADriverContextP ctx)
1469 struct i965_driver_data *i965 = i965_driver_data(ctx);
1470 struct intel_batchbuffer *batch = i965->batch;
1471 struct i965_render_state *render_state = &i965->render_state;
1472 struct intel_region *dest_region = render_state->draw_region;
1473 unsigned int blt_cmd, br13;
1476 blt_cmd = XY_COLOR_BLT_CMD;
1478 pitch = dest_region->pitch;
1480 if (dest_region->cpp == 4) {
1482 blt_cmd |= (XY_COLOR_BLT_WRITE_RGB | XY_COLOR_BLT_WRITE_ALPHA);
1484 assert(dest_region->cpp == 2);
1488 if (dest_region->tiling != I915_TILING_NONE) {
1489 blt_cmd |= XY_COLOR_BLT_DST_TILED;
1495 if (IS_GEN6(i965->intel.device_id) ||
1496 IS_GEN7(i965->intel.device_id)) {
1497 intel_batchbuffer_start_atomic_blt(batch, 24);
1498 BEGIN_BLT_BATCH(batch, 6);
1500 intel_batchbuffer_start_atomic(batch, 24);
1501 BEGIN_BATCH(batch, 6);
1504 OUT_BATCH(batch, blt_cmd);
1505 OUT_BATCH(batch, br13);
1506 OUT_BATCH(batch, (dest_region->y << 16) | (dest_region->x));
1507 OUT_BATCH(batch, ((dest_region->y + dest_region->height) << 16) |
1508 (dest_region->x + dest_region->width));
1509 OUT_RELOC(batch, dest_region->bo,
1510 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
1512 OUT_BATCH(batch, 0x0);
1513 ADVANCE_BATCH(batch);
1514 intel_batchbuffer_end_atomic(batch);
1518 i965_surface_render_pipeline_setup(VADriverContextP ctx)
1520 struct i965_driver_data *i965 = i965_driver_data(ctx);
1521 struct intel_batchbuffer *batch = i965->batch;
1523 i965_clear_dest_region(ctx);
1524 intel_batchbuffer_start_atomic(batch, 0x1000);
1525 intel_batchbuffer_emit_mi_flush(batch);
1526 i965_render_pipeline_select(ctx);
1527 i965_render_state_sip(ctx);
1528 i965_render_state_base_address(ctx);
1529 i965_render_binding_table_pointers(ctx);
1530 i965_render_constant_color(ctx);
1531 i965_render_pipelined_pointers(ctx);
1532 i965_render_urb_layout(ctx);
1533 i965_render_cs_urb_layout(ctx);
1534 i965_render_constant_buffer(ctx);
1535 i965_render_drawing_rectangle(ctx);
1536 i965_render_vertex_elements(ctx);
1537 i965_render_startup(ctx);
1538 intel_batchbuffer_end_atomic(batch);
1542 i965_subpic_render_pipeline_setup(VADriverContextP ctx)
1544 struct i965_driver_data *i965 = i965_driver_data(ctx);
1545 struct intel_batchbuffer *batch = i965->batch;
1547 intel_batchbuffer_start_atomic(batch, 0x1000);
1548 intel_batchbuffer_emit_mi_flush(batch);
1549 i965_render_pipeline_select(ctx);
1550 i965_render_state_sip(ctx);
1551 i965_render_state_base_address(ctx);
1552 i965_render_binding_table_pointers(ctx);
1553 i965_render_constant_color(ctx);
1554 i965_render_pipelined_pointers(ctx);
1555 i965_render_urb_layout(ctx);
1556 i965_render_cs_urb_layout(ctx);
1557 i965_render_drawing_rectangle(ctx);
1558 i965_render_vertex_elements(ctx);
1559 i965_render_startup(ctx);
1560 intel_batchbuffer_end_atomic(batch);
1565 i965_render_initialize(VADriverContextP ctx)
1567 struct i965_driver_data *i965 = i965_driver_data(ctx);
1568 struct i965_render_state *render_state = &i965->render_state;
1572 dri_bo_unreference(render_state->vb.vertex_buffer);
1573 bo = dri_bo_alloc(i965->intel.bufmgr,
1578 render_state->vb.vertex_buffer = bo;
1581 dri_bo_unreference(render_state->vs.state);
1582 bo = dri_bo_alloc(i965->intel.bufmgr,
1584 sizeof(struct i965_vs_unit_state),
1587 render_state->vs.state = bo;
1592 dri_bo_unreference(render_state->sf.state);
1593 bo = dri_bo_alloc(i965->intel.bufmgr,
1595 sizeof(struct i965_sf_unit_state),
1598 render_state->sf.state = bo;
1601 dri_bo_unreference(render_state->wm.surface_state_binding_table_bo);
1602 bo = dri_bo_alloc(i965->intel.bufmgr,
1603 "surface state & binding table",
1604 (SURFACE_STATE_PADDED_SIZE + sizeof(unsigned int)) * MAX_RENDER_SURFACES,
1607 render_state->wm.surface_state_binding_table_bo = bo;
1609 dri_bo_unreference(render_state->wm.sampler);
1610 bo = dri_bo_alloc(i965->intel.bufmgr,
1612 MAX_SAMPLERS * sizeof(struct i965_sampler_state),
1615 render_state->wm.sampler = bo;
1616 render_state->wm.sampler_count = 0;
1618 dri_bo_unreference(render_state->wm.state);
1619 bo = dri_bo_alloc(i965->intel.bufmgr,
1621 sizeof(struct i965_wm_unit_state),
1624 render_state->wm.state = bo;
1626 /* COLOR CALCULATOR */
1627 dri_bo_unreference(render_state->cc.state);
1628 bo = dri_bo_alloc(i965->intel.bufmgr,
1630 sizeof(struct i965_cc_unit_state),
1633 render_state->cc.state = bo;
1635 dri_bo_unreference(render_state->cc.viewport);
1636 bo = dri_bo_alloc(i965->intel.bufmgr,
1638 sizeof(struct i965_cc_viewport),
1641 render_state->cc.viewport = bo;
1645 i965_render_put_surface(
1646 VADriverContextP ctx,
1647 VASurfaceID surface,
1648 const VARectangle *src_rect,
1649 const VARectangle *dst_rect,
1653 struct i965_driver_data *i965 = i965_driver_data(ctx);
1654 struct intel_batchbuffer *batch = i965->batch;
1656 i965_render_initialize(ctx);
1657 i965_surface_render_state_setup(ctx, surface, src_rect, dst_rect, flags);
1658 i965_surface_render_pipeline_setup(ctx);
1659 intel_batchbuffer_flush(batch);
1663 i965_render_put_subpicture(
1664 VADriverContextP ctx,
1665 VASurfaceID surface,
1666 const VARectangle *src_rect,
1667 const VARectangle *dst_rect
1670 struct i965_driver_data *i965 = i965_driver_data(ctx);
1671 struct intel_batchbuffer *batch = i965->batch;
1672 struct object_surface *obj_surface = SURFACE(surface);
1673 unsigned int index = obj_surface->subpic_render_idx;
1674 struct object_subpic *obj_subpic = SUBPIC(obj_surface->subpic[index]);
1678 i965_render_initialize(ctx);
1679 i965_subpic_render_state_setup(ctx, surface, src_rect, dst_rect);
1680 i965_subpic_render_pipeline_setup(ctx);
1681 i965_render_upload_image_palette(ctx, obj_subpic->image, 0xff);
1682 intel_batchbuffer_flush(batch);
1689 gen6_render_initialize(VADriverContextP ctx)
1691 struct i965_driver_data *i965 = i965_driver_data(ctx);
1692 struct i965_render_state *render_state = &i965->render_state;
1696 dri_bo_unreference(render_state->vb.vertex_buffer);
1697 bo = dri_bo_alloc(i965->intel.bufmgr,
1702 render_state->vb.vertex_buffer = bo;
1705 dri_bo_unreference(render_state->wm.surface_state_binding_table_bo);
1706 bo = dri_bo_alloc(i965->intel.bufmgr,
1707 "surface state & binding table",
1708 (SURFACE_STATE_PADDED_SIZE + sizeof(unsigned int)) * MAX_RENDER_SURFACES,
1711 render_state->wm.surface_state_binding_table_bo = bo;
1713 dri_bo_unreference(render_state->wm.sampler);
1714 bo = dri_bo_alloc(i965->intel.bufmgr,
1716 MAX_SAMPLERS * sizeof(struct i965_sampler_state),
1719 render_state->wm.sampler = bo;
1720 render_state->wm.sampler_count = 0;
1722 /* COLOR CALCULATOR */
1723 dri_bo_unreference(render_state->cc.state);
1724 bo = dri_bo_alloc(i965->intel.bufmgr,
1726 sizeof(struct gen6_color_calc_state),
1729 render_state->cc.state = bo;
1732 dri_bo_unreference(render_state->cc.viewport);
1733 bo = dri_bo_alloc(i965->intel.bufmgr,
1735 sizeof(struct i965_cc_viewport),
1738 render_state->cc.viewport = bo;
1741 dri_bo_unreference(render_state->cc.blend);
1742 bo = dri_bo_alloc(i965->intel.bufmgr,
1744 sizeof(struct gen6_blend_state),
1747 render_state->cc.blend = bo;
1749 /* DEPTH & STENCIL STATE */
1750 dri_bo_unreference(render_state->cc.depth_stencil);
1751 bo = dri_bo_alloc(i965->intel.bufmgr,
1752 "depth & stencil state",
1753 sizeof(struct gen6_depth_stencil_state),
1756 render_state->cc.depth_stencil = bo;
1760 gen6_render_color_calc_state(VADriverContextP ctx)
1762 struct i965_driver_data *i965 = i965_driver_data(ctx);
1763 struct i965_render_state *render_state = &i965->render_state;
1764 struct gen6_color_calc_state *color_calc_state;
1766 dri_bo_map(render_state->cc.state, 1);
1767 assert(render_state->cc.state->virtual);
1768 color_calc_state = render_state->cc.state->virtual;
1769 memset(color_calc_state, 0, sizeof(*color_calc_state));
1770 color_calc_state->constant_r = 1.0;
1771 color_calc_state->constant_g = 0.0;
1772 color_calc_state->constant_b = 1.0;
1773 color_calc_state->constant_a = 1.0;
1774 dri_bo_unmap(render_state->cc.state);
1778 gen6_render_blend_state(VADriverContextP ctx)
1780 struct i965_driver_data *i965 = i965_driver_data(ctx);
1781 struct i965_render_state *render_state = &i965->render_state;
1782 struct gen6_blend_state *blend_state;
1784 dri_bo_map(render_state->cc.blend, 1);
1785 assert(render_state->cc.blend->virtual);
1786 blend_state = render_state->cc.blend->virtual;
1787 memset(blend_state, 0, sizeof(*blend_state));
1788 blend_state->blend1.logic_op_enable = 1;
1789 blend_state->blend1.logic_op_func = 0xc;
1790 dri_bo_unmap(render_state->cc.blend);
1794 gen6_render_depth_stencil_state(VADriverContextP ctx)
1796 struct i965_driver_data *i965 = i965_driver_data(ctx);
1797 struct i965_render_state *render_state = &i965->render_state;
1798 struct gen6_depth_stencil_state *depth_stencil_state;
1800 dri_bo_map(render_state->cc.depth_stencil, 1);
1801 assert(render_state->cc.depth_stencil->virtual);
1802 depth_stencil_state = render_state->cc.depth_stencil->virtual;
1803 memset(depth_stencil_state, 0, sizeof(*depth_stencil_state));
1804 dri_bo_unmap(render_state->cc.depth_stencil);
1808 gen6_render_setup_states(
1809 VADriverContextP ctx,
1810 VASurfaceID surface,
1811 const VARectangle *src_rect,
1812 const VARectangle *dst_rect,
1816 i965_render_dest_surface_state(ctx, 0);
1817 i965_render_src_surfaces_state(ctx, surface, flags);
1818 i965_render_sampler(ctx);
1819 i965_render_cc_viewport(ctx);
1820 gen6_render_color_calc_state(ctx);
1821 gen6_render_blend_state(ctx);
1822 gen6_render_depth_stencil_state(ctx);
1823 i965_render_upload_constants(ctx, surface);
1824 i965_render_upload_vertex(ctx, surface, src_rect, dst_rect);
1828 gen6_emit_invarient_states(VADriverContextP ctx)
1830 struct i965_driver_data *i965 = i965_driver_data(ctx);
1831 struct intel_batchbuffer *batch = i965->batch;
1833 OUT_BATCH(batch, CMD_PIPELINE_SELECT | PIPELINE_SELECT_3D);
1835 OUT_BATCH(batch, GEN6_3DSTATE_MULTISAMPLE | (3 - 2));
1836 OUT_BATCH(batch, GEN6_3DSTATE_MULTISAMPLE_PIXEL_LOCATION_CENTER |
1837 GEN6_3DSTATE_MULTISAMPLE_NUMSAMPLES_1); /* 1 sample/pixel */
1838 OUT_BATCH(batch, 0);
1840 OUT_BATCH(batch, GEN6_3DSTATE_SAMPLE_MASK | (2 - 2));
1841 OUT_BATCH(batch, 1);
1843 /* Set system instruction pointer */
1844 OUT_BATCH(batch, CMD_STATE_SIP | 0);
1845 OUT_BATCH(batch, 0);
1849 gen6_emit_state_base_address(VADriverContextP ctx)
1851 struct i965_driver_data *i965 = i965_driver_data(ctx);
1852 struct intel_batchbuffer *batch = i965->batch;
1853 struct i965_render_state *render_state = &i965->render_state;
1855 OUT_BATCH(batch, CMD_STATE_BASE_ADDRESS | (10 - 2));
1856 OUT_BATCH(batch, BASE_ADDRESS_MODIFY); /* General state base address */
1857 OUT_RELOC(batch, render_state->wm.surface_state_binding_table_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, BASE_ADDRESS_MODIFY); /* Surface state base address */
1858 OUT_BATCH(batch, BASE_ADDRESS_MODIFY); /* Dynamic state base address */
1859 OUT_BATCH(batch, BASE_ADDRESS_MODIFY); /* Indirect object base address */
1860 OUT_BATCH(batch, BASE_ADDRESS_MODIFY); /* Instruction base address */
1861 OUT_BATCH(batch, BASE_ADDRESS_MODIFY); /* General state upper bound */
1862 OUT_BATCH(batch, BASE_ADDRESS_MODIFY); /* Dynamic state upper bound */
1863 OUT_BATCH(batch, BASE_ADDRESS_MODIFY); /* Indirect object upper bound */
1864 OUT_BATCH(batch, BASE_ADDRESS_MODIFY); /* Instruction access upper bound */
1868 gen6_emit_viewport_state_pointers(VADriverContextP ctx)
1870 struct i965_driver_data *i965 = i965_driver_data(ctx);
1871 struct intel_batchbuffer *batch = i965->batch;
1872 struct i965_render_state *render_state = &i965->render_state;
1874 OUT_BATCH(batch, GEN6_3DSTATE_VIEWPORT_STATE_POINTERS |
1875 GEN6_3DSTATE_VIEWPORT_STATE_MODIFY_CC |
1877 OUT_BATCH(batch, 0);
1878 OUT_BATCH(batch, 0);
1879 OUT_RELOC(batch, render_state->cc.viewport, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
1883 gen6_emit_urb(VADriverContextP ctx)
1885 struct i965_driver_data *i965 = i965_driver_data(ctx);
1886 struct intel_batchbuffer *batch = i965->batch;
1888 OUT_BATCH(batch, GEN6_3DSTATE_URB | (3 - 2));
1889 OUT_BATCH(batch, ((1 - 1) << GEN6_3DSTATE_URB_VS_SIZE_SHIFT) |
1890 (24 << GEN6_3DSTATE_URB_VS_ENTRIES_SHIFT)); /* at least 24 on GEN6 */
1891 OUT_BATCH(batch, (0 << GEN6_3DSTATE_URB_GS_SIZE_SHIFT) |
1892 (0 << GEN6_3DSTATE_URB_GS_ENTRIES_SHIFT)); /* no GS thread */
1896 gen6_emit_cc_state_pointers(VADriverContextP ctx)
1898 struct i965_driver_data *i965 = i965_driver_data(ctx);
1899 struct intel_batchbuffer *batch = i965->batch;
1900 struct i965_render_state *render_state = &i965->render_state;
1902 OUT_BATCH(batch, GEN6_3DSTATE_CC_STATE_POINTERS | (4 - 2));
1903 OUT_RELOC(batch, render_state->cc.blend, I915_GEM_DOMAIN_INSTRUCTION, 0, 1);
1904 OUT_RELOC(batch, render_state->cc.depth_stencil, I915_GEM_DOMAIN_INSTRUCTION, 0, 1);
1905 OUT_RELOC(batch, render_state->cc.state, I915_GEM_DOMAIN_INSTRUCTION, 0, 1);
1909 gen6_emit_sampler_state_pointers(VADriverContextP ctx)
1911 struct i965_driver_data *i965 = i965_driver_data(ctx);
1912 struct intel_batchbuffer *batch = i965->batch;
1913 struct i965_render_state *render_state = &i965->render_state;
1915 OUT_BATCH(batch, GEN6_3DSTATE_SAMPLER_STATE_POINTERS |
1916 GEN6_3DSTATE_SAMPLER_STATE_MODIFY_PS |
1918 OUT_BATCH(batch, 0); /* VS */
1919 OUT_BATCH(batch, 0); /* GS */
1920 OUT_RELOC(batch,render_state->wm.sampler, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
1924 gen6_emit_binding_table(VADriverContextP ctx)
1926 struct i965_driver_data *i965 = i965_driver_data(ctx);
1927 struct intel_batchbuffer *batch = i965->batch;
1929 /* Binding table pointers */
1930 OUT_BATCH(batch, CMD_BINDING_TABLE_POINTERS |
1931 GEN6_BINDING_TABLE_MODIFY_PS |
1933 OUT_BATCH(batch, 0); /* vs */
1934 OUT_BATCH(batch, 0); /* gs */
1935 /* Only the PS uses the binding table */
1936 OUT_BATCH(batch, BINDING_TABLE_OFFSET);
1940 gen6_emit_depth_buffer_state(VADriverContextP ctx)
1942 struct i965_driver_data *i965 = i965_driver_data(ctx);
1943 struct intel_batchbuffer *batch = i965->batch;
1945 OUT_BATCH(batch, CMD_DEPTH_BUFFER | (7 - 2));
1946 OUT_BATCH(batch, (I965_SURFACE_NULL << CMD_DEPTH_BUFFER_TYPE_SHIFT) |
1947 (I965_DEPTHFORMAT_D32_FLOAT << CMD_DEPTH_BUFFER_FORMAT_SHIFT));
1948 OUT_BATCH(batch, 0);
1949 OUT_BATCH(batch, 0);
1950 OUT_BATCH(batch, 0);
1951 OUT_BATCH(batch, 0);
1952 OUT_BATCH(batch, 0);
1954 OUT_BATCH(batch, CMD_CLEAR_PARAMS | (2 - 2));
1955 OUT_BATCH(batch, 0);
1959 gen6_emit_drawing_rectangle(VADriverContextP ctx)
1961 i965_render_drawing_rectangle(ctx);
1965 gen6_emit_vs_state(VADriverContextP ctx)
1967 struct i965_driver_data *i965 = i965_driver_data(ctx);
1968 struct intel_batchbuffer *batch = i965->batch;
1970 /* disable VS constant buffer */
1971 OUT_BATCH(batch, GEN6_3DSTATE_CONSTANT_VS | (5 - 2));
1972 OUT_BATCH(batch, 0);
1973 OUT_BATCH(batch, 0);
1974 OUT_BATCH(batch, 0);
1975 OUT_BATCH(batch, 0);
1977 OUT_BATCH(batch, GEN6_3DSTATE_VS | (6 - 2));
1978 OUT_BATCH(batch, 0); /* without VS kernel */
1979 OUT_BATCH(batch, 0);
1980 OUT_BATCH(batch, 0);
1981 OUT_BATCH(batch, 0);
1982 OUT_BATCH(batch, 0); /* pass-through */
1986 gen6_emit_gs_state(VADriverContextP ctx)
1988 struct i965_driver_data *i965 = i965_driver_data(ctx);
1989 struct intel_batchbuffer *batch = i965->batch;
1991 /* disable GS constant buffer */
1992 OUT_BATCH(batch, GEN6_3DSTATE_CONSTANT_GS | (5 - 2));
1993 OUT_BATCH(batch, 0);
1994 OUT_BATCH(batch, 0);
1995 OUT_BATCH(batch, 0);
1996 OUT_BATCH(batch, 0);
1998 OUT_BATCH(batch, GEN6_3DSTATE_GS | (7 - 2));
1999 OUT_BATCH(batch, 0); /* without GS kernel */
2000 OUT_BATCH(batch, 0);
2001 OUT_BATCH(batch, 0);
2002 OUT_BATCH(batch, 0);
2003 OUT_BATCH(batch, 0);
2004 OUT_BATCH(batch, 0); /* pass-through */
2008 gen6_emit_clip_state(VADriverContextP ctx)
2010 struct i965_driver_data *i965 = i965_driver_data(ctx);
2011 struct intel_batchbuffer *batch = i965->batch;
2013 OUT_BATCH(batch, GEN6_3DSTATE_CLIP | (4 - 2));
2014 OUT_BATCH(batch, 0);
2015 OUT_BATCH(batch, 0); /* pass-through */
2016 OUT_BATCH(batch, 0);
2020 gen6_emit_sf_state(VADriverContextP ctx)
2022 struct i965_driver_data *i965 = i965_driver_data(ctx);
2023 struct intel_batchbuffer *batch = i965->batch;
2025 OUT_BATCH(batch, GEN6_3DSTATE_SF | (20 - 2));
2026 OUT_BATCH(batch, (1 << GEN6_3DSTATE_SF_NUM_OUTPUTS_SHIFT) |
2027 (1 << GEN6_3DSTATE_SF_URB_ENTRY_READ_LENGTH_SHIFT) |
2028 (0 << GEN6_3DSTATE_SF_URB_ENTRY_READ_OFFSET_SHIFT));
2029 OUT_BATCH(batch, 0);
2030 OUT_BATCH(batch, GEN6_3DSTATE_SF_CULL_NONE);
2031 OUT_BATCH(batch, 2 << GEN6_3DSTATE_SF_TRIFAN_PROVOKE_SHIFT); /* DW4 */
2032 OUT_BATCH(batch, 0);
2033 OUT_BATCH(batch, 0);
2034 OUT_BATCH(batch, 0);
2035 OUT_BATCH(batch, 0);
2036 OUT_BATCH(batch, 0); /* DW9 */
2037 OUT_BATCH(batch, 0);
2038 OUT_BATCH(batch, 0);
2039 OUT_BATCH(batch, 0);
2040 OUT_BATCH(batch, 0);
2041 OUT_BATCH(batch, 0); /* DW14 */
2042 OUT_BATCH(batch, 0);
2043 OUT_BATCH(batch, 0);
2044 OUT_BATCH(batch, 0);
2045 OUT_BATCH(batch, 0);
2046 OUT_BATCH(batch, 0); /* DW19 */
2050 gen6_emit_wm_state(VADriverContextP ctx, int kernel)
2052 struct i965_driver_data *i965 = i965_driver_data(ctx);
2053 struct intel_batchbuffer *batch = i965->batch;
2054 struct i965_render_state *render_state = &i965->render_state;
2056 OUT_BATCH(batch, GEN6_3DSTATE_CONSTANT_PS |
2057 GEN6_3DSTATE_CONSTANT_BUFFER_0_ENABLE |
2060 render_state->curbe.bo,
2061 I915_GEM_DOMAIN_INSTRUCTION, 0,
2063 OUT_BATCH(batch, 0);
2064 OUT_BATCH(batch, 0);
2065 OUT_BATCH(batch, 0);
2067 OUT_BATCH(batch, GEN6_3DSTATE_WM | (9 - 2));
2068 OUT_RELOC(batch, render_state->render_kernels[kernel].bo,
2069 I915_GEM_DOMAIN_INSTRUCTION, 0,
2071 OUT_BATCH(batch, (1 << GEN6_3DSTATE_WM_SAMPLER_COUNT_SHITF) |
2072 (5 << GEN6_3DSTATE_WM_BINDING_TABLE_ENTRY_COUNT_SHIFT));
2073 OUT_BATCH(batch, 0);
2074 OUT_BATCH(batch, (6 << GEN6_3DSTATE_WM_DISPATCH_START_GRF_0_SHIFT)); /* DW4 */
2075 OUT_BATCH(batch, ((40 - 1) << GEN6_3DSTATE_WM_MAX_THREADS_SHIFT) |
2076 GEN6_3DSTATE_WM_DISPATCH_ENABLE |
2077 GEN6_3DSTATE_WM_16_DISPATCH_ENABLE);
2078 OUT_BATCH(batch, (1 << GEN6_3DSTATE_WM_NUM_SF_OUTPUTS_SHIFT) |
2079 GEN6_3DSTATE_WM_PERSPECTIVE_PIXEL_BARYCENTRIC);
2080 OUT_BATCH(batch, 0);
2081 OUT_BATCH(batch, 0);
2085 gen6_emit_vertex_element_state(VADriverContextP ctx)
2087 struct i965_driver_data *i965 = i965_driver_data(ctx);
2088 struct intel_batchbuffer *batch = i965->batch;
2090 /* Set up our vertex elements, sourced from the single vertex buffer. */
2091 OUT_BATCH(batch, CMD_VERTEX_ELEMENTS | (5 - 2));
2092 /* offset 0: X,Y -> {X, Y, 1.0, 1.0} */
2093 OUT_BATCH(batch, (0 << GEN6_VE0_VERTEX_BUFFER_INDEX_SHIFT) |
2095 (I965_SURFACEFORMAT_R32G32_FLOAT << VE0_FORMAT_SHIFT) |
2096 (0 << VE0_OFFSET_SHIFT));
2097 OUT_BATCH(batch, (I965_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT) |
2098 (I965_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT) |
2099 (I965_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_2_SHIFT) |
2100 (I965_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT));
2101 /* offset 8: S0, T0 -> {S0, T0, 1.0, 1.0} */
2102 OUT_BATCH(batch, (0 << GEN6_VE0_VERTEX_BUFFER_INDEX_SHIFT) |
2104 (I965_SURFACEFORMAT_R32G32_FLOAT << VE0_FORMAT_SHIFT) |
2105 (8 << VE0_OFFSET_SHIFT));
2106 OUT_BATCH(batch, (I965_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT) |
2107 (I965_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT) |
2108 (I965_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_2_SHIFT) |
2109 (I965_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT));
2113 gen6_emit_vertices(VADriverContextP ctx)
2115 struct i965_driver_data *i965 = i965_driver_data(ctx);
2116 struct intel_batchbuffer *batch = i965->batch;
2117 struct i965_render_state *render_state = &i965->render_state;
2119 BEGIN_BATCH(batch, 11);
2120 OUT_BATCH(batch, CMD_VERTEX_BUFFERS | 3);
2122 (0 << GEN6_VB0_BUFFER_INDEX_SHIFT) |
2123 GEN6_VB0_VERTEXDATA |
2124 ((4 * 4) << VB0_BUFFER_PITCH_SHIFT));
2125 OUT_RELOC(batch, render_state->vb.vertex_buffer, I915_GEM_DOMAIN_VERTEX, 0, 0);
2126 OUT_RELOC(batch, render_state->vb.vertex_buffer, I915_GEM_DOMAIN_VERTEX, 0, 12 * 4);
2127 OUT_BATCH(batch, 0);
2131 _3DPRIMITIVE_VERTEX_SEQUENTIAL |
2132 (_3DPRIM_RECTLIST << _3DPRIMITIVE_TOPOLOGY_SHIFT) |
2135 OUT_BATCH(batch, 3); /* vertex count per instance */
2136 OUT_BATCH(batch, 0); /* start vertex offset */
2137 OUT_BATCH(batch, 1); /* single instance */
2138 OUT_BATCH(batch, 0); /* start instance location */
2139 OUT_BATCH(batch, 0); /* index buffer offset, ignored */
2140 ADVANCE_BATCH(batch);
2144 gen6_render_emit_states(VADriverContextP ctx, int kernel)
2146 struct i965_driver_data *i965 = i965_driver_data(ctx);
2147 struct intel_batchbuffer *batch = i965->batch;
2149 intel_batchbuffer_start_atomic(batch, 0x1000);
2150 intel_batchbuffer_emit_mi_flush(batch);
2151 gen6_emit_invarient_states(ctx);
2152 gen6_emit_state_base_address(ctx);
2153 gen6_emit_viewport_state_pointers(ctx);
2155 gen6_emit_cc_state_pointers(ctx);
2156 gen6_emit_sampler_state_pointers(ctx);
2157 gen6_emit_vs_state(ctx);
2158 gen6_emit_gs_state(ctx);
2159 gen6_emit_clip_state(ctx);
2160 gen6_emit_sf_state(ctx);
2161 gen6_emit_wm_state(ctx, kernel);
2162 gen6_emit_binding_table(ctx);
2163 gen6_emit_depth_buffer_state(ctx);
2164 gen6_emit_drawing_rectangle(ctx);
2165 gen6_emit_vertex_element_state(ctx);
2166 gen6_emit_vertices(ctx);
2167 intel_batchbuffer_end_atomic(batch);
2171 gen6_render_put_surface(
2172 VADriverContextP ctx,
2173 VASurfaceID surface,
2174 const VARectangle *src_rect,
2175 const VARectangle *dst_rect,
2179 struct i965_driver_data *i965 = i965_driver_data(ctx);
2180 struct intel_batchbuffer *batch = i965->batch;
2182 gen6_render_initialize(ctx);
2183 gen6_render_setup_states(ctx, surface, src_rect, dst_rect, flags);
2184 i965_clear_dest_region(ctx);
2185 gen6_render_emit_states(ctx, PS_KERNEL);
2186 intel_batchbuffer_flush(batch);
2190 gen6_subpicture_render_blend_state(VADriverContextP ctx)
2192 struct i965_driver_data *i965 = i965_driver_data(ctx);
2193 struct i965_render_state *render_state = &i965->render_state;
2194 struct gen6_blend_state *blend_state;
2196 dri_bo_unmap(render_state->cc.state);
2197 dri_bo_map(render_state->cc.blend, 1);
2198 assert(render_state->cc.blend->virtual);
2199 blend_state = render_state->cc.blend->virtual;
2200 memset(blend_state, 0, sizeof(*blend_state));
2201 blend_state->blend0.dest_blend_factor = I965_BLENDFACTOR_INV_SRC_ALPHA;
2202 blend_state->blend0.source_blend_factor = I965_BLENDFACTOR_SRC_ALPHA;
2203 blend_state->blend0.blend_func = I965_BLENDFUNCTION_ADD;
2204 blend_state->blend0.blend_enable = 1;
2205 blend_state->blend1.post_blend_clamp_enable = 1;
2206 blend_state->blend1.pre_blend_clamp_enable = 1;
2207 blend_state->blend1.clamp_range = 0; /* clamp range [0, 1] */
2208 dri_bo_unmap(render_state->cc.blend);
2212 gen6_subpicture_render_setup_states(
2213 VADriverContextP ctx,
2214 VASurfaceID surface,
2215 const VARectangle *src_rect,
2216 const VARectangle *dst_rect
2219 i965_render_dest_surface_state(ctx, 0);
2220 i965_subpic_render_src_surfaces_state(ctx, surface);
2221 i965_render_sampler(ctx);
2222 i965_render_cc_viewport(ctx);
2223 gen6_render_color_calc_state(ctx);
2224 gen6_subpicture_render_blend_state(ctx);
2225 gen6_render_depth_stencil_state(ctx);
2226 i965_subpic_render_upload_constants(ctx, surface);
2227 i965_subpic_render_upload_vertex(ctx, surface, dst_rect);
2231 gen6_render_put_subpicture(
2232 VADriverContextP ctx,
2233 VASurfaceID surface,
2234 const VARectangle *src_rect,
2235 const VARectangle *dst_rect
2238 struct i965_driver_data *i965 = i965_driver_data(ctx);
2239 struct intel_batchbuffer *batch = i965->batch;
2240 struct object_surface *obj_surface = SURFACE(surface);
2241 unsigned int index = obj_surface->subpic_render_idx;
2242 struct object_subpic *obj_subpic = SUBPIC(obj_surface->subpic[index]);
2245 gen6_render_initialize(ctx);
2246 gen6_subpicture_render_setup_states(ctx, surface, src_rect, dst_rect);
2247 gen6_render_emit_states(ctx, PS_SUBPIC_KERNEL);
2248 i965_render_upload_image_palette(ctx, obj_subpic->image, 0xff);
2249 intel_batchbuffer_flush(batch);
2256 gen7_render_initialize(VADriverContextP ctx)
2258 struct i965_driver_data *i965 = i965_driver_data(ctx);
2259 struct i965_render_state *render_state = &i965->render_state;
2263 dri_bo_unreference(render_state->vb.vertex_buffer);
2264 bo = dri_bo_alloc(i965->intel.bufmgr,
2269 render_state->vb.vertex_buffer = bo;
2272 dri_bo_unreference(render_state->wm.surface_state_binding_table_bo);
2273 bo = dri_bo_alloc(i965->intel.bufmgr,
2274 "surface state & binding table",
2275 (SURFACE_STATE_PADDED_SIZE + sizeof(unsigned int)) * MAX_RENDER_SURFACES,
2278 render_state->wm.surface_state_binding_table_bo = bo;
2280 dri_bo_unreference(render_state->wm.sampler);
2281 bo = dri_bo_alloc(i965->intel.bufmgr,
2283 MAX_SAMPLERS * sizeof(struct gen7_sampler_state),
2286 render_state->wm.sampler = bo;
2287 render_state->wm.sampler_count = 0;
2289 /* COLOR CALCULATOR */
2290 dri_bo_unreference(render_state->cc.state);
2291 bo = dri_bo_alloc(i965->intel.bufmgr,
2293 sizeof(struct gen6_color_calc_state),
2296 render_state->cc.state = bo;
2299 dri_bo_unreference(render_state->cc.viewport);
2300 bo = dri_bo_alloc(i965->intel.bufmgr,
2302 sizeof(struct i965_cc_viewport),
2305 render_state->cc.viewport = bo;
2308 dri_bo_unreference(render_state->cc.blend);
2309 bo = dri_bo_alloc(i965->intel.bufmgr,
2311 sizeof(struct gen6_blend_state),
2314 render_state->cc.blend = bo;
2316 /* DEPTH & STENCIL STATE */
2317 dri_bo_unreference(render_state->cc.depth_stencil);
2318 bo = dri_bo_alloc(i965->intel.bufmgr,
2319 "depth & stencil state",
2320 sizeof(struct gen6_depth_stencil_state),
2323 render_state->cc.depth_stencil = bo;
2327 gen7_render_color_calc_state(VADriverContextP ctx)
2329 struct i965_driver_data *i965 = i965_driver_data(ctx);
2330 struct i965_render_state *render_state = &i965->render_state;
2331 struct gen6_color_calc_state *color_calc_state;
2333 dri_bo_map(render_state->cc.state, 1);
2334 assert(render_state->cc.state->virtual);
2335 color_calc_state = render_state->cc.state->virtual;
2336 memset(color_calc_state, 0, sizeof(*color_calc_state));
2337 color_calc_state->constant_r = 1.0;
2338 color_calc_state->constant_g = 0.0;
2339 color_calc_state->constant_b = 1.0;
2340 color_calc_state->constant_a = 1.0;
2341 dri_bo_unmap(render_state->cc.state);
2345 gen7_render_blend_state(VADriverContextP ctx)
2347 struct i965_driver_data *i965 = i965_driver_data(ctx);
2348 struct i965_render_state *render_state = &i965->render_state;
2349 struct gen6_blend_state *blend_state;
2351 dri_bo_map(render_state->cc.blend, 1);
2352 assert(render_state->cc.blend->virtual);
2353 blend_state = render_state->cc.blend->virtual;
2354 memset(blend_state, 0, sizeof(*blend_state));
2355 blend_state->blend1.logic_op_enable = 1;
2356 blend_state->blend1.logic_op_func = 0xc;
2357 blend_state->blend1.pre_blend_clamp_enable = 1;
2358 dri_bo_unmap(render_state->cc.blend);
2362 gen7_render_depth_stencil_state(VADriverContextP ctx)
2364 struct i965_driver_data *i965 = i965_driver_data(ctx);
2365 struct i965_render_state *render_state = &i965->render_state;
2366 struct gen6_depth_stencil_state *depth_stencil_state;
2368 dri_bo_map(render_state->cc.depth_stencil, 1);
2369 assert(render_state->cc.depth_stencil->virtual);
2370 depth_stencil_state = render_state->cc.depth_stencil->virtual;
2371 memset(depth_stencil_state, 0, sizeof(*depth_stencil_state));
2372 dri_bo_unmap(render_state->cc.depth_stencil);
2376 gen7_render_sampler(VADriverContextP ctx)
2378 struct i965_driver_data *i965 = i965_driver_data(ctx);
2379 struct i965_render_state *render_state = &i965->render_state;
2380 struct gen7_sampler_state *sampler_state;
2383 assert(render_state->wm.sampler_count > 0);
2384 assert(render_state->wm.sampler_count <= MAX_SAMPLERS);
2386 dri_bo_map(render_state->wm.sampler, 1);
2387 assert(render_state->wm.sampler->virtual);
2388 sampler_state = render_state->wm.sampler->virtual;
2389 for (i = 0; i < render_state->wm.sampler_count; i++) {
2390 memset(sampler_state, 0, sizeof(*sampler_state));
2391 sampler_state->ss0.min_filter = I965_MAPFILTER_LINEAR;
2392 sampler_state->ss0.mag_filter = I965_MAPFILTER_LINEAR;
2393 sampler_state->ss3.r_wrap_mode = I965_TEXCOORDMODE_CLAMP;
2394 sampler_state->ss3.s_wrap_mode = I965_TEXCOORDMODE_CLAMP;
2395 sampler_state->ss3.t_wrap_mode = I965_TEXCOORDMODE_CLAMP;
2399 dri_bo_unmap(render_state->wm.sampler);
2403 gen7_render_setup_states(
2404 VADriverContextP ctx,
2405 VASurfaceID surface,
2406 const VARectangle *src_rect,
2407 const VARectangle *dst_rect,
2411 i965_render_dest_surface_state(ctx, 0);
2412 i965_render_src_surfaces_state(ctx, surface, flags);
2413 gen7_render_sampler(ctx);
2414 i965_render_cc_viewport(ctx);
2415 gen7_render_color_calc_state(ctx);
2416 gen7_render_blend_state(ctx);
2417 gen7_render_depth_stencil_state(ctx);
2418 i965_render_upload_constants(ctx, surface);
2419 i965_render_upload_vertex(ctx, surface, src_rect, dst_rect);
2423 gen7_emit_invarient_states(VADriverContextP ctx)
2425 struct i965_driver_data *i965 = i965_driver_data(ctx);
2426 struct intel_batchbuffer *batch = i965->batch;
2428 BEGIN_BATCH(batch, 1);
2429 OUT_BATCH(batch, CMD_PIPELINE_SELECT | PIPELINE_SELECT_3D);
2430 ADVANCE_BATCH(batch);
2432 BEGIN_BATCH(batch, 4);
2433 OUT_BATCH(batch, GEN6_3DSTATE_MULTISAMPLE | (4 - 2));
2434 OUT_BATCH(batch, GEN6_3DSTATE_MULTISAMPLE_PIXEL_LOCATION_CENTER |
2435 GEN6_3DSTATE_MULTISAMPLE_NUMSAMPLES_1); /* 1 sample/pixel */
2436 OUT_BATCH(batch, 0);
2437 OUT_BATCH(batch, 0);
2438 ADVANCE_BATCH(batch);
2440 BEGIN_BATCH(batch, 2);
2441 OUT_BATCH(batch, GEN6_3DSTATE_SAMPLE_MASK | (2 - 2));
2442 OUT_BATCH(batch, 1);
2443 ADVANCE_BATCH(batch);
2445 /* Set system instruction pointer */
2446 BEGIN_BATCH(batch, 2);
2447 OUT_BATCH(batch, CMD_STATE_SIP | 0);
2448 OUT_BATCH(batch, 0);
2449 ADVANCE_BATCH(batch);
2453 gen7_emit_state_base_address(VADriverContextP ctx)
2455 struct i965_driver_data *i965 = i965_driver_data(ctx);
2456 struct intel_batchbuffer *batch = i965->batch;
2457 struct i965_render_state *render_state = &i965->render_state;
2459 OUT_BATCH(batch, CMD_STATE_BASE_ADDRESS | (10 - 2));
2460 OUT_BATCH(batch, BASE_ADDRESS_MODIFY); /* General state base address */
2461 OUT_RELOC(batch, render_state->wm.surface_state_binding_table_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, BASE_ADDRESS_MODIFY); /* Surface state base address */
2462 OUT_BATCH(batch, BASE_ADDRESS_MODIFY); /* Dynamic state base address */
2463 OUT_BATCH(batch, BASE_ADDRESS_MODIFY); /* Indirect object base address */
2464 OUT_BATCH(batch, BASE_ADDRESS_MODIFY); /* Instruction base address */
2465 OUT_BATCH(batch, BASE_ADDRESS_MODIFY); /* General state upper bound */
2466 OUT_BATCH(batch, BASE_ADDRESS_MODIFY); /* Dynamic state upper bound */
2467 OUT_BATCH(batch, BASE_ADDRESS_MODIFY); /* Indirect object upper bound */
2468 OUT_BATCH(batch, BASE_ADDRESS_MODIFY); /* Instruction access upper bound */
2472 gen7_emit_viewport_state_pointers(VADriverContextP ctx)
2474 struct i965_driver_data *i965 = i965_driver_data(ctx);
2475 struct intel_batchbuffer *batch = i965->batch;
2476 struct i965_render_state *render_state = &i965->render_state;
2478 BEGIN_BATCH(batch, 2);
2479 OUT_BATCH(batch, GEN7_3DSTATE_VIEWPORT_STATE_POINTERS_CC | (2 - 2));
2481 render_state->cc.viewport,
2482 I915_GEM_DOMAIN_INSTRUCTION, 0,
2484 ADVANCE_BATCH(batch);
2486 BEGIN_BATCH(batch, 2);
2487 OUT_BATCH(batch, GEN7_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CL | (2 - 2));
2488 OUT_BATCH(batch, 0);
2489 ADVANCE_BATCH(batch);
2493 * URB layout on GEN7
2494 * ----------------------------------------
2495 * | PS Push Constants (8KB) | VS entries |
2496 * ----------------------------------------
2499 gen7_emit_urb(VADriverContextP ctx)
2501 struct i965_driver_data *i965 = i965_driver_data(ctx);
2502 struct intel_batchbuffer *batch = i965->batch;
2503 unsigned int num_urb_entries = 32;
2505 if (IS_HASWELL(i965->intel.device_id))
2506 num_urb_entries = 64;
2508 BEGIN_BATCH(batch, 2);
2509 OUT_BATCH(batch, GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_PS | (2 - 2));
2510 OUT_BATCH(batch, 8); /* in 1KBs */
2511 ADVANCE_BATCH(batch);
2513 BEGIN_BATCH(batch, 2);
2514 OUT_BATCH(batch, GEN7_3DSTATE_URB_VS | (2 - 2));
2516 (num_urb_entries << GEN7_URB_ENTRY_NUMBER_SHIFT) |
2517 (2 - 1) << GEN7_URB_ENTRY_SIZE_SHIFT |
2518 (1 << GEN7_URB_STARTING_ADDRESS_SHIFT));
2519 ADVANCE_BATCH(batch);
2521 BEGIN_BATCH(batch, 2);
2522 OUT_BATCH(batch, GEN7_3DSTATE_URB_GS | (2 - 2));
2524 (0 << GEN7_URB_ENTRY_SIZE_SHIFT) |
2525 (1 << GEN7_URB_STARTING_ADDRESS_SHIFT));
2526 ADVANCE_BATCH(batch);
2528 BEGIN_BATCH(batch, 2);
2529 OUT_BATCH(batch, GEN7_3DSTATE_URB_HS | (2 - 2));
2531 (0 << GEN7_URB_ENTRY_SIZE_SHIFT) |
2532 (2 << GEN7_URB_STARTING_ADDRESS_SHIFT));
2533 ADVANCE_BATCH(batch);
2535 BEGIN_BATCH(batch, 2);
2536 OUT_BATCH(batch, GEN7_3DSTATE_URB_DS | (2 - 2));
2538 (0 << GEN7_URB_ENTRY_SIZE_SHIFT) |
2539 (2 << GEN7_URB_STARTING_ADDRESS_SHIFT));
2540 ADVANCE_BATCH(batch);
2544 gen7_emit_cc_state_pointers(VADriverContextP ctx)
2546 struct i965_driver_data *i965 = i965_driver_data(ctx);
2547 struct intel_batchbuffer *batch = i965->batch;
2548 struct i965_render_state *render_state = &i965->render_state;
2550 BEGIN_BATCH(batch, 2);
2551 OUT_BATCH(batch, GEN6_3DSTATE_CC_STATE_POINTERS | (2 - 2));
2553 render_state->cc.state,
2554 I915_GEM_DOMAIN_INSTRUCTION, 0,
2556 ADVANCE_BATCH(batch);
2558 BEGIN_BATCH(batch, 2);
2559 OUT_BATCH(batch, GEN7_3DSTATE_BLEND_STATE_POINTERS | (2 - 2));
2561 render_state->cc.blend,
2562 I915_GEM_DOMAIN_INSTRUCTION, 0,
2564 ADVANCE_BATCH(batch);
2566 BEGIN_BATCH(batch, 2);
2567 OUT_BATCH(batch, GEN7_3DSTATE_DEPTH_STENCIL_STATE_POINTERS | (2 - 2));
2569 render_state->cc.depth_stencil,
2570 I915_GEM_DOMAIN_INSTRUCTION, 0,
2572 ADVANCE_BATCH(batch);
2576 gen7_emit_sampler_state_pointers(VADriverContextP ctx)
2578 struct i965_driver_data *i965 = i965_driver_data(ctx);
2579 struct intel_batchbuffer *batch = i965->batch;
2580 struct i965_render_state *render_state = &i965->render_state;
2582 BEGIN_BATCH(batch, 2);
2583 OUT_BATCH(batch, GEN7_3DSTATE_SAMPLER_STATE_POINTERS_PS | (2 - 2));
2585 render_state->wm.sampler,
2586 I915_GEM_DOMAIN_INSTRUCTION, 0,
2588 ADVANCE_BATCH(batch);
2592 gen7_emit_binding_table(VADriverContextP ctx)
2594 struct i965_driver_data *i965 = i965_driver_data(ctx);
2595 struct intel_batchbuffer *batch = i965->batch;
2597 BEGIN_BATCH(batch, 2);
2598 OUT_BATCH(batch, GEN7_3DSTATE_BINDING_TABLE_POINTERS_PS | (2 - 2));
2599 OUT_BATCH(batch, BINDING_TABLE_OFFSET);
2600 ADVANCE_BATCH(batch);
2604 gen7_emit_depth_buffer_state(VADriverContextP ctx)
2606 struct i965_driver_data *i965 = i965_driver_data(ctx);
2607 struct intel_batchbuffer *batch = i965->batch;
2609 BEGIN_BATCH(batch, 7);
2610 OUT_BATCH(batch, GEN7_3DSTATE_DEPTH_BUFFER | (7 - 2));
2612 (I965_DEPTHFORMAT_D32_FLOAT << 18) |
2613 (I965_SURFACE_NULL << 29));
2614 OUT_BATCH(batch, 0);
2615 OUT_BATCH(batch, 0);
2616 OUT_BATCH(batch, 0);
2617 OUT_BATCH(batch, 0);
2618 OUT_BATCH(batch, 0);
2619 ADVANCE_BATCH(batch);
2621 BEGIN_BATCH(batch, 3);
2622 OUT_BATCH(batch, GEN7_3DSTATE_CLEAR_PARAMS | (3 - 2));
2623 OUT_BATCH(batch, 0);
2624 OUT_BATCH(batch, 0);
2625 ADVANCE_BATCH(batch);
2629 gen7_emit_drawing_rectangle(VADriverContextP ctx)
2631 i965_render_drawing_rectangle(ctx);
2635 gen7_emit_vs_state(VADriverContextP ctx)
2637 struct i965_driver_data *i965 = i965_driver_data(ctx);
2638 struct intel_batchbuffer *batch = i965->batch;
2640 /* disable VS constant buffer */
2641 OUT_BATCH(batch, GEN6_3DSTATE_CONSTANT_VS | (7 - 2));
2642 OUT_BATCH(batch, 0);
2643 OUT_BATCH(batch, 0);
2644 OUT_BATCH(batch, 0);
2645 OUT_BATCH(batch, 0);
2646 OUT_BATCH(batch, 0);
2647 OUT_BATCH(batch, 0);
2649 OUT_BATCH(batch, GEN6_3DSTATE_VS | (6 - 2));
2650 OUT_BATCH(batch, 0); /* without VS kernel */
2651 OUT_BATCH(batch, 0);
2652 OUT_BATCH(batch, 0);
2653 OUT_BATCH(batch, 0);
2654 OUT_BATCH(batch, 0); /* pass-through */
2658 gen7_emit_bypass_state(VADriverContextP ctx)
2660 struct i965_driver_data *i965 = i965_driver_data(ctx);
2661 struct intel_batchbuffer *batch = i965->batch;
2664 BEGIN_BATCH(batch, 7);
2665 OUT_BATCH(batch, GEN6_3DSTATE_CONSTANT_GS | (7 - 2));
2666 OUT_BATCH(batch, 0);
2667 OUT_BATCH(batch, 0);
2668 OUT_BATCH(batch, 0);
2669 OUT_BATCH(batch, 0);
2670 OUT_BATCH(batch, 0);
2671 OUT_BATCH(batch, 0);
2672 ADVANCE_BATCH(batch);
2674 BEGIN_BATCH(batch, 7);
2675 OUT_BATCH(batch, GEN6_3DSTATE_GS | (7 - 2));
2676 OUT_BATCH(batch, 0); /* without GS kernel */
2677 OUT_BATCH(batch, 0);
2678 OUT_BATCH(batch, 0);
2679 OUT_BATCH(batch, 0);
2680 OUT_BATCH(batch, 0);
2681 OUT_BATCH(batch, 0); /* pass-through */
2682 ADVANCE_BATCH(batch);
2684 BEGIN_BATCH(batch, 2);
2685 OUT_BATCH(batch, GEN7_3DSTATE_BINDING_TABLE_POINTERS_GS | (2 - 2));
2686 OUT_BATCH(batch, 0);
2687 ADVANCE_BATCH(batch);
2690 BEGIN_BATCH(batch, 7);
2691 OUT_BATCH(batch, GEN7_3DSTATE_CONSTANT_HS | (7 - 2));
2692 OUT_BATCH(batch, 0);
2693 OUT_BATCH(batch, 0);
2694 OUT_BATCH(batch, 0);
2695 OUT_BATCH(batch, 0);
2696 OUT_BATCH(batch, 0);
2697 OUT_BATCH(batch, 0);
2698 ADVANCE_BATCH(batch);
2700 BEGIN_BATCH(batch, 7);
2701 OUT_BATCH(batch, GEN7_3DSTATE_HS | (7 - 2));
2702 OUT_BATCH(batch, 0);
2703 OUT_BATCH(batch, 0);
2704 OUT_BATCH(batch, 0);
2705 OUT_BATCH(batch, 0);
2706 OUT_BATCH(batch, 0);
2707 OUT_BATCH(batch, 0);
2708 ADVANCE_BATCH(batch);
2710 BEGIN_BATCH(batch, 2);
2711 OUT_BATCH(batch, GEN7_3DSTATE_BINDING_TABLE_POINTERS_HS | (2 - 2));
2712 OUT_BATCH(batch, 0);
2713 ADVANCE_BATCH(batch);
2716 BEGIN_BATCH(batch, 4);
2717 OUT_BATCH(batch, GEN7_3DSTATE_TE | (4 - 2));
2718 OUT_BATCH(batch, 0);
2719 OUT_BATCH(batch, 0);
2720 OUT_BATCH(batch, 0);
2721 ADVANCE_BATCH(batch);
2724 BEGIN_BATCH(batch, 7);
2725 OUT_BATCH(batch, GEN7_3DSTATE_CONSTANT_DS | (7 - 2));
2726 OUT_BATCH(batch, 0);
2727 OUT_BATCH(batch, 0);
2728 OUT_BATCH(batch, 0);
2729 OUT_BATCH(batch, 0);
2730 OUT_BATCH(batch, 0);
2731 OUT_BATCH(batch, 0);
2732 ADVANCE_BATCH(batch);
2734 BEGIN_BATCH(batch, 6);
2735 OUT_BATCH(batch, GEN7_3DSTATE_DS | (6 - 2));
2736 OUT_BATCH(batch, 0);
2737 OUT_BATCH(batch, 0);
2738 OUT_BATCH(batch, 0);
2739 OUT_BATCH(batch, 0);
2740 OUT_BATCH(batch, 0);
2741 ADVANCE_BATCH(batch);
2743 BEGIN_BATCH(batch, 2);
2744 OUT_BATCH(batch, GEN7_3DSTATE_BINDING_TABLE_POINTERS_DS | (2 - 2));
2745 OUT_BATCH(batch, 0);
2746 ADVANCE_BATCH(batch);
2748 /* Disable STREAMOUT */
2749 BEGIN_BATCH(batch, 3);
2750 OUT_BATCH(batch, GEN7_3DSTATE_STREAMOUT | (3 - 2));
2751 OUT_BATCH(batch, 0);
2752 OUT_BATCH(batch, 0);
2753 ADVANCE_BATCH(batch);
2757 gen7_emit_clip_state(VADriverContextP ctx)
2759 struct i965_driver_data *i965 = i965_driver_data(ctx);
2760 struct intel_batchbuffer *batch = i965->batch;
2762 OUT_BATCH(batch, GEN6_3DSTATE_CLIP | (4 - 2));
2763 OUT_BATCH(batch, 0);
2764 OUT_BATCH(batch, 0); /* pass-through */
2765 OUT_BATCH(batch, 0);
2769 gen7_emit_sf_state(VADriverContextP ctx)
2771 struct i965_driver_data *i965 = i965_driver_data(ctx);
2772 struct intel_batchbuffer *batch = i965->batch;
2774 BEGIN_BATCH(batch, 14);
2775 OUT_BATCH(batch, GEN7_3DSTATE_SBE | (14 - 2));
2777 (1 << GEN7_SBE_NUM_OUTPUTS_SHIFT) |
2778 (1 << GEN7_SBE_URB_ENTRY_READ_LENGTH_SHIFT) |
2779 (0 << GEN7_SBE_URB_ENTRY_READ_OFFSET_SHIFT));
2780 OUT_BATCH(batch, 0);
2781 OUT_BATCH(batch, 0);
2782 OUT_BATCH(batch, 0); /* DW4 */
2783 OUT_BATCH(batch, 0);
2784 OUT_BATCH(batch, 0);
2785 OUT_BATCH(batch, 0);
2786 OUT_BATCH(batch, 0);
2787 OUT_BATCH(batch, 0); /* DW9 */
2788 OUT_BATCH(batch, 0);
2789 OUT_BATCH(batch, 0);
2790 OUT_BATCH(batch, 0);
2791 OUT_BATCH(batch, 0);
2792 ADVANCE_BATCH(batch);
2794 BEGIN_BATCH(batch, 7);
2795 OUT_BATCH(batch, GEN6_3DSTATE_SF | (7 - 2));
2796 OUT_BATCH(batch, 0);
2797 OUT_BATCH(batch, GEN6_3DSTATE_SF_CULL_NONE);
2798 OUT_BATCH(batch, 2 << GEN6_3DSTATE_SF_TRIFAN_PROVOKE_SHIFT);
2799 OUT_BATCH(batch, 0);
2800 OUT_BATCH(batch, 0);
2801 OUT_BATCH(batch, 0);
2802 ADVANCE_BATCH(batch);
2806 gen7_emit_wm_state(VADriverContextP ctx, int kernel)
2808 struct i965_driver_data *i965 = i965_driver_data(ctx);
2809 struct intel_batchbuffer *batch = i965->batch;
2810 struct i965_render_state *render_state = &i965->render_state;
2811 unsigned int max_threads_shift = GEN7_PS_MAX_THREADS_SHIFT_IVB;
2812 unsigned int num_samples = 0;
2814 if (IS_HASWELL(i965->intel.device_id)) {
2815 max_threads_shift = GEN7_PS_MAX_THREADS_SHIFT_HSW;
2816 num_samples = 1 << GEN7_PS_SAMPLE_MASK_SHIFT_HSW;
2819 BEGIN_BATCH(batch, 3);
2820 OUT_BATCH(batch, GEN6_3DSTATE_WM | (3 - 2));
2822 GEN7_WM_DISPATCH_ENABLE |
2823 GEN7_WM_PERSPECTIVE_PIXEL_BARYCENTRIC);
2824 OUT_BATCH(batch, 0);
2825 ADVANCE_BATCH(batch);
2827 BEGIN_BATCH(batch, 7);
2828 OUT_BATCH(batch, GEN6_3DSTATE_CONSTANT_PS | (7 - 2));
2829 OUT_BATCH(batch, 1);
2830 OUT_BATCH(batch, 0);
2832 render_state->curbe.bo,
2833 I915_GEM_DOMAIN_INSTRUCTION, 0,
2835 OUT_BATCH(batch, 0);
2836 OUT_BATCH(batch, 0);
2837 OUT_BATCH(batch, 0);
2838 ADVANCE_BATCH(batch);
2840 BEGIN_BATCH(batch, 8);
2841 OUT_BATCH(batch, GEN7_3DSTATE_PS | (8 - 2));
2843 render_state->render_kernels[kernel].bo,
2844 I915_GEM_DOMAIN_INSTRUCTION, 0,
2847 (1 << GEN7_PS_SAMPLER_COUNT_SHIFT) |
2848 (5 << GEN7_PS_BINDING_TABLE_ENTRY_COUNT_SHIFT));
2849 OUT_BATCH(batch, 0); /* scratch space base offset */
2851 ((86 - 1) << max_threads_shift) | num_samples |
2852 GEN7_PS_PUSH_CONSTANT_ENABLE |
2853 GEN7_PS_ATTRIBUTE_ENABLE |
2854 GEN7_PS_16_DISPATCH_ENABLE);
2856 (6 << GEN7_PS_DISPATCH_START_GRF_SHIFT_0));
2857 OUT_BATCH(batch, 0); /* kernel 1 pointer */
2858 OUT_BATCH(batch, 0); /* kernel 2 pointer */
2859 ADVANCE_BATCH(batch);
2863 gen7_emit_vertex_element_state(VADriverContextP ctx)
2865 struct i965_driver_data *i965 = i965_driver_data(ctx);
2866 struct intel_batchbuffer *batch = i965->batch;
2868 /* Set up our vertex elements, sourced from the single vertex buffer. */
2869 OUT_BATCH(batch, CMD_VERTEX_ELEMENTS | (5 - 2));
2870 /* offset 0: X,Y -> {X, Y, 1.0, 1.0} */
2871 OUT_BATCH(batch, (0 << GEN6_VE0_VERTEX_BUFFER_INDEX_SHIFT) |
2873 (I965_SURFACEFORMAT_R32G32_FLOAT << VE0_FORMAT_SHIFT) |
2874 (0 << VE0_OFFSET_SHIFT));
2875 OUT_BATCH(batch, (I965_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT) |
2876 (I965_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT) |
2877 (I965_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_2_SHIFT) |
2878 (I965_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT));
2879 /* offset 8: S0, T0 -> {S0, T0, 1.0, 1.0} */
2880 OUT_BATCH(batch, (0 << GEN6_VE0_VERTEX_BUFFER_INDEX_SHIFT) |
2882 (I965_SURFACEFORMAT_R32G32_FLOAT << VE0_FORMAT_SHIFT) |
2883 (8 << VE0_OFFSET_SHIFT));
2884 OUT_BATCH(batch, (I965_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT) |
2885 (I965_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT) |
2886 (I965_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_2_SHIFT) |
2887 (I965_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT));
2891 gen7_emit_vertices(VADriverContextP ctx)
2893 struct i965_driver_data *i965 = i965_driver_data(ctx);
2894 struct intel_batchbuffer *batch = i965->batch;
2895 struct i965_render_state *render_state = &i965->render_state;
2897 BEGIN_BATCH(batch, 5);
2898 OUT_BATCH(batch, CMD_VERTEX_BUFFERS | (5 - 2));
2900 (0 << GEN6_VB0_BUFFER_INDEX_SHIFT) |
2901 GEN6_VB0_VERTEXDATA |
2902 GEN7_VB0_ADDRESS_MODIFYENABLE |
2903 ((4 * 4) << VB0_BUFFER_PITCH_SHIFT));
2904 OUT_RELOC(batch, render_state->vb.vertex_buffer, I915_GEM_DOMAIN_VERTEX, 0, 0);
2905 OUT_RELOC(batch, render_state->vb.vertex_buffer, I915_GEM_DOMAIN_VERTEX, 0, 12 * 4);
2906 OUT_BATCH(batch, 0);
2907 ADVANCE_BATCH(batch);
2909 BEGIN_BATCH(batch, 7);
2910 OUT_BATCH(batch, CMD_3DPRIMITIVE | (7 - 2));
2913 GEN7_3DPRIM_VERTEXBUFFER_ACCESS_SEQUENTIAL);
2914 OUT_BATCH(batch, 3); /* vertex count per instance */
2915 OUT_BATCH(batch, 0); /* start vertex offset */
2916 OUT_BATCH(batch, 1); /* single instance */
2917 OUT_BATCH(batch, 0); /* start instance location */
2918 OUT_BATCH(batch, 0);
2919 ADVANCE_BATCH(batch);
2923 gen7_render_emit_states(VADriverContextP ctx, int kernel)
2925 struct i965_driver_data *i965 = i965_driver_data(ctx);
2926 struct intel_batchbuffer *batch = i965->batch;
2928 intel_batchbuffer_start_atomic(batch, 0x1000);
2929 intel_batchbuffer_emit_mi_flush(batch);
2930 gen7_emit_invarient_states(ctx);
2931 gen7_emit_state_base_address(ctx);
2932 gen7_emit_viewport_state_pointers(ctx);
2934 gen7_emit_cc_state_pointers(ctx);
2935 gen7_emit_sampler_state_pointers(ctx);
2936 gen7_emit_bypass_state(ctx);
2937 gen7_emit_vs_state(ctx);
2938 gen7_emit_clip_state(ctx);
2939 gen7_emit_sf_state(ctx);
2940 gen7_emit_wm_state(ctx, kernel);
2941 gen7_emit_binding_table(ctx);
2942 gen7_emit_depth_buffer_state(ctx);
2943 gen7_emit_drawing_rectangle(ctx);
2944 gen7_emit_vertex_element_state(ctx);
2945 gen7_emit_vertices(ctx);
2946 intel_batchbuffer_end_atomic(batch);
2950 gen7_render_put_surface(
2951 VADriverContextP ctx,
2952 VASurfaceID surface,
2953 const VARectangle *src_rect,
2954 const VARectangle *dst_rect,
2958 struct i965_driver_data *i965 = i965_driver_data(ctx);
2959 struct intel_batchbuffer *batch = i965->batch;
2961 gen7_render_initialize(ctx);
2962 gen7_render_setup_states(ctx, surface, src_rect, dst_rect, flags);
2963 i965_clear_dest_region(ctx);
2964 gen7_render_emit_states(ctx, PS_KERNEL);
2965 intel_batchbuffer_flush(batch);
2969 gen7_subpicture_render_blend_state(VADriverContextP ctx)
2971 struct i965_driver_data *i965 = i965_driver_data(ctx);
2972 struct i965_render_state *render_state = &i965->render_state;
2973 struct gen6_blend_state *blend_state;
2975 dri_bo_unmap(render_state->cc.state);
2976 dri_bo_map(render_state->cc.blend, 1);
2977 assert(render_state->cc.blend->virtual);
2978 blend_state = render_state->cc.blend->virtual;
2979 memset(blend_state, 0, sizeof(*blend_state));
2980 blend_state->blend0.dest_blend_factor = I965_BLENDFACTOR_INV_SRC_ALPHA;
2981 blend_state->blend0.source_blend_factor = I965_BLENDFACTOR_SRC_ALPHA;
2982 blend_state->blend0.blend_func = I965_BLENDFUNCTION_ADD;
2983 blend_state->blend0.blend_enable = 1;
2984 blend_state->blend1.post_blend_clamp_enable = 1;
2985 blend_state->blend1.pre_blend_clamp_enable = 1;
2986 blend_state->blend1.clamp_range = 0; /* clamp range [0, 1] */
2987 dri_bo_unmap(render_state->cc.blend);
2991 gen7_subpicture_render_setup_states(
2992 VADriverContextP ctx,
2993 VASurfaceID surface,
2994 const VARectangle *src_rect,
2995 const VARectangle *dst_rect
2998 i965_render_dest_surface_state(ctx, 0);
2999 i965_subpic_render_src_surfaces_state(ctx, surface);
3000 i965_render_sampler(ctx);
3001 i965_render_cc_viewport(ctx);
3002 gen7_render_color_calc_state(ctx);
3003 gen7_subpicture_render_blend_state(ctx);
3004 gen7_render_depth_stencil_state(ctx);
3005 i965_subpic_render_upload_constants(ctx, surface);
3006 i965_subpic_render_upload_vertex(ctx, surface, dst_rect);
3010 gen7_render_put_subpicture(
3011 VADriverContextP ctx,
3012 VASurfaceID surface,
3013 const VARectangle *src_rect,
3014 const VARectangle *dst_rect
3017 struct i965_driver_data *i965 = i965_driver_data(ctx);
3018 struct intel_batchbuffer *batch = i965->batch;
3019 struct object_surface *obj_surface = SURFACE(surface);
3020 unsigned int index = obj_surface->subpic_render_idx;
3021 struct object_subpic *obj_subpic = SUBPIC(obj_surface->subpic[index]);
3024 gen7_render_initialize(ctx);
3025 gen7_subpicture_render_setup_states(ctx, surface, src_rect, dst_rect);
3026 gen7_render_emit_states(ctx, PS_SUBPIC_KERNEL);
3027 i965_render_upload_image_palette(ctx, obj_subpic->image, 0xff);
3028 intel_batchbuffer_flush(batch);
3036 i965_DestroySurfaces(VADriverContextP ctx,
3037 VASurfaceID *surface_list,
3040 intel_render_put_surface(
3041 VADriverContextP ctx,
3042 VASurfaceID surface,
3043 const VARectangle *src_rect,
3044 const VARectangle *dst_rect,
3048 struct i965_driver_data *i965 = i965_driver_data(ctx);
3049 int has_done_scaling = 0;
3050 VASurfaceID in_surface_id = surface;
3051 VASurfaceID out_surface_id = i965_post_processing(ctx, surface, src_rect, dst_rect, flags, &has_done_scaling);
3053 assert((!has_done_scaling) || (out_surface_id != VA_INVALID_ID));
3055 if (out_surface_id != VA_INVALID_ID)
3056 in_surface_id = out_surface_id;
3058 if (IS_GEN7(i965->intel.device_id))
3059 gen7_render_put_surface(ctx, in_surface_id, has_done_scaling ? dst_rect : src_rect, dst_rect, flags);
3060 else if (IS_GEN6(i965->intel.device_id))
3061 gen6_render_put_surface(ctx, in_surface_id, has_done_scaling ? dst_rect : src_rect, dst_rect, flags);
3063 i965_render_put_surface(ctx, in_surface_id, has_done_scaling ? dst_rect : src_rect, dst_rect, flags);
3065 if (in_surface_id != surface)
3066 i965_DestroySurfaces(ctx, &in_surface_id, 1);
3070 intel_render_put_subpicture(
3071 VADriverContextP ctx,
3072 VASurfaceID surface,
3073 const VARectangle *src_rect,
3074 const VARectangle *dst_rect
3077 struct i965_driver_data *i965 = i965_driver_data(ctx);
3079 if (IS_GEN7(i965->intel.device_id))
3080 gen7_render_put_subpicture(ctx, surface, src_rect, dst_rect);
3081 else if (IS_GEN6(i965->intel.device_id))
3082 gen6_render_put_subpicture(ctx, surface, src_rect, dst_rect);
3084 i965_render_put_subpicture(ctx, surface, src_rect, dst_rect);
3088 i965_render_init(VADriverContextP ctx)
3090 struct i965_driver_data *i965 = i965_driver_data(ctx);
3091 struct i965_render_state *render_state = &i965->render_state;
3095 assert(NUM_RENDER_KERNEL == (sizeof(render_kernels_gen5) /
3096 sizeof(render_kernels_gen5[0])));
3097 assert(NUM_RENDER_KERNEL == (sizeof(render_kernels_gen6) /
3098 sizeof(render_kernels_gen6[0])));
3100 if (IS_GEN7(i965->intel.device_id))
3101 memcpy(render_state->render_kernels,
3102 (IS_HASWELL(i965->intel.device_id) ? render_kernels_gen7_haswell : render_kernels_gen7),
3103 sizeof(render_state->render_kernels));
3104 else if (IS_GEN6(i965->intel.device_id))
3105 memcpy(render_state->render_kernels, render_kernels_gen6, sizeof(render_state->render_kernels));
3106 else if (IS_IRONLAKE(i965->intel.device_id))
3107 memcpy(render_state->render_kernels, render_kernels_gen5, sizeof(render_state->render_kernels));
3109 memcpy(render_state->render_kernels, render_kernels_gen4, sizeof(render_state->render_kernels));
3111 for (i = 0; i < NUM_RENDER_KERNEL; i++) {
3112 struct i965_kernel *kernel = &render_state->render_kernels[i];
3117 kernel->bo = dri_bo_alloc(i965->intel.bufmgr,
3119 kernel->size, 0x1000);
3121 dri_bo_subdata(kernel->bo, 0, kernel->size, kernel->bin);
3124 /* constant buffer */
3125 render_state->curbe.bo = dri_bo_alloc(i965->intel.bufmgr,
3128 assert(render_state->curbe.bo);
3134 i965_render_terminate(VADriverContextP ctx)
3137 struct i965_driver_data *i965 = i965_driver_data(ctx);
3138 struct i965_render_state *render_state = &i965->render_state;
3140 dri_bo_unreference(render_state->curbe.bo);
3141 render_state->curbe.bo = NULL;
3143 for (i = 0; i < NUM_RENDER_KERNEL; i++) {
3144 struct i965_kernel *kernel = &render_state->render_kernels[i];
3146 dri_bo_unreference(kernel->bo);
3150 dri_bo_unreference(render_state->vb.vertex_buffer);
3151 render_state->vb.vertex_buffer = NULL;
3152 dri_bo_unreference(render_state->vs.state);
3153 render_state->vs.state = NULL;
3154 dri_bo_unreference(render_state->sf.state);
3155 render_state->sf.state = NULL;
3156 dri_bo_unreference(render_state->wm.sampler);
3157 render_state->wm.sampler = NULL;
3158 dri_bo_unreference(render_state->wm.state);
3159 render_state->wm.state = NULL;
3160 dri_bo_unreference(render_state->wm.surface_state_binding_table_bo);
3161 dri_bo_unreference(render_state->cc.viewport);
3162 render_state->cc.viewport = NULL;
3163 dri_bo_unreference(render_state->cc.state);
3164 render_state->cc.state = NULL;
3165 dri_bo_unreference(render_state->cc.blend);
3166 render_state->cc.blend = NULL;
3167 dri_bo_unreference(render_state->cc.depth_stencil);
3168 render_state->cc.depth_stencil = NULL;
3170 if (render_state->draw_region) {
3171 dri_bo_unreference(render_state->draw_region->bo);
3172 free(render_state->draw_region);
3173 render_state->draw_region = NULL;