2 * Copyright © 2006 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Eric Anholt <eric@anholt.net>
25 * Keith Packard <keithp@keithp.com>
26 * Xiang Haihao <haihao.xiang@intel.com>
31 * Most of rendering codes are ported from xf86-video-intel/src/i965_video.c
40 #include <va/va_drmcommon.h>
42 #include "intel_batchbuffer.h"
43 #include "intel_driver.h"
44 #include "i965_defines.h"
45 #include "i965_drv_video.h"
46 #include "i965_structs.h"
48 #include "i965_render.h"
50 #define SF_KERNEL_NUM_GRF 16
51 #define SF_MAX_THREADS 1
53 static const uint32_t sf_kernel_static[][4] =
55 #include "shaders/render/exa_sf.g4b"
58 #define PS_KERNEL_NUM_GRF 48
59 #define PS_MAX_THREADS 32
61 #define I965_GRF_BLOCKS(nreg) ((nreg + 15) / 16 - 1)
63 static const uint32_t ps_kernel_static[][4] =
65 #include "shaders/render/exa_wm_xy.g4b"
66 #include "shaders/render/exa_wm_src_affine.g4b"
67 #include "shaders/render/exa_wm_src_sample_planar.g4b"
68 #include "shaders/render/exa_wm_yuv_color_balance.g4b"
69 #include "shaders/render/exa_wm_yuv_rgb.g4b"
70 #include "shaders/render/exa_wm_write.g4b"
72 static const uint32_t ps_subpic_kernel_static[][4] =
74 #include "shaders/render/exa_wm_xy.g4b"
75 #include "shaders/render/exa_wm_src_affine.g4b"
76 #include "shaders/render/exa_wm_src_sample_argb.g4b"
77 #include "shaders/render/exa_wm_write.g4b"
81 static const uint32_t sf_kernel_static_gen5[][4] =
83 #include "shaders/render/exa_sf.g4b.gen5"
86 static const uint32_t ps_kernel_static_gen5[][4] =
88 #include "shaders/render/exa_wm_xy.g4b.gen5"
89 #include "shaders/render/exa_wm_src_affine.g4b.gen5"
90 #include "shaders/render/exa_wm_src_sample_planar.g4b.gen5"
91 #include "shaders/render/exa_wm_yuv_color_balance.g4b.gen5"
92 #include "shaders/render/exa_wm_yuv_rgb.g4b.gen5"
93 #include "shaders/render/exa_wm_write.g4b.gen5"
95 static const uint32_t ps_subpic_kernel_static_gen5[][4] =
97 #include "shaders/render/exa_wm_xy.g4b.gen5"
98 #include "shaders/render/exa_wm_src_affine.g4b.gen5"
99 #include "shaders/render/exa_wm_src_sample_argb.g4b.gen5"
100 #include "shaders/render/exa_wm_write.g4b.gen5"
103 /* programs for Sandybridge */
104 static const uint32_t sf_kernel_static_gen6[][4] =
108 static const uint32_t ps_kernel_static_gen6[][4] = {
109 #include "shaders/render/exa_wm_src_affine.g6b"
110 #include "shaders/render/exa_wm_src_sample_planar.g6b"
111 #include "shaders/render/exa_wm_yuv_color_balance.g6b"
112 #include "shaders/render/exa_wm_yuv_rgb.g6b"
113 #include "shaders/render/exa_wm_write.g6b"
116 static const uint32_t ps_subpic_kernel_static_gen6[][4] = {
117 #include "shaders/render/exa_wm_src_affine.g6b"
118 #include "shaders/render/exa_wm_src_sample_argb.g6b"
119 #include "shaders/render/exa_wm_write.g6b"
122 /* programs for Ivybridge */
123 static const uint32_t sf_kernel_static_gen7[][4] =
127 static const uint32_t ps_kernel_static_gen7[][4] = {
128 #include "shaders/render/exa_wm_src_affine.g7b"
129 #include "shaders/render/exa_wm_src_sample_planar.g7b"
130 #include "shaders/render/exa_wm_yuv_color_balance.g7b"
131 #include "shaders/render/exa_wm_yuv_rgb.g7b"
132 #include "shaders/render/exa_wm_write.g7b"
135 static const uint32_t ps_subpic_kernel_static_gen7[][4] = {
136 #include "shaders/render/exa_wm_src_affine.g7b"
137 #include "shaders/render/exa_wm_src_sample_argb.g7b"
138 #include "shaders/render/exa_wm_write.g7b"
141 /* Programs for Haswell */
142 static const uint32_t ps_kernel_static_gen7_haswell[][4] = {
143 #include "shaders/render/exa_wm_src_affine.g7b"
144 #include "shaders/render/exa_wm_src_sample_planar.g7b.haswell"
145 #include "shaders/render/exa_wm_yuv_color_balance.g7b.haswell"
146 #include "shaders/render/exa_wm_yuv_rgb.g7b"
147 #include "shaders/render/exa_wm_write.g7b"
150 #define SURFACE_STATE_PADDED_SIZE_I965 ALIGN(sizeof(struct i965_surface_state), 32)
151 #define SURFACE_STATE_PADDED_SIZE_GEN7 ALIGN(sizeof(struct gen7_surface_state), 32)
152 #define SURFACE_STATE_PADDED_SIZE MAX(SURFACE_STATE_PADDED_SIZE_I965, SURFACE_STATE_PADDED_SIZE_GEN7)
153 #define SURFACE_STATE_OFFSET(index) (SURFACE_STATE_PADDED_SIZE * index)
154 #define BINDING_TABLE_OFFSET SURFACE_STATE_OFFSET(MAX_RENDER_SURFACES)
156 static uint32_t float_to_uint (float f)
174 static struct i965_kernel render_kernels_gen4[] = {
179 sizeof(sf_kernel_static),
186 sizeof(ps_kernel_static),
193 ps_subpic_kernel_static,
194 sizeof(ps_subpic_kernel_static),
199 static struct i965_kernel render_kernels_gen5[] = {
203 sf_kernel_static_gen5,
204 sizeof(sf_kernel_static_gen5),
210 ps_kernel_static_gen5,
211 sizeof(ps_kernel_static_gen5),
218 ps_subpic_kernel_static_gen5,
219 sizeof(ps_subpic_kernel_static_gen5),
224 static struct i965_kernel render_kernels_gen6[] = {
228 sf_kernel_static_gen6,
229 sizeof(sf_kernel_static_gen6),
235 ps_kernel_static_gen6,
236 sizeof(ps_kernel_static_gen6),
243 ps_subpic_kernel_static_gen6,
244 sizeof(ps_subpic_kernel_static_gen6),
249 static struct i965_kernel render_kernels_gen7[] = {
253 sf_kernel_static_gen7,
254 sizeof(sf_kernel_static_gen7),
260 ps_kernel_static_gen7,
261 sizeof(ps_kernel_static_gen7),
268 ps_subpic_kernel_static_gen7,
269 sizeof(ps_subpic_kernel_static_gen7),
274 static struct i965_kernel render_kernels_gen7_haswell[] = {
278 sf_kernel_static_gen7,
279 sizeof(sf_kernel_static_gen7),
285 ps_kernel_static_gen7_haswell,
286 sizeof(ps_kernel_static_gen7_haswell),
293 ps_subpic_kernel_static_gen7,
294 sizeof(ps_subpic_kernel_static_gen7),
299 #define URB_VS_ENTRIES 8
300 #define URB_VS_ENTRY_SIZE 1
302 #define URB_GS_ENTRIES 0
303 #define URB_GS_ENTRY_SIZE 0
305 #define URB_CLIP_ENTRIES 0
306 #define URB_CLIP_ENTRY_SIZE 0
308 #define URB_SF_ENTRIES 1
309 #define URB_SF_ENTRY_SIZE 2
311 #define URB_CS_ENTRIES 4
312 #define URB_CS_ENTRY_SIZE 4
315 i965_render_vs_unit(VADriverContextP ctx)
317 struct i965_driver_data *i965 = i965_driver_data(ctx);
318 struct i965_render_state *render_state = &i965->render_state;
319 struct i965_vs_unit_state *vs_state;
321 dri_bo_map(render_state->vs.state, 1);
322 assert(render_state->vs.state->virtual);
323 vs_state = render_state->vs.state->virtual;
324 memset(vs_state, 0, sizeof(*vs_state));
326 if (IS_IRONLAKE(i965->intel.device_id))
327 vs_state->thread4.nr_urb_entries = URB_VS_ENTRIES >> 2;
329 vs_state->thread4.nr_urb_entries = URB_VS_ENTRIES;
331 vs_state->thread4.urb_entry_allocation_size = URB_VS_ENTRY_SIZE - 1;
332 vs_state->vs6.vs_enable = 0;
333 vs_state->vs6.vert_cache_disable = 1;
335 dri_bo_unmap(render_state->vs.state);
339 i965_render_sf_unit(VADriverContextP ctx)
341 struct i965_driver_data *i965 = i965_driver_data(ctx);
342 struct i965_render_state *render_state = &i965->render_state;
343 struct i965_sf_unit_state *sf_state;
345 dri_bo_map(render_state->sf.state, 1);
346 assert(render_state->sf.state->virtual);
347 sf_state = render_state->sf.state->virtual;
348 memset(sf_state, 0, sizeof(*sf_state));
350 sf_state->thread0.grf_reg_count = I965_GRF_BLOCKS(SF_KERNEL_NUM_GRF);
351 sf_state->thread0.kernel_start_pointer = render_state->render_kernels[SF_KERNEL].bo->offset >> 6;
353 sf_state->sf1.single_program_flow = 1; /* XXX */
354 sf_state->sf1.binding_table_entry_count = 0;
355 sf_state->sf1.thread_priority = 0;
356 sf_state->sf1.floating_point_mode = 0; /* Mesa does this */
357 sf_state->sf1.illegal_op_exception_enable = 1;
358 sf_state->sf1.mask_stack_exception_enable = 1;
359 sf_state->sf1.sw_exception_enable = 1;
361 /* scratch space is not used in our kernel */
362 sf_state->thread2.per_thread_scratch_space = 0;
363 sf_state->thread2.scratch_space_base_pointer = 0;
365 sf_state->thread3.const_urb_entry_read_length = 0; /* no const URBs */
366 sf_state->thread3.const_urb_entry_read_offset = 0; /* no const URBs */
367 sf_state->thread3.urb_entry_read_length = 1; /* 1 URB per vertex */
368 sf_state->thread3.urb_entry_read_offset = 0;
369 sf_state->thread3.dispatch_grf_start_reg = 3;
371 sf_state->thread4.max_threads = SF_MAX_THREADS - 1;
372 sf_state->thread4.urb_entry_allocation_size = URB_SF_ENTRY_SIZE - 1;
373 sf_state->thread4.nr_urb_entries = URB_SF_ENTRIES;
374 sf_state->thread4.stats_enable = 1;
376 sf_state->sf5.viewport_transform = 0; /* skip viewport */
378 sf_state->sf6.cull_mode = I965_CULLMODE_NONE;
379 sf_state->sf6.scissor = 0;
381 sf_state->sf7.trifan_pv = 2;
383 sf_state->sf6.dest_org_vbias = 0x8;
384 sf_state->sf6.dest_org_hbias = 0x8;
386 dri_bo_emit_reloc(render_state->sf.state,
387 I915_GEM_DOMAIN_INSTRUCTION, 0,
388 sf_state->thread0.grf_reg_count << 1,
389 offsetof(struct i965_sf_unit_state, thread0),
390 render_state->render_kernels[SF_KERNEL].bo);
392 dri_bo_unmap(render_state->sf.state);
396 i965_render_sampler(VADriverContextP ctx)
398 struct i965_driver_data *i965 = i965_driver_data(ctx);
399 struct i965_render_state *render_state = &i965->render_state;
400 struct i965_sampler_state *sampler_state;
403 assert(render_state->wm.sampler_count > 0);
404 assert(render_state->wm.sampler_count <= MAX_SAMPLERS);
406 dri_bo_map(render_state->wm.sampler, 1);
407 assert(render_state->wm.sampler->virtual);
408 sampler_state = render_state->wm.sampler->virtual;
409 for (i = 0; i < render_state->wm.sampler_count; i++) {
410 memset(sampler_state, 0, sizeof(*sampler_state));
411 sampler_state->ss0.min_filter = I965_MAPFILTER_LINEAR;
412 sampler_state->ss0.mag_filter = I965_MAPFILTER_LINEAR;
413 sampler_state->ss1.r_wrap_mode = I965_TEXCOORDMODE_CLAMP;
414 sampler_state->ss1.s_wrap_mode = I965_TEXCOORDMODE_CLAMP;
415 sampler_state->ss1.t_wrap_mode = I965_TEXCOORDMODE_CLAMP;
419 dri_bo_unmap(render_state->wm.sampler);
422 i965_subpic_render_wm_unit(VADriverContextP ctx)
424 struct i965_driver_data *i965 = i965_driver_data(ctx);
425 struct i965_render_state *render_state = &i965->render_state;
426 struct i965_wm_unit_state *wm_state;
428 assert(render_state->wm.sampler);
430 dri_bo_map(render_state->wm.state, 1);
431 assert(render_state->wm.state->virtual);
432 wm_state = render_state->wm.state->virtual;
433 memset(wm_state, 0, sizeof(*wm_state));
435 wm_state->thread0.grf_reg_count = I965_GRF_BLOCKS(PS_KERNEL_NUM_GRF);
436 wm_state->thread0.kernel_start_pointer = render_state->render_kernels[PS_SUBPIC_KERNEL].bo->offset >> 6;
438 wm_state->thread1.single_program_flow = 1; /* XXX */
440 if (IS_IRONLAKE(i965->intel.device_id))
441 wm_state->thread1.binding_table_entry_count = 0; /* hardware requirement */
443 wm_state->thread1.binding_table_entry_count = 7;
445 wm_state->thread2.scratch_space_base_pointer = 0;
446 wm_state->thread2.per_thread_scratch_space = 0; /* 1024 bytes */
448 wm_state->thread3.dispatch_grf_start_reg = 2; /* XXX */
449 wm_state->thread3.const_urb_entry_read_length = 4;
450 wm_state->thread3.const_urb_entry_read_offset = 0;
451 wm_state->thread3.urb_entry_read_length = 1; /* XXX */
452 wm_state->thread3.urb_entry_read_offset = 0; /* XXX */
454 wm_state->wm4.stats_enable = 0;
455 wm_state->wm4.sampler_state_pointer = render_state->wm.sampler->offset >> 5;
457 if (IS_IRONLAKE(i965->intel.device_id)) {
458 wm_state->wm4.sampler_count = 0; /* hardware requirement */
460 wm_state->wm4.sampler_count = (render_state->wm.sampler_count + 3) / 4;
463 wm_state->wm5.max_threads = render_state->max_wm_threads - 1;
464 wm_state->wm5.thread_dispatch_enable = 1;
465 wm_state->wm5.enable_16_pix = 1;
466 wm_state->wm5.enable_8_pix = 0;
467 wm_state->wm5.early_depth_test = 1;
469 dri_bo_emit_reloc(render_state->wm.state,
470 I915_GEM_DOMAIN_INSTRUCTION, 0,
471 wm_state->thread0.grf_reg_count << 1,
472 offsetof(struct i965_wm_unit_state, thread0),
473 render_state->render_kernels[PS_SUBPIC_KERNEL].bo);
475 dri_bo_emit_reloc(render_state->wm.state,
476 I915_GEM_DOMAIN_INSTRUCTION, 0,
477 wm_state->wm4.sampler_count << 2,
478 offsetof(struct i965_wm_unit_state, wm4),
479 render_state->wm.sampler);
481 dri_bo_unmap(render_state->wm.state);
486 i965_render_wm_unit(VADriverContextP ctx)
488 struct i965_driver_data *i965 = i965_driver_data(ctx);
489 struct i965_render_state *render_state = &i965->render_state;
490 struct i965_wm_unit_state *wm_state;
492 assert(render_state->wm.sampler);
494 dri_bo_map(render_state->wm.state, 1);
495 assert(render_state->wm.state->virtual);
496 wm_state = render_state->wm.state->virtual;
497 memset(wm_state, 0, sizeof(*wm_state));
499 wm_state->thread0.grf_reg_count = I965_GRF_BLOCKS(PS_KERNEL_NUM_GRF);
500 wm_state->thread0.kernel_start_pointer = render_state->render_kernels[PS_KERNEL].bo->offset >> 6;
502 wm_state->thread1.single_program_flow = 1; /* XXX */
504 if (IS_IRONLAKE(i965->intel.device_id))
505 wm_state->thread1.binding_table_entry_count = 0; /* hardware requirement */
507 wm_state->thread1.binding_table_entry_count = 7;
509 wm_state->thread2.scratch_space_base_pointer = 0;
510 wm_state->thread2.per_thread_scratch_space = 0; /* 1024 bytes */
512 wm_state->thread3.dispatch_grf_start_reg = 2; /* XXX */
513 wm_state->thread3.const_urb_entry_read_length = 4;
514 wm_state->thread3.const_urb_entry_read_offset = 0;
515 wm_state->thread3.urb_entry_read_length = 1; /* XXX */
516 wm_state->thread3.urb_entry_read_offset = 0; /* XXX */
518 wm_state->wm4.stats_enable = 0;
519 wm_state->wm4.sampler_state_pointer = render_state->wm.sampler->offset >> 5;
521 if (IS_IRONLAKE(i965->intel.device_id)) {
522 wm_state->wm4.sampler_count = 0; /* hardware requirement */
524 wm_state->wm4.sampler_count = (render_state->wm.sampler_count + 3) / 4;
527 wm_state->wm5.max_threads = render_state->max_wm_threads - 1;
528 wm_state->wm5.thread_dispatch_enable = 1;
529 wm_state->wm5.enable_16_pix = 1;
530 wm_state->wm5.enable_8_pix = 0;
531 wm_state->wm5.early_depth_test = 1;
533 dri_bo_emit_reloc(render_state->wm.state,
534 I915_GEM_DOMAIN_INSTRUCTION, 0,
535 wm_state->thread0.grf_reg_count << 1,
536 offsetof(struct i965_wm_unit_state, thread0),
537 render_state->render_kernels[PS_KERNEL].bo);
539 dri_bo_emit_reloc(render_state->wm.state,
540 I915_GEM_DOMAIN_INSTRUCTION, 0,
541 wm_state->wm4.sampler_count << 2,
542 offsetof(struct i965_wm_unit_state, wm4),
543 render_state->wm.sampler);
545 dri_bo_unmap(render_state->wm.state);
549 i965_render_cc_viewport(VADriverContextP ctx)
551 struct i965_driver_data *i965 = i965_driver_data(ctx);
552 struct i965_render_state *render_state = &i965->render_state;
553 struct i965_cc_viewport *cc_viewport;
555 dri_bo_map(render_state->cc.viewport, 1);
556 assert(render_state->cc.viewport->virtual);
557 cc_viewport = render_state->cc.viewport->virtual;
558 memset(cc_viewport, 0, sizeof(*cc_viewport));
560 cc_viewport->min_depth = -1.e35;
561 cc_viewport->max_depth = 1.e35;
563 dri_bo_unmap(render_state->cc.viewport);
567 i965_subpic_render_cc_unit(VADriverContextP ctx)
569 struct i965_driver_data *i965 = i965_driver_data(ctx);
570 struct i965_render_state *render_state = &i965->render_state;
571 struct i965_cc_unit_state *cc_state;
573 assert(render_state->cc.viewport);
575 dri_bo_map(render_state->cc.state, 1);
576 assert(render_state->cc.state->virtual);
577 cc_state = render_state->cc.state->virtual;
578 memset(cc_state, 0, sizeof(*cc_state));
580 cc_state->cc0.stencil_enable = 0; /* disable stencil */
581 cc_state->cc2.depth_test = 0; /* disable depth test */
582 cc_state->cc2.logicop_enable = 0; /* disable logic op */
583 cc_state->cc3.ia_blend_enable = 0 ; /* blend alpha just like colors */
584 cc_state->cc3.blend_enable = 1; /* enable color blend */
585 cc_state->cc3.alpha_test = 0; /* disable alpha test */
586 cc_state->cc3.alpha_test_format = 0;//0:ALPHATEST_UNORM8; /*store alpha value with UNORM8 */
587 cc_state->cc3.alpha_test_func = 5;//COMPAREFUNCTION_LESS; /*pass if less than the reference */
588 cc_state->cc4.cc_viewport_state_offset = render_state->cc.viewport->offset >> 5;
590 cc_state->cc5.dither_enable = 0; /* disable dither */
591 cc_state->cc5.logicop_func = 0xc; /* WHITE */
592 cc_state->cc5.statistics_enable = 1;
593 cc_state->cc5.ia_blend_function = I965_BLENDFUNCTION_ADD;
594 cc_state->cc5.ia_src_blend_factor = I965_BLENDFACTOR_DST_ALPHA;
595 cc_state->cc5.ia_dest_blend_factor = I965_BLENDFACTOR_DST_ALPHA;
597 cc_state->cc6.clamp_post_alpha_blend = 0;
598 cc_state->cc6.clamp_pre_alpha_blend =0;
600 /*final color = src_color*src_blend_factor +/- dst_color*dest_color_blend_factor*/
601 cc_state->cc6.blend_function = I965_BLENDFUNCTION_ADD;
602 cc_state->cc6.src_blend_factor = I965_BLENDFACTOR_SRC_ALPHA;
603 cc_state->cc6.dest_blend_factor = I965_BLENDFACTOR_INV_SRC_ALPHA;
605 /*alpha test reference*/
606 cc_state->cc7.alpha_ref.f =0.0 ;
609 dri_bo_emit_reloc(render_state->cc.state,
610 I915_GEM_DOMAIN_INSTRUCTION, 0,
612 offsetof(struct i965_cc_unit_state, cc4),
613 render_state->cc.viewport);
615 dri_bo_unmap(render_state->cc.state);
620 i965_render_cc_unit(VADriverContextP ctx)
622 struct i965_driver_data *i965 = i965_driver_data(ctx);
623 struct i965_render_state *render_state = &i965->render_state;
624 struct i965_cc_unit_state *cc_state;
626 assert(render_state->cc.viewport);
628 dri_bo_map(render_state->cc.state, 1);
629 assert(render_state->cc.state->virtual);
630 cc_state = render_state->cc.state->virtual;
631 memset(cc_state, 0, sizeof(*cc_state));
633 cc_state->cc0.stencil_enable = 0; /* disable stencil */
634 cc_state->cc2.depth_test = 0; /* disable depth test */
635 cc_state->cc2.logicop_enable = 1; /* enable logic op */
636 cc_state->cc3.ia_blend_enable = 0; /* blend alpha just like colors */
637 cc_state->cc3.blend_enable = 0; /* disable color blend */
638 cc_state->cc3.alpha_test = 0; /* disable alpha test */
639 cc_state->cc4.cc_viewport_state_offset = render_state->cc.viewport->offset >> 5;
641 cc_state->cc5.dither_enable = 0; /* disable dither */
642 cc_state->cc5.logicop_func = 0xc; /* WHITE */
643 cc_state->cc5.statistics_enable = 1;
644 cc_state->cc5.ia_blend_function = I965_BLENDFUNCTION_ADD;
645 cc_state->cc5.ia_src_blend_factor = I965_BLENDFACTOR_ONE;
646 cc_state->cc5.ia_dest_blend_factor = I965_BLENDFACTOR_ONE;
648 dri_bo_emit_reloc(render_state->cc.state,
649 I915_GEM_DOMAIN_INSTRUCTION, 0,
651 offsetof(struct i965_cc_unit_state, cc4),
652 render_state->cc.viewport);
654 dri_bo_unmap(render_state->cc.state);
658 i965_render_set_surface_tiling(struct i965_surface_state *ss, unsigned int tiling)
661 case I915_TILING_NONE:
662 ss->ss3.tiled_surface = 0;
663 ss->ss3.tile_walk = 0;
666 ss->ss3.tiled_surface = 1;
667 ss->ss3.tile_walk = I965_TILEWALK_XMAJOR;
670 ss->ss3.tiled_surface = 1;
671 ss->ss3.tile_walk = I965_TILEWALK_YMAJOR;
677 i965_render_set_surface_state(
678 struct i965_surface_state *ss,
680 unsigned long offset,
689 unsigned int swizzle;
691 memset(ss, 0, sizeof(*ss));
693 switch (flags & (I965_PP_FLAG_TOP_FIELD|I965_PP_FLAG_BOTTOM_FIELD)) {
694 case I965_PP_FLAG_BOTTOM_FIELD:
695 ss->ss0.vert_line_stride_ofs = 1;
697 case I965_PP_FLAG_TOP_FIELD:
698 ss->ss0.vert_line_stride = 1;
703 ss->ss0.surface_type = I965_SURFACE_2D;
704 ss->ss0.surface_format = format;
705 ss->ss0.color_blend = 1;
707 ss->ss1.base_addr = bo->offset + offset;
709 ss->ss2.width = width - 1;
710 ss->ss2.height = height - 1;
712 ss->ss3.pitch = pitch - 1;
714 dri_bo_get_tiling(bo, &tiling, &swizzle);
715 i965_render_set_surface_tiling(ss, tiling);
719 gen7_render_set_surface_tiling(struct gen7_surface_state *ss, uint32_t tiling)
722 case I915_TILING_NONE:
723 ss->ss0.tiled_surface = 0;
724 ss->ss0.tile_walk = 0;
727 ss->ss0.tiled_surface = 1;
728 ss->ss0.tile_walk = I965_TILEWALK_XMAJOR;
731 ss->ss0.tiled_surface = 1;
732 ss->ss0.tile_walk = I965_TILEWALK_YMAJOR;
737 /* Set "Shader Channel Select" */
739 gen7_render_set_surface_scs(struct gen7_surface_state *ss)
741 ss->ss7.shader_chanel_select_r = HSW_SCS_RED;
742 ss->ss7.shader_chanel_select_g = HSW_SCS_GREEN;
743 ss->ss7.shader_chanel_select_b = HSW_SCS_BLUE;
744 ss->ss7.shader_chanel_select_a = HSW_SCS_ALPHA;
748 gen7_render_set_surface_state(
749 struct gen7_surface_state *ss,
751 unsigned long offset,
760 unsigned int swizzle;
762 memset(ss, 0, sizeof(*ss));
764 switch (flags & (I965_PP_FLAG_TOP_FIELD|I965_PP_FLAG_BOTTOM_FIELD)) {
765 case I965_PP_FLAG_BOTTOM_FIELD:
766 ss->ss0.vert_line_stride_ofs = 1;
768 case I965_PP_FLAG_TOP_FIELD:
769 ss->ss0.vert_line_stride = 1;
774 ss->ss0.surface_type = I965_SURFACE_2D;
775 ss->ss0.surface_format = format;
777 ss->ss1.base_addr = bo->offset + offset;
779 ss->ss2.width = width - 1;
780 ss->ss2.height = height - 1;
782 ss->ss3.pitch = pitch - 1;
784 dri_bo_get_tiling(bo, &tiling, &swizzle);
785 gen7_render_set_surface_tiling(ss, tiling);
789 i965_render_src_surface_state(
790 VADriverContextP ctx,
793 unsigned long offset,
801 struct i965_driver_data *i965 = i965_driver_data(ctx);
802 struct i965_render_state *render_state = &i965->render_state;
804 dri_bo *ss_bo = render_state->wm.surface_state_binding_table_bo;
806 assert(index < MAX_RENDER_SURFACES);
808 dri_bo_map(ss_bo, 1);
809 assert(ss_bo->virtual);
810 ss = (char *)ss_bo->virtual + SURFACE_STATE_OFFSET(index);
812 if (IS_GEN7(i965->intel.device_id)) {
813 gen7_render_set_surface_state(ss,
816 pitch, format, flags);
817 if (IS_HASWELL(i965->intel.device_id))
818 gen7_render_set_surface_scs(ss);
819 dri_bo_emit_reloc(ss_bo,
820 I915_GEM_DOMAIN_SAMPLER, 0,
822 SURFACE_STATE_OFFSET(index) + offsetof(struct gen7_surface_state, ss1),
825 i965_render_set_surface_state(ss,
828 pitch, format, flags);
829 dri_bo_emit_reloc(ss_bo,
830 I915_GEM_DOMAIN_SAMPLER, 0,
832 SURFACE_STATE_OFFSET(index) + offsetof(struct i965_surface_state, ss1),
836 ((unsigned int *)((char *)ss_bo->virtual + BINDING_TABLE_OFFSET))[index] = SURFACE_STATE_OFFSET(index);
838 render_state->wm.sampler_count++;
842 i965_render_src_surfaces_state(
843 VADriverContextP ctx,
844 struct object_surface *obj_surface,
852 region_pitch = obj_surface->width;
853 rw = obj_surface->orig_width;
854 rh = obj_surface->orig_height;
855 region = obj_surface->bo;
857 i965_render_src_surface_state(ctx, 1, region, 0, rw, rh, region_pitch, I965_SURFACEFORMAT_R8_UNORM, flags); /* Y */
858 i965_render_src_surface_state(ctx, 2, region, 0, rw, rh, region_pitch, I965_SURFACEFORMAT_R8_UNORM, flags);
860 if (obj_surface->fourcc == VA_FOURCC('N', 'V', '1', '2')) {
861 i965_render_src_surface_state(ctx, 3, region,
862 region_pitch * obj_surface->y_cb_offset,
863 obj_surface->cb_cr_width, obj_surface->cb_cr_height, obj_surface->cb_cr_pitch,
864 I965_SURFACEFORMAT_R8G8_UNORM, flags); /* UV */
865 i965_render_src_surface_state(ctx, 4, region,
866 region_pitch * obj_surface->y_cb_offset,
867 obj_surface->cb_cr_width, obj_surface->cb_cr_height, obj_surface->cb_cr_pitch,
868 I965_SURFACEFORMAT_R8G8_UNORM, flags);
870 i965_render_src_surface_state(ctx, 3, region,
871 region_pitch * obj_surface->y_cb_offset,
872 obj_surface->cb_cr_width, obj_surface->cb_cr_height, obj_surface->cb_cr_pitch,
873 I965_SURFACEFORMAT_R8_UNORM, flags); /* U */
874 i965_render_src_surface_state(ctx, 4, region,
875 region_pitch * obj_surface->y_cb_offset,
876 obj_surface->cb_cr_width, obj_surface->cb_cr_height, obj_surface->cb_cr_pitch,
877 I965_SURFACEFORMAT_R8_UNORM, flags);
878 i965_render_src_surface_state(ctx, 5, region,
879 region_pitch * obj_surface->y_cr_offset,
880 obj_surface->cb_cr_width, obj_surface->cb_cr_height, obj_surface->cb_cr_pitch,
881 I965_SURFACEFORMAT_R8_UNORM, flags); /* V */
882 i965_render_src_surface_state(ctx, 6, region,
883 region_pitch * obj_surface->y_cr_offset,
884 obj_surface->cb_cr_width, obj_surface->cb_cr_height, obj_surface->cb_cr_pitch,
885 I965_SURFACEFORMAT_R8_UNORM, flags);
890 i965_subpic_render_src_surfaces_state(VADriverContextP ctx,
891 struct object_surface *obj_surface)
893 dri_bo *subpic_region;
894 unsigned int index = obj_surface->subpic_render_idx;
895 struct object_subpic *obj_subpic = obj_surface->obj_subpic[index];
896 struct object_image *obj_image = obj_subpic->obj_image;
899 assert(obj_surface->bo);
900 subpic_region = obj_image->bo;
901 /*subpicture surface*/
902 i965_render_src_surface_state(ctx, 1, subpic_region, 0, obj_subpic->width, obj_subpic->height, obj_subpic->pitch, obj_subpic->format, 0);
903 i965_render_src_surface_state(ctx, 2, subpic_region, 0, obj_subpic->width, obj_subpic->height, obj_subpic->pitch, obj_subpic->format, 0);
907 i965_render_dest_surface_state(VADriverContextP ctx, int index)
909 struct i965_driver_data *i965 = i965_driver_data(ctx);
910 struct i965_render_state *render_state = &i965->render_state;
911 struct intel_region *dest_region = render_state->draw_region;
913 dri_bo *ss_bo = render_state->wm.surface_state_binding_table_bo;
915 assert(index < MAX_RENDER_SURFACES);
917 if (dest_region->cpp == 2) {
918 format = I965_SURFACEFORMAT_B5G6R5_UNORM;
920 format = I965_SURFACEFORMAT_B8G8R8A8_UNORM;
923 dri_bo_map(ss_bo, 1);
924 assert(ss_bo->virtual);
925 ss = (char *)ss_bo->virtual + SURFACE_STATE_OFFSET(index);
927 if (IS_GEN7(i965->intel.device_id)) {
928 gen7_render_set_surface_state(ss,
930 dest_region->width, dest_region->height,
931 dest_region->pitch, format, 0);
932 if (IS_HASWELL(i965->intel.device_id))
933 gen7_render_set_surface_scs(ss);
934 dri_bo_emit_reloc(ss_bo,
935 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
937 SURFACE_STATE_OFFSET(index) + offsetof(struct gen7_surface_state, ss1),
940 i965_render_set_surface_state(ss,
942 dest_region->width, dest_region->height,
943 dest_region->pitch, format, 0);
944 dri_bo_emit_reloc(ss_bo,
945 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
947 SURFACE_STATE_OFFSET(index) + offsetof(struct i965_surface_state, ss1),
951 ((unsigned int *)((char *)ss_bo->virtual + BINDING_TABLE_OFFSET))[index] = SURFACE_STATE_OFFSET(index);
956 i965_fill_vertex_buffer(
957 VADriverContextP ctx,
958 float tex_coords[4], /* [(u1,v1);(u2,v2)] */
959 float vid_coords[4] /* [(x1,y1);(x2,y2)] */
962 struct i965_driver_data * const i965 = i965_driver_data(ctx);
965 enum { X1, Y1, X2, Y2 };
967 static const unsigned int g_rotation_indices[][6] = {
968 [VA_ROTATION_NONE] = { X2, Y2, X1, Y2, X1, Y1 },
969 [VA_ROTATION_90] = { X2, Y1, X2, Y2, X1, Y2 },
970 [VA_ROTATION_180] = { X1, Y1, X2, Y1, X2, Y2 },
971 [VA_ROTATION_270] = { X1, Y2, X1, Y1, X2, Y1 },
974 const unsigned int * const rotation_indices =
975 g_rotation_indices[i965->rotation_attrib->value];
977 vb[0] = tex_coords[rotation_indices[0]]; /* bottom-right corner */
978 vb[1] = tex_coords[rotation_indices[1]];
979 vb[2] = vid_coords[X2];
980 vb[3] = vid_coords[Y2];
982 vb[4] = tex_coords[rotation_indices[2]]; /* bottom-left corner */
983 vb[5] = tex_coords[rotation_indices[3]];
984 vb[6] = vid_coords[X1];
985 vb[7] = vid_coords[Y2];
987 vb[8] = tex_coords[rotation_indices[4]]; /* top-left corner */
988 vb[9] = tex_coords[rotation_indices[5]];
989 vb[10] = vid_coords[X1];
990 vb[11] = vid_coords[Y1];
992 dri_bo_subdata(i965->render_state.vb.vertex_buffer, 0, sizeof(vb), vb);
996 i965_subpic_render_upload_vertex(VADriverContextP ctx,
997 struct object_surface *obj_surface,
998 const VARectangle *output_rect)
1000 unsigned int index = obj_surface->subpic_render_idx;
1001 struct object_subpic *obj_subpic = obj_surface->obj_subpic[index];
1002 float tex_coords[4], vid_coords[4];
1003 VARectangle dst_rect;
1005 if (obj_subpic->flags & VA_SUBPICTURE_DESTINATION_IS_SCREEN_COORD)
1006 dst_rect = obj_subpic->dst_rect;
1008 const float sx = (float)output_rect->width / obj_surface->orig_width;
1009 const float sy = (float)output_rect->height / obj_surface->orig_height;
1010 dst_rect.x = output_rect->x + sx * obj_subpic->dst_rect.x;
1011 dst_rect.y = output_rect->y + sy * obj_subpic->dst_rect.y;
1012 dst_rect.width = sx * obj_subpic->dst_rect.width;
1013 dst_rect.height = sy * obj_subpic->dst_rect.height;
1016 tex_coords[0] = (float)obj_subpic->src_rect.x / obj_subpic->width;
1017 tex_coords[1] = (float)obj_subpic->src_rect.y / obj_subpic->height;
1018 tex_coords[2] = (float)(obj_subpic->src_rect.x + obj_subpic->src_rect.width) / obj_subpic->width;
1019 tex_coords[3] = (float)(obj_subpic->src_rect.y + obj_subpic->src_rect.height) / obj_subpic->height;
1021 vid_coords[0] = dst_rect.x;
1022 vid_coords[1] = dst_rect.y;
1023 vid_coords[2] = (float)(dst_rect.x + dst_rect.width);
1024 vid_coords[3] = (float)(dst_rect.y + dst_rect.height);
1026 i965_fill_vertex_buffer(ctx, tex_coords, vid_coords);
1030 i965_render_upload_vertex(
1031 VADriverContextP ctx,
1032 struct object_surface *obj_surface,
1033 const VARectangle *src_rect,
1034 const VARectangle *dst_rect
1037 struct i965_driver_data *i965 = i965_driver_data(ctx);
1038 struct i965_render_state *render_state = &i965->render_state;
1039 struct intel_region *dest_region = render_state->draw_region;
1040 float tex_coords[4], vid_coords[4];
1043 width = obj_surface->orig_width;
1044 height = obj_surface->orig_height;
1046 tex_coords[0] = (float)src_rect->x / width;
1047 tex_coords[1] = (float)src_rect->y / height;
1048 tex_coords[2] = (float)(src_rect->x + src_rect->width) / width;
1049 tex_coords[3] = (float)(src_rect->y + src_rect->height) / height;
1051 vid_coords[0] = dest_region->x + dst_rect->x;
1052 vid_coords[1] = dest_region->y + dst_rect->y;
1053 vid_coords[2] = vid_coords[0] + dst_rect->width;
1054 vid_coords[3] = vid_coords[1] + dst_rect->height;
1056 i965_fill_vertex_buffer(ctx, tex_coords, vid_coords);
1059 #define PI 3.1415926
1062 i965_render_upload_constants(VADriverContextP ctx,
1063 struct object_surface *obj_surface)
1065 struct i965_driver_data *i965 = i965_driver_data(ctx);
1066 struct i965_render_state *render_state = &i965->render_state;
1067 unsigned short *constant_buffer;
1068 float *color_balance_base;
1069 float contrast = (float)i965->contrast_attrib->value / DEFAULT_CONTRAST;
1070 float brightness = (float)i965->brightness_attrib->value / 255; /* YUV is float in the shader */
1071 float hue = (float)i965->hue_attrib->value / 180 * PI;
1072 float saturation = (float)i965->saturation_attrib->value / DEFAULT_SATURATION;
1074 dri_bo_map(render_state->curbe.bo, 1);
1075 assert(render_state->curbe.bo->virtual);
1076 constant_buffer = render_state->curbe.bo->virtual;
1078 if (obj_surface->subsampling == SUBSAMPLE_YUV400) {
1079 assert(obj_surface->fourcc == VA_FOURCC('Y', '8', '0', '0'));
1081 constant_buffer[0] = 2;
1083 if (obj_surface->fourcc == VA_FOURCC('N', 'V', '1', '2'))
1084 constant_buffer[0] = 1;
1086 constant_buffer[0] = 0;
1089 if (i965->contrast_attrib->value == DEFAULT_CONTRAST &&
1090 i965->brightness_attrib->value == DEFAULT_BRIGHTNESS &&
1091 i965->hue_attrib->value == DEFAULT_HUE &&
1092 i965->saturation_attrib->value == DEFAULT_SATURATION)
1093 constant_buffer[1] = 1; /* skip color balance transformation */
1095 constant_buffer[1] = 0;
1097 color_balance_base = (float *)constant_buffer + 4;
1098 *color_balance_base++ = contrast;
1099 *color_balance_base++ = brightness;
1100 *color_balance_base++ = cos(hue) * contrast * saturation;
1101 *color_balance_base++ = sin(hue) * contrast * saturation;
1103 dri_bo_unmap(render_state->curbe.bo);
1107 i965_subpic_render_upload_constants(VADriverContextP ctx,
1108 struct object_surface *obj_surface)
1110 struct i965_driver_data *i965 = i965_driver_data(ctx);
1111 struct i965_render_state *render_state = &i965->render_state;
1112 float *constant_buffer;
1113 float global_alpha = 1.0;
1114 unsigned int index = obj_surface->subpic_render_idx;
1115 struct object_subpic *obj_subpic = obj_surface->obj_subpic[index];
1117 if (obj_subpic->flags & VA_SUBPICTURE_GLOBAL_ALPHA) {
1118 global_alpha = obj_subpic->global_alpha;
1121 dri_bo_map(render_state->curbe.bo, 1);
1123 assert(render_state->curbe.bo->virtual);
1124 constant_buffer = render_state->curbe.bo->virtual;
1125 *constant_buffer = global_alpha;
1127 dri_bo_unmap(render_state->curbe.bo);
1131 i965_surface_render_state_setup(
1132 VADriverContextP ctx,
1133 struct object_surface *obj_surface,
1134 const VARectangle *src_rect,
1135 const VARectangle *dst_rect,
1139 i965_render_vs_unit(ctx);
1140 i965_render_sf_unit(ctx);
1141 i965_render_dest_surface_state(ctx, 0);
1142 i965_render_src_surfaces_state(ctx, obj_surface, flags);
1143 i965_render_sampler(ctx);
1144 i965_render_wm_unit(ctx);
1145 i965_render_cc_viewport(ctx);
1146 i965_render_cc_unit(ctx);
1147 i965_render_upload_vertex(ctx, obj_surface, src_rect, dst_rect);
1148 i965_render_upload_constants(ctx, obj_surface);
1152 i965_subpic_render_state_setup(
1153 VADriverContextP ctx,
1154 struct object_surface *obj_surface,
1155 const VARectangle *src_rect,
1156 const VARectangle *dst_rect
1159 i965_render_vs_unit(ctx);
1160 i965_render_sf_unit(ctx);
1161 i965_render_dest_surface_state(ctx, 0);
1162 i965_subpic_render_src_surfaces_state(ctx, obj_surface);
1163 i965_render_sampler(ctx);
1164 i965_subpic_render_wm_unit(ctx);
1165 i965_render_cc_viewport(ctx);
1166 i965_subpic_render_cc_unit(ctx);
1167 i965_subpic_render_upload_constants(ctx, obj_surface);
1168 i965_subpic_render_upload_vertex(ctx, obj_surface, dst_rect);
1173 i965_render_pipeline_select(VADriverContextP ctx)
1175 struct i965_driver_data *i965 = i965_driver_data(ctx);
1176 struct intel_batchbuffer *batch = i965->batch;
1178 BEGIN_BATCH(batch, 1);
1179 OUT_BATCH(batch, CMD_PIPELINE_SELECT | PIPELINE_SELECT_3D);
1180 ADVANCE_BATCH(batch);
1184 i965_render_state_sip(VADriverContextP ctx)
1186 struct i965_driver_data *i965 = i965_driver_data(ctx);
1187 struct intel_batchbuffer *batch = i965->batch;
1189 BEGIN_BATCH(batch, 2);
1190 OUT_BATCH(batch, CMD_STATE_SIP | 0);
1191 OUT_BATCH(batch, 0);
1192 ADVANCE_BATCH(batch);
1196 i965_render_state_base_address(VADriverContextP ctx)
1198 struct i965_driver_data *i965 = i965_driver_data(ctx);
1199 struct intel_batchbuffer *batch = i965->batch;
1200 struct i965_render_state *render_state = &i965->render_state;
1202 if (IS_IRONLAKE(i965->intel.device_id)) {
1203 BEGIN_BATCH(batch, 8);
1204 OUT_BATCH(batch, CMD_STATE_BASE_ADDRESS | 6);
1205 OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
1206 OUT_RELOC(batch, render_state->wm.surface_state_binding_table_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, BASE_ADDRESS_MODIFY);
1207 OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
1208 OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
1209 OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
1210 OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
1211 OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
1212 ADVANCE_BATCH(batch);
1214 BEGIN_BATCH(batch, 6);
1215 OUT_BATCH(batch, CMD_STATE_BASE_ADDRESS | 4);
1216 OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
1217 OUT_RELOC(batch, render_state->wm.surface_state_binding_table_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, BASE_ADDRESS_MODIFY);
1218 OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
1219 OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
1220 OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
1221 ADVANCE_BATCH(batch);
1226 i965_render_binding_table_pointers(VADriverContextP ctx)
1228 struct i965_driver_data *i965 = i965_driver_data(ctx);
1229 struct intel_batchbuffer *batch = i965->batch;
1231 BEGIN_BATCH(batch, 6);
1232 OUT_BATCH(batch, CMD_BINDING_TABLE_POINTERS | 4);
1233 OUT_BATCH(batch, 0); /* vs */
1234 OUT_BATCH(batch, 0); /* gs */
1235 OUT_BATCH(batch, 0); /* clip */
1236 OUT_BATCH(batch, 0); /* sf */
1237 OUT_BATCH(batch, BINDING_TABLE_OFFSET);
1238 ADVANCE_BATCH(batch);
1242 i965_render_constant_color(VADriverContextP ctx)
1244 struct i965_driver_data *i965 = i965_driver_data(ctx);
1245 struct intel_batchbuffer *batch = i965->batch;
1247 BEGIN_BATCH(batch, 5);
1248 OUT_BATCH(batch, CMD_CONSTANT_COLOR | 3);
1249 OUT_BATCH(batch, float_to_uint(1.0));
1250 OUT_BATCH(batch, float_to_uint(0.0));
1251 OUT_BATCH(batch, float_to_uint(1.0));
1252 OUT_BATCH(batch, float_to_uint(1.0));
1253 ADVANCE_BATCH(batch);
1257 i965_render_pipelined_pointers(VADriverContextP ctx)
1259 struct i965_driver_data *i965 = i965_driver_data(ctx);
1260 struct intel_batchbuffer *batch = i965->batch;
1261 struct i965_render_state *render_state = &i965->render_state;
1263 BEGIN_BATCH(batch, 7);
1264 OUT_BATCH(batch, CMD_PIPELINED_POINTERS | 5);
1265 OUT_RELOC(batch, render_state->vs.state, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
1266 OUT_BATCH(batch, 0); /* disable GS */
1267 OUT_BATCH(batch, 0); /* disable CLIP */
1268 OUT_RELOC(batch, render_state->sf.state, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
1269 OUT_RELOC(batch, render_state->wm.state, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
1270 OUT_RELOC(batch, render_state->cc.state, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
1271 ADVANCE_BATCH(batch);
1275 i965_render_urb_layout(VADriverContextP ctx)
1277 struct i965_driver_data *i965 = i965_driver_data(ctx);
1278 struct intel_batchbuffer *batch = i965->batch;
1279 int urb_vs_start, urb_vs_size;
1280 int urb_gs_start, urb_gs_size;
1281 int urb_clip_start, urb_clip_size;
1282 int urb_sf_start, urb_sf_size;
1283 int urb_cs_start, urb_cs_size;
1286 urb_vs_size = URB_VS_ENTRIES * URB_VS_ENTRY_SIZE;
1287 urb_gs_start = urb_vs_start + urb_vs_size;
1288 urb_gs_size = URB_GS_ENTRIES * URB_GS_ENTRY_SIZE;
1289 urb_clip_start = urb_gs_start + urb_gs_size;
1290 urb_clip_size = URB_CLIP_ENTRIES * URB_CLIP_ENTRY_SIZE;
1291 urb_sf_start = urb_clip_start + urb_clip_size;
1292 urb_sf_size = URB_SF_ENTRIES * URB_SF_ENTRY_SIZE;
1293 urb_cs_start = urb_sf_start + urb_sf_size;
1294 urb_cs_size = URB_CS_ENTRIES * URB_CS_ENTRY_SIZE;
1296 BEGIN_BATCH(batch, 3);
1306 ((urb_clip_start + urb_clip_size) << UF1_CLIP_FENCE_SHIFT) |
1307 ((urb_gs_start + urb_gs_size) << UF1_GS_FENCE_SHIFT) |
1308 ((urb_vs_start + urb_vs_size) << UF1_VS_FENCE_SHIFT));
1310 ((urb_cs_start + urb_cs_size) << UF2_CS_FENCE_SHIFT) |
1311 ((urb_sf_start + urb_sf_size) << UF2_SF_FENCE_SHIFT));
1312 ADVANCE_BATCH(batch);
1316 i965_render_cs_urb_layout(VADriverContextP ctx)
1318 struct i965_driver_data *i965 = i965_driver_data(ctx);
1319 struct intel_batchbuffer *batch = i965->batch;
1321 BEGIN_BATCH(batch, 2);
1322 OUT_BATCH(batch, CMD_CS_URB_STATE | 0);
1324 ((URB_CS_ENTRY_SIZE - 1) << 4) | /* URB Entry Allocation Size */
1325 (URB_CS_ENTRIES << 0)); /* Number of URB Entries */
1326 ADVANCE_BATCH(batch);
1330 i965_render_constant_buffer(VADriverContextP ctx)
1332 struct i965_driver_data *i965 = i965_driver_data(ctx);
1333 struct intel_batchbuffer *batch = i965->batch;
1334 struct i965_render_state *render_state = &i965->render_state;
1336 BEGIN_BATCH(batch, 2);
1337 OUT_BATCH(batch, CMD_CONSTANT_BUFFER | (1 << 8) | (2 - 2));
1338 OUT_RELOC(batch, render_state->curbe.bo,
1339 I915_GEM_DOMAIN_INSTRUCTION, 0,
1340 URB_CS_ENTRY_SIZE - 1);
1341 ADVANCE_BATCH(batch);
1345 i965_render_drawing_rectangle(VADriverContextP ctx)
1347 struct i965_driver_data *i965 = i965_driver_data(ctx);
1348 struct intel_batchbuffer *batch = i965->batch;
1349 struct i965_render_state *render_state = &i965->render_state;
1350 struct intel_region *dest_region = render_state->draw_region;
1352 BEGIN_BATCH(batch, 4);
1353 OUT_BATCH(batch, CMD_DRAWING_RECTANGLE | 2);
1354 OUT_BATCH(batch, 0x00000000);
1355 OUT_BATCH(batch, (dest_region->width - 1) | (dest_region->height - 1) << 16);
1356 OUT_BATCH(batch, 0x00000000);
1357 ADVANCE_BATCH(batch);
1361 i965_render_vertex_elements(VADriverContextP ctx)
1363 struct i965_driver_data *i965 = i965_driver_data(ctx);
1364 struct intel_batchbuffer *batch = i965->batch;
1366 if (IS_IRONLAKE(i965->intel.device_id)) {
1367 BEGIN_BATCH(batch, 5);
1368 OUT_BATCH(batch, CMD_VERTEX_ELEMENTS | 3);
1369 /* offset 0: X,Y -> {X, Y, 1.0, 1.0} */
1370 OUT_BATCH(batch, (0 << VE0_VERTEX_BUFFER_INDEX_SHIFT) |
1372 (I965_SURFACEFORMAT_R32G32_FLOAT << VE0_FORMAT_SHIFT) |
1373 (0 << VE0_OFFSET_SHIFT));
1374 OUT_BATCH(batch, (I965_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT) |
1375 (I965_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT) |
1376 (I965_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_2_SHIFT) |
1377 (I965_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT));
1378 /* offset 8: S0, T0 -> {S0, T0, 1.0, 1.0} */
1379 OUT_BATCH(batch, (0 << VE0_VERTEX_BUFFER_INDEX_SHIFT) |
1381 (I965_SURFACEFORMAT_R32G32_FLOAT << VE0_FORMAT_SHIFT) |
1382 (8 << VE0_OFFSET_SHIFT));
1383 OUT_BATCH(batch, (I965_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT) |
1384 (I965_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT) |
1385 (I965_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_2_SHIFT) |
1386 (I965_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT));
1387 ADVANCE_BATCH(batch);
1389 BEGIN_BATCH(batch, 5);
1390 OUT_BATCH(batch, CMD_VERTEX_ELEMENTS | 3);
1391 /* offset 0: X,Y -> {X, Y, 1.0, 1.0} */
1392 OUT_BATCH(batch, (0 << VE0_VERTEX_BUFFER_INDEX_SHIFT) |
1394 (I965_SURFACEFORMAT_R32G32_FLOAT << VE0_FORMAT_SHIFT) |
1395 (0 << VE0_OFFSET_SHIFT));
1396 OUT_BATCH(batch, (I965_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT) |
1397 (I965_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT) |
1398 (I965_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_2_SHIFT) |
1399 (I965_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT) |
1400 (0 << VE1_DESTINATION_ELEMENT_OFFSET_SHIFT));
1401 /* offset 8: S0, T0 -> {S0, T0, 1.0, 1.0} */
1402 OUT_BATCH(batch, (0 << VE0_VERTEX_BUFFER_INDEX_SHIFT) |
1404 (I965_SURFACEFORMAT_R32G32_FLOAT << VE0_FORMAT_SHIFT) |
1405 (8 << VE0_OFFSET_SHIFT));
1406 OUT_BATCH(batch, (I965_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT) |
1407 (I965_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT) |
1408 (I965_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_2_SHIFT) |
1409 (I965_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT) |
1410 (4 << VE1_DESTINATION_ELEMENT_OFFSET_SHIFT));
1411 ADVANCE_BATCH(batch);
1416 i965_render_upload_image_palette(
1417 VADriverContextP ctx,
1418 struct object_image *obj_image,
1422 struct i965_driver_data *i965 = i965_driver_data(ctx);
1423 struct intel_batchbuffer *batch = i965->batch;
1431 if (obj_image->image.num_palette_entries == 0)
1434 BEGIN_BATCH(batch, 1 + obj_image->image.num_palette_entries);
1435 OUT_BATCH(batch, CMD_SAMPLER_PALETTE_LOAD | (obj_image->image.num_palette_entries - 1));
1437 //int32_t out[16]; //0-23:color 23-31:alpha
1438 for (i = 0; i < obj_image->image.num_palette_entries; i++)
1439 OUT_BATCH(batch, (alpha << 24) | obj_image->palette[i]);
1440 ADVANCE_BATCH(batch);
1444 i965_render_startup(VADriverContextP ctx)
1446 struct i965_driver_data *i965 = i965_driver_data(ctx);
1447 struct intel_batchbuffer *batch = i965->batch;
1448 struct i965_render_state *render_state = &i965->render_state;
1450 BEGIN_BATCH(batch, 11);
1451 OUT_BATCH(batch, CMD_VERTEX_BUFFERS | 3);
1453 (0 << VB0_BUFFER_INDEX_SHIFT) |
1455 ((4 * 4) << VB0_BUFFER_PITCH_SHIFT));
1456 OUT_RELOC(batch, render_state->vb.vertex_buffer, I915_GEM_DOMAIN_VERTEX, 0, 0);
1458 if (IS_IRONLAKE(i965->intel.device_id))
1459 OUT_RELOC(batch, render_state->vb.vertex_buffer, I915_GEM_DOMAIN_VERTEX, 0, 12 * 4);
1461 OUT_BATCH(batch, 3);
1463 OUT_BATCH(batch, 0);
1467 _3DPRIMITIVE_VERTEX_SEQUENTIAL |
1468 (_3DPRIM_RECTLIST << _3DPRIMITIVE_TOPOLOGY_SHIFT) |
1471 OUT_BATCH(batch, 3); /* vertex count per instance */
1472 OUT_BATCH(batch, 0); /* start vertex offset */
1473 OUT_BATCH(batch, 1); /* single instance */
1474 OUT_BATCH(batch, 0); /* start instance location */
1475 OUT_BATCH(batch, 0); /* index buffer offset, ignored */
1476 ADVANCE_BATCH(batch);
1480 i965_clear_dest_region(VADriverContextP ctx)
1482 struct i965_driver_data *i965 = i965_driver_data(ctx);
1483 struct intel_batchbuffer *batch = i965->batch;
1484 struct i965_render_state *render_state = &i965->render_state;
1485 struct intel_region *dest_region = render_state->draw_region;
1486 unsigned int blt_cmd, br13;
1489 blt_cmd = XY_COLOR_BLT_CMD;
1491 pitch = dest_region->pitch;
1493 if (dest_region->cpp == 4) {
1495 blt_cmd |= (XY_COLOR_BLT_WRITE_RGB | XY_COLOR_BLT_WRITE_ALPHA);
1497 assert(dest_region->cpp == 2);
1501 if (dest_region->tiling != I915_TILING_NONE) {
1502 blt_cmd |= XY_COLOR_BLT_DST_TILED;
1508 if (IS_GEN6(i965->intel.device_id) ||
1509 IS_GEN7(i965->intel.device_id)) {
1510 intel_batchbuffer_start_atomic_blt(batch, 24);
1511 BEGIN_BLT_BATCH(batch, 6);
1513 intel_batchbuffer_start_atomic(batch, 24);
1514 BEGIN_BATCH(batch, 6);
1517 OUT_BATCH(batch, blt_cmd);
1518 OUT_BATCH(batch, br13);
1519 OUT_BATCH(batch, (dest_region->y << 16) | (dest_region->x));
1520 OUT_BATCH(batch, ((dest_region->y + dest_region->height) << 16) |
1521 (dest_region->x + dest_region->width));
1522 OUT_RELOC(batch, dest_region->bo,
1523 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
1525 OUT_BATCH(batch, 0x0);
1526 ADVANCE_BATCH(batch);
1527 intel_batchbuffer_end_atomic(batch);
1531 i965_surface_render_pipeline_setup(VADriverContextP ctx)
1533 struct i965_driver_data *i965 = i965_driver_data(ctx);
1534 struct intel_batchbuffer *batch = i965->batch;
1536 i965_clear_dest_region(ctx);
1537 intel_batchbuffer_start_atomic(batch, 0x1000);
1538 intel_batchbuffer_emit_mi_flush(batch);
1539 i965_render_pipeline_select(ctx);
1540 i965_render_state_sip(ctx);
1541 i965_render_state_base_address(ctx);
1542 i965_render_binding_table_pointers(ctx);
1543 i965_render_constant_color(ctx);
1544 i965_render_pipelined_pointers(ctx);
1545 i965_render_urb_layout(ctx);
1546 i965_render_cs_urb_layout(ctx);
1547 i965_render_constant_buffer(ctx);
1548 i965_render_drawing_rectangle(ctx);
1549 i965_render_vertex_elements(ctx);
1550 i965_render_startup(ctx);
1551 intel_batchbuffer_end_atomic(batch);
1555 i965_subpic_render_pipeline_setup(VADriverContextP ctx)
1557 struct i965_driver_data *i965 = i965_driver_data(ctx);
1558 struct intel_batchbuffer *batch = i965->batch;
1560 intel_batchbuffer_start_atomic(batch, 0x1000);
1561 intel_batchbuffer_emit_mi_flush(batch);
1562 i965_render_pipeline_select(ctx);
1563 i965_render_state_sip(ctx);
1564 i965_render_state_base_address(ctx);
1565 i965_render_binding_table_pointers(ctx);
1566 i965_render_constant_color(ctx);
1567 i965_render_pipelined_pointers(ctx);
1568 i965_render_urb_layout(ctx);
1569 i965_render_cs_urb_layout(ctx);
1570 i965_render_drawing_rectangle(ctx);
1571 i965_render_vertex_elements(ctx);
1572 i965_render_startup(ctx);
1573 intel_batchbuffer_end_atomic(batch);
1578 i965_render_initialize(VADriverContextP ctx)
1580 struct i965_driver_data *i965 = i965_driver_data(ctx);
1581 struct i965_render_state *render_state = &i965->render_state;
1585 dri_bo_unreference(render_state->vb.vertex_buffer);
1586 bo = dri_bo_alloc(i965->intel.bufmgr,
1591 render_state->vb.vertex_buffer = bo;
1594 dri_bo_unreference(render_state->vs.state);
1595 bo = dri_bo_alloc(i965->intel.bufmgr,
1597 sizeof(struct i965_vs_unit_state),
1600 render_state->vs.state = bo;
1605 dri_bo_unreference(render_state->sf.state);
1606 bo = dri_bo_alloc(i965->intel.bufmgr,
1608 sizeof(struct i965_sf_unit_state),
1611 render_state->sf.state = bo;
1614 dri_bo_unreference(render_state->wm.surface_state_binding_table_bo);
1615 bo = dri_bo_alloc(i965->intel.bufmgr,
1616 "surface state & binding table",
1617 (SURFACE_STATE_PADDED_SIZE + sizeof(unsigned int)) * MAX_RENDER_SURFACES,
1620 render_state->wm.surface_state_binding_table_bo = bo;
1622 dri_bo_unreference(render_state->wm.sampler);
1623 bo = dri_bo_alloc(i965->intel.bufmgr,
1625 MAX_SAMPLERS * sizeof(struct i965_sampler_state),
1628 render_state->wm.sampler = bo;
1629 render_state->wm.sampler_count = 0;
1631 dri_bo_unreference(render_state->wm.state);
1632 bo = dri_bo_alloc(i965->intel.bufmgr,
1634 sizeof(struct i965_wm_unit_state),
1637 render_state->wm.state = bo;
1639 /* COLOR CALCULATOR */
1640 dri_bo_unreference(render_state->cc.state);
1641 bo = dri_bo_alloc(i965->intel.bufmgr,
1643 sizeof(struct i965_cc_unit_state),
1646 render_state->cc.state = bo;
1648 dri_bo_unreference(render_state->cc.viewport);
1649 bo = dri_bo_alloc(i965->intel.bufmgr,
1651 sizeof(struct i965_cc_viewport),
1654 render_state->cc.viewport = bo;
1658 i965_render_put_surface(
1659 VADriverContextP ctx,
1660 struct object_surface *obj_surface,
1661 const VARectangle *src_rect,
1662 const VARectangle *dst_rect,
1666 struct i965_driver_data *i965 = i965_driver_data(ctx);
1667 struct intel_batchbuffer *batch = i965->batch;
1669 i965_render_initialize(ctx);
1670 i965_surface_render_state_setup(ctx, obj_surface, src_rect, dst_rect, flags);
1671 i965_surface_render_pipeline_setup(ctx);
1672 intel_batchbuffer_flush(batch);
1676 i965_render_put_subpicture(
1677 VADriverContextP ctx,
1678 struct object_surface *obj_surface,
1679 const VARectangle *src_rect,
1680 const VARectangle *dst_rect
1683 struct i965_driver_data *i965 = i965_driver_data(ctx);
1684 struct intel_batchbuffer *batch = i965->batch;
1685 unsigned int index = obj_surface->subpic_render_idx;
1686 struct object_subpic *obj_subpic = obj_surface->obj_subpic[index];
1690 i965_render_initialize(ctx);
1691 i965_subpic_render_state_setup(ctx, obj_surface, src_rect, dst_rect);
1692 i965_subpic_render_pipeline_setup(ctx);
1693 i965_render_upload_image_palette(ctx, obj_subpic->obj_image, 0xff);
1694 intel_batchbuffer_flush(batch);
1701 gen6_render_initialize(VADriverContextP ctx)
1703 struct i965_driver_data *i965 = i965_driver_data(ctx);
1704 struct i965_render_state *render_state = &i965->render_state;
1708 dri_bo_unreference(render_state->vb.vertex_buffer);
1709 bo = dri_bo_alloc(i965->intel.bufmgr,
1714 render_state->vb.vertex_buffer = bo;
1717 dri_bo_unreference(render_state->wm.surface_state_binding_table_bo);
1718 bo = dri_bo_alloc(i965->intel.bufmgr,
1719 "surface state & binding table",
1720 (SURFACE_STATE_PADDED_SIZE + sizeof(unsigned int)) * MAX_RENDER_SURFACES,
1723 render_state->wm.surface_state_binding_table_bo = bo;
1725 dri_bo_unreference(render_state->wm.sampler);
1726 bo = dri_bo_alloc(i965->intel.bufmgr,
1728 MAX_SAMPLERS * sizeof(struct i965_sampler_state),
1731 render_state->wm.sampler = bo;
1732 render_state->wm.sampler_count = 0;
1734 /* COLOR CALCULATOR */
1735 dri_bo_unreference(render_state->cc.state);
1736 bo = dri_bo_alloc(i965->intel.bufmgr,
1738 sizeof(struct gen6_color_calc_state),
1741 render_state->cc.state = bo;
1744 dri_bo_unreference(render_state->cc.viewport);
1745 bo = dri_bo_alloc(i965->intel.bufmgr,
1747 sizeof(struct i965_cc_viewport),
1750 render_state->cc.viewport = bo;
1753 dri_bo_unreference(render_state->cc.blend);
1754 bo = dri_bo_alloc(i965->intel.bufmgr,
1756 sizeof(struct gen6_blend_state),
1759 render_state->cc.blend = bo;
1761 /* DEPTH & STENCIL STATE */
1762 dri_bo_unreference(render_state->cc.depth_stencil);
1763 bo = dri_bo_alloc(i965->intel.bufmgr,
1764 "depth & stencil state",
1765 sizeof(struct gen6_depth_stencil_state),
1768 render_state->cc.depth_stencil = bo;
1772 gen6_render_color_calc_state(VADriverContextP ctx)
1774 struct i965_driver_data *i965 = i965_driver_data(ctx);
1775 struct i965_render_state *render_state = &i965->render_state;
1776 struct gen6_color_calc_state *color_calc_state;
1778 dri_bo_map(render_state->cc.state, 1);
1779 assert(render_state->cc.state->virtual);
1780 color_calc_state = render_state->cc.state->virtual;
1781 memset(color_calc_state, 0, sizeof(*color_calc_state));
1782 color_calc_state->constant_r = 1.0;
1783 color_calc_state->constant_g = 0.0;
1784 color_calc_state->constant_b = 1.0;
1785 color_calc_state->constant_a = 1.0;
1786 dri_bo_unmap(render_state->cc.state);
1790 gen6_render_blend_state(VADriverContextP ctx)
1792 struct i965_driver_data *i965 = i965_driver_data(ctx);
1793 struct i965_render_state *render_state = &i965->render_state;
1794 struct gen6_blend_state *blend_state;
1796 dri_bo_map(render_state->cc.blend, 1);
1797 assert(render_state->cc.blend->virtual);
1798 blend_state = render_state->cc.blend->virtual;
1799 memset(blend_state, 0, sizeof(*blend_state));
1800 blend_state->blend1.logic_op_enable = 1;
1801 blend_state->blend1.logic_op_func = 0xc;
1802 dri_bo_unmap(render_state->cc.blend);
1806 gen6_render_depth_stencil_state(VADriverContextP ctx)
1808 struct i965_driver_data *i965 = i965_driver_data(ctx);
1809 struct i965_render_state *render_state = &i965->render_state;
1810 struct gen6_depth_stencil_state *depth_stencil_state;
1812 dri_bo_map(render_state->cc.depth_stencil, 1);
1813 assert(render_state->cc.depth_stencil->virtual);
1814 depth_stencil_state = render_state->cc.depth_stencil->virtual;
1815 memset(depth_stencil_state, 0, sizeof(*depth_stencil_state));
1816 dri_bo_unmap(render_state->cc.depth_stencil);
1820 gen6_render_setup_states(
1821 VADriverContextP ctx,
1822 struct object_surface *obj_surface,
1823 const VARectangle *src_rect,
1824 const VARectangle *dst_rect,
1828 i965_render_dest_surface_state(ctx, 0);
1829 i965_render_src_surfaces_state(ctx, obj_surface, flags);
1830 i965_render_sampler(ctx);
1831 i965_render_cc_viewport(ctx);
1832 gen6_render_color_calc_state(ctx);
1833 gen6_render_blend_state(ctx);
1834 gen6_render_depth_stencil_state(ctx);
1835 i965_render_upload_constants(ctx, obj_surface);
1836 i965_render_upload_vertex(ctx, obj_surface, src_rect, dst_rect);
1840 gen6_emit_invarient_states(VADriverContextP ctx)
1842 struct i965_driver_data *i965 = i965_driver_data(ctx);
1843 struct intel_batchbuffer *batch = i965->batch;
1845 OUT_BATCH(batch, CMD_PIPELINE_SELECT | PIPELINE_SELECT_3D);
1847 OUT_BATCH(batch, GEN6_3DSTATE_MULTISAMPLE | (3 - 2));
1848 OUT_BATCH(batch, GEN6_3DSTATE_MULTISAMPLE_PIXEL_LOCATION_CENTER |
1849 GEN6_3DSTATE_MULTISAMPLE_NUMSAMPLES_1); /* 1 sample/pixel */
1850 OUT_BATCH(batch, 0);
1852 OUT_BATCH(batch, GEN6_3DSTATE_SAMPLE_MASK | (2 - 2));
1853 OUT_BATCH(batch, 1);
1855 /* Set system instruction pointer */
1856 OUT_BATCH(batch, CMD_STATE_SIP | 0);
1857 OUT_BATCH(batch, 0);
1861 gen6_emit_state_base_address(VADriverContextP ctx)
1863 struct i965_driver_data *i965 = i965_driver_data(ctx);
1864 struct intel_batchbuffer *batch = i965->batch;
1865 struct i965_render_state *render_state = &i965->render_state;
1867 OUT_BATCH(batch, CMD_STATE_BASE_ADDRESS | (10 - 2));
1868 OUT_BATCH(batch, BASE_ADDRESS_MODIFY); /* General state base address */
1869 OUT_RELOC(batch, render_state->wm.surface_state_binding_table_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, BASE_ADDRESS_MODIFY); /* Surface state base address */
1870 OUT_BATCH(batch, BASE_ADDRESS_MODIFY); /* Dynamic state base address */
1871 OUT_BATCH(batch, BASE_ADDRESS_MODIFY); /* Indirect object base address */
1872 OUT_BATCH(batch, BASE_ADDRESS_MODIFY); /* Instruction base address */
1873 OUT_BATCH(batch, BASE_ADDRESS_MODIFY); /* General state upper bound */
1874 OUT_BATCH(batch, BASE_ADDRESS_MODIFY); /* Dynamic state upper bound */
1875 OUT_BATCH(batch, BASE_ADDRESS_MODIFY); /* Indirect object upper bound */
1876 OUT_BATCH(batch, BASE_ADDRESS_MODIFY); /* Instruction access upper bound */
1880 gen6_emit_viewport_state_pointers(VADriverContextP ctx)
1882 struct i965_driver_data *i965 = i965_driver_data(ctx);
1883 struct intel_batchbuffer *batch = i965->batch;
1884 struct i965_render_state *render_state = &i965->render_state;
1886 OUT_BATCH(batch, GEN6_3DSTATE_VIEWPORT_STATE_POINTERS |
1887 GEN6_3DSTATE_VIEWPORT_STATE_MODIFY_CC |
1889 OUT_BATCH(batch, 0);
1890 OUT_BATCH(batch, 0);
1891 OUT_RELOC(batch, render_state->cc.viewport, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
1895 gen6_emit_urb(VADriverContextP ctx)
1897 struct i965_driver_data *i965 = i965_driver_data(ctx);
1898 struct intel_batchbuffer *batch = i965->batch;
1900 OUT_BATCH(batch, GEN6_3DSTATE_URB | (3 - 2));
1901 OUT_BATCH(batch, ((1 - 1) << GEN6_3DSTATE_URB_VS_SIZE_SHIFT) |
1902 (24 << GEN6_3DSTATE_URB_VS_ENTRIES_SHIFT)); /* at least 24 on GEN6 */
1903 OUT_BATCH(batch, (0 << GEN6_3DSTATE_URB_GS_SIZE_SHIFT) |
1904 (0 << GEN6_3DSTATE_URB_GS_ENTRIES_SHIFT)); /* no GS thread */
1908 gen6_emit_cc_state_pointers(VADriverContextP ctx)
1910 struct i965_driver_data *i965 = i965_driver_data(ctx);
1911 struct intel_batchbuffer *batch = i965->batch;
1912 struct i965_render_state *render_state = &i965->render_state;
1914 OUT_BATCH(batch, GEN6_3DSTATE_CC_STATE_POINTERS | (4 - 2));
1915 OUT_RELOC(batch, render_state->cc.blend, I915_GEM_DOMAIN_INSTRUCTION, 0, 1);
1916 OUT_RELOC(batch, render_state->cc.depth_stencil, I915_GEM_DOMAIN_INSTRUCTION, 0, 1);
1917 OUT_RELOC(batch, render_state->cc.state, I915_GEM_DOMAIN_INSTRUCTION, 0, 1);
1921 gen6_emit_sampler_state_pointers(VADriverContextP ctx)
1923 struct i965_driver_data *i965 = i965_driver_data(ctx);
1924 struct intel_batchbuffer *batch = i965->batch;
1925 struct i965_render_state *render_state = &i965->render_state;
1927 OUT_BATCH(batch, GEN6_3DSTATE_SAMPLER_STATE_POINTERS |
1928 GEN6_3DSTATE_SAMPLER_STATE_MODIFY_PS |
1930 OUT_BATCH(batch, 0); /* VS */
1931 OUT_BATCH(batch, 0); /* GS */
1932 OUT_RELOC(batch,render_state->wm.sampler, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
1936 gen6_emit_binding_table(VADriverContextP ctx)
1938 struct i965_driver_data *i965 = i965_driver_data(ctx);
1939 struct intel_batchbuffer *batch = i965->batch;
1941 /* Binding table pointers */
1942 OUT_BATCH(batch, CMD_BINDING_TABLE_POINTERS |
1943 GEN6_BINDING_TABLE_MODIFY_PS |
1945 OUT_BATCH(batch, 0); /* vs */
1946 OUT_BATCH(batch, 0); /* gs */
1947 /* Only the PS uses the binding table */
1948 OUT_BATCH(batch, BINDING_TABLE_OFFSET);
1952 gen6_emit_depth_buffer_state(VADriverContextP ctx)
1954 struct i965_driver_data *i965 = i965_driver_data(ctx);
1955 struct intel_batchbuffer *batch = i965->batch;
1957 OUT_BATCH(batch, CMD_DEPTH_BUFFER | (7 - 2));
1958 OUT_BATCH(batch, (I965_SURFACE_NULL << CMD_DEPTH_BUFFER_TYPE_SHIFT) |
1959 (I965_DEPTHFORMAT_D32_FLOAT << CMD_DEPTH_BUFFER_FORMAT_SHIFT));
1960 OUT_BATCH(batch, 0);
1961 OUT_BATCH(batch, 0);
1962 OUT_BATCH(batch, 0);
1963 OUT_BATCH(batch, 0);
1964 OUT_BATCH(batch, 0);
1966 OUT_BATCH(batch, CMD_CLEAR_PARAMS | (2 - 2));
1967 OUT_BATCH(batch, 0);
1971 gen6_emit_drawing_rectangle(VADriverContextP ctx)
1973 i965_render_drawing_rectangle(ctx);
1977 gen6_emit_vs_state(VADriverContextP ctx)
1979 struct i965_driver_data *i965 = i965_driver_data(ctx);
1980 struct intel_batchbuffer *batch = i965->batch;
1982 /* disable VS constant buffer */
1983 OUT_BATCH(batch, GEN6_3DSTATE_CONSTANT_VS | (5 - 2));
1984 OUT_BATCH(batch, 0);
1985 OUT_BATCH(batch, 0);
1986 OUT_BATCH(batch, 0);
1987 OUT_BATCH(batch, 0);
1989 OUT_BATCH(batch, GEN6_3DSTATE_VS | (6 - 2));
1990 OUT_BATCH(batch, 0); /* without VS kernel */
1991 OUT_BATCH(batch, 0);
1992 OUT_BATCH(batch, 0);
1993 OUT_BATCH(batch, 0);
1994 OUT_BATCH(batch, 0); /* pass-through */
1998 gen6_emit_gs_state(VADriverContextP ctx)
2000 struct i965_driver_data *i965 = i965_driver_data(ctx);
2001 struct intel_batchbuffer *batch = i965->batch;
2003 /* disable GS constant buffer */
2004 OUT_BATCH(batch, GEN6_3DSTATE_CONSTANT_GS | (5 - 2));
2005 OUT_BATCH(batch, 0);
2006 OUT_BATCH(batch, 0);
2007 OUT_BATCH(batch, 0);
2008 OUT_BATCH(batch, 0);
2010 OUT_BATCH(batch, GEN6_3DSTATE_GS | (7 - 2));
2011 OUT_BATCH(batch, 0); /* without GS kernel */
2012 OUT_BATCH(batch, 0);
2013 OUT_BATCH(batch, 0);
2014 OUT_BATCH(batch, 0);
2015 OUT_BATCH(batch, 0);
2016 OUT_BATCH(batch, 0); /* pass-through */
2020 gen6_emit_clip_state(VADriverContextP ctx)
2022 struct i965_driver_data *i965 = i965_driver_data(ctx);
2023 struct intel_batchbuffer *batch = i965->batch;
2025 OUT_BATCH(batch, GEN6_3DSTATE_CLIP | (4 - 2));
2026 OUT_BATCH(batch, 0);
2027 OUT_BATCH(batch, 0); /* pass-through */
2028 OUT_BATCH(batch, 0);
2032 gen6_emit_sf_state(VADriverContextP ctx)
2034 struct i965_driver_data *i965 = i965_driver_data(ctx);
2035 struct intel_batchbuffer *batch = i965->batch;
2037 OUT_BATCH(batch, GEN6_3DSTATE_SF | (20 - 2));
2038 OUT_BATCH(batch, (1 << GEN6_3DSTATE_SF_NUM_OUTPUTS_SHIFT) |
2039 (1 << GEN6_3DSTATE_SF_URB_ENTRY_READ_LENGTH_SHIFT) |
2040 (0 << GEN6_3DSTATE_SF_URB_ENTRY_READ_OFFSET_SHIFT));
2041 OUT_BATCH(batch, 0);
2042 OUT_BATCH(batch, GEN6_3DSTATE_SF_CULL_NONE);
2043 OUT_BATCH(batch, 2 << GEN6_3DSTATE_SF_TRIFAN_PROVOKE_SHIFT); /* DW4 */
2044 OUT_BATCH(batch, 0);
2045 OUT_BATCH(batch, 0);
2046 OUT_BATCH(batch, 0);
2047 OUT_BATCH(batch, 0);
2048 OUT_BATCH(batch, 0); /* DW9 */
2049 OUT_BATCH(batch, 0);
2050 OUT_BATCH(batch, 0);
2051 OUT_BATCH(batch, 0);
2052 OUT_BATCH(batch, 0);
2053 OUT_BATCH(batch, 0); /* DW14 */
2054 OUT_BATCH(batch, 0);
2055 OUT_BATCH(batch, 0);
2056 OUT_BATCH(batch, 0);
2057 OUT_BATCH(batch, 0);
2058 OUT_BATCH(batch, 0); /* DW19 */
2062 gen6_emit_wm_state(VADriverContextP ctx, int kernel)
2064 struct i965_driver_data *i965 = i965_driver_data(ctx);
2065 struct intel_batchbuffer *batch = i965->batch;
2066 struct i965_render_state *render_state = &i965->render_state;
2068 OUT_BATCH(batch, GEN6_3DSTATE_CONSTANT_PS |
2069 GEN6_3DSTATE_CONSTANT_BUFFER_0_ENABLE |
2072 render_state->curbe.bo,
2073 I915_GEM_DOMAIN_INSTRUCTION, 0,
2074 (URB_CS_ENTRY_SIZE-1));
2075 OUT_BATCH(batch, 0);
2076 OUT_BATCH(batch, 0);
2077 OUT_BATCH(batch, 0);
2079 OUT_BATCH(batch, GEN6_3DSTATE_WM | (9 - 2));
2080 OUT_RELOC(batch, render_state->render_kernels[kernel].bo,
2081 I915_GEM_DOMAIN_INSTRUCTION, 0,
2083 OUT_BATCH(batch, (1 << GEN6_3DSTATE_WM_SAMPLER_COUNT_SHITF) |
2084 (5 << GEN6_3DSTATE_WM_BINDING_TABLE_ENTRY_COUNT_SHIFT));
2085 OUT_BATCH(batch, 0);
2086 OUT_BATCH(batch, (6 << GEN6_3DSTATE_WM_DISPATCH_START_GRF_0_SHIFT)); /* DW4 */
2087 OUT_BATCH(batch, ((render_state->max_wm_threads - 1) << GEN6_3DSTATE_WM_MAX_THREADS_SHIFT) |
2088 GEN6_3DSTATE_WM_DISPATCH_ENABLE |
2089 GEN6_3DSTATE_WM_16_DISPATCH_ENABLE);
2090 OUT_BATCH(batch, (1 << GEN6_3DSTATE_WM_NUM_SF_OUTPUTS_SHIFT) |
2091 GEN6_3DSTATE_WM_PERSPECTIVE_PIXEL_BARYCENTRIC);
2092 OUT_BATCH(batch, 0);
2093 OUT_BATCH(batch, 0);
2097 gen6_emit_vertex_element_state(VADriverContextP ctx)
2099 struct i965_driver_data *i965 = i965_driver_data(ctx);
2100 struct intel_batchbuffer *batch = i965->batch;
2102 /* Set up our vertex elements, sourced from the single vertex buffer. */
2103 OUT_BATCH(batch, CMD_VERTEX_ELEMENTS | (5 - 2));
2104 /* offset 0: X,Y -> {X, Y, 1.0, 1.0} */
2105 OUT_BATCH(batch, (0 << GEN6_VE0_VERTEX_BUFFER_INDEX_SHIFT) |
2107 (I965_SURFACEFORMAT_R32G32_FLOAT << VE0_FORMAT_SHIFT) |
2108 (0 << VE0_OFFSET_SHIFT));
2109 OUT_BATCH(batch, (I965_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT) |
2110 (I965_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT) |
2111 (I965_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_2_SHIFT) |
2112 (I965_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT));
2113 /* offset 8: S0, T0 -> {S0, T0, 1.0, 1.0} */
2114 OUT_BATCH(batch, (0 << GEN6_VE0_VERTEX_BUFFER_INDEX_SHIFT) |
2116 (I965_SURFACEFORMAT_R32G32_FLOAT << VE0_FORMAT_SHIFT) |
2117 (8 << VE0_OFFSET_SHIFT));
2118 OUT_BATCH(batch, (I965_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT) |
2119 (I965_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT) |
2120 (I965_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_2_SHIFT) |
2121 (I965_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT));
2125 gen6_emit_vertices(VADriverContextP ctx)
2127 struct i965_driver_data *i965 = i965_driver_data(ctx);
2128 struct intel_batchbuffer *batch = i965->batch;
2129 struct i965_render_state *render_state = &i965->render_state;
2131 BEGIN_BATCH(batch, 11);
2132 OUT_BATCH(batch, CMD_VERTEX_BUFFERS | 3);
2134 (0 << GEN6_VB0_BUFFER_INDEX_SHIFT) |
2135 GEN6_VB0_VERTEXDATA |
2136 ((4 * 4) << VB0_BUFFER_PITCH_SHIFT));
2137 OUT_RELOC(batch, render_state->vb.vertex_buffer, I915_GEM_DOMAIN_VERTEX, 0, 0);
2138 OUT_RELOC(batch, render_state->vb.vertex_buffer, I915_GEM_DOMAIN_VERTEX, 0, 12 * 4);
2139 OUT_BATCH(batch, 0);
2143 _3DPRIMITIVE_VERTEX_SEQUENTIAL |
2144 (_3DPRIM_RECTLIST << _3DPRIMITIVE_TOPOLOGY_SHIFT) |
2147 OUT_BATCH(batch, 3); /* vertex count per instance */
2148 OUT_BATCH(batch, 0); /* start vertex offset */
2149 OUT_BATCH(batch, 1); /* single instance */
2150 OUT_BATCH(batch, 0); /* start instance location */
2151 OUT_BATCH(batch, 0); /* index buffer offset, ignored */
2152 ADVANCE_BATCH(batch);
2156 gen6_render_emit_states(VADriverContextP ctx, int kernel)
2158 struct i965_driver_data *i965 = i965_driver_data(ctx);
2159 struct intel_batchbuffer *batch = i965->batch;
2161 intel_batchbuffer_start_atomic(batch, 0x1000);
2162 intel_batchbuffer_emit_mi_flush(batch);
2163 gen6_emit_invarient_states(ctx);
2164 gen6_emit_state_base_address(ctx);
2165 gen6_emit_viewport_state_pointers(ctx);
2167 gen6_emit_cc_state_pointers(ctx);
2168 gen6_emit_sampler_state_pointers(ctx);
2169 gen6_emit_vs_state(ctx);
2170 gen6_emit_gs_state(ctx);
2171 gen6_emit_clip_state(ctx);
2172 gen6_emit_sf_state(ctx);
2173 gen6_emit_wm_state(ctx, kernel);
2174 gen6_emit_binding_table(ctx);
2175 gen6_emit_depth_buffer_state(ctx);
2176 gen6_emit_drawing_rectangle(ctx);
2177 gen6_emit_vertex_element_state(ctx);
2178 gen6_emit_vertices(ctx);
2179 intel_batchbuffer_end_atomic(batch);
2183 gen6_render_put_surface(
2184 VADriverContextP ctx,
2185 struct object_surface *obj_surface,
2186 const VARectangle *src_rect,
2187 const VARectangle *dst_rect,
2191 struct i965_driver_data *i965 = i965_driver_data(ctx);
2192 struct intel_batchbuffer *batch = i965->batch;
2194 gen6_render_initialize(ctx);
2195 gen6_render_setup_states(ctx, obj_surface, src_rect, dst_rect, flags);
2196 i965_clear_dest_region(ctx);
2197 gen6_render_emit_states(ctx, PS_KERNEL);
2198 intel_batchbuffer_flush(batch);
2202 gen6_subpicture_render_blend_state(VADriverContextP ctx)
2204 struct i965_driver_data *i965 = i965_driver_data(ctx);
2205 struct i965_render_state *render_state = &i965->render_state;
2206 struct gen6_blend_state *blend_state;
2208 dri_bo_unmap(render_state->cc.state);
2209 dri_bo_map(render_state->cc.blend, 1);
2210 assert(render_state->cc.blend->virtual);
2211 blend_state = render_state->cc.blend->virtual;
2212 memset(blend_state, 0, sizeof(*blend_state));
2213 blend_state->blend0.dest_blend_factor = I965_BLENDFACTOR_INV_SRC_ALPHA;
2214 blend_state->blend0.source_blend_factor = I965_BLENDFACTOR_SRC_ALPHA;
2215 blend_state->blend0.blend_func = I965_BLENDFUNCTION_ADD;
2216 blend_state->blend0.blend_enable = 1;
2217 blend_state->blend1.post_blend_clamp_enable = 1;
2218 blend_state->blend1.pre_blend_clamp_enable = 1;
2219 blend_state->blend1.clamp_range = 0; /* clamp range [0, 1] */
2220 dri_bo_unmap(render_state->cc.blend);
2224 gen6_subpicture_render_setup_states(
2225 VADriverContextP ctx,
2226 struct object_surface *obj_surface,
2227 const VARectangle *src_rect,
2228 const VARectangle *dst_rect
2231 i965_render_dest_surface_state(ctx, 0);
2232 i965_subpic_render_src_surfaces_state(ctx, obj_surface);
2233 i965_render_sampler(ctx);
2234 i965_render_cc_viewport(ctx);
2235 gen6_render_color_calc_state(ctx);
2236 gen6_subpicture_render_blend_state(ctx);
2237 gen6_render_depth_stencil_state(ctx);
2238 i965_subpic_render_upload_constants(ctx, obj_surface);
2239 i965_subpic_render_upload_vertex(ctx, obj_surface, dst_rect);
2243 gen6_render_put_subpicture(
2244 VADriverContextP ctx,
2245 struct object_surface *obj_surface,
2246 const VARectangle *src_rect,
2247 const VARectangle *dst_rect
2250 struct i965_driver_data *i965 = i965_driver_data(ctx);
2251 struct intel_batchbuffer *batch = i965->batch;
2252 unsigned int index = obj_surface->subpic_render_idx;
2253 struct object_subpic *obj_subpic = obj_surface->obj_subpic[index];
2256 gen6_render_initialize(ctx);
2257 gen6_subpicture_render_setup_states(ctx, obj_surface, src_rect, dst_rect);
2258 gen6_render_emit_states(ctx, PS_SUBPIC_KERNEL);
2259 i965_render_upload_image_palette(ctx, obj_subpic->obj_image, 0xff);
2260 intel_batchbuffer_flush(batch);
2267 gen7_render_initialize(VADriverContextP ctx)
2269 struct i965_driver_data *i965 = i965_driver_data(ctx);
2270 struct i965_render_state *render_state = &i965->render_state;
2274 dri_bo_unreference(render_state->vb.vertex_buffer);
2275 bo = dri_bo_alloc(i965->intel.bufmgr,
2280 render_state->vb.vertex_buffer = bo;
2283 dri_bo_unreference(render_state->wm.surface_state_binding_table_bo);
2284 bo = dri_bo_alloc(i965->intel.bufmgr,
2285 "surface state & binding table",
2286 (SURFACE_STATE_PADDED_SIZE + sizeof(unsigned int)) * MAX_RENDER_SURFACES,
2289 render_state->wm.surface_state_binding_table_bo = bo;
2291 dri_bo_unreference(render_state->wm.sampler);
2292 bo = dri_bo_alloc(i965->intel.bufmgr,
2294 MAX_SAMPLERS * sizeof(struct gen7_sampler_state),
2297 render_state->wm.sampler = bo;
2298 render_state->wm.sampler_count = 0;
2300 /* COLOR CALCULATOR */
2301 dri_bo_unreference(render_state->cc.state);
2302 bo = dri_bo_alloc(i965->intel.bufmgr,
2304 sizeof(struct gen6_color_calc_state),
2307 render_state->cc.state = bo;
2310 dri_bo_unreference(render_state->cc.viewport);
2311 bo = dri_bo_alloc(i965->intel.bufmgr,
2313 sizeof(struct i965_cc_viewport),
2316 render_state->cc.viewport = bo;
2319 dri_bo_unreference(render_state->cc.blend);
2320 bo = dri_bo_alloc(i965->intel.bufmgr,
2322 sizeof(struct gen6_blend_state),
2325 render_state->cc.blend = bo;
2327 /* DEPTH & STENCIL STATE */
2328 dri_bo_unreference(render_state->cc.depth_stencil);
2329 bo = dri_bo_alloc(i965->intel.bufmgr,
2330 "depth & stencil state",
2331 sizeof(struct gen6_depth_stencil_state),
2334 render_state->cc.depth_stencil = bo;
2338 gen7_render_color_calc_state(VADriverContextP ctx)
2340 struct i965_driver_data *i965 = i965_driver_data(ctx);
2341 struct i965_render_state *render_state = &i965->render_state;
2342 struct gen6_color_calc_state *color_calc_state;
2344 dri_bo_map(render_state->cc.state, 1);
2345 assert(render_state->cc.state->virtual);
2346 color_calc_state = render_state->cc.state->virtual;
2347 memset(color_calc_state, 0, sizeof(*color_calc_state));
2348 color_calc_state->constant_r = 1.0;
2349 color_calc_state->constant_g = 0.0;
2350 color_calc_state->constant_b = 1.0;
2351 color_calc_state->constant_a = 1.0;
2352 dri_bo_unmap(render_state->cc.state);
2356 gen7_render_blend_state(VADriverContextP ctx)
2358 struct i965_driver_data *i965 = i965_driver_data(ctx);
2359 struct i965_render_state *render_state = &i965->render_state;
2360 struct gen6_blend_state *blend_state;
2362 dri_bo_map(render_state->cc.blend, 1);
2363 assert(render_state->cc.blend->virtual);
2364 blend_state = render_state->cc.blend->virtual;
2365 memset(blend_state, 0, sizeof(*blend_state));
2366 blend_state->blend1.logic_op_enable = 1;
2367 blend_state->blend1.logic_op_func = 0xc;
2368 blend_state->blend1.pre_blend_clamp_enable = 1;
2369 dri_bo_unmap(render_state->cc.blend);
2373 gen7_render_depth_stencil_state(VADriverContextP ctx)
2375 struct i965_driver_data *i965 = i965_driver_data(ctx);
2376 struct i965_render_state *render_state = &i965->render_state;
2377 struct gen6_depth_stencil_state *depth_stencil_state;
2379 dri_bo_map(render_state->cc.depth_stencil, 1);
2380 assert(render_state->cc.depth_stencil->virtual);
2381 depth_stencil_state = render_state->cc.depth_stencil->virtual;
2382 memset(depth_stencil_state, 0, sizeof(*depth_stencil_state));
2383 dri_bo_unmap(render_state->cc.depth_stencil);
2387 gen7_render_sampler(VADriverContextP ctx)
2389 struct i965_driver_data *i965 = i965_driver_data(ctx);
2390 struct i965_render_state *render_state = &i965->render_state;
2391 struct gen7_sampler_state *sampler_state;
2394 assert(render_state->wm.sampler_count > 0);
2395 assert(render_state->wm.sampler_count <= MAX_SAMPLERS);
2397 dri_bo_map(render_state->wm.sampler, 1);
2398 assert(render_state->wm.sampler->virtual);
2399 sampler_state = render_state->wm.sampler->virtual;
2400 for (i = 0; i < render_state->wm.sampler_count; i++) {
2401 memset(sampler_state, 0, sizeof(*sampler_state));
2402 sampler_state->ss0.min_filter = I965_MAPFILTER_LINEAR;
2403 sampler_state->ss0.mag_filter = I965_MAPFILTER_LINEAR;
2404 sampler_state->ss3.r_wrap_mode = I965_TEXCOORDMODE_CLAMP;
2405 sampler_state->ss3.s_wrap_mode = I965_TEXCOORDMODE_CLAMP;
2406 sampler_state->ss3.t_wrap_mode = I965_TEXCOORDMODE_CLAMP;
2410 dri_bo_unmap(render_state->wm.sampler);
2414 gen7_render_setup_states(
2415 VADriverContextP ctx,
2416 struct object_surface *obj_surface,
2417 const VARectangle *src_rect,
2418 const VARectangle *dst_rect,
2422 i965_render_dest_surface_state(ctx, 0);
2423 i965_render_src_surfaces_state(ctx, obj_surface, flags);
2424 gen7_render_sampler(ctx);
2425 i965_render_cc_viewport(ctx);
2426 gen7_render_color_calc_state(ctx);
2427 gen7_render_blend_state(ctx);
2428 gen7_render_depth_stencil_state(ctx);
2429 i965_render_upload_constants(ctx, obj_surface);
2430 i965_render_upload_vertex(ctx, obj_surface, src_rect, dst_rect);
2434 gen7_emit_invarient_states(VADriverContextP ctx)
2436 struct i965_driver_data *i965 = i965_driver_data(ctx);
2437 struct intel_batchbuffer *batch = i965->batch;
2439 BEGIN_BATCH(batch, 1);
2440 OUT_BATCH(batch, CMD_PIPELINE_SELECT | PIPELINE_SELECT_3D);
2441 ADVANCE_BATCH(batch);
2443 BEGIN_BATCH(batch, 4);
2444 OUT_BATCH(batch, GEN6_3DSTATE_MULTISAMPLE | (4 - 2));
2445 OUT_BATCH(batch, GEN6_3DSTATE_MULTISAMPLE_PIXEL_LOCATION_CENTER |
2446 GEN6_3DSTATE_MULTISAMPLE_NUMSAMPLES_1); /* 1 sample/pixel */
2447 OUT_BATCH(batch, 0);
2448 OUT_BATCH(batch, 0);
2449 ADVANCE_BATCH(batch);
2451 BEGIN_BATCH(batch, 2);
2452 OUT_BATCH(batch, GEN6_3DSTATE_SAMPLE_MASK | (2 - 2));
2453 OUT_BATCH(batch, 1);
2454 ADVANCE_BATCH(batch);
2456 /* Set system instruction pointer */
2457 BEGIN_BATCH(batch, 2);
2458 OUT_BATCH(batch, CMD_STATE_SIP | 0);
2459 OUT_BATCH(batch, 0);
2460 ADVANCE_BATCH(batch);
2464 gen7_emit_state_base_address(VADriverContextP ctx)
2466 struct i965_driver_data *i965 = i965_driver_data(ctx);
2467 struct intel_batchbuffer *batch = i965->batch;
2468 struct i965_render_state *render_state = &i965->render_state;
2470 OUT_BATCH(batch, CMD_STATE_BASE_ADDRESS | (10 - 2));
2471 OUT_BATCH(batch, BASE_ADDRESS_MODIFY); /* General state base address */
2472 OUT_RELOC(batch, render_state->wm.surface_state_binding_table_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, BASE_ADDRESS_MODIFY); /* Surface state base address */
2473 OUT_BATCH(batch, BASE_ADDRESS_MODIFY); /* Dynamic state base address */
2474 OUT_BATCH(batch, BASE_ADDRESS_MODIFY); /* Indirect object base address */
2475 OUT_BATCH(batch, BASE_ADDRESS_MODIFY); /* Instruction base address */
2476 OUT_BATCH(batch, BASE_ADDRESS_MODIFY); /* General state upper bound */
2477 OUT_BATCH(batch, BASE_ADDRESS_MODIFY); /* Dynamic state upper bound */
2478 OUT_BATCH(batch, BASE_ADDRESS_MODIFY); /* Indirect object upper bound */
2479 OUT_BATCH(batch, BASE_ADDRESS_MODIFY); /* Instruction access upper bound */
2483 gen7_emit_viewport_state_pointers(VADriverContextP ctx)
2485 struct i965_driver_data *i965 = i965_driver_data(ctx);
2486 struct intel_batchbuffer *batch = i965->batch;
2487 struct i965_render_state *render_state = &i965->render_state;
2489 BEGIN_BATCH(batch, 2);
2490 OUT_BATCH(batch, GEN7_3DSTATE_VIEWPORT_STATE_POINTERS_CC | (2 - 2));
2492 render_state->cc.viewport,
2493 I915_GEM_DOMAIN_INSTRUCTION, 0,
2495 ADVANCE_BATCH(batch);
2497 BEGIN_BATCH(batch, 2);
2498 OUT_BATCH(batch, GEN7_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CL | (2 - 2));
2499 OUT_BATCH(batch, 0);
2500 ADVANCE_BATCH(batch);
2504 * URB layout on GEN7
2505 * ----------------------------------------
2506 * | PS Push Constants (8KB) | VS entries |
2507 * ----------------------------------------
2510 gen7_emit_urb(VADriverContextP ctx)
2512 struct i965_driver_data *i965 = i965_driver_data(ctx);
2513 struct intel_batchbuffer *batch = i965->batch;
2514 unsigned int num_urb_entries = 32;
2516 if (IS_HASWELL(i965->intel.device_id))
2517 num_urb_entries = 64;
2519 BEGIN_BATCH(batch, 2);
2520 OUT_BATCH(batch, GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_PS | (2 - 2));
2521 OUT_BATCH(batch, 8); /* in 1KBs */
2522 ADVANCE_BATCH(batch);
2524 BEGIN_BATCH(batch, 2);
2525 OUT_BATCH(batch, GEN7_3DSTATE_URB_VS | (2 - 2));
2527 (num_urb_entries << GEN7_URB_ENTRY_NUMBER_SHIFT) |
2528 (2 - 1) << GEN7_URB_ENTRY_SIZE_SHIFT |
2529 (1 << GEN7_URB_STARTING_ADDRESS_SHIFT));
2530 ADVANCE_BATCH(batch);
2532 BEGIN_BATCH(batch, 2);
2533 OUT_BATCH(batch, GEN7_3DSTATE_URB_GS | (2 - 2));
2535 (0 << GEN7_URB_ENTRY_SIZE_SHIFT) |
2536 (1 << GEN7_URB_STARTING_ADDRESS_SHIFT));
2537 ADVANCE_BATCH(batch);
2539 BEGIN_BATCH(batch, 2);
2540 OUT_BATCH(batch, GEN7_3DSTATE_URB_HS | (2 - 2));
2542 (0 << GEN7_URB_ENTRY_SIZE_SHIFT) |
2543 (2 << GEN7_URB_STARTING_ADDRESS_SHIFT));
2544 ADVANCE_BATCH(batch);
2546 BEGIN_BATCH(batch, 2);
2547 OUT_BATCH(batch, GEN7_3DSTATE_URB_DS | (2 - 2));
2549 (0 << GEN7_URB_ENTRY_SIZE_SHIFT) |
2550 (2 << GEN7_URB_STARTING_ADDRESS_SHIFT));
2551 ADVANCE_BATCH(batch);
2555 gen7_emit_cc_state_pointers(VADriverContextP ctx)
2557 struct i965_driver_data *i965 = i965_driver_data(ctx);
2558 struct intel_batchbuffer *batch = i965->batch;
2559 struct i965_render_state *render_state = &i965->render_state;
2561 BEGIN_BATCH(batch, 2);
2562 OUT_BATCH(batch, GEN6_3DSTATE_CC_STATE_POINTERS | (2 - 2));
2564 render_state->cc.state,
2565 I915_GEM_DOMAIN_INSTRUCTION, 0,
2567 ADVANCE_BATCH(batch);
2569 BEGIN_BATCH(batch, 2);
2570 OUT_BATCH(batch, GEN7_3DSTATE_BLEND_STATE_POINTERS | (2 - 2));
2572 render_state->cc.blend,
2573 I915_GEM_DOMAIN_INSTRUCTION, 0,
2575 ADVANCE_BATCH(batch);
2577 BEGIN_BATCH(batch, 2);
2578 OUT_BATCH(batch, GEN7_3DSTATE_DEPTH_STENCIL_STATE_POINTERS | (2 - 2));
2580 render_state->cc.depth_stencil,
2581 I915_GEM_DOMAIN_INSTRUCTION, 0,
2583 ADVANCE_BATCH(batch);
2587 gen7_emit_sampler_state_pointers(VADriverContextP ctx)
2589 struct i965_driver_data *i965 = i965_driver_data(ctx);
2590 struct intel_batchbuffer *batch = i965->batch;
2591 struct i965_render_state *render_state = &i965->render_state;
2593 BEGIN_BATCH(batch, 2);
2594 OUT_BATCH(batch, GEN7_3DSTATE_SAMPLER_STATE_POINTERS_PS | (2 - 2));
2596 render_state->wm.sampler,
2597 I915_GEM_DOMAIN_INSTRUCTION, 0,
2599 ADVANCE_BATCH(batch);
2603 gen7_emit_binding_table(VADriverContextP ctx)
2605 struct i965_driver_data *i965 = i965_driver_data(ctx);
2606 struct intel_batchbuffer *batch = i965->batch;
2608 BEGIN_BATCH(batch, 2);
2609 OUT_BATCH(batch, GEN7_3DSTATE_BINDING_TABLE_POINTERS_PS | (2 - 2));
2610 OUT_BATCH(batch, BINDING_TABLE_OFFSET);
2611 ADVANCE_BATCH(batch);
2615 gen7_emit_depth_buffer_state(VADriverContextP ctx)
2617 struct i965_driver_data *i965 = i965_driver_data(ctx);
2618 struct intel_batchbuffer *batch = i965->batch;
2620 BEGIN_BATCH(batch, 7);
2621 OUT_BATCH(batch, GEN7_3DSTATE_DEPTH_BUFFER | (7 - 2));
2623 (I965_DEPTHFORMAT_D32_FLOAT << 18) |
2624 (I965_SURFACE_NULL << 29));
2625 OUT_BATCH(batch, 0);
2626 OUT_BATCH(batch, 0);
2627 OUT_BATCH(batch, 0);
2628 OUT_BATCH(batch, 0);
2629 OUT_BATCH(batch, 0);
2630 ADVANCE_BATCH(batch);
2632 BEGIN_BATCH(batch, 3);
2633 OUT_BATCH(batch, GEN7_3DSTATE_CLEAR_PARAMS | (3 - 2));
2634 OUT_BATCH(batch, 0);
2635 OUT_BATCH(batch, 0);
2636 ADVANCE_BATCH(batch);
2640 gen7_emit_drawing_rectangle(VADriverContextP ctx)
2642 i965_render_drawing_rectangle(ctx);
2646 gen7_emit_vs_state(VADriverContextP ctx)
2648 struct i965_driver_data *i965 = i965_driver_data(ctx);
2649 struct intel_batchbuffer *batch = i965->batch;
2651 /* disable VS constant buffer */
2652 OUT_BATCH(batch, GEN6_3DSTATE_CONSTANT_VS | (7 - 2));
2653 OUT_BATCH(batch, 0);
2654 OUT_BATCH(batch, 0);
2655 OUT_BATCH(batch, 0);
2656 OUT_BATCH(batch, 0);
2657 OUT_BATCH(batch, 0);
2658 OUT_BATCH(batch, 0);
2660 OUT_BATCH(batch, GEN6_3DSTATE_VS | (6 - 2));
2661 OUT_BATCH(batch, 0); /* without VS kernel */
2662 OUT_BATCH(batch, 0);
2663 OUT_BATCH(batch, 0);
2664 OUT_BATCH(batch, 0);
2665 OUT_BATCH(batch, 0); /* pass-through */
2669 gen7_emit_bypass_state(VADriverContextP ctx)
2671 struct i965_driver_data *i965 = i965_driver_data(ctx);
2672 struct intel_batchbuffer *batch = i965->batch;
2675 BEGIN_BATCH(batch, 7);
2676 OUT_BATCH(batch, GEN6_3DSTATE_CONSTANT_GS | (7 - 2));
2677 OUT_BATCH(batch, 0);
2678 OUT_BATCH(batch, 0);
2679 OUT_BATCH(batch, 0);
2680 OUT_BATCH(batch, 0);
2681 OUT_BATCH(batch, 0);
2682 OUT_BATCH(batch, 0);
2683 ADVANCE_BATCH(batch);
2685 BEGIN_BATCH(batch, 7);
2686 OUT_BATCH(batch, GEN6_3DSTATE_GS | (7 - 2));
2687 OUT_BATCH(batch, 0); /* without GS kernel */
2688 OUT_BATCH(batch, 0);
2689 OUT_BATCH(batch, 0);
2690 OUT_BATCH(batch, 0);
2691 OUT_BATCH(batch, 0);
2692 OUT_BATCH(batch, 0); /* pass-through */
2693 ADVANCE_BATCH(batch);
2695 BEGIN_BATCH(batch, 2);
2696 OUT_BATCH(batch, GEN7_3DSTATE_BINDING_TABLE_POINTERS_GS | (2 - 2));
2697 OUT_BATCH(batch, 0);
2698 ADVANCE_BATCH(batch);
2701 BEGIN_BATCH(batch, 7);
2702 OUT_BATCH(batch, GEN7_3DSTATE_CONSTANT_HS | (7 - 2));
2703 OUT_BATCH(batch, 0);
2704 OUT_BATCH(batch, 0);
2705 OUT_BATCH(batch, 0);
2706 OUT_BATCH(batch, 0);
2707 OUT_BATCH(batch, 0);
2708 OUT_BATCH(batch, 0);
2709 ADVANCE_BATCH(batch);
2711 BEGIN_BATCH(batch, 7);
2712 OUT_BATCH(batch, GEN7_3DSTATE_HS | (7 - 2));
2713 OUT_BATCH(batch, 0);
2714 OUT_BATCH(batch, 0);
2715 OUT_BATCH(batch, 0);
2716 OUT_BATCH(batch, 0);
2717 OUT_BATCH(batch, 0);
2718 OUT_BATCH(batch, 0);
2719 ADVANCE_BATCH(batch);
2721 BEGIN_BATCH(batch, 2);
2722 OUT_BATCH(batch, GEN7_3DSTATE_BINDING_TABLE_POINTERS_HS | (2 - 2));
2723 OUT_BATCH(batch, 0);
2724 ADVANCE_BATCH(batch);
2727 BEGIN_BATCH(batch, 4);
2728 OUT_BATCH(batch, GEN7_3DSTATE_TE | (4 - 2));
2729 OUT_BATCH(batch, 0);
2730 OUT_BATCH(batch, 0);
2731 OUT_BATCH(batch, 0);
2732 ADVANCE_BATCH(batch);
2735 BEGIN_BATCH(batch, 7);
2736 OUT_BATCH(batch, GEN7_3DSTATE_CONSTANT_DS | (7 - 2));
2737 OUT_BATCH(batch, 0);
2738 OUT_BATCH(batch, 0);
2739 OUT_BATCH(batch, 0);
2740 OUT_BATCH(batch, 0);
2741 OUT_BATCH(batch, 0);
2742 OUT_BATCH(batch, 0);
2743 ADVANCE_BATCH(batch);
2745 BEGIN_BATCH(batch, 6);
2746 OUT_BATCH(batch, GEN7_3DSTATE_DS | (6 - 2));
2747 OUT_BATCH(batch, 0);
2748 OUT_BATCH(batch, 0);
2749 OUT_BATCH(batch, 0);
2750 OUT_BATCH(batch, 0);
2751 OUT_BATCH(batch, 0);
2752 ADVANCE_BATCH(batch);
2754 BEGIN_BATCH(batch, 2);
2755 OUT_BATCH(batch, GEN7_3DSTATE_BINDING_TABLE_POINTERS_DS | (2 - 2));
2756 OUT_BATCH(batch, 0);
2757 ADVANCE_BATCH(batch);
2759 /* Disable STREAMOUT */
2760 BEGIN_BATCH(batch, 3);
2761 OUT_BATCH(batch, GEN7_3DSTATE_STREAMOUT | (3 - 2));
2762 OUT_BATCH(batch, 0);
2763 OUT_BATCH(batch, 0);
2764 ADVANCE_BATCH(batch);
2768 gen7_emit_clip_state(VADriverContextP ctx)
2770 struct i965_driver_data *i965 = i965_driver_data(ctx);
2771 struct intel_batchbuffer *batch = i965->batch;
2773 OUT_BATCH(batch, GEN6_3DSTATE_CLIP | (4 - 2));
2774 OUT_BATCH(batch, 0);
2775 OUT_BATCH(batch, 0); /* pass-through */
2776 OUT_BATCH(batch, 0);
2780 gen7_emit_sf_state(VADriverContextP ctx)
2782 struct i965_driver_data *i965 = i965_driver_data(ctx);
2783 struct intel_batchbuffer *batch = i965->batch;
2785 BEGIN_BATCH(batch, 14);
2786 OUT_BATCH(batch, GEN7_3DSTATE_SBE | (14 - 2));
2788 (1 << GEN7_SBE_NUM_OUTPUTS_SHIFT) |
2789 (1 << GEN7_SBE_URB_ENTRY_READ_LENGTH_SHIFT) |
2790 (0 << GEN7_SBE_URB_ENTRY_READ_OFFSET_SHIFT));
2791 OUT_BATCH(batch, 0);
2792 OUT_BATCH(batch, 0);
2793 OUT_BATCH(batch, 0); /* DW4 */
2794 OUT_BATCH(batch, 0);
2795 OUT_BATCH(batch, 0);
2796 OUT_BATCH(batch, 0);
2797 OUT_BATCH(batch, 0);
2798 OUT_BATCH(batch, 0); /* DW9 */
2799 OUT_BATCH(batch, 0);
2800 OUT_BATCH(batch, 0);
2801 OUT_BATCH(batch, 0);
2802 OUT_BATCH(batch, 0);
2803 ADVANCE_BATCH(batch);
2805 BEGIN_BATCH(batch, 7);
2806 OUT_BATCH(batch, GEN6_3DSTATE_SF | (7 - 2));
2807 OUT_BATCH(batch, 0);
2808 OUT_BATCH(batch, GEN6_3DSTATE_SF_CULL_NONE);
2809 OUT_BATCH(batch, 2 << GEN6_3DSTATE_SF_TRIFAN_PROVOKE_SHIFT);
2810 OUT_BATCH(batch, 0);
2811 OUT_BATCH(batch, 0);
2812 OUT_BATCH(batch, 0);
2813 ADVANCE_BATCH(batch);
2817 gen7_emit_wm_state(VADriverContextP ctx, int kernel)
2819 struct i965_driver_data *i965 = i965_driver_data(ctx);
2820 struct intel_batchbuffer *batch = i965->batch;
2821 struct i965_render_state *render_state = &i965->render_state;
2822 unsigned int max_threads_shift = GEN7_PS_MAX_THREADS_SHIFT_IVB;
2823 unsigned int num_samples = 0;
2825 if (IS_HASWELL(i965->intel.device_id)) {
2826 max_threads_shift = GEN7_PS_MAX_THREADS_SHIFT_HSW;
2827 num_samples = 1 << GEN7_PS_SAMPLE_MASK_SHIFT_HSW;
2830 BEGIN_BATCH(batch, 3);
2831 OUT_BATCH(batch, GEN6_3DSTATE_WM | (3 - 2));
2833 GEN7_WM_DISPATCH_ENABLE |
2834 GEN7_WM_PERSPECTIVE_PIXEL_BARYCENTRIC);
2835 OUT_BATCH(batch, 0);
2836 ADVANCE_BATCH(batch);
2838 BEGIN_BATCH(batch, 7);
2839 OUT_BATCH(batch, GEN6_3DSTATE_CONSTANT_PS | (7 - 2));
2840 OUT_BATCH(batch, URB_CS_ENTRY_SIZE);
2841 OUT_BATCH(batch, 0);
2843 render_state->curbe.bo,
2844 I915_GEM_DOMAIN_INSTRUCTION, 0,
2846 OUT_BATCH(batch, 0);
2847 OUT_BATCH(batch, 0);
2848 OUT_BATCH(batch, 0);
2849 ADVANCE_BATCH(batch);
2851 BEGIN_BATCH(batch, 8);
2852 OUT_BATCH(batch, GEN7_3DSTATE_PS | (8 - 2));
2854 render_state->render_kernels[kernel].bo,
2855 I915_GEM_DOMAIN_INSTRUCTION, 0,
2858 (1 << GEN7_PS_SAMPLER_COUNT_SHIFT) |
2859 (5 << GEN7_PS_BINDING_TABLE_ENTRY_COUNT_SHIFT));
2860 OUT_BATCH(batch, 0); /* scratch space base offset */
2862 ((render_state->max_wm_threads - 1) << max_threads_shift) | num_samples |
2863 GEN7_PS_PUSH_CONSTANT_ENABLE |
2864 GEN7_PS_ATTRIBUTE_ENABLE |
2865 GEN7_PS_16_DISPATCH_ENABLE);
2867 (6 << GEN7_PS_DISPATCH_START_GRF_SHIFT_0));
2868 OUT_BATCH(batch, 0); /* kernel 1 pointer */
2869 OUT_BATCH(batch, 0); /* kernel 2 pointer */
2870 ADVANCE_BATCH(batch);
2874 gen7_emit_vertex_element_state(VADriverContextP ctx)
2876 struct i965_driver_data *i965 = i965_driver_data(ctx);
2877 struct intel_batchbuffer *batch = i965->batch;
2879 /* Set up our vertex elements, sourced from the single vertex buffer. */
2880 OUT_BATCH(batch, CMD_VERTEX_ELEMENTS | (5 - 2));
2881 /* offset 0: X,Y -> {X, Y, 1.0, 1.0} */
2882 OUT_BATCH(batch, (0 << GEN6_VE0_VERTEX_BUFFER_INDEX_SHIFT) |
2884 (I965_SURFACEFORMAT_R32G32_FLOAT << VE0_FORMAT_SHIFT) |
2885 (0 << VE0_OFFSET_SHIFT));
2886 OUT_BATCH(batch, (I965_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT) |
2887 (I965_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT) |
2888 (I965_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_2_SHIFT) |
2889 (I965_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT));
2890 /* offset 8: S0, T0 -> {S0, T0, 1.0, 1.0} */
2891 OUT_BATCH(batch, (0 << GEN6_VE0_VERTEX_BUFFER_INDEX_SHIFT) |
2893 (I965_SURFACEFORMAT_R32G32_FLOAT << VE0_FORMAT_SHIFT) |
2894 (8 << VE0_OFFSET_SHIFT));
2895 OUT_BATCH(batch, (I965_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT) |
2896 (I965_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT) |
2897 (I965_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_2_SHIFT) |
2898 (I965_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT));
2902 gen7_emit_vertices(VADriverContextP ctx)
2904 struct i965_driver_data *i965 = i965_driver_data(ctx);
2905 struct intel_batchbuffer *batch = i965->batch;
2906 struct i965_render_state *render_state = &i965->render_state;
2908 BEGIN_BATCH(batch, 5);
2909 OUT_BATCH(batch, CMD_VERTEX_BUFFERS | (5 - 2));
2911 (0 << GEN6_VB0_BUFFER_INDEX_SHIFT) |
2912 GEN6_VB0_VERTEXDATA |
2913 GEN7_VB0_ADDRESS_MODIFYENABLE |
2914 ((4 * 4) << VB0_BUFFER_PITCH_SHIFT));
2915 OUT_RELOC(batch, render_state->vb.vertex_buffer, I915_GEM_DOMAIN_VERTEX, 0, 0);
2916 OUT_RELOC(batch, render_state->vb.vertex_buffer, I915_GEM_DOMAIN_VERTEX, 0, 12 * 4);
2917 OUT_BATCH(batch, 0);
2918 ADVANCE_BATCH(batch);
2920 BEGIN_BATCH(batch, 7);
2921 OUT_BATCH(batch, CMD_3DPRIMITIVE | (7 - 2));
2924 GEN7_3DPRIM_VERTEXBUFFER_ACCESS_SEQUENTIAL);
2925 OUT_BATCH(batch, 3); /* vertex count per instance */
2926 OUT_BATCH(batch, 0); /* start vertex offset */
2927 OUT_BATCH(batch, 1); /* single instance */
2928 OUT_BATCH(batch, 0); /* start instance location */
2929 OUT_BATCH(batch, 0);
2930 ADVANCE_BATCH(batch);
2934 gen7_render_emit_states(VADriverContextP ctx, int kernel)
2936 struct i965_driver_data *i965 = i965_driver_data(ctx);
2937 struct intel_batchbuffer *batch = i965->batch;
2939 intel_batchbuffer_start_atomic(batch, 0x1000);
2940 intel_batchbuffer_emit_mi_flush(batch);
2941 gen7_emit_invarient_states(ctx);
2942 gen7_emit_state_base_address(ctx);
2943 gen7_emit_viewport_state_pointers(ctx);
2945 gen7_emit_cc_state_pointers(ctx);
2946 gen7_emit_sampler_state_pointers(ctx);
2947 gen7_emit_bypass_state(ctx);
2948 gen7_emit_vs_state(ctx);
2949 gen7_emit_clip_state(ctx);
2950 gen7_emit_sf_state(ctx);
2951 gen7_emit_wm_state(ctx, kernel);
2952 gen7_emit_binding_table(ctx);
2953 gen7_emit_depth_buffer_state(ctx);
2954 gen7_emit_drawing_rectangle(ctx);
2955 gen7_emit_vertex_element_state(ctx);
2956 gen7_emit_vertices(ctx);
2957 intel_batchbuffer_end_atomic(batch);
2961 gen7_render_put_surface(
2962 VADriverContextP ctx,
2963 struct object_surface *obj_surface,
2964 const VARectangle *src_rect,
2965 const VARectangle *dst_rect,
2969 struct i965_driver_data *i965 = i965_driver_data(ctx);
2970 struct intel_batchbuffer *batch = i965->batch;
2972 gen7_render_initialize(ctx);
2973 gen7_render_setup_states(ctx, obj_surface, src_rect, dst_rect, flags);
2974 i965_clear_dest_region(ctx);
2975 gen7_render_emit_states(ctx, PS_KERNEL);
2976 intel_batchbuffer_flush(batch);
2980 gen7_subpicture_render_blend_state(VADriverContextP ctx)
2982 struct i965_driver_data *i965 = i965_driver_data(ctx);
2983 struct i965_render_state *render_state = &i965->render_state;
2984 struct gen6_blend_state *blend_state;
2986 dri_bo_unmap(render_state->cc.state);
2987 dri_bo_map(render_state->cc.blend, 1);
2988 assert(render_state->cc.blend->virtual);
2989 blend_state = render_state->cc.blend->virtual;
2990 memset(blend_state, 0, sizeof(*blend_state));
2991 blend_state->blend0.dest_blend_factor = I965_BLENDFACTOR_INV_SRC_ALPHA;
2992 blend_state->blend0.source_blend_factor = I965_BLENDFACTOR_SRC_ALPHA;
2993 blend_state->blend0.blend_func = I965_BLENDFUNCTION_ADD;
2994 blend_state->blend0.blend_enable = 1;
2995 blend_state->blend1.post_blend_clamp_enable = 1;
2996 blend_state->blend1.pre_blend_clamp_enable = 1;
2997 blend_state->blend1.clamp_range = 0; /* clamp range [0, 1] */
2998 dri_bo_unmap(render_state->cc.blend);
3002 gen7_subpicture_render_setup_states(
3003 VADriverContextP ctx,
3004 struct object_surface *obj_surface,
3005 const VARectangle *src_rect,
3006 const VARectangle *dst_rect
3009 i965_render_dest_surface_state(ctx, 0);
3010 i965_subpic_render_src_surfaces_state(ctx, obj_surface);
3011 i965_render_sampler(ctx);
3012 i965_render_cc_viewport(ctx);
3013 gen7_render_color_calc_state(ctx);
3014 gen7_subpicture_render_blend_state(ctx);
3015 gen7_render_depth_stencil_state(ctx);
3016 i965_subpic_render_upload_constants(ctx, obj_surface);
3017 i965_subpic_render_upload_vertex(ctx, obj_surface, dst_rect);
3021 gen7_render_put_subpicture(
3022 VADriverContextP ctx,
3023 struct object_surface *obj_surface,
3024 const VARectangle *src_rect,
3025 const VARectangle *dst_rect
3028 struct i965_driver_data *i965 = i965_driver_data(ctx);
3029 struct intel_batchbuffer *batch = i965->batch;
3030 unsigned int index = obj_surface->subpic_render_idx;
3031 struct object_subpic *obj_subpic = obj_surface->obj_subpic[index];
3034 gen7_render_initialize(ctx);
3035 gen7_subpicture_render_setup_states(ctx, obj_surface, src_rect, dst_rect);
3036 gen7_render_emit_states(ctx, PS_SUBPIC_KERNEL);
3037 i965_render_upload_image_palette(ctx, obj_subpic->obj_image, 0xff);
3038 intel_batchbuffer_flush(batch);
3046 i965_DestroySurfaces(VADriverContextP ctx,
3047 VASurfaceID *surface_list,
3050 intel_render_put_surface(
3051 VADriverContextP ctx,
3052 struct object_surface *obj_surface,
3053 const VARectangle *src_rect,
3054 const VARectangle *dst_rect,
3058 struct i965_driver_data *i965 = i965_driver_data(ctx);
3059 int has_done_scaling = 0;
3060 VASurfaceID out_surface_id = i965_post_processing(ctx,
3067 assert((!has_done_scaling) || (out_surface_id != VA_INVALID_ID));
3069 if (out_surface_id != VA_INVALID_ID) {
3070 struct object_surface *new_obj_surface = SURFACE(out_surface_id);
3072 if (new_obj_surface && new_obj_surface->bo)
3073 obj_surface = new_obj_surface;
3075 if (has_done_scaling)
3076 src_rect = dst_rect;
3079 if (IS_GEN7(i965->intel.device_id))
3080 gen7_render_put_surface(ctx, obj_surface, src_rect, dst_rect, flags);
3081 else if (IS_GEN6(i965->intel.device_id))
3082 gen6_render_put_surface(ctx, obj_surface, src_rect, dst_rect, flags);
3084 i965_render_put_surface(ctx, obj_surface, src_rect, dst_rect, flags);
3086 if (out_surface_id != VA_INVALID_ID)
3087 i965_DestroySurfaces(ctx, &out_surface_id, 1);
3091 intel_render_put_subpicture(
3092 VADriverContextP ctx,
3093 struct object_surface *obj_surface,
3094 const VARectangle *src_rect,
3095 const VARectangle *dst_rect
3098 struct i965_driver_data *i965 = i965_driver_data(ctx);
3100 if (IS_GEN7(i965->intel.device_id))
3101 gen7_render_put_subpicture(ctx, obj_surface, src_rect, dst_rect);
3102 else if (IS_GEN6(i965->intel.device_id))
3103 gen6_render_put_subpicture(ctx, obj_surface, src_rect, dst_rect);
3105 i965_render_put_subpicture(ctx, obj_surface, src_rect, dst_rect);
3109 i965_render_init(VADriverContextP ctx)
3111 struct i965_driver_data *i965 = i965_driver_data(ctx);
3112 struct i965_render_state *render_state = &i965->render_state;
3116 assert(NUM_RENDER_KERNEL == (sizeof(render_kernels_gen5) /
3117 sizeof(render_kernels_gen5[0])));
3118 assert(NUM_RENDER_KERNEL == (sizeof(render_kernels_gen6) /
3119 sizeof(render_kernels_gen6[0])));
3121 if (IS_GEN7(i965->intel.device_id))
3122 memcpy(render_state->render_kernels,
3123 (IS_HASWELL(i965->intel.device_id) ? render_kernels_gen7_haswell : render_kernels_gen7),
3124 sizeof(render_state->render_kernels));
3125 else if (IS_GEN6(i965->intel.device_id))
3126 memcpy(render_state->render_kernels, render_kernels_gen6, sizeof(render_state->render_kernels));
3127 else if (IS_IRONLAKE(i965->intel.device_id))
3128 memcpy(render_state->render_kernels, render_kernels_gen5, sizeof(render_state->render_kernels));
3130 memcpy(render_state->render_kernels, render_kernels_gen4, sizeof(render_state->render_kernels));
3132 for (i = 0; i < NUM_RENDER_KERNEL; i++) {
3133 struct i965_kernel *kernel = &render_state->render_kernels[i];
3138 kernel->bo = dri_bo_alloc(i965->intel.bufmgr,
3140 kernel->size, 0x1000);
3142 dri_bo_subdata(kernel->bo, 0, kernel->size, kernel->bin);
3145 /* constant buffer */
3146 render_state->curbe.bo = dri_bo_alloc(i965->intel.bufmgr,
3149 assert(render_state->curbe.bo);
3151 if (IS_HSW_GT1(i965->intel.device_id)) {
3152 render_state->max_wm_threads = 102;
3153 } else if (IS_HSW_GT2(i965->intel.device_id)) {
3154 render_state->max_wm_threads = 204;
3155 } else if (IS_HSW_GT3(i965->intel.device_id)) {
3156 render_state->max_wm_threads = 408;
3157 } else if (IS_IVB_GT1(i965->intel.device_id) || IS_BAYTRAIL(i965->intel.device_id)) {
3158 render_state->max_wm_threads = 48;
3159 } else if (IS_IVB_GT2(i965->intel.device_id)) {
3160 render_state->max_wm_threads = 172;
3161 } else if (IS_SNB_GT1(i965->intel.device_id)) {
3162 render_state->max_wm_threads = 40;
3163 } else if (IS_SNB_GT2(i965->intel.device_id)) {
3164 render_state->max_wm_threads = 80;
3165 } else if (IS_IRONLAKE(i965->intel.device_id)) {
3166 render_state->max_wm_threads = 72; /* 12 * 6 */
3167 } else if (IS_G4X(i965->intel.device_id)) {
3168 render_state->max_wm_threads = 50; /* 12 * 5 */
3170 /* should never get here !!! */
3178 i965_render_terminate(VADriverContextP ctx)
3181 struct i965_driver_data *i965 = i965_driver_data(ctx);
3182 struct i965_render_state *render_state = &i965->render_state;
3184 dri_bo_unreference(render_state->curbe.bo);
3185 render_state->curbe.bo = NULL;
3187 for (i = 0; i < NUM_RENDER_KERNEL; i++) {
3188 struct i965_kernel *kernel = &render_state->render_kernels[i];
3190 dri_bo_unreference(kernel->bo);
3194 dri_bo_unreference(render_state->vb.vertex_buffer);
3195 render_state->vb.vertex_buffer = NULL;
3196 dri_bo_unreference(render_state->vs.state);
3197 render_state->vs.state = NULL;
3198 dri_bo_unreference(render_state->sf.state);
3199 render_state->sf.state = NULL;
3200 dri_bo_unreference(render_state->wm.sampler);
3201 render_state->wm.sampler = NULL;
3202 dri_bo_unreference(render_state->wm.state);
3203 render_state->wm.state = NULL;
3204 dri_bo_unreference(render_state->wm.surface_state_binding_table_bo);
3205 dri_bo_unreference(render_state->cc.viewport);
3206 render_state->cc.viewport = NULL;
3207 dri_bo_unreference(render_state->cc.state);
3208 render_state->cc.state = NULL;
3209 dri_bo_unreference(render_state->cc.blend);
3210 render_state->cc.blend = NULL;
3211 dri_bo_unreference(render_state->cc.depth_stencil);
3212 render_state->cc.depth_stencil = NULL;
3214 if (render_state->draw_region) {
3215 dri_bo_unreference(render_state->draw_region->bo);
3216 free(render_state->draw_region);
3217 render_state->draw_region = NULL;