2 * Copyright © 2006 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Eric Anholt <eric@anholt.net>
25 * Keith Packard <keithp@keithp.com>
26 * Xiang Haihao <haihao.xiang@intel.com>
31 * Most of rendering codes are ported from xf86-video-intel/src/i965_video.c
39 #include "intel_batchbuffer.h"
40 #include "intel_driver.h"
41 #include "i965_defines.h"
42 #include "i965_drv_video.h"
43 #include "i965_structs.h"
45 #include "i965_render.h"
47 #define SF_KERNEL_NUM_GRF 16
48 #define SF_MAX_THREADS 1
50 static const uint32_t sf_kernel_static[][4] =
52 #include "shaders/render/exa_sf.g4b"
55 #define PS_KERNEL_NUM_GRF 32
56 #define PS_MAX_THREADS 32
58 #define I965_GRF_BLOCKS(nreg) ((nreg + 15) / 16 - 1)
60 static const uint32_t ps_kernel_static[][4] =
62 #include "shaders/render/exa_wm_xy.g4b"
63 #include "shaders/render/exa_wm_src_affine.g4b"
64 #include "shaders/render/exa_wm_src_sample_planar.g4b"
65 #include "shaders/render/exa_wm_yuv_rgb.g4b"
66 #include "shaders/render/exa_wm_write.g4b"
68 static const uint32_t ps_subpic_kernel_static[][4] =
70 #include "shaders/render/exa_wm_xy.g4b"
71 #include "shaders/render/exa_wm_src_affine.g4b"
72 #include "shaders/render/exa_wm_src_sample_argb.g4b"
73 #include "shaders/render/exa_wm_write.g4b"
77 static const uint32_t sf_kernel_static_gen5[][4] =
79 #include "shaders/render/exa_sf.g4b.gen5"
82 static const uint32_t ps_kernel_static_gen5[][4] =
84 #include "shaders/render/exa_wm_xy.g4b.gen5"
85 #include "shaders/render/exa_wm_src_affine.g4b.gen5"
86 #include "shaders/render/exa_wm_src_sample_planar.g4b.gen5"
87 #include "shaders/render/exa_wm_yuv_rgb.g4b.gen5"
88 #include "shaders/render/exa_wm_write.g4b.gen5"
90 static const uint32_t ps_subpic_kernel_static_gen5[][4] =
92 #include "shaders/render/exa_wm_xy.g4b.gen5"
93 #include "shaders/render/exa_wm_src_affine.g4b.gen5"
94 #include "shaders/render/exa_wm_src_sample_argb.g4b.gen5"
95 #include "shaders/render/exa_wm_write.g4b.gen5"
98 /* programs for Sandybridge */
99 static const uint32_t sf_kernel_static_gen6[][4] =
103 static const uint32_t ps_kernel_static_gen6[][4] = {
104 #include "shaders/render/exa_wm_src_affine.g6b"
105 #include "shaders/render/exa_wm_src_sample_planar.g6b"
106 #include "shaders/render/exa_wm_yuv_rgb.g6b"
107 #include "shaders/render/exa_wm_write.g6b"
110 static const uint32_t ps_subpic_kernel_static_gen6[][4] = {
111 #include "shaders/render/exa_wm_src_affine.g6b"
112 #include "shaders/render/exa_wm_src_sample_argb.g6b"
113 #include "shaders/render/exa_wm_write.g6b"
116 /* programs for Ivybridge */
117 static const uint32_t sf_kernel_static_gen7[][4] =
121 static const uint32_t ps_kernel_static_gen7[][4] = {
122 #include "shaders/render/exa_wm_src_affine.g7b"
123 #include "shaders/render/exa_wm_src_sample_planar.g7b"
124 #include "shaders/render/exa_wm_yuv_rgb.g7b"
125 #include "shaders/render/exa_wm_write.g7b"
128 static const uint32_t ps_subpic_kernel_static_gen7[][4] = {
129 #include "shaders/render/exa_wm_src_affine.g7b"
130 #include "shaders/render/exa_wm_src_sample_argb.g7b"
131 #include "shaders/render/exa_wm_write.g7b"
134 /* Programs for Haswell */
135 static const uint32_t ps_kernel_static_gen7_haswell[][4] = {
136 #include "shaders/render/exa_wm_src_affine.g7b"
137 #include "shaders/render/exa_wm_src_sample_planar.g7b.haswell"
138 #include "shaders/render/exa_wm_yuv_rgb.g7b"
139 #include "shaders/render/exa_wm_write.g7b"
142 #define SURFACE_STATE_PADDED_SIZE_I965 ALIGN(sizeof(struct i965_surface_state), 32)
143 #define SURFACE_STATE_PADDED_SIZE_GEN7 ALIGN(sizeof(struct gen7_surface_state), 32)
144 #define SURFACE_STATE_PADDED_SIZE MAX(SURFACE_STATE_PADDED_SIZE_I965, SURFACE_STATE_PADDED_SIZE_GEN7)
145 #define SURFACE_STATE_OFFSET(index) (SURFACE_STATE_PADDED_SIZE * index)
146 #define BINDING_TABLE_OFFSET SURFACE_STATE_OFFSET(MAX_RENDER_SURFACES)
148 static uint32_t float_to_uint (float f)
166 static struct i965_kernel render_kernels_gen4[] = {
171 sizeof(sf_kernel_static),
178 sizeof(ps_kernel_static),
185 ps_subpic_kernel_static,
186 sizeof(ps_subpic_kernel_static),
191 static struct i965_kernel render_kernels_gen5[] = {
195 sf_kernel_static_gen5,
196 sizeof(sf_kernel_static_gen5),
202 ps_kernel_static_gen5,
203 sizeof(ps_kernel_static_gen5),
210 ps_subpic_kernel_static_gen5,
211 sizeof(ps_subpic_kernel_static_gen5),
216 static struct i965_kernel render_kernels_gen6[] = {
220 sf_kernel_static_gen6,
221 sizeof(sf_kernel_static_gen6),
227 ps_kernel_static_gen6,
228 sizeof(ps_kernel_static_gen6),
235 ps_subpic_kernel_static_gen6,
236 sizeof(ps_subpic_kernel_static_gen6),
241 static struct i965_kernel render_kernels_gen7[] = {
245 sf_kernel_static_gen7,
246 sizeof(sf_kernel_static_gen7),
252 ps_kernel_static_gen7,
253 sizeof(ps_kernel_static_gen7),
260 ps_subpic_kernel_static_gen7,
261 sizeof(ps_subpic_kernel_static_gen7),
266 static struct i965_kernel render_kernels_gen7_haswell[] = {
270 sf_kernel_static_gen7,
271 sizeof(sf_kernel_static_gen7),
277 ps_kernel_static_gen7_haswell,
278 sizeof(ps_kernel_static_gen7_haswell),
285 ps_subpic_kernel_static_gen7,
286 sizeof(ps_subpic_kernel_static_gen7),
291 #define URB_VS_ENTRIES 8
292 #define URB_VS_ENTRY_SIZE 1
294 #define URB_GS_ENTRIES 0
295 #define URB_GS_ENTRY_SIZE 0
297 #define URB_CLIP_ENTRIES 0
298 #define URB_CLIP_ENTRY_SIZE 0
300 #define URB_SF_ENTRIES 1
301 #define URB_SF_ENTRY_SIZE 2
303 #define URB_CS_ENTRIES 1
304 #define URB_CS_ENTRY_SIZE 1
307 i965_render_vs_unit(VADriverContextP ctx)
309 struct i965_driver_data *i965 = i965_driver_data(ctx);
310 struct i965_render_state *render_state = &i965->render_state;
311 struct i965_vs_unit_state *vs_state;
313 dri_bo_map(render_state->vs.state, 1);
314 assert(render_state->vs.state->virtual);
315 vs_state = render_state->vs.state->virtual;
316 memset(vs_state, 0, sizeof(*vs_state));
318 if (IS_IRONLAKE(i965->intel.device_id))
319 vs_state->thread4.nr_urb_entries = URB_VS_ENTRIES >> 2;
321 vs_state->thread4.nr_urb_entries = URB_VS_ENTRIES;
323 vs_state->thread4.urb_entry_allocation_size = URB_VS_ENTRY_SIZE - 1;
324 vs_state->vs6.vs_enable = 0;
325 vs_state->vs6.vert_cache_disable = 1;
327 dri_bo_unmap(render_state->vs.state);
331 i965_render_sf_unit(VADriverContextP ctx)
333 struct i965_driver_data *i965 = i965_driver_data(ctx);
334 struct i965_render_state *render_state = &i965->render_state;
335 struct i965_sf_unit_state *sf_state;
337 dri_bo_map(render_state->sf.state, 1);
338 assert(render_state->sf.state->virtual);
339 sf_state = render_state->sf.state->virtual;
340 memset(sf_state, 0, sizeof(*sf_state));
342 sf_state->thread0.grf_reg_count = I965_GRF_BLOCKS(SF_KERNEL_NUM_GRF);
343 sf_state->thread0.kernel_start_pointer = render_state->render_kernels[SF_KERNEL].bo->offset >> 6;
345 sf_state->sf1.single_program_flow = 1; /* XXX */
346 sf_state->sf1.binding_table_entry_count = 0;
347 sf_state->sf1.thread_priority = 0;
348 sf_state->sf1.floating_point_mode = 0; /* Mesa does this */
349 sf_state->sf1.illegal_op_exception_enable = 1;
350 sf_state->sf1.mask_stack_exception_enable = 1;
351 sf_state->sf1.sw_exception_enable = 1;
353 /* scratch space is not used in our kernel */
354 sf_state->thread2.per_thread_scratch_space = 0;
355 sf_state->thread2.scratch_space_base_pointer = 0;
357 sf_state->thread3.const_urb_entry_read_length = 0; /* no const URBs */
358 sf_state->thread3.const_urb_entry_read_offset = 0; /* no const URBs */
359 sf_state->thread3.urb_entry_read_length = 1; /* 1 URB per vertex */
360 sf_state->thread3.urb_entry_read_offset = 0;
361 sf_state->thread3.dispatch_grf_start_reg = 3;
363 sf_state->thread4.max_threads = SF_MAX_THREADS - 1;
364 sf_state->thread4.urb_entry_allocation_size = URB_SF_ENTRY_SIZE - 1;
365 sf_state->thread4.nr_urb_entries = URB_SF_ENTRIES;
366 sf_state->thread4.stats_enable = 1;
368 sf_state->sf5.viewport_transform = 0; /* skip viewport */
370 sf_state->sf6.cull_mode = I965_CULLMODE_NONE;
371 sf_state->sf6.scissor = 0;
373 sf_state->sf7.trifan_pv = 2;
375 sf_state->sf6.dest_org_vbias = 0x8;
376 sf_state->sf6.dest_org_hbias = 0x8;
378 dri_bo_emit_reloc(render_state->sf.state,
379 I915_GEM_DOMAIN_INSTRUCTION, 0,
380 sf_state->thread0.grf_reg_count << 1,
381 offsetof(struct i965_sf_unit_state, thread0),
382 render_state->render_kernels[SF_KERNEL].bo);
384 dri_bo_unmap(render_state->sf.state);
388 i965_render_sampler(VADriverContextP ctx)
390 struct i965_driver_data *i965 = i965_driver_data(ctx);
391 struct i965_render_state *render_state = &i965->render_state;
392 struct i965_sampler_state *sampler_state;
395 assert(render_state->wm.sampler_count > 0);
396 assert(render_state->wm.sampler_count <= MAX_SAMPLERS);
398 dri_bo_map(render_state->wm.sampler, 1);
399 assert(render_state->wm.sampler->virtual);
400 sampler_state = render_state->wm.sampler->virtual;
401 for (i = 0; i < render_state->wm.sampler_count; i++) {
402 memset(sampler_state, 0, sizeof(*sampler_state));
403 sampler_state->ss0.min_filter = I965_MAPFILTER_LINEAR;
404 sampler_state->ss0.mag_filter = I965_MAPFILTER_LINEAR;
405 sampler_state->ss1.r_wrap_mode = I965_TEXCOORDMODE_CLAMP;
406 sampler_state->ss1.s_wrap_mode = I965_TEXCOORDMODE_CLAMP;
407 sampler_state->ss1.t_wrap_mode = I965_TEXCOORDMODE_CLAMP;
411 dri_bo_unmap(render_state->wm.sampler);
414 i965_subpic_render_wm_unit(VADriverContextP ctx)
416 struct i965_driver_data *i965 = i965_driver_data(ctx);
417 struct i965_render_state *render_state = &i965->render_state;
418 struct i965_wm_unit_state *wm_state;
420 assert(render_state->wm.sampler);
422 dri_bo_map(render_state->wm.state, 1);
423 assert(render_state->wm.state->virtual);
424 wm_state = render_state->wm.state->virtual;
425 memset(wm_state, 0, sizeof(*wm_state));
427 wm_state->thread0.grf_reg_count = I965_GRF_BLOCKS(PS_KERNEL_NUM_GRF);
428 wm_state->thread0.kernel_start_pointer = render_state->render_kernels[PS_SUBPIC_KERNEL].bo->offset >> 6;
430 wm_state->thread1.single_program_flow = 1; /* XXX */
432 if (IS_IRONLAKE(i965->intel.device_id))
433 wm_state->thread1.binding_table_entry_count = 0; /* hardware requirement */
435 wm_state->thread1.binding_table_entry_count = 7;
437 wm_state->thread2.scratch_space_base_pointer = 0;
438 wm_state->thread2.per_thread_scratch_space = 0; /* 1024 bytes */
440 wm_state->thread3.dispatch_grf_start_reg = 3; /* XXX */
441 wm_state->thread3.const_urb_entry_read_length = 0;
442 wm_state->thread3.const_urb_entry_read_offset = 0;
443 wm_state->thread3.urb_entry_read_length = 1; /* XXX */
444 wm_state->thread3.urb_entry_read_offset = 0; /* XXX */
446 wm_state->wm4.stats_enable = 0;
447 wm_state->wm4.sampler_state_pointer = render_state->wm.sampler->offset >> 5;
449 if (IS_IRONLAKE(i965->intel.device_id)) {
450 wm_state->wm4.sampler_count = 0; /* hardware requirement */
451 wm_state->wm5.max_threads = 12 * 6 - 1;
453 wm_state->wm4.sampler_count = (render_state->wm.sampler_count + 3) / 4;
454 wm_state->wm5.max_threads = 10 * 5 - 1;
457 wm_state->wm5.thread_dispatch_enable = 1;
458 wm_state->wm5.enable_16_pix = 1;
459 wm_state->wm5.enable_8_pix = 0;
460 wm_state->wm5.early_depth_test = 1;
462 dri_bo_emit_reloc(render_state->wm.state,
463 I915_GEM_DOMAIN_INSTRUCTION, 0,
464 wm_state->thread0.grf_reg_count << 1,
465 offsetof(struct i965_wm_unit_state, thread0),
466 render_state->render_kernels[PS_SUBPIC_KERNEL].bo);
468 dri_bo_emit_reloc(render_state->wm.state,
469 I915_GEM_DOMAIN_INSTRUCTION, 0,
470 wm_state->wm4.sampler_count << 2,
471 offsetof(struct i965_wm_unit_state, wm4),
472 render_state->wm.sampler);
474 dri_bo_unmap(render_state->wm.state);
479 i965_render_wm_unit(VADriverContextP ctx)
481 struct i965_driver_data *i965 = i965_driver_data(ctx);
482 struct i965_render_state *render_state = &i965->render_state;
483 struct i965_wm_unit_state *wm_state;
485 assert(render_state->wm.sampler);
487 dri_bo_map(render_state->wm.state, 1);
488 assert(render_state->wm.state->virtual);
489 wm_state = render_state->wm.state->virtual;
490 memset(wm_state, 0, sizeof(*wm_state));
492 wm_state->thread0.grf_reg_count = I965_GRF_BLOCKS(PS_KERNEL_NUM_GRF);
493 wm_state->thread0.kernel_start_pointer = render_state->render_kernels[PS_KERNEL].bo->offset >> 6;
495 wm_state->thread1.single_program_flow = 1; /* XXX */
497 if (IS_IRONLAKE(i965->intel.device_id))
498 wm_state->thread1.binding_table_entry_count = 0; /* hardware requirement */
500 wm_state->thread1.binding_table_entry_count = 7;
502 wm_state->thread2.scratch_space_base_pointer = 0;
503 wm_state->thread2.per_thread_scratch_space = 0; /* 1024 bytes */
505 wm_state->thread3.dispatch_grf_start_reg = 2; /* XXX */
506 wm_state->thread3.const_urb_entry_read_length = 1;
507 wm_state->thread3.const_urb_entry_read_offset = 0;
508 wm_state->thread3.urb_entry_read_length = 1; /* XXX */
509 wm_state->thread3.urb_entry_read_offset = 0; /* XXX */
511 wm_state->wm4.stats_enable = 0;
512 wm_state->wm4.sampler_state_pointer = render_state->wm.sampler->offset >> 5;
514 if (IS_IRONLAKE(i965->intel.device_id)) {
515 wm_state->wm4.sampler_count = 0; /* hardware requirement */
516 wm_state->wm5.max_threads = 12 * 6 - 1;
518 wm_state->wm4.sampler_count = (render_state->wm.sampler_count + 3) / 4;
519 wm_state->wm5.max_threads = 10 * 5 - 1;
522 wm_state->wm5.thread_dispatch_enable = 1;
523 wm_state->wm5.enable_16_pix = 1;
524 wm_state->wm5.enable_8_pix = 0;
525 wm_state->wm5.early_depth_test = 1;
527 dri_bo_emit_reloc(render_state->wm.state,
528 I915_GEM_DOMAIN_INSTRUCTION, 0,
529 wm_state->thread0.grf_reg_count << 1,
530 offsetof(struct i965_wm_unit_state, thread0),
531 render_state->render_kernels[PS_KERNEL].bo);
533 dri_bo_emit_reloc(render_state->wm.state,
534 I915_GEM_DOMAIN_INSTRUCTION, 0,
535 wm_state->wm4.sampler_count << 2,
536 offsetof(struct i965_wm_unit_state, wm4),
537 render_state->wm.sampler);
539 dri_bo_unmap(render_state->wm.state);
543 i965_render_cc_viewport(VADriverContextP ctx)
545 struct i965_driver_data *i965 = i965_driver_data(ctx);
546 struct i965_render_state *render_state = &i965->render_state;
547 struct i965_cc_viewport *cc_viewport;
549 dri_bo_map(render_state->cc.viewport, 1);
550 assert(render_state->cc.viewport->virtual);
551 cc_viewport = render_state->cc.viewport->virtual;
552 memset(cc_viewport, 0, sizeof(*cc_viewport));
554 cc_viewport->min_depth = -1.e35;
555 cc_viewport->max_depth = 1.e35;
557 dri_bo_unmap(render_state->cc.viewport);
561 i965_subpic_render_cc_unit(VADriverContextP ctx)
563 struct i965_driver_data *i965 = i965_driver_data(ctx);
564 struct i965_render_state *render_state = &i965->render_state;
565 struct i965_cc_unit_state *cc_state;
567 assert(render_state->cc.viewport);
569 dri_bo_map(render_state->cc.state, 1);
570 assert(render_state->cc.state->virtual);
571 cc_state = render_state->cc.state->virtual;
572 memset(cc_state, 0, sizeof(*cc_state));
574 cc_state->cc0.stencil_enable = 0; /* disable stencil */
575 cc_state->cc2.depth_test = 0; /* disable depth test */
576 cc_state->cc2.logicop_enable = 0; /* disable logic op */
577 cc_state->cc3.ia_blend_enable = 0 ; /* blend alpha just like colors */
578 cc_state->cc3.blend_enable = 1; /* enable color blend */
579 cc_state->cc3.alpha_test = 0; /* disable alpha test */
580 cc_state->cc3.alpha_test_format = 0;//0:ALPHATEST_UNORM8; /*store alpha value with UNORM8 */
581 cc_state->cc3.alpha_test_func = 5;//COMPAREFUNCTION_LESS; /*pass if less than the reference */
582 cc_state->cc4.cc_viewport_state_offset = render_state->cc.viewport->offset >> 5;
584 cc_state->cc5.dither_enable = 0; /* disable dither */
585 cc_state->cc5.logicop_func = 0xc; /* WHITE */
586 cc_state->cc5.statistics_enable = 1;
587 cc_state->cc5.ia_blend_function = I965_BLENDFUNCTION_ADD;
588 cc_state->cc5.ia_src_blend_factor = I965_BLENDFACTOR_DST_ALPHA;
589 cc_state->cc5.ia_dest_blend_factor = I965_BLENDFACTOR_DST_ALPHA;
591 cc_state->cc6.clamp_post_alpha_blend = 0;
592 cc_state->cc6.clamp_pre_alpha_blend =0;
594 /*final color = src_color*src_blend_factor +/- dst_color*dest_color_blend_factor*/
595 cc_state->cc6.blend_function = I965_BLENDFUNCTION_ADD;
596 cc_state->cc6.src_blend_factor = I965_BLENDFACTOR_SRC_ALPHA;
597 cc_state->cc6.dest_blend_factor = I965_BLENDFACTOR_INV_SRC_ALPHA;
599 /*alpha test reference*/
600 cc_state->cc7.alpha_ref.f =0.0 ;
603 dri_bo_emit_reloc(render_state->cc.state,
604 I915_GEM_DOMAIN_INSTRUCTION, 0,
606 offsetof(struct i965_cc_unit_state, cc4),
607 render_state->cc.viewport);
609 dri_bo_unmap(render_state->cc.state);
614 i965_render_cc_unit(VADriverContextP ctx)
616 struct i965_driver_data *i965 = i965_driver_data(ctx);
617 struct i965_render_state *render_state = &i965->render_state;
618 struct i965_cc_unit_state *cc_state;
620 assert(render_state->cc.viewport);
622 dri_bo_map(render_state->cc.state, 1);
623 assert(render_state->cc.state->virtual);
624 cc_state = render_state->cc.state->virtual;
625 memset(cc_state, 0, sizeof(*cc_state));
627 cc_state->cc0.stencil_enable = 0; /* disable stencil */
628 cc_state->cc2.depth_test = 0; /* disable depth test */
629 cc_state->cc2.logicop_enable = 1; /* enable logic op */
630 cc_state->cc3.ia_blend_enable = 0; /* blend alpha just like colors */
631 cc_state->cc3.blend_enable = 0; /* disable color blend */
632 cc_state->cc3.alpha_test = 0; /* disable alpha test */
633 cc_state->cc4.cc_viewport_state_offset = render_state->cc.viewport->offset >> 5;
635 cc_state->cc5.dither_enable = 0; /* disable dither */
636 cc_state->cc5.logicop_func = 0xc; /* WHITE */
637 cc_state->cc5.statistics_enable = 1;
638 cc_state->cc5.ia_blend_function = I965_BLENDFUNCTION_ADD;
639 cc_state->cc5.ia_src_blend_factor = I965_BLENDFACTOR_ONE;
640 cc_state->cc5.ia_dest_blend_factor = I965_BLENDFACTOR_ONE;
642 dri_bo_emit_reloc(render_state->cc.state,
643 I915_GEM_DOMAIN_INSTRUCTION, 0,
645 offsetof(struct i965_cc_unit_state, cc4),
646 render_state->cc.viewport);
648 dri_bo_unmap(render_state->cc.state);
652 i965_render_set_surface_tiling(struct i965_surface_state *ss, unsigned int tiling)
655 case I915_TILING_NONE:
656 ss->ss3.tiled_surface = 0;
657 ss->ss3.tile_walk = 0;
660 ss->ss3.tiled_surface = 1;
661 ss->ss3.tile_walk = I965_TILEWALK_XMAJOR;
664 ss->ss3.tiled_surface = 1;
665 ss->ss3.tile_walk = I965_TILEWALK_YMAJOR;
671 i965_render_set_surface_state(
672 struct i965_surface_state *ss,
674 unsigned long offset,
683 unsigned int swizzle;
685 memset(ss, 0, sizeof(*ss));
687 switch (flags & (I965_PP_FLAG_TOP_FIELD|I965_PP_FLAG_BOTTOM_FIELD)) {
688 case I965_PP_FLAG_BOTTOM_FIELD:
689 ss->ss0.vert_line_stride_ofs = 1;
691 case I965_PP_FLAG_TOP_FIELD:
692 ss->ss0.vert_line_stride = 1;
697 ss->ss0.surface_type = I965_SURFACE_2D;
698 ss->ss0.surface_format = format;
699 ss->ss0.color_blend = 1;
701 ss->ss1.base_addr = bo->offset + offset;
703 ss->ss2.width = width - 1;
704 ss->ss2.height = height - 1;
706 ss->ss3.pitch = pitch - 1;
708 dri_bo_get_tiling(bo, &tiling, &swizzle);
709 i965_render_set_surface_tiling(ss, tiling);
713 gen7_render_set_surface_tiling(struct gen7_surface_state *ss, uint32_t tiling)
716 case I915_TILING_NONE:
717 ss->ss0.tiled_surface = 0;
718 ss->ss0.tile_walk = 0;
721 ss->ss0.tiled_surface = 1;
722 ss->ss0.tile_walk = I965_TILEWALK_XMAJOR;
725 ss->ss0.tiled_surface = 1;
726 ss->ss0.tile_walk = I965_TILEWALK_YMAJOR;
731 /* Set "Shader Channel Select" */
733 gen7_render_set_surface_scs(struct gen7_surface_state *ss)
735 ss->ss7.shader_chanel_select_r = HSW_SCS_RED;
736 ss->ss7.shader_chanel_select_g = HSW_SCS_GREEN;
737 ss->ss7.shader_chanel_select_b = HSW_SCS_BLUE;
738 ss->ss7.shader_chanel_select_a = HSW_SCS_ALPHA;
742 gen7_render_set_surface_state(
743 struct gen7_surface_state *ss,
745 unsigned long offset,
754 unsigned int swizzle;
756 memset(ss, 0, sizeof(*ss));
758 switch (flags & (I965_PP_FLAG_TOP_FIELD|I965_PP_FLAG_BOTTOM_FIELD)) {
759 case I965_PP_FLAG_BOTTOM_FIELD:
760 ss->ss0.vert_line_stride_ofs = 1;
762 case I965_PP_FLAG_TOP_FIELD:
763 ss->ss0.vert_line_stride = 1;
768 ss->ss0.surface_type = I965_SURFACE_2D;
769 ss->ss0.surface_format = format;
771 ss->ss1.base_addr = bo->offset + offset;
773 ss->ss2.width = width - 1;
774 ss->ss2.height = height - 1;
776 ss->ss3.pitch = pitch - 1;
778 dri_bo_get_tiling(bo, &tiling, &swizzle);
779 gen7_render_set_surface_tiling(ss, tiling);
783 i965_render_src_surface_state(
784 VADriverContextP ctx,
787 unsigned long offset,
795 struct i965_driver_data *i965 = i965_driver_data(ctx);
796 struct i965_render_state *render_state = &i965->render_state;
798 dri_bo *ss_bo = render_state->wm.surface_state_binding_table_bo;
800 assert(index < MAX_RENDER_SURFACES);
802 dri_bo_map(ss_bo, 1);
803 assert(ss_bo->virtual);
804 ss = (char *)ss_bo->virtual + SURFACE_STATE_OFFSET(index);
806 if (IS_GEN7(i965->intel.device_id)) {
807 gen7_render_set_surface_state(ss,
810 pitch, format, flags);
811 if (IS_HASWELL(i965->intel.device_id))
812 gen7_render_set_surface_scs(ss);
813 dri_bo_emit_reloc(ss_bo,
814 I915_GEM_DOMAIN_SAMPLER, 0,
816 SURFACE_STATE_OFFSET(index) + offsetof(struct gen7_surface_state, ss1),
819 i965_render_set_surface_state(ss,
822 pitch, format, flags);
823 dri_bo_emit_reloc(ss_bo,
824 I915_GEM_DOMAIN_SAMPLER, 0,
826 SURFACE_STATE_OFFSET(index) + offsetof(struct i965_surface_state, ss1),
830 ((unsigned int *)((char *)ss_bo->virtual + BINDING_TABLE_OFFSET))[index] = SURFACE_STATE_OFFSET(index);
832 render_state->wm.sampler_count++;
836 i965_render_src_surfaces_state(
837 VADriverContextP ctx,
842 struct i965_driver_data *i965 = i965_driver_data(ctx);
843 struct object_surface *obj_surface;
848 obj_surface = SURFACE(surface);
851 region_pitch = obj_surface->width;
852 rw = obj_surface->orig_width;
853 rh = obj_surface->orig_height;
854 region = obj_surface->bo;
856 i965_render_src_surface_state(ctx, 1, region, 0, rw, rh, region_pitch, I965_SURFACEFORMAT_R8_UNORM, flags); /* Y */
857 i965_render_src_surface_state(ctx, 2, region, 0, rw, rh, region_pitch, I965_SURFACEFORMAT_R8_UNORM, flags);
859 if (obj_surface->fourcc == VA_FOURCC('N', 'V', '1', '2')) {
860 i965_render_src_surface_state(ctx, 3, region,
861 region_pitch * obj_surface->y_cb_offset,
862 obj_surface->cb_cr_width, obj_surface->cb_cr_height, obj_surface->cb_cr_pitch,
863 I965_SURFACEFORMAT_R8G8_UNORM, flags); /* UV */
864 i965_render_src_surface_state(ctx, 4, region,
865 region_pitch * obj_surface->y_cb_offset,
866 obj_surface->cb_cr_width, obj_surface->cb_cr_height, obj_surface->cb_cr_pitch,
867 I965_SURFACEFORMAT_R8G8_UNORM, flags);
869 i965_render_src_surface_state(ctx, 3, region,
870 region_pitch * obj_surface->y_cb_offset,
871 obj_surface->cb_cr_width, obj_surface->cb_cr_height, obj_surface->cb_cr_pitch,
872 I965_SURFACEFORMAT_R8_UNORM, flags); /* U */
873 i965_render_src_surface_state(ctx, 4, region,
874 region_pitch * obj_surface->y_cb_offset,
875 obj_surface->cb_cr_width, obj_surface->cb_cr_height, obj_surface->cb_cr_pitch,
876 I965_SURFACEFORMAT_R8_UNORM, flags);
877 i965_render_src_surface_state(ctx, 5, region,
878 region_pitch * obj_surface->y_cr_offset,
879 obj_surface->cb_cr_width, obj_surface->cb_cr_height, obj_surface->cb_cr_pitch,
880 I965_SURFACEFORMAT_R8_UNORM, flags); /* V */
881 i965_render_src_surface_state(ctx, 6, region,
882 region_pitch * obj_surface->y_cr_offset,
883 obj_surface->cb_cr_width, obj_surface->cb_cr_height, obj_surface->cb_cr_pitch,
884 I965_SURFACEFORMAT_R8_UNORM, flags);
889 i965_subpic_render_src_surfaces_state(VADriverContextP ctx,
892 struct i965_driver_data *i965 = i965_driver_data(ctx);
893 struct object_surface *obj_surface = SURFACE(surface);
896 dri_bo *subpic_region;
897 struct object_subpic *obj_subpic = SUBPIC(obj_surface->subpic);
898 struct object_image *obj_image = IMAGE(obj_subpic->image);
900 assert(obj_surface->bo);
901 w = obj_surface->width;
902 h = obj_surface->height;
903 region = obj_surface->bo;
904 subpic_region = obj_image->bo;
905 /*subpicture surface*/
906 i965_render_src_surface_state(ctx, 1, subpic_region, 0, obj_subpic->width, obj_subpic->height, obj_subpic->pitch, obj_subpic->format, 0);
907 i965_render_src_surface_state(ctx, 2, subpic_region, 0, obj_subpic->width, obj_subpic->height, obj_subpic->pitch, obj_subpic->format, 0);
911 i965_render_dest_surface_state(VADriverContextP ctx, int index)
913 struct i965_driver_data *i965 = i965_driver_data(ctx);
914 struct i965_render_state *render_state = &i965->render_state;
915 struct intel_region *dest_region = render_state->draw_region;
917 dri_bo *ss_bo = render_state->wm.surface_state_binding_table_bo;
919 assert(index < MAX_RENDER_SURFACES);
921 if (dest_region->cpp == 2) {
922 format = I965_SURFACEFORMAT_B5G6R5_UNORM;
924 format = I965_SURFACEFORMAT_B8G8R8A8_UNORM;
927 dri_bo_map(ss_bo, 1);
928 assert(ss_bo->virtual);
929 ss = (char *)ss_bo->virtual + SURFACE_STATE_OFFSET(index);
931 if (IS_GEN7(i965->intel.device_id)) {
932 gen7_render_set_surface_state(ss,
934 dest_region->width, dest_region->height,
935 dest_region->pitch, format, 0);
936 if (IS_HASWELL(i965->intel.device_id))
937 gen7_render_set_surface_scs(ss);
938 dri_bo_emit_reloc(ss_bo,
939 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
941 SURFACE_STATE_OFFSET(index) + offsetof(struct gen7_surface_state, ss1),
944 i965_render_set_surface_state(ss,
946 dest_region->width, dest_region->height,
947 dest_region->pitch, format, 0);
948 dri_bo_emit_reloc(ss_bo,
949 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
951 SURFACE_STATE_OFFSET(index) + offsetof(struct i965_surface_state, ss1),
955 ((unsigned int *)((char *)ss_bo->virtual + BINDING_TABLE_OFFSET))[index] = SURFACE_STATE_OFFSET(index);
960 i965_fill_vertex_buffer(
961 VADriverContextP ctx,
962 float tex_coords[4], /* [(u1,v1);(u2,v2)] */
963 float vid_coords[4] /* [(x1,y1);(x2,y2)] */
966 struct i965_driver_data * const i965 = i965_driver_data(ctx);
969 enum { X1, Y1, X2, Y2 };
971 static const unsigned int g_rotation_indices[][6] = {
972 [VA_ROTATION_NONE] = { X2, Y2, X1, Y2, X1, Y1 },
973 [VA_ROTATION_90] = { X2, Y1, X2, Y2, X1, Y2 },
974 [VA_ROTATION_180] = { X1, Y1, X2, Y1, X2, Y2 },
975 [VA_ROTATION_270] = { X1, Y2, X1, Y1, X2, Y1 },
978 const unsigned int * const rotation_indices =
979 g_rotation_indices[i965->rotation_attrib->value];
981 vb[0] = tex_coords[rotation_indices[0]]; /* bottom-right corner */
982 vb[1] = tex_coords[rotation_indices[1]];
983 vb[2] = vid_coords[X2];
984 vb[3] = vid_coords[Y2];
986 vb[4] = tex_coords[rotation_indices[2]]; /* bottom-left corner */
987 vb[5] = tex_coords[rotation_indices[3]];
988 vb[6] = vid_coords[X1];
989 vb[7] = vid_coords[Y2];
991 vb[8] = tex_coords[rotation_indices[4]]; /* top-left corner */
992 vb[9] = tex_coords[rotation_indices[5]];
993 vb[10] = vid_coords[X1];
994 vb[11] = vid_coords[Y1];
996 dri_bo_subdata(i965->render_state.vb.vertex_buffer, 0, sizeof(vb), vb);
1000 i965_subpic_render_upload_vertex(VADriverContextP ctx,
1001 VASurfaceID surface,
1002 const VARectangle *output_rect)
1004 struct i965_driver_data *i965 = i965_driver_data(ctx);
1005 struct object_surface *obj_surface = SURFACE(surface);
1006 struct object_subpic *obj_subpic = SUBPIC(obj_surface->subpic);
1007 float tex_coords[4], vid_coords[4];
1008 VARectangle dst_rect;
1010 if (obj_subpic->flags & VA_SUBPICTURE_DESTINATION_IS_SCREEN_COORD)
1011 dst_rect = obj_subpic->dst_rect;
1013 const float sx = (float)output_rect->width / obj_surface->orig_width;
1014 const float sy = (float)output_rect->height / obj_surface->orig_height;
1015 dst_rect.x = output_rect->x + sx * obj_subpic->dst_rect.x;
1016 dst_rect.y = output_rect->y + sy * obj_subpic->dst_rect.y;
1017 dst_rect.width = sx * obj_subpic->dst_rect.width;
1018 dst_rect.height = sy * obj_subpic->dst_rect.height;
1021 tex_coords[0] = (float)obj_subpic->src_rect.x / obj_subpic->width;
1022 tex_coords[1] = (float)obj_subpic->src_rect.y / obj_subpic->height;
1023 tex_coords[2] = (float)(obj_subpic->src_rect.x + obj_subpic->src_rect.width) / obj_subpic->width;
1024 tex_coords[3] = (float)(obj_subpic->src_rect.y + obj_subpic->src_rect.height) / obj_subpic->height;
1026 vid_coords[0] = dst_rect.x;
1027 vid_coords[1] = dst_rect.y;
1028 vid_coords[2] = (float)(dst_rect.x + dst_rect.width);
1029 vid_coords[3] = (float)(dst_rect.y + dst_rect.height);
1031 i965_fill_vertex_buffer(ctx, tex_coords, vid_coords);
1035 i965_render_upload_vertex(
1036 VADriverContextP ctx,
1037 VASurfaceID surface,
1038 const VARectangle *src_rect,
1039 const VARectangle *dst_rect
1042 struct i965_driver_data *i965 = i965_driver_data(ctx);
1043 struct i965_render_state *render_state = &i965->render_state;
1044 struct intel_region *dest_region = render_state->draw_region;
1045 struct object_surface *obj_surface;
1046 float tex_coords[4], vid_coords[4];
1049 obj_surface = SURFACE(surface);
1052 width = obj_surface->orig_width;
1053 height = obj_surface->orig_height;
1055 tex_coords[0] = (float)src_rect->x / width;
1056 tex_coords[1] = (float)src_rect->y / height;
1057 tex_coords[2] = (float)(src_rect->x + src_rect->width) / width;
1058 tex_coords[3] = (float)(src_rect->y + src_rect->height) / height;
1060 vid_coords[0] = dest_region->x + dst_rect->x;
1061 vid_coords[1] = dest_region->y + dst_rect->y;
1062 vid_coords[2] = vid_coords[0] + dst_rect->width;
1063 vid_coords[3] = vid_coords[1] + dst_rect->height;
1065 i965_fill_vertex_buffer(ctx, tex_coords, vid_coords);
1069 i965_render_upload_constants(VADriverContextP ctx,
1070 VASurfaceID surface)
1072 struct i965_driver_data *i965 = i965_driver_data(ctx);
1073 struct i965_render_state *render_state = &i965->render_state;
1074 unsigned short *constant_buffer;
1075 struct object_surface *obj_surface = SURFACE(surface);
1077 dri_bo_map(render_state->curbe.bo, 1);
1078 assert(render_state->curbe.bo->virtual);
1079 constant_buffer = render_state->curbe.bo->virtual;
1081 if (obj_surface->subsampling == SUBSAMPLE_YUV400) {
1082 assert(obj_surface->fourcc == VA_FOURCC('I', 'M', 'C', '1') ||
1083 obj_surface->fourcc == VA_FOURCC('I', 'M', 'C', '3'));
1084 *constant_buffer = 2;
1086 if (obj_surface->fourcc == VA_FOURCC('N', 'V', '1', '2'))
1087 *constant_buffer = 1;
1089 *constant_buffer = 0;
1092 dri_bo_unmap(render_state->curbe.bo);
1096 i965_surface_render_state_setup(
1097 VADriverContextP ctx,
1098 VASurfaceID surface,
1099 const VARectangle *src_rect,
1100 const VARectangle *dst_rect,
1104 i965_render_vs_unit(ctx);
1105 i965_render_sf_unit(ctx);
1106 i965_render_dest_surface_state(ctx, 0);
1107 i965_render_src_surfaces_state(ctx, surface, flags);
1108 i965_render_sampler(ctx);
1109 i965_render_wm_unit(ctx);
1110 i965_render_cc_viewport(ctx);
1111 i965_render_cc_unit(ctx);
1112 i965_render_upload_vertex(ctx, surface, src_rect, dst_rect);
1113 i965_render_upload_constants(ctx, surface);
1117 i965_subpic_render_state_setup(
1118 VADriverContextP ctx,
1119 VASurfaceID surface,
1120 const VARectangle *src_rect,
1121 const VARectangle *dst_rect
1124 i965_render_vs_unit(ctx);
1125 i965_render_sf_unit(ctx);
1126 i965_render_dest_surface_state(ctx, 0);
1127 i965_subpic_render_src_surfaces_state(ctx, surface);
1128 i965_render_sampler(ctx);
1129 i965_subpic_render_wm_unit(ctx);
1130 i965_render_cc_viewport(ctx);
1131 i965_subpic_render_cc_unit(ctx);
1132 i965_subpic_render_upload_vertex(ctx, surface, dst_rect);
1137 i965_render_pipeline_select(VADriverContextP ctx)
1139 struct i965_driver_data *i965 = i965_driver_data(ctx);
1140 struct intel_batchbuffer *batch = i965->batch;
1142 BEGIN_BATCH(batch, 1);
1143 OUT_BATCH(batch, CMD_PIPELINE_SELECT | PIPELINE_SELECT_3D);
1144 ADVANCE_BATCH(batch);
1148 i965_render_state_sip(VADriverContextP ctx)
1150 struct i965_driver_data *i965 = i965_driver_data(ctx);
1151 struct intel_batchbuffer *batch = i965->batch;
1153 BEGIN_BATCH(batch, 2);
1154 OUT_BATCH(batch, CMD_STATE_SIP | 0);
1155 OUT_BATCH(batch, 0);
1156 ADVANCE_BATCH(batch);
1160 i965_render_state_base_address(VADriverContextP ctx)
1162 struct i965_driver_data *i965 = i965_driver_data(ctx);
1163 struct intel_batchbuffer *batch = i965->batch;
1164 struct i965_render_state *render_state = &i965->render_state;
1166 if (IS_IRONLAKE(i965->intel.device_id)) {
1167 BEGIN_BATCH(batch, 8);
1168 OUT_BATCH(batch, CMD_STATE_BASE_ADDRESS | 6);
1169 OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
1170 OUT_RELOC(batch, render_state->wm.surface_state_binding_table_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, BASE_ADDRESS_MODIFY);
1171 OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
1172 OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
1173 OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
1174 OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
1175 OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
1176 ADVANCE_BATCH(batch);
1178 BEGIN_BATCH(batch, 6);
1179 OUT_BATCH(batch, CMD_STATE_BASE_ADDRESS | 4);
1180 OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
1181 OUT_RELOC(batch, render_state->wm.surface_state_binding_table_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, BASE_ADDRESS_MODIFY);
1182 OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
1183 OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
1184 OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
1185 ADVANCE_BATCH(batch);
1190 i965_render_binding_table_pointers(VADriverContextP ctx)
1192 struct i965_driver_data *i965 = i965_driver_data(ctx);
1193 struct intel_batchbuffer *batch = i965->batch;
1195 BEGIN_BATCH(batch, 6);
1196 OUT_BATCH(batch, CMD_BINDING_TABLE_POINTERS | 4);
1197 OUT_BATCH(batch, 0); /* vs */
1198 OUT_BATCH(batch, 0); /* gs */
1199 OUT_BATCH(batch, 0); /* clip */
1200 OUT_BATCH(batch, 0); /* sf */
1201 OUT_BATCH(batch, BINDING_TABLE_OFFSET);
1202 ADVANCE_BATCH(batch);
1206 i965_render_constant_color(VADriverContextP ctx)
1208 struct i965_driver_data *i965 = i965_driver_data(ctx);
1209 struct intel_batchbuffer *batch = i965->batch;
1211 BEGIN_BATCH(batch, 5);
1212 OUT_BATCH(batch, CMD_CONSTANT_COLOR | 3);
1213 OUT_BATCH(batch, float_to_uint(1.0));
1214 OUT_BATCH(batch, float_to_uint(0.0));
1215 OUT_BATCH(batch, float_to_uint(1.0));
1216 OUT_BATCH(batch, float_to_uint(1.0));
1217 ADVANCE_BATCH(batch);
1221 i965_render_pipelined_pointers(VADriverContextP ctx)
1223 struct i965_driver_data *i965 = i965_driver_data(ctx);
1224 struct intel_batchbuffer *batch = i965->batch;
1225 struct i965_render_state *render_state = &i965->render_state;
1227 BEGIN_BATCH(batch, 7);
1228 OUT_BATCH(batch, CMD_PIPELINED_POINTERS | 5);
1229 OUT_RELOC(batch, render_state->vs.state, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
1230 OUT_BATCH(batch, 0); /* disable GS */
1231 OUT_BATCH(batch, 0); /* disable CLIP */
1232 OUT_RELOC(batch, render_state->sf.state, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
1233 OUT_RELOC(batch, render_state->wm.state, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
1234 OUT_RELOC(batch, render_state->cc.state, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
1235 ADVANCE_BATCH(batch);
1239 i965_render_urb_layout(VADriverContextP ctx)
1241 struct i965_driver_data *i965 = i965_driver_data(ctx);
1242 struct intel_batchbuffer *batch = i965->batch;
1243 int urb_vs_start, urb_vs_size;
1244 int urb_gs_start, urb_gs_size;
1245 int urb_clip_start, urb_clip_size;
1246 int urb_sf_start, urb_sf_size;
1247 int urb_cs_start, urb_cs_size;
1250 urb_vs_size = URB_VS_ENTRIES * URB_VS_ENTRY_SIZE;
1251 urb_gs_start = urb_vs_start + urb_vs_size;
1252 urb_gs_size = URB_GS_ENTRIES * URB_GS_ENTRY_SIZE;
1253 urb_clip_start = urb_gs_start + urb_gs_size;
1254 urb_clip_size = URB_CLIP_ENTRIES * URB_CLIP_ENTRY_SIZE;
1255 urb_sf_start = urb_clip_start + urb_clip_size;
1256 urb_sf_size = URB_SF_ENTRIES * URB_SF_ENTRY_SIZE;
1257 urb_cs_start = urb_sf_start + urb_sf_size;
1258 urb_cs_size = URB_CS_ENTRIES * URB_CS_ENTRY_SIZE;
1260 BEGIN_BATCH(batch, 3);
1270 ((urb_clip_start + urb_clip_size) << UF1_CLIP_FENCE_SHIFT) |
1271 ((urb_gs_start + urb_gs_size) << UF1_GS_FENCE_SHIFT) |
1272 ((urb_vs_start + urb_vs_size) << UF1_VS_FENCE_SHIFT));
1274 ((urb_cs_start + urb_cs_size) << UF2_CS_FENCE_SHIFT) |
1275 ((urb_sf_start + urb_sf_size) << UF2_SF_FENCE_SHIFT));
1276 ADVANCE_BATCH(batch);
1280 i965_render_cs_urb_layout(VADriverContextP ctx)
1282 struct i965_driver_data *i965 = i965_driver_data(ctx);
1283 struct intel_batchbuffer *batch = i965->batch;
1285 BEGIN_BATCH(batch, 2);
1286 OUT_BATCH(batch, CMD_CS_URB_STATE | 0);
1288 ((URB_CS_ENTRY_SIZE - 1) << 4) | /* URB Entry Allocation Size */
1289 (URB_CS_ENTRIES << 0)); /* Number of URB Entries */
1290 ADVANCE_BATCH(batch);
1294 i965_render_constant_buffer(VADriverContextP ctx)
1296 struct i965_driver_data *i965 = i965_driver_data(ctx);
1297 struct intel_batchbuffer *batch = i965->batch;
1298 struct i965_render_state *render_state = &i965->render_state;
1300 BEGIN_BATCH(batch, 2);
1301 OUT_BATCH(batch, CMD_CONSTANT_BUFFER | (1 << 8) | (2 - 2));
1302 OUT_RELOC(batch, render_state->curbe.bo,
1303 I915_GEM_DOMAIN_INSTRUCTION, 0,
1304 URB_CS_ENTRY_SIZE - 1);
1305 ADVANCE_BATCH(batch);
1309 i965_render_drawing_rectangle(VADriverContextP ctx)
1311 struct i965_driver_data *i965 = i965_driver_data(ctx);
1312 struct intel_batchbuffer *batch = i965->batch;
1313 struct i965_render_state *render_state = &i965->render_state;
1314 struct intel_region *dest_region = render_state->draw_region;
1316 BEGIN_BATCH(batch, 4);
1317 OUT_BATCH(batch, CMD_DRAWING_RECTANGLE | 2);
1318 OUT_BATCH(batch, 0x00000000);
1319 OUT_BATCH(batch, (dest_region->width - 1) | (dest_region->height - 1) << 16);
1320 OUT_BATCH(batch, 0x00000000);
1321 ADVANCE_BATCH(batch);
1325 i965_render_vertex_elements(VADriverContextP ctx)
1327 struct i965_driver_data *i965 = i965_driver_data(ctx);
1328 struct intel_batchbuffer *batch = i965->batch;
1330 if (IS_IRONLAKE(i965->intel.device_id)) {
1331 BEGIN_BATCH(batch, 5);
1332 OUT_BATCH(batch, CMD_VERTEX_ELEMENTS | 3);
1333 /* offset 0: X,Y -> {X, Y, 1.0, 1.0} */
1334 OUT_BATCH(batch, (0 << VE0_VERTEX_BUFFER_INDEX_SHIFT) |
1336 (I965_SURFACEFORMAT_R32G32_FLOAT << VE0_FORMAT_SHIFT) |
1337 (0 << VE0_OFFSET_SHIFT));
1338 OUT_BATCH(batch, (I965_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT) |
1339 (I965_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT) |
1340 (I965_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_2_SHIFT) |
1341 (I965_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT));
1342 /* offset 8: S0, T0 -> {S0, T0, 1.0, 1.0} */
1343 OUT_BATCH(batch, (0 << VE0_VERTEX_BUFFER_INDEX_SHIFT) |
1345 (I965_SURFACEFORMAT_R32G32_FLOAT << VE0_FORMAT_SHIFT) |
1346 (8 << VE0_OFFSET_SHIFT));
1347 OUT_BATCH(batch, (I965_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT) |
1348 (I965_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT) |
1349 (I965_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_2_SHIFT) |
1350 (I965_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT));
1351 ADVANCE_BATCH(batch);
1353 BEGIN_BATCH(batch, 5);
1354 OUT_BATCH(batch, CMD_VERTEX_ELEMENTS | 3);
1355 /* offset 0: X,Y -> {X, Y, 1.0, 1.0} */
1356 OUT_BATCH(batch, (0 << VE0_VERTEX_BUFFER_INDEX_SHIFT) |
1358 (I965_SURFACEFORMAT_R32G32_FLOAT << VE0_FORMAT_SHIFT) |
1359 (0 << VE0_OFFSET_SHIFT));
1360 OUT_BATCH(batch, (I965_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT) |
1361 (I965_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT) |
1362 (I965_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_2_SHIFT) |
1363 (I965_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT) |
1364 (0 << VE1_DESTINATION_ELEMENT_OFFSET_SHIFT));
1365 /* offset 8: S0, T0 -> {S0, T0, 1.0, 1.0} */
1366 OUT_BATCH(batch, (0 << VE0_VERTEX_BUFFER_INDEX_SHIFT) |
1368 (I965_SURFACEFORMAT_R32G32_FLOAT << VE0_FORMAT_SHIFT) |
1369 (8 << VE0_OFFSET_SHIFT));
1370 OUT_BATCH(batch, (I965_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT) |
1371 (I965_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT) |
1372 (I965_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_2_SHIFT) |
1373 (I965_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT) |
1374 (4 << VE1_DESTINATION_ELEMENT_OFFSET_SHIFT));
1375 ADVANCE_BATCH(batch);
1380 i965_render_upload_image_palette(
1381 VADriverContextP ctx,
1386 struct i965_driver_data *i965 = i965_driver_data(ctx);
1387 struct intel_batchbuffer *batch = i965->batch;
1390 struct object_image *obj_image = IMAGE(image_id);
1393 if (obj_image->image.num_palette_entries == 0)
1396 BEGIN_BATCH(batch, 1 + obj_image->image.num_palette_entries);
1397 OUT_BATCH(batch, CMD_SAMPLER_PALETTE_LOAD | (obj_image->image.num_palette_entries - 1));
1399 //int32_t out[16]; //0-23:color 23-31:alpha
1400 for (i = 0; i < obj_image->image.num_palette_entries; i++)
1401 OUT_BATCH(batch, (alpha << 24) | obj_image->palette[i]);
1402 ADVANCE_BATCH(batch);
1406 i965_render_startup(VADriverContextP ctx)
1408 struct i965_driver_data *i965 = i965_driver_data(ctx);
1409 struct intel_batchbuffer *batch = i965->batch;
1410 struct i965_render_state *render_state = &i965->render_state;
1412 BEGIN_BATCH(batch, 11);
1413 OUT_BATCH(batch, CMD_VERTEX_BUFFERS | 3);
1415 (0 << VB0_BUFFER_INDEX_SHIFT) |
1417 ((4 * 4) << VB0_BUFFER_PITCH_SHIFT));
1418 OUT_RELOC(batch, render_state->vb.vertex_buffer, I915_GEM_DOMAIN_VERTEX, 0, 0);
1420 if (IS_IRONLAKE(i965->intel.device_id))
1421 OUT_RELOC(batch, render_state->vb.vertex_buffer, I915_GEM_DOMAIN_VERTEX, 0, 12 * 4);
1423 OUT_BATCH(batch, 3);
1425 OUT_BATCH(batch, 0);
1429 _3DPRIMITIVE_VERTEX_SEQUENTIAL |
1430 (_3DPRIM_RECTLIST << _3DPRIMITIVE_TOPOLOGY_SHIFT) |
1433 OUT_BATCH(batch, 3); /* vertex count per instance */
1434 OUT_BATCH(batch, 0); /* start vertex offset */
1435 OUT_BATCH(batch, 1); /* single instance */
1436 OUT_BATCH(batch, 0); /* start instance location */
1437 OUT_BATCH(batch, 0); /* index buffer offset, ignored */
1438 ADVANCE_BATCH(batch);
1442 i965_clear_dest_region(VADriverContextP ctx)
1444 struct i965_driver_data *i965 = i965_driver_data(ctx);
1445 struct intel_batchbuffer *batch = i965->batch;
1446 struct i965_render_state *render_state = &i965->render_state;
1447 struct intel_region *dest_region = render_state->draw_region;
1448 unsigned int blt_cmd, br13;
1451 blt_cmd = XY_COLOR_BLT_CMD;
1453 pitch = dest_region->pitch;
1455 if (dest_region->cpp == 4) {
1457 blt_cmd |= (XY_COLOR_BLT_WRITE_RGB | XY_COLOR_BLT_WRITE_ALPHA);
1459 assert(dest_region->cpp == 2);
1463 if (dest_region->tiling != I915_TILING_NONE) {
1464 blt_cmd |= XY_COLOR_BLT_DST_TILED;
1470 if (IS_GEN6(i965->intel.device_id) ||
1471 IS_GEN7(i965->intel.device_id)) {
1472 intel_batchbuffer_start_atomic_blt(batch, 24);
1473 BEGIN_BLT_BATCH(batch, 6);
1475 intel_batchbuffer_start_atomic(batch, 24);
1476 BEGIN_BATCH(batch, 6);
1479 OUT_BATCH(batch, blt_cmd);
1480 OUT_BATCH(batch, br13);
1481 OUT_BATCH(batch, (dest_region->y << 16) | (dest_region->x));
1482 OUT_BATCH(batch, ((dest_region->y + dest_region->height) << 16) |
1483 (dest_region->x + dest_region->width));
1484 OUT_RELOC(batch, dest_region->bo,
1485 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
1487 OUT_BATCH(batch, 0x0);
1488 ADVANCE_BATCH(batch);
1489 intel_batchbuffer_end_atomic(batch);
1493 i965_surface_render_pipeline_setup(VADriverContextP ctx)
1495 struct i965_driver_data *i965 = i965_driver_data(ctx);
1496 struct intel_batchbuffer *batch = i965->batch;
1498 i965_clear_dest_region(ctx);
1499 intel_batchbuffer_start_atomic(batch, 0x1000);
1500 intel_batchbuffer_emit_mi_flush(batch);
1501 i965_render_pipeline_select(ctx);
1502 i965_render_state_sip(ctx);
1503 i965_render_state_base_address(ctx);
1504 i965_render_binding_table_pointers(ctx);
1505 i965_render_constant_color(ctx);
1506 i965_render_pipelined_pointers(ctx);
1507 i965_render_urb_layout(ctx);
1508 i965_render_cs_urb_layout(ctx);
1509 i965_render_constant_buffer(ctx);
1510 i965_render_drawing_rectangle(ctx);
1511 i965_render_vertex_elements(ctx);
1512 i965_render_startup(ctx);
1513 intel_batchbuffer_end_atomic(batch);
1517 i965_subpic_render_pipeline_setup(VADriverContextP ctx)
1519 struct i965_driver_data *i965 = i965_driver_data(ctx);
1520 struct intel_batchbuffer *batch = i965->batch;
1522 intel_batchbuffer_start_atomic(batch, 0x1000);
1523 intel_batchbuffer_emit_mi_flush(batch);
1524 i965_render_pipeline_select(ctx);
1525 i965_render_state_sip(ctx);
1526 i965_render_state_base_address(ctx);
1527 i965_render_binding_table_pointers(ctx);
1528 i965_render_constant_color(ctx);
1529 i965_render_pipelined_pointers(ctx);
1530 i965_render_urb_layout(ctx);
1531 i965_render_cs_urb_layout(ctx);
1532 i965_render_drawing_rectangle(ctx);
1533 i965_render_vertex_elements(ctx);
1534 i965_render_startup(ctx);
1535 intel_batchbuffer_end_atomic(batch);
1540 i965_render_initialize(VADriverContextP ctx)
1542 struct i965_driver_data *i965 = i965_driver_data(ctx);
1543 struct i965_render_state *render_state = &i965->render_state;
1547 dri_bo_unreference(render_state->vb.vertex_buffer);
1548 bo = dri_bo_alloc(i965->intel.bufmgr,
1553 render_state->vb.vertex_buffer = bo;
1556 dri_bo_unreference(render_state->vs.state);
1557 bo = dri_bo_alloc(i965->intel.bufmgr,
1559 sizeof(struct i965_vs_unit_state),
1562 render_state->vs.state = bo;
1567 dri_bo_unreference(render_state->sf.state);
1568 bo = dri_bo_alloc(i965->intel.bufmgr,
1570 sizeof(struct i965_sf_unit_state),
1573 render_state->sf.state = bo;
1576 dri_bo_unreference(render_state->wm.surface_state_binding_table_bo);
1577 bo = dri_bo_alloc(i965->intel.bufmgr,
1578 "surface state & binding table",
1579 (SURFACE_STATE_PADDED_SIZE + sizeof(unsigned int)) * MAX_RENDER_SURFACES,
1582 render_state->wm.surface_state_binding_table_bo = bo;
1584 dri_bo_unreference(render_state->wm.sampler);
1585 bo = dri_bo_alloc(i965->intel.bufmgr,
1587 MAX_SAMPLERS * sizeof(struct i965_sampler_state),
1590 render_state->wm.sampler = bo;
1591 render_state->wm.sampler_count = 0;
1593 dri_bo_unreference(render_state->wm.state);
1594 bo = dri_bo_alloc(i965->intel.bufmgr,
1596 sizeof(struct i965_wm_unit_state),
1599 render_state->wm.state = bo;
1601 /* COLOR CALCULATOR */
1602 dri_bo_unreference(render_state->cc.state);
1603 bo = dri_bo_alloc(i965->intel.bufmgr,
1605 sizeof(struct i965_cc_unit_state),
1608 render_state->cc.state = bo;
1610 dri_bo_unreference(render_state->cc.viewport);
1611 bo = dri_bo_alloc(i965->intel.bufmgr,
1613 sizeof(struct i965_cc_viewport),
1616 render_state->cc.viewport = bo;
1620 i965_render_put_surface(
1621 VADriverContextP ctx,
1622 VASurfaceID surface,
1623 const VARectangle *src_rect,
1624 const VARectangle *dst_rect,
1628 struct i965_driver_data *i965 = i965_driver_data(ctx);
1629 struct intel_batchbuffer *batch = i965->batch;
1631 i965_render_initialize(ctx);
1632 i965_surface_render_state_setup(ctx, surface, src_rect, dst_rect, flags);
1633 i965_surface_render_pipeline_setup(ctx);
1634 intel_batchbuffer_flush(batch);
1638 i965_render_put_subpicture(
1639 VADriverContextP ctx,
1640 VASurfaceID surface,
1641 const VARectangle *src_rect,
1642 const VARectangle *dst_rect
1645 struct i965_driver_data *i965 = i965_driver_data(ctx);
1646 struct intel_batchbuffer *batch = i965->batch;
1647 struct object_surface *obj_surface = SURFACE(surface);
1648 struct object_subpic *obj_subpic = SUBPIC(obj_surface->subpic);
1652 i965_render_initialize(ctx);
1653 i965_subpic_render_state_setup(ctx, surface, src_rect, dst_rect);
1654 i965_subpic_render_pipeline_setup(ctx);
1655 i965_render_upload_image_palette(ctx, obj_subpic->image, 0xff);
1656 intel_batchbuffer_flush(batch);
1663 gen6_render_initialize(VADriverContextP ctx)
1665 struct i965_driver_data *i965 = i965_driver_data(ctx);
1666 struct i965_render_state *render_state = &i965->render_state;
1670 dri_bo_unreference(render_state->vb.vertex_buffer);
1671 bo = dri_bo_alloc(i965->intel.bufmgr,
1676 render_state->vb.vertex_buffer = bo;
1679 dri_bo_unreference(render_state->wm.surface_state_binding_table_bo);
1680 bo = dri_bo_alloc(i965->intel.bufmgr,
1681 "surface state & binding table",
1682 (SURFACE_STATE_PADDED_SIZE + sizeof(unsigned int)) * MAX_RENDER_SURFACES,
1685 render_state->wm.surface_state_binding_table_bo = bo;
1687 dri_bo_unreference(render_state->wm.sampler);
1688 bo = dri_bo_alloc(i965->intel.bufmgr,
1690 MAX_SAMPLERS * sizeof(struct i965_sampler_state),
1693 render_state->wm.sampler = bo;
1694 render_state->wm.sampler_count = 0;
1696 /* COLOR CALCULATOR */
1697 dri_bo_unreference(render_state->cc.state);
1698 bo = dri_bo_alloc(i965->intel.bufmgr,
1700 sizeof(struct gen6_color_calc_state),
1703 render_state->cc.state = bo;
1706 dri_bo_unreference(render_state->cc.viewport);
1707 bo = dri_bo_alloc(i965->intel.bufmgr,
1709 sizeof(struct i965_cc_viewport),
1712 render_state->cc.viewport = bo;
1715 dri_bo_unreference(render_state->cc.blend);
1716 bo = dri_bo_alloc(i965->intel.bufmgr,
1718 sizeof(struct gen6_blend_state),
1721 render_state->cc.blend = bo;
1723 /* DEPTH & STENCIL STATE */
1724 dri_bo_unreference(render_state->cc.depth_stencil);
1725 bo = dri_bo_alloc(i965->intel.bufmgr,
1726 "depth & stencil state",
1727 sizeof(struct gen6_depth_stencil_state),
1730 render_state->cc.depth_stencil = bo;
1734 gen6_render_color_calc_state(VADriverContextP ctx)
1736 struct i965_driver_data *i965 = i965_driver_data(ctx);
1737 struct i965_render_state *render_state = &i965->render_state;
1738 struct gen6_color_calc_state *color_calc_state;
1740 dri_bo_map(render_state->cc.state, 1);
1741 assert(render_state->cc.state->virtual);
1742 color_calc_state = render_state->cc.state->virtual;
1743 memset(color_calc_state, 0, sizeof(*color_calc_state));
1744 color_calc_state->constant_r = 1.0;
1745 color_calc_state->constant_g = 0.0;
1746 color_calc_state->constant_b = 1.0;
1747 color_calc_state->constant_a = 1.0;
1748 dri_bo_unmap(render_state->cc.state);
1752 gen6_render_blend_state(VADriverContextP ctx)
1754 struct i965_driver_data *i965 = i965_driver_data(ctx);
1755 struct i965_render_state *render_state = &i965->render_state;
1756 struct gen6_blend_state *blend_state;
1758 dri_bo_map(render_state->cc.blend, 1);
1759 assert(render_state->cc.blend->virtual);
1760 blend_state = render_state->cc.blend->virtual;
1761 memset(blend_state, 0, sizeof(*blend_state));
1762 blend_state->blend1.logic_op_enable = 1;
1763 blend_state->blend1.logic_op_func = 0xc;
1764 dri_bo_unmap(render_state->cc.blend);
1768 gen6_render_depth_stencil_state(VADriverContextP ctx)
1770 struct i965_driver_data *i965 = i965_driver_data(ctx);
1771 struct i965_render_state *render_state = &i965->render_state;
1772 struct gen6_depth_stencil_state *depth_stencil_state;
1774 dri_bo_map(render_state->cc.depth_stencil, 1);
1775 assert(render_state->cc.depth_stencil->virtual);
1776 depth_stencil_state = render_state->cc.depth_stencil->virtual;
1777 memset(depth_stencil_state, 0, sizeof(*depth_stencil_state));
1778 dri_bo_unmap(render_state->cc.depth_stencil);
1782 gen6_render_setup_states(
1783 VADriverContextP ctx,
1784 VASurfaceID surface,
1785 const VARectangle *src_rect,
1786 const VARectangle *dst_rect,
1790 i965_render_dest_surface_state(ctx, 0);
1791 i965_render_src_surfaces_state(ctx, surface, flags);
1792 i965_render_sampler(ctx);
1793 i965_render_cc_viewport(ctx);
1794 gen6_render_color_calc_state(ctx);
1795 gen6_render_blend_state(ctx);
1796 gen6_render_depth_stencil_state(ctx);
1797 i965_render_upload_constants(ctx, surface);
1798 i965_render_upload_vertex(ctx, surface, src_rect, dst_rect);
1802 gen6_emit_invarient_states(VADriverContextP ctx)
1804 struct i965_driver_data *i965 = i965_driver_data(ctx);
1805 struct intel_batchbuffer *batch = i965->batch;
1807 OUT_BATCH(batch, CMD_PIPELINE_SELECT | PIPELINE_SELECT_3D);
1809 OUT_BATCH(batch, GEN6_3DSTATE_MULTISAMPLE | (3 - 2));
1810 OUT_BATCH(batch, GEN6_3DSTATE_MULTISAMPLE_PIXEL_LOCATION_CENTER |
1811 GEN6_3DSTATE_MULTISAMPLE_NUMSAMPLES_1); /* 1 sample/pixel */
1812 OUT_BATCH(batch, 0);
1814 OUT_BATCH(batch, GEN6_3DSTATE_SAMPLE_MASK | (2 - 2));
1815 OUT_BATCH(batch, 1);
1817 /* Set system instruction pointer */
1818 OUT_BATCH(batch, CMD_STATE_SIP | 0);
1819 OUT_BATCH(batch, 0);
1823 gen6_emit_state_base_address(VADriverContextP ctx)
1825 struct i965_driver_data *i965 = i965_driver_data(ctx);
1826 struct intel_batchbuffer *batch = i965->batch;
1827 struct i965_render_state *render_state = &i965->render_state;
1829 OUT_BATCH(batch, CMD_STATE_BASE_ADDRESS | (10 - 2));
1830 OUT_BATCH(batch, BASE_ADDRESS_MODIFY); /* General state base address */
1831 OUT_RELOC(batch, render_state->wm.surface_state_binding_table_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, BASE_ADDRESS_MODIFY); /* Surface state base address */
1832 OUT_BATCH(batch, BASE_ADDRESS_MODIFY); /* Dynamic state base address */
1833 OUT_BATCH(batch, BASE_ADDRESS_MODIFY); /* Indirect object base address */
1834 OUT_BATCH(batch, BASE_ADDRESS_MODIFY); /* Instruction base address */
1835 OUT_BATCH(batch, BASE_ADDRESS_MODIFY); /* General state upper bound */
1836 OUT_BATCH(batch, BASE_ADDRESS_MODIFY); /* Dynamic state upper bound */
1837 OUT_BATCH(batch, BASE_ADDRESS_MODIFY); /* Indirect object upper bound */
1838 OUT_BATCH(batch, BASE_ADDRESS_MODIFY); /* Instruction access upper bound */
1842 gen6_emit_viewport_state_pointers(VADriverContextP ctx)
1844 struct i965_driver_data *i965 = i965_driver_data(ctx);
1845 struct intel_batchbuffer *batch = i965->batch;
1846 struct i965_render_state *render_state = &i965->render_state;
1848 OUT_BATCH(batch, GEN6_3DSTATE_VIEWPORT_STATE_POINTERS |
1849 GEN6_3DSTATE_VIEWPORT_STATE_MODIFY_CC |
1851 OUT_BATCH(batch, 0);
1852 OUT_BATCH(batch, 0);
1853 OUT_RELOC(batch, render_state->cc.viewport, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
1857 gen6_emit_urb(VADriverContextP ctx)
1859 struct i965_driver_data *i965 = i965_driver_data(ctx);
1860 struct intel_batchbuffer *batch = i965->batch;
1862 OUT_BATCH(batch, GEN6_3DSTATE_URB | (3 - 2));
1863 OUT_BATCH(batch, ((1 - 1) << GEN6_3DSTATE_URB_VS_SIZE_SHIFT) |
1864 (24 << GEN6_3DSTATE_URB_VS_ENTRIES_SHIFT)); /* at least 24 on GEN6 */
1865 OUT_BATCH(batch, (0 << GEN6_3DSTATE_URB_GS_SIZE_SHIFT) |
1866 (0 << GEN6_3DSTATE_URB_GS_ENTRIES_SHIFT)); /* no GS thread */
1870 gen6_emit_cc_state_pointers(VADriverContextP ctx)
1872 struct i965_driver_data *i965 = i965_driver_data(ctx);
1873 struct intel_batchbuffer *batch = i965->batch;
1874 struct i965_render_state *render_state = &i965->render_state;
1876 OUT_BATCH(batch, GEN6_3DSTATE_CC_STATE_POINTERS | (4 - 2));
1877 OUT_RELOC(batch, render_state->cc.blend, I915_GEM_DOMAIN_INSTRUCTION, 0, 1);
1878 OUT_RELOC(batch, render_state->cc.depth_stencil, I915_GEM_DOMAIN_INSTRUCTION, 0, 1);
1879 OUT_RELOC(batch, render_state->cc.state, I915_GEM_DOMAIN_INSTRUCTION, 0, 1);
1883 gen6_emit_sampler_state_pointers(VADriverContextP ctx)
1885 struct i965_driver_data *i965 = i965_driver_data(ctx);
1886 struct intel_batchbuffer *batch = i965->batch;
1887 struct i965_render_state *render_state = &i965->render_state;
1889 OUT_BATCH(batch, GEN6_3DSTATE_SAMPLER_STATE_POINTERS |
1890 GEN6_3DSTATE_SAMPLER_STATE_MODIFY_PS |
1892 OUT_BATCH(batch, 0); /* VS */
1893 OUT_BATCH(batch, 0); /* GS */
1894 OUT_RELOC(batch,render_state->wm.sampler, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
1898 gen6_emit_binding_table(VADriverContextP ctx)
1900 struct i965_driver_data *i965 = i965_driver_data(ctx);
1901 struct intel_batchbuffer *batch = i965->batch;
1903 /* Binding table pointers */
1904 OUT_BATCH(batch, CMD_BINDING_TABLE_POINTERS |
1905 GEN6_BINDING_TABLE_MODIFY_PS |
1907 OUT_BATCH(batch, 0); /* vs */
1908 OUT_BATCH(batch, 0); /* gs */
1909 /* Only the PS uses the binding table */
1910 OUT_BATCH(batch, BINDING_TABLE_OFFSET);
1914 gen6_emit_depth_buffer_state(VADriverContextP ctx)
1916 struct i965_driver_data *i965 = i965_driver_data(ctx);
1917 struct intel_batchbuffer *batch = i965->batch;
1919 OUT_BATCH(batch, CMD_DEPTH_BUFFER | (7 - 2));
1920 OUT_BATCH(batch, (I965_SURFACE_NULL << CMD_DEPTH_BUFFER_TYPE_SHIFT) |
1921 (I965_DEPTHFORMAT_D32_FLOAT << CMD_DEPTH_BUFFER_FORMAT_SHIFT));
1922 OUT_BATCH(batch, 0);
1923 OUT_BATCH(batch, 0);
1924 OUT_BATCH(batch, 0);
1925 OUT_BATCH(batch, 0);
1926 OUT_BATCH(batch, 0);
1928 OUT_BATCH(batch, CMD_CLEAR_PARAMS | (2 - 2));
1929 OUT_BATCH(batch, 0);
1933 gen6_emit_drawing_rectangle(VADriverContextP ctx)
1935 i965_render_drawing_rectangle(ctx);
1939 gen6_emit_vs_state(VADriverContextP ctx)
1941 struct i965_driver_data *i965 = i965_driver_data(ctx);
1942 struct intel_batchbuffer *batch = i965->batch;
1944 /* disable VS constant buffer */
1945 OUT_BATCH(batch, GEN6_3DSTATE_CONSTANT_VS | (5 - 2));
1946 OUT_BATCH(batch, 0);
1947 OUT_BATCH(batch, 0);
1948 OUT_BATCH(batch, 0);
1949 OUT_BATCH(batch, 0);
1951 OUT_BATCH(batch, GEN6_3DSTATE_VS | (6 - 2));
1952 OUT_BATCH(batch, 0); /* without VS kernel */
1953 OUT_BATCH(batch, 0);
1954 OUT_BATCH(batch, 0);
1955 OUT_BATCH(batch, 0);
1956 OUT_BATCH(batch, 0); /* pass-through */
1960 gen6_emit_gs_state(VADriverContextP ctx)
1962 struct i965_driver_data *i965 = i965_driver_data(ctx);
1963 struct intel_batchbuffer *batch = i965->batch;
1965 /* disable GS constant buffer */
1966 OUT_BATCH(batch, GEN6_3DSTATE_CONSTANT_GS | (5 - 2));
1967 OUT_BATCH(batch, 0);
1968 OUT_BATCH(batch, 0);
1969 OUT_BATCH(batch, 0);
1970 OUT_BATCH(batch, 0);
1972 OUT_BATCH(batch, GEN6_3DSTATE_GS | (7 - 2));
1973 OUT_BATCH(batch, 0); /* without GS kernel */
1974 OUT_BATCH(batch, 0);
1975 OUT_BATCH(batch, 0);
1976 OUT_BATCH(batch, 0);
1977 OUT_BATCH(batch, 0);
1978 OUT_BATCH(batch, 0); /* pass-through */
1982 gen6_emit_clip_state(VADriverContextP ctx)
1984 struct i965_driver_data *i965 = i965_driver_data(ctx);
1985 struct intel_batchbuffer *batch = i965->batch;
1987 OUT_BATCH(batch, GEN6_3DSTATE_CLIP | (4 - 2));
1988 OUT_BATCH(batch, 0);
1989 OUT_BATCH(batch, 0); /* pass-through */
1990 OUT_BATCH(batch, 0);
1994 gen6_emit_sf_state(VADriverContextP ctx)
1996 struct i965_driver_data *i965 = i965_driver_data(ctx);
1997 struct intel_batchbuffer *batch = i965->batch;
1999 OUT_BATCH(batch, GEN6_3DSTATE_SF | (20 - 2));
2000 OUT_BATCH(batch, (1 << GEN6_3DSTATE_SF_NUM_OUTPUTS_SHIFT) |
2001 (1 << GEN6_3DSTATE_SF_URB_ENTRY_READ_LENGTH_SHIFT) |
2002 (0 << GEN6_3DSTATE_SF_URB_ENTRY_READ_OFFSET_SHIFT));
2003 OUT_BATCH(batch, 0);
2004 OUT_BATCH(batch, GEN6_3DSTATE_SF_CULL_NONE);
2005 OUT_BATCH(batch, 2 << GEN6_3DSTATE_SF_TRIFAN_PROVOKE_SHIFT); /* DW4 */
2006 OUT_BATCH(batch, 0);
2007 OUT_BATCH(batch, 0);
2008 OUT_BATCH(batch, 0);
2009 OUT_BATCH(batch, 0);
2010 OUT_BATCH(batch, 0); /* DW9 */
2011 OUT_BATCH(batch, 0);
2012 OUT_BATCH(batch, 0);
2013 OUT_BATCH(batch, 0);
2014 OUT_BATCH(batch, 0);
2015 OUT_BATCH(batch, 0); /* DW14 */
2016 OUT_BATCH(batch, 0);
2017 OUT_BATCH(batch, 0);
2018 OUT_BATCH(batch, 0);
2019 OUT_BATCH(batch, 0);
2020 OUT_BATCH(batch, 0); /* DW19 */
2024 gen6_emit_wm_state(VADriverContextP ctx, int kernel)
2026 struct i965_driver_data *i965 = i965_driver_data(ctx);
2027 struct intel_batchbuffer *batch = i965->batch;
2028 struct i965_render_state *render_state = &i965->render_state;
2030 OUT_BATCH(batch, GEN6_3DSTATE_CONSTANT_PS |
2031 GEN6_3DSTATE_CONSTANT_BUFFER_0_ENABLE |
2034 render_state->curbe.bo,
2035 I915_GEM_DOMAIN_INSTRUCTION, 0,
2037 OUT_BATCH(batch, 0);
2038 OUT_BATCH(batch, 0);
2039 OUT_BATCH(batch, 0);
2041 OUT_BATCH(batch, GEN6_3DSTATE_WM | (9 - 2));
2042 OUT_RELOC(batch, render_state->render_kernels[kernel].bo,
2043 I915_GEM_DOMAIN_INSTRUCTION, 0,
2045 OUT_BATCH(batch, (1 << GEN6_3DSTATE_WM_SAMPLER_COUNT_SHITF) |
2046 (5 << GEN6_3DSTATE_WM_BINDING_TABLE_ENTRY_COUNT_SHIFT));
2047 OUT_BATCH(batch, 0);
2048 OUT_BATCH(batch, (6 << GEN6_3DSTATE_WM_DISPATCH_START_GRF_0_SHIFT)); /* DW4 */
2049 OUT_BATCH(batch, ((40 - 1) << GEN6_3DSTATE_WM_MAX_THREADS_SHIFT) |
2050 GEN6_3DSTATE_WM_DISPATCH_ENABLE |
2051 GEN6_3DSTATE_WM_16_DISPATCH_ENABLE);
2052 OUT_BATCH(batch, (1 << GEN6_3DSTATE_WM_NUM_SF_OUTPUTS_SHIFT) |
2053 GEN6_3DSTATE_WM_PERSPECTIVE_PIXEL_BARYCENTRIC);
2054 OUT_BATCH(batch, 0);
2055 OUT_BATCH(batch, 0);
2059 gen6_emit_vertex_element_state(VADriverContextP ctx)
2061 struct i965_driver_data *i965 = i965_driver_data(ctx);
2062 struct intel_batchbuffer *batch = i965->batch;
2064 /* Set up our vertex elements, sourced from the single vertex buffer. */
2065 OUT_BATCH(batch, CMD_VERTEX_ELEMENTS | (5 - 2));
2066 /* offset 0: X,Y -> {X, Y, 1.0, 1.0} */
2067 OUT_BATCH(batch, (0 << GEN6_VE0_VERTEX_BUFFER_INDEX_SHIFT) |
2069 (I965_SURFACEFORMAT_R32G32_FLOAT << VE0_FORMAT_SHIFT) |
2070 (0 << VE0_OFFSET_SHIFT));
2071 OUT_BATCH(batch, (I965_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT) |
2072 (I965_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT) |
2073 (I965_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_2_SHIFT) |
2074 (I965_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT));
2075 /* offset 8: S0, T0 -> {S0, T0, 1.0, 1.0} */
2076 OUT_BATCH(batch, (0 << GEN6_VE0_VERTEX_BUFFER_INDEX_SHIFT) |
2078 (I965_SURFACEFORMAT_R32G32_FLOAT << VE0_FORMAT_SHIFT) |
2079 (8 << VE0_OFFSET_SHIFT));
2080 OUT_BATCH(batch, (I965_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT) |
2081 (I965_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT) |
2082 (I965_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_2_SHIFT) |
2083 (I965_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT));
2087 gen6_emit_vertices(VADriverContextP ctx)
2089 struct i965_driver_data *i965 = i965_driver_data(ctx);
2090 struct intel_batchbuffer *batch = i965->batch;
2091 struct i965_render_state *render_state = &i965->render_state;
2093 BEGIN_BATCH(batch, 11);
2094 OUT_BATCH(batch, CMD_VERTEX_BUFFERS | 3);
2096 (0 << GEN6_VB0_BUFFER_INDEX_SHIFT) |
2097 GEN6_VB0_VERTEXDATA |
2098 ((4 * 4) << VB0_BUFFER_PITCH_SHIFT));
2099 OUT_RELOC(batch, render_state->vb.vertex_buffer, I915_GEM_DOMAIN_VERTEX, 0, 0);
2100 OUT_RELOC(batch, render_state->vb.vertex_buffer, I915_GEM_DOMAIN_VERTEX, 0, 12 * 4);
2101 OUT_BATCH(batch, 0);
2105 _3DPRIMITIVE_VERTEX_SEQUENTIAL |
2106 (_3DPRIM_RECTLIST << _3DPRIMITIVE_TOPOLOGY_SHIFT) |
2109 OUT_BATCH(batch, 3); /* vertex count per instance */
2110 OUT_BATCH(batch, 0); /* start vertex offset */
2111 OUT_BATCH(batch, 1); /* single instance */
2112 OUT_BATCH(batch, 0); /* start instance location */
2113 OUT_BATCH(batch, 0); /* index buffer offset, ignored */
2114 ADVANCE_BATCH(batch);
2118 gen6_render_emit_states(VADriverContextP ctx, int kernel)
2120 struct i965_driver_data *i965 = i965_driver_data(ctx);
2121 struct intel_batchbuffer *batch = i965->batch;
2123 intel_batchbuffer_start_atomic(batch, 0x1000);
2124 intel_batchbuffer_emit_mi_flush(batch);
2125 gen6_emit_invarient_states(ctx);
2126 gen6_emit_state_base_address(ctx);
2127 gen6_emit_viewport_state_pointers(ctx);
2129 gen6_emit_cc_state_pointers(ctx);
2130 gen6_emit_sampler_state_pointers(ctx);
2131 gen6_emit_vs_state(ctx);
2132 gen6_emit_gs_state(ctx);
2133 gen6_emit_clip_state(ctx);
2134 gen6_emit_sf_state(ctx);
2135 gen6_emit_wm_state(ctx, kernel);
2136 gen6_emit_binding_table(ctx);
2137 gen6_emit_depth_buffer_state(ctx);
2138 gen6_emit_drawing_rectangle(ctx);
2139 gen6_emit_vertex_element_state(ctx);
2140 gen6_emit_vertices(ctx);
2141 intel_batchbuffer_end_atomic(batch);
2145 gen6_render_put_surface(
2146 VADriverContextP ctx,
2147 VASurfaceID surface,
2148 const VARectangle *src_rect,
2149 const VARectangle *dst_rect,
2153 struct i965_driver_data *i965 = i965_driver_data(ctx);
2154 struct intel_batchbuffer *batch = i965->batch;
2156 gen6_render_initialize(ctx);
2157 gen6_render_setup_states(ctx, surface, src_rect, dst_rect, flags);
2158 i965_clear_dest_region(ctx);
2159 gen6_render_emit_states(ctx, PS_KERNEL);
2160 intel_batchbuffer_flush(batch);
2164 gen6_subpicture_render_blend_state(VADriverContextP ctx)
2166 struct i965_driver_data *i965 = i965_driver_data(ctx);
2167 struct i965_render_state *render_state = &i965->render_state;
2168 struct gen6_blend_state *blend_state;
2170 dri_bo_unmap(render_state->cc.state);
2171 dri_bo_map(render_state->cc.blend, 1);
2172 assert(render_state->cc.blend->virtual);
2173 blend_state = render_state->cc.blend->virtual;
2174 memset(blend_state, 0, sizeof(*blend_state));
2175 blend_state->blend0.dest_blend_factor = I965_BLENDFACTOR_INV_SRC_ALPHA;
2176 blend_state->blend0.source_blend_factor = I965_BLENDFACTOR_SRC_ALPHA;
2177 blend_state->blend0.blend_func = I965_BLENDFUNCTION_ADD;
2178 blend_state->blend0.blend_enable = 1;
2179 blend_state->blend1.post_blend_clamp_enable = 1;
2180 blend_state->blend1.pre_blend_clamp_enable = 1;
2181 blend_state->blend1.clamp_range = 0; /* clamp range [0, 1] */
2182 dri_bo_unmap(render_state->cc.blend);
2186 gen6_subpicture_render_setup_states(
2187 VADriverContextP ctx,
2188 VASurfaceID surface,
2189 const VARectangle *src_rect,
2190 const VARectangle *dst_rect
2193 i965_render_dest_surface_state(ctx, 0);
2194 i965_subpic_render_src_surfaces_state(ctx, surface);
2195 i965_render_sampler(ctx);
2196 i965_render_cc_viewport(ctx);
2197 gen6_render_color_calc_state(ctx);
2198 gen6_subpicture_render_blend_state(ctx);
2199 gen6_render_depth_stencil_state(ctx);
2200 i965_subpic_render_upload_vertex(ctx, surface, dst_rect);
2204 gen6_render_put_subpicture(
2205 VADriverContextP ctx,
2206 VASurfaceID surface,
2207 const VARectangle *src_rect,
2208 const VARectangle *dst_rect
2211 struct i965_driver_data *i965 = i965_driver_data(ctx);
2212 struct intel_batchbuffer *batch = i965->batch;
2213 struct object_surface *obj_surface = SURFACE(surface);
2214 struct object_subpic *obj_subpic = SUBPIC(obj_surface->subpic);
2217 gen6_render_initialize(ctx);
2218 gen6_subpicture_render_setup_states(ctx, surface, src_rect, dst_rect);
2219 gen6_render_emit_states(ctx, PS_SUBPIC_KERNEL);
2220 i965_render_upload_image_palette(ctx, obj_subpic->image, 0xff);
2221 intel_batchbuffer_flush(batch);
2228 gen7_render_initialize(VADriverContextP ctx)
2230 struct i965_driver_data *i965 = i965_driver_data(ctx);
2231 struct i965_render_state *render_state = &i965->render_state;
2235 dri_bo_unreference(render_state->vb.vertex_buffer);
2236 bo = dri_bo_alloc(i965->intel.bufmgr,
2241 render_state->vb.vertex_buffer = bo;
2244 dri_bo_unreference(render_state->wm.surface_state_binding_table_bo);
2245 bo = dri_bo_alloc(i965->intel.bufmgr,
2246 "surface state & binding table",
2247 (SURFACE_STATE_PADDED_SIZE + sizeof(unsigned int)) * MAX_RENDER_SURFACES,
2250 render_state->wm.surface_state_binding_table_bo = bo;
2252 dri_bo_unreference(render_state->wm.sampler);
2253 bo = dri_bo_alloc(i965->intel.bufmgr,
2255 MAX_SAMPLERS * sizeof(struct gen7_sampler_state),
2258 render_state->wm.sampler = bo;
2259 render_state->wm.sampler_count = 0;
2261 /* COLOR CALCULATOR */
2262 dri_bo_unreference(render_state->cc.state);
2263 bo = dri_bo_alloc(i965->intel.bufmgr,
2265 sizeof(struct gen6_color_calc_state),
2268 render_state->cc.state = bo;
2271 dri_bo_unreference(render_state->cc.viewport);
2272 bo = dri_bo_alloc(i965->intel.bufmgr,
2274 sizeof(struct i965_cc_viewport),
2277 render_state->cc.viewport = bo;
2280 dri_bo_unreference(render_state->cc.blend);
2281 bo = dri_bo_alloc(i965->intel.bufmgr,
2283 sizeof(struct gen6_blend_state),
2286 render_state->cc.blend = bo;
2288 /* DEPTH & STENCIL STATE */
2289 dri_bo_unreference(render_state->cc.depth_stencil);
2290 bo = dri_bo_alloc(i965->intel.bufmgr,
2291 "depth & stencil state",
2292 sizeof(struct gen6_depth_stencil_state),
2295 render_state->cc.depth_stencil = bo;
2299 gen7_render_color_calc_state(VADriverContextP ctx)
2301 struct i965_driver_data *i965 = i965_driver_data(ctx);
2302 struct i965_render_state *render_state = &i965->render_state;
2303 struct gen6_color_calc_state *color_calc_state;
2305 dri_bo_map(render_state->cc.state, 1);
2306 assert(render_state->cc.state->virtual);
2307 color_calc_state = render_state->cc.state->virtual;
2308 memset(color_calc_state, 0, sizeof(*color_calc_state));
2309 color_calc_state->constant_r = 1.0;
2310 color_calc_state->constant_g = 0.0;
2311 color_calc_state->constant_b = 1.0;
2312 color_calc_state->constant_a = 1.0;
2313 dri_bo_unmap(render_state->cc.state);
2317 gen7_render_blend_state(VADriverContextP ctx)
2319 struct i965_driver_data *i965 = i965_driver_data(ctx);
2320 struct i965_render_state *render_state = &i965->render_state;
2321 struct gen6_blend_state *blend_state;
2323 dri_bo_map(render_state->cc.blend, 1);
2324 assert(render_state->cc.blend->virtual);
2325 blend_state = render_state->cc.blend->virtual;
2326 memset(blend_state, 0, sizeof(*blend_state));
2327 blend_state->blend1.logic_op_enable = 1;
2328 blend_state->blend1.logic_op_func = 0xc;
2329 blend_state->blend1.pre_blend_clamp_enable = 1;
2330 dri_bo_unmap(render_state->cc.blend);
2334 gen7_render_depth_stencil_state(VADriverContextP ctx)
2336 struct i965_driver_data *i965 = i965_driver_data(ctx);
2337 struct i965_render_state *render_state = &i965->render_state;
2338 struct gen6_depth_stencil_state *depth_stencil_state;
2340 dri_bo_map(render_state->cc.depth_stencil, 1);
2341 assert(render_state->cc.depth_stencil->virtual);
2342 depth_stencil_state = render_state->cc.depth_stencil->virtual;
2343 memset(depth_stencil_state, 0, sizeof(*depth_stencil_state));
2344 dri_bo_unmap(render_state->cc.depth_stencil);
2348 gen7_render_sampler(VADriverContextP ctx)
2350 struct i965_driver_data *i965 = i965_driver_data(ctx);
2351 struct i965_render_state *render_state = &i965->render_state;
2352 struct gen7_sampler_state *sampler_state;
2355 assert(render_state->wm.sampler_count > 0);
2356 assert(render_state->wm.sampler_count <= MAX_SAMPLERS);
2358 dri_bo_map(render_state->wm.sampler, 1);
2359 assert(render_state->wm.sampler->virtual);
2360 sampler_state = render_state->wm.sampler->virtual;
2361 for (i = 0; i < render_state->wm.sampler_count; i++) {
2362 memset(sampler_state, 0, sizeof(*sampler_state));
2363 sampler_state->ss0.min_filter = I965_MAPFILTER_LINEAR;
2364 sampler_state->ss0.mag_filter = I965_MAPFILTER_LINEAR;
2365 sampler_state->ss3.r_wrap_mode = I965_TEXCOORDMODE_CLAMP;
2366 sampler_state->ss3.s_wrap_mode = I965_TEXCOORDMODE_CLAMP;
2367 sampler_state->ss3.t_wrap_mode = I965_TEXCOORDMODE_CLAMP;
2371 dri_bo_unmap(render_state->wm.sampler);
2375 gen7_render_setup_states(
2376 VADriverContextP ctx,
2377 VASurfaceID surface,
2378 const VARectangle *src_rect,
2379 const VARectangle *dst_rect,
2383 i965_render_dest_surface_state(ctx, 0);
2384 i965_render_src_surfaces_state(ctx, surface, flags);
2385 gen7_render_sampler(ctx);
2386 i965_render_cc_viewport(ctx);
2387 gen7_render_color_calc_state(ctx);
2388 gen7_render_blend_state(ctx);
2389 gen7_render_depth_stencil_state(ctx);
2390 i965_render_upload_constants(ctx, surface);
2391 i965_render_upload_vertex(ctx, surface, src_rect, dst_rect);
2395 gen7_emit_invarient_states(VADriverContextP ctx)
2397 struct i965_driver_data *i965 = i965_driver_data(ctx);
2398 struct intel_batchbuffer *batch = i965->batch;
2400 BEGIN_BATCH(batch, 1);
2401 OUT_BATCH(batch, CMD_PIPELINE_SELECT | PIPELINE_SELECT_3D);
2402 ADVANCE_BATCH(batch);
2404 BEGIN_BATCH(batch, 4);
2405 OUT_BATCH(batch, GEN6_3DSTATE_MULTISAMPLE | (4 - 2));
2406 OUT_BATCH(batch, GEN6_3DSTATE_MULTISAMPLE_PIXEL_LOCATION_CENTER |
2407 GEN6_3DSTATE_MULTISAMPLE_NUMSAMPLES_1); /* 1 sample/pixel */
2408 OUT_BATCH(batch, 0);
2409 OUT_BATCH(batch, 0);
2410 ADVANCE_BATCH(batch);
2412 BEGIN_BATCH(batch, 2);
2413 OUT_BATCH(batch, GEN6_3DSTATE_SAMPLE_MASK | (2 - 2));
2414 OUT_BATCH(batch, 1);
2415 ADVANCE_BATCH(batch);
2417 /* Set system instruction pointer */
2418 BEGIN_BATCH(batch, 2);
2419 OUT_BATCH(batch, CMD_STATE_SIP | 0);
2420 OUT_BATCH(batch, 0);
2421 ADVANCE_BATCH(batch);
2425 gen7_emit_state_base_address(VADriverContextP ctx)
2427 struct i965_driver_data *i965 = i965_driver_data(ctx);
2428 struct intel_batchbuffer *batch = i965->batch;
2429 struct i965_render_state *render_state = &i965->render_state;
2431 OUT_BATCH(batch, CMD_STATE_BASE_ADDRESS | (10 - 2));
2432 OUT_BATCH(batch, BASE_ADDRESS_MODIFY); /* General state base address */
2433 OUT_RELOC(batch, render_state->wm.surface_state_binding_table_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, BASE_ADDRESS_MODIFY); /* Surface state base address */
2434 OUT_BATCH(batch, BASE_ADDRESS_MODIFY); /* Dynamic state base address */
2435 OUT_BATCH(batch, BASE_ADDRESS_MODIFY); /* Indirect object base address */
2436 OUT_BATCH(batch, BASE_ADDRESS_MODIFY); /* Instruction base address */
2437 OUT_BATCH(batch, BASE_ADDRESS_MODIFY); /* General state upper bound */
2438 OUT_BATCH(batch, BASE_ADDRESS_MODIFY); /* Dynamic state upper bound */
2439 OUT_BATCH(batch, BASE_ADDRESS_MODIFY); /* Indirect object upper bound */
2440 OUT_BATCH(batch, BASE_ADDRESS_MODIFY); /* Instruction access upper bound */
2444 gen7_emit_viewport_state_pointers(VADriverContextP ctx)
2446 struct i965_driver_data *i965 = i965_driver_data(ctx);
2447 struct intel_batchbuffer *batch = i965->batch;
2448 struct i965_render_state *render_state = &i965->render_state;
2450 BEGIN_BATCH(batch, 2);
2451 OUT_BATCH(batch, GEN7_3DSTATE_VIEWPORT_STATE_POINTERS_CC | (2 - 2));
2453 render_state->cc.viewport,
2454 I915_GEM_DOMAIN_INSTRUCTION, 0,
2456 ADVANCE_BATCH(batch);
2458 BEGIN_BATCH(batch, 2);
2459 OUT_BATCH(batch, GEN7_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CL | (2 - 2));
2460 OUT_BATCH(batch, 0);
2461 ADVANCE_BATCH(batch);
2465 * URB layout on GEN7
2466 * ----------------------------------------
2467 * | PS Push Constants (8KB) | VS entries |
2468 * ----------------------------------------
2471 gen7_emit_urb(VADriverContextP ctx)
2473 struct i965_driver_data *i965 = i965_driver_data(ctx);
2474 struct intel_batchbuffer *batch = i965->batch;
2475 unsigned int num_urb_entries = 32;
2477 if (IS_HASWELL(i965->intel.device_id))
2478 num_urb_entries = 64;
2480 BEGIN_BATCH(batch, 2);
2481 OUT_BATCH(batch, GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_PS | (2 - 2));
2482 OUT_BATCH(batch, 8); /* in 1KBs */
2483 ADVANCE_BATCH(batch);
2485 BEGIN_BATCH(batch, 2);
2486 OUT_BATCH(batch, GEN7_3DSTATE_URB_VS | (2 - 2));
2488 (num_urb_entries << GEN7_URB_ENTRY_NUMBER_SHIFT) |
2489 (2 - 1) << GEN7_URB_ENTRY_SIZE_SHIFT |
2490 (1 << GEN7_URB_STARTING_ADDRESS_SHIFT));
2491 ADVANCE_BATCH(batch);
2493 BEGIN_BATCH(batch, 2);
2494 OUT_BATCH(batch, GEN7_3DSTATE_URB_GS | (2 - 2));
2496 (0 << GEN7_URB_ENTRY_SIZE_SHIFT) |
2497 (1 << GEN7_URB_STARTING_ADDRESS_SHIFT));
2498 ADVANCE_BATCH(batch);
2500 BEGIN_BATCH(batch, 2);
2501 OUT_BATCH(batch, GEN7_3DSTATE_URB_HS | (2 - 2));
2503 (0 << GEN7_URB_ENTRY_SIZE_SHIFT) |
2504 (2 << GEN7_URB_STARTING_ADDRESS_SHIFT));
2505 ADVANCE_BATCH(batch);
2507 BEGIN_BATCH(batch, 2);
2508 OUT_BATCH(batch, GEN7_3DSTATE_URB_DS | (2 - 2));
2510 (0 << GEN7_URB_ENTRY_SIZE_SHIFT) |
2511 (2 << GEN7_URB_STARTING_ADDRESS_SHIFT));
2512 ADVANCE_BATCH(batch);
2516 gen7_emit_cc_state_pointers(VADriverContextP ctx)
2518 struct i965_driver_data *i965 = i965_driver_data(ctx);
2519 struct intel_batchbuffer *batch = i965->batch;
2520 struct i965_render_state *render_state = &i965->render_state;
2522 BEGIN_BATCH(batch, 2);
2523 OUT_BATCH(batch, GEN6_3DSTATE_CC_STATE_POINTERS | (2 - 2));
2525 render_state->cc.state,
2526 I915_GEM_DOMAIN_INSTRUCTION, 0,
2528 ADVANCE_BATCH(batch);
2530 BEGIN_BATCH(batch, 2);
2531 OUT_BATCH(batch, GEN7_3DSTATE_BLEND_STATE_POINTERS | (2 - 2));
2533 render_state->cc.blend,
2534 I915_GEM_DOMAIN_INSTRUCTION, 0,
2536 ADVANCE_BATCH(batch);
2538 BEGIN_BATCH(batch, 2);
2539 OUT_BATCH(batch, GEN7_3DSTATE_DEPTH_STENCIL_STATE_POINTERS | (2 - 2));
2541 render_state->cc.depth_stencil,
2542 I915_GEM_DOMAIN_INSTRUCTION, 0,
2544 ADVANCE_BATCH(batch);
2548 gen7_emit_sampler_state_pointers(VADriverContextP ctx)
2550 struct i965_driver_data *i965 = i965_driver_data(ctx);
2551 struct intel_batchbuffer *batch = i965->batch;
2552 struct i965_render_state *render_state = &i965->render_state;
2554 BEGIN_BATCH(batch, 2);
2555 OUT_BATCH(batch, GEN7_3DSTATE_SAMPLER_STATE_POINTERS_PS | (2 - 2));
2557 render_state->wm.sampler,
2558 I915_GEM_DOMAIN_INSTRUCTION, 0,
2560 ADVANCE_BATCH(batch);
2564 gen7_emit_binding_table(VADriverContextP ctx)
2566 struct i965_driver_data *i965 = i965_driver_data(ctx);
2567 struct intel_batchbuffer *batch = i965->batch;
2569 BEGIN_BATCH(batch, 2);
2570 OUT_BATCH(batch, GEN7_3DSTATE_BINDING_TABLE_POINTERS_PS | (2 - 2));
2571 OUT_BATCH(batch, BINDING_TABLE_OFFSET);
2572 ADVANCE_BATCH(batch);
2576 gen7_emit_depth_buffer_state(VADriverContextP ctx)
2578 struct i965_driver_data *i965 = i965_driver_data(ctx);
2579 struct intel_batchbuffer *batch = i965->batch;
2581 BEGIN_BATCH(batch, 7);
2582 OUT_BATCH(batch, GEN7_3DSTATE_DEPTH_BUFFER | (7 - 2));
2584 (I965_DEPTHFORMAT_D32_FLOAT << 18) |
2585 (I965_SURFACE_NULL << 29));
2586 OUT_BATCH(batch, 0);
2587 OUT_BATCH(batch, 0);
2588 OUT_BATCH(batch, 0);
2589 OUT_BATCH(batch, 0);
2590 OUT_BATCH(batch, 0);
2591 ADVANCE_BATCH(batch);
2593 BEGIN_BATCH(batch, 3);
2594 OUT_BATCH(batch, GEN7_3DSTATE_CLEAR_PARAMS | (3 - 2));
2595 OUT_BATCH(batch, 0);
2596 OUT_BATCH(batch, 0);
2597 ADVANCE_BATCH(batch);
2601 gen7_emit_drawing_rectangle(VADriverContextP ctx)
2603 i965_render_drawing_rectangle(ctx);
2607 gen7_emit_vs_state(VADriverContextP ctx)
2609 struct i965_driver_data *i965 = i965_driver_data(ctx);
2610 struct intel_batchbuffer *batch = i965->batch;
2612 /* disable VS constant buffer */
2613 OUT_BATCH(batch, GEN6_3DSTATE_CONSTANT_VS | (7 - 2));
2614 OUT_BATCH(batch, 0);
2615 OUT_BATCH(batch, 0);
2616 OUT_BATCH(batch, 0);
2617 OUT_BATCH(batch, 0);
2618 OUT_BATCH(batch, 0);
2619 OUT_BATCH(batch, 0);
2621 OUT_BATCH(batch, GEN6_3DSTATE_VS | (6 - 2));
2622 OUT_BATCH(batch, 0); /* without VS kernel */
2623 OUT_BATCH(batch, 0);
2624 OUT_BATCH(batch, 0);
2625 OUT_BATCH(batch, 0);
2626 OUT_BATCH(batch, 0); /* pass-through */
2630 gen7_emit_bypass_state(VADriverContextP ctx)
2632 struct i965_driver_data *i965 = i965_driver_data(ctx);
2633 struct intel_batchbuffer *batch = i965->batch;
2636 BEGIN_BATCH(batch, 7);
2637 OUT_BATCH(batch, GEN6_3DSTATE_CONSTANT_GS | (7 - 2));
2638 OUT_BATCH(batch, 0);
2639 OUT_BATCH(batch, 0);
2640 OUT_BATCH(batch, 0);
2641 OUT_BATCH(batch, 0);
2642 OUT_BATCH(batch, 0);
2643 OUT_BATCH(batch, 0);
2644 ADVANCE_BATCH(batch);
2646 BEGIN_BATCH(batch, 7);
2647 OUT_BATCH(batch, GEN6_3DSTATE_GS | (7 - 2));
2648 OUT_BATCH(batch, 0); /* without GS kernel */
2649 OUT_BATCH(batch, 0);
2650 OUT_BATCH(batch, 0);
2651 OUT_BATCH(batch, 0);
2652 OUT_BATCH(batch, 0);
2653 OUT_BATCH(batch, 0); /* pass-through */
2654 ADVANCE_BATCH(batch);
2656 BEGIN_BATCH(batch, 2);
2657 OUT_BATCH(batch, GEN7_3DSTATE_BINDING_TABLE_POINTERS_GS | (2 - 2));
2658 OUT_BATCH(batch, 0);
2659 ADVANCE_BATCH(batch);
2662 BEGIN_BATCH(batch, 7);
2663 OUT_BATCH(batch, GEN7_3DSTATE_CONSTANT_HS | (7 - 2));
2664 OUT_BATCH(batch, 0);
2665 OUT_BATCH(batch, 0);
2666 OUT_BATCH(batch, 0);
2667 OUT_BATCH(batch, 0);
2668 OUT_BATCH(batch, 0);
2669 OUT_BATCH(batch, 0);
2670 ADVANCE_BATCH(batch);
2672 BEGIN_BATCH(batch, 7);
2673 OUT_BATCH(batch, GEN7_3DSTATE_HS | (7 - 2));
2674 OUT_BATCH(batch, 0);
2675 OUT_BATCH(batch, 0);
2676 OUT_BATCH(batch, 0);
2677 OUT_BATCH(batch, 0);
2678 OUT_BATCH(batch, 0);
2679 OUT_BATCH(batch, 0);
2680 ADVANCE_BATCH(batch);
2682 BEGIN_BATCH(batch, 2);
2683 OUT_BATCH(batch, GEN7_3DSTATE_BINDING_TABLE_POINTERS_HS | (2 - 2));
2684 OUT_BATCH(batch, 0);
2685 ADVANCE_BATCH(batch);
2688 BEGIN_BATCH(batch, 4);
2689 OUT_BATCH(batch, GEN7_3DSTATE_TE | (4 - 2));
2690 OUT_BATCH(batch, 0);
2691 OUT_BATCH(batch, 0);
2692 OUT_BATCH(batch, 0);
2693 ADVANCE_BATCH(batch);
2696 BEGIN_BATCH(batch, 7);
2697 OUT_BATCH(batch, GEN7_3DSTATE_CONSTANT_DS | (7 - 2));
2698 OUT_BATCH(batch, 0);
2699 OUT_BATCH(batch, 0);
2700 OUT_BATCH(batch, 0);
2701 OUT_BATCH(batch, 0);
2702 OUT_BATCH(batch, 0);
2703 OUT_BATCH(batch, 0);
2704 ADVANCE_BATCH(batch);
2706 BEGIN_BATCH(batch, 6);
2707 OUT_BATCH(batch, GEN7_3DSTATE_DS | (6 - 2));
2708 OUT_BATCH(batch, 0);
2709 OUT_BATCH(batch, 0);
2710 OUT_BATCH(batch, 0);
2711 OUT_BATCH(batch, 0);
2712 OUT_BATCH(batch, 0);
2713 ADVANCE_BATCH(batch);
2715 BEGIN_BATCH(batch, 2);
2716 OUT_BATCH(batch, GEN7_3DSTATE_BINDING_TABLE_POINTERS_DS | (2 - 2));
2717 OUT_BATCH(batch, 0);
2718 ADVANCE_BATCH(batch);
2720 /* Disable STREAMOUT */
2721 BEGIN_BATCH(batch, 3);
2722 OUT_BATCH(batch, GEN7_3DSTATE_STREAMOUT | (3 - 2));
2723 OUT_BATCH(batch, 0);
2724 OUT_BATCH(batch, 0);
2725 ADVANCE_BATCH(batch);
2729 gen7_emit_clip_state(VADriverContextP ctx)
2731 struct i965_driver_data *i965 = i965_driver_data(ctx);
2732 struct intel_batchbuffer *batch = i965->batch;
2734 OUT_BATCH(batch, GEN6_3DSTATE_CLIP | (4 - 2));
2735 OUT_BATCH(batch, 0);
2736 OUT_BATCH(batch, 0); /* pass-through */
2737 OUT_BATCH(batch, 0);
2741 gen7_emit_sf_state(VADriverContextP ctx)
2743 struct i965_driver_data *i965 = i965_driver_data(ctx);
2744 struct intel_batchbuffer *batch = i965->batch;
2746 BEGIN_BATCH(batch, 14);
2747 OUT_BATCH(batch, GEN7_3DSTATE_SBE | (14 - 2));
2749 (1 << GEN7_SBE_NUM_OUTPUTS_SHIFT) |
2750 (1 << GEN7_SBE_URB_ENTRY_READ_LENGTH_SHIFT) |
2751 (0 << GEN7_SBE_URB_ENTRY_READ_OFFSET_SHIFT));
2752 OUT_BATCH(batch, 0);
2753 OUT_BATCH(batch, 0);
2754 OUT_BATCH(batch, 0); /* DW4 */
2755 OUT_BATCH(batch, 0);
2756 OUT_BATCH(batch, 0);
2757 OUT_BATCH(batch, 0);
2758 OUT_BATCH(batch, 0);
2759 OUT_BATCH(batch, 0); /* DW9 */
2760 OUT_BATCH(batch, 0);
2761 OUT_BATCH(batch, 0);
2762 OUT_BATCH(batch, 0);
2763 OUT_BATCH(batch, 0);
2764 ADVANCE_BATCH(batch);
2766 BEGIN_BATCH(batch, 7);
2767 OUT_BATCH(batch, GEN6_3DSTATE_SF | (7 - 2));
2768 OUT_BATCH(batch, 0);
2769 OUT_BATCH(batch, GEN6_3DSTATE_SF_CULL_NONE);
2770 OUT_BATCH(batch, 2 << GEN6_3DSTATE_SF_TRIFAN_PROVOKE_SHIFT);
2771 OUT_BATCH(batch, 0);
2772 OUT_BATCH(batch, 0);
2773 OUT_BATCH(batch, 0);
2774 ADVANCE_BATCH(batch);
2778 gen7_emit_wm_state(VADriverContextP ctx, int kernel)
2780 struct i965_driver_data *i965 = i965_driver_data(ctx);
2781 struct intel_batchbuffer *batch = i965->batch;
2782 struct i965_render_state *render_state = &i965->render_state;
2783 unsigned int max_threads_shift = GEN7_PS_MAX_THREADS_SHIFT_IVB;
2784 unsigned int num_samples = 0;
2786 if (IS_HASWELL(i965->intel.device_id)) {
2787 max_threads_shift = GEN7_PS_MAX_THREADS_SHIFT_HSW;
2788 num_samples = 1 << GEN7_PS_SAMPLE_MASK_SHIFT_HSW;
2791 BEGIN_BATCH(batch, 3);
2792 OUT_BATCH(batch, GEN6_3DSTATE_WM | (3 - 2));
2794 GEN7_WM_DISPATCH_ENABLE |
2795 GEN7_WM_PERSPECTIVE_PIXEL_BARYCENTRIC);
2796 OUT_BATCH(batch, 0);
2797 ADVANCE_BATCH(batch);
2799 BEGIN_BATCH(batch, 7);
2800 OUT_BATCH(batch, GEN6_3DSTATE_CONSTANT_PS | (7 - 2));
2801 OUT_BATCH(batch, 1);
2802 OUT_BATCH(batch, 0);
2804 render_state->curbe.bo,
2805 I915_GEM_DOMAIN_INSTRUCTION, 0,
2807 OUT_BATCH(batch, 0);
2808 OUT_BATCH(batch, 0);
2809 OUT_BATCH(batch, 0);
2810 ADVANCE_BATCH(batch);
2812 BEGIN_BATCH(batch, 8);
2813 OUT_BATCH(batch, GEN7_3DSTATE_PS | (8 - 2));
2815 render_state->render_kernels[kernel].bo,
2816 I915_GEM_DOMAIN_INSTRUCTION, 0,
2819 (1 << GEN7_PS_SAMPLER_COUNT_SHIFT) |
2820 (5 << GEN7_PS_BINDING_TABLE_ENTRY_COUNT_SHIFT));
2821 OUT_BATCH(batch, 0); /* scratch space base offset */
2823 ((86 - 1) << max_threads_shift) | num_samples |
2824 GEN7_PS_PUSH_CONSTANT_ENABLE |
2825 GEN7_PS_ATTRIBUTE_ENABLE |
2826 GEN7_PS_16_DISPATCH_ENABLE);
2828 (6 << GEN7_PS_DISPATCH_START_GRF_SHIFT_0));
2829 OUT_BATCH(batch, 0); /* kernel 1 pointer */
2830 OUT_BATCH(batch, 0); /* kernel 2 pointer */
2831 ADVANCE_BATCH(batch);
2835 gen7_emit_vertex_element_state(VADriverContextP ctx)
2837 struct i965_driver_data *i965 = i965_driver_data(ctx);
2838 struct intel_batchbuffer *batch = i965->batch;
2840 /* Set up our vertex elements, sourced from the single vertex buffer. */
2841 OUT_BATCH(batch, CMD_VERTEX_ELEMENTS | (5 - 2));
2842 /* offset 0: X,Y -> {X, Y, 1.0, 1.0} */
2843 OUT_BATCH(batch, (0 << GEN6_VE0_VERTEX_BUFFER_INDEX_SHIFT) |
2845 (I965_SURFACEFORMAT_R32G32_FLOAT << VE0_FORMAT_SHIFT) |
2846 (0 << VE0_OFFSET_SHIFT));
2847 OUT_BATCH(batch, (I965_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT) |
2848 (I965_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT) |
2849 (I965_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_2_SHIFT) |
2850 (I965_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT));
2851 /* offset 8: S0, T0 -> {S0, T0, 1.0, 1.0} */
2852 OUT_BATCH(batch, (0 << GEN6_VE0_VERTEX_BUFFER_INDEX_SHIFT) |
2854 (I965_SURFACEFORMAT_R32G32_FLOAT << VE0_FORMAT_SHIFT) |
2855 (8 << VE0_OFFSET_SHIFT));
2856 OUT_BATCH(batch, (I965_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT) |
2857 (I965_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT) |
2858 (I965_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_2_SHIFT) |
2859 (I965_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT));
2863 gen7_emit_vertices(VADriverContextP ctx)
2865 struct i965_driver_data *i965 = i965_driver_data(ctx);
2866 struct intel_batchbuffer *batch = i965->batch;
2867 struct i965_render_state *render_state = &i965->render_state;
2869 BEGIN_BATCH(batch, 5);
2870 OUT_BATCH(batch, CMD_VERTEX_BUFFERS | (5 - 2));
2872 (0 << GEN6_VB0_BUFFER_INDEX_SHIFT) |
2873 GEN6_VB0_VERTEXDATA |
2874 GEN7_VB0_ADDRESS_MODIFYENABLE |
2875 ((4 * 4) << VB0_BUFFER_PITCH_SHIFT));
2876 OUT_RELOC(batch, render_state->vb.vertex_buffer, I915_GEM_DOMAIN_VERTEX, 0, 0);
2877 OUT_RELOC(batch, render_state->vb.vertex_buffer, I915_GEM_DOMAIN_VERTEX, 0, 12 * 4);
2878 OUT_BATCH(batch, 0);
2879 ADVANCE_BATCH(batch);
2881 BEGIN_BATCH(batch, 7);
2882 OUT_BATCH(batch, CMD_3DPRIMITIVE | (7 - 2));
2885 GEN7_3DPRIM_VERTEXBUFFER_ACCESS_SEQUENTIAL);
2886 OUT_BATCH(batch, 3); /* vertex count per instance */
2887 OUT_BATCH(batch, 0); /* start vertex offset */
2888 OUT_BATCH(batch, 1); /* single instance */
2889 OUT_BATCH(batch, 0); /* start instance location */
2890 OUT_BATCH(batch, 0);
2891 ADVANCE_BATCH(batch);
2895 gen7_render_emit_states(VADriverContextP ctx, int kernel)
2897 struct i965_driver_data *i965 = i965_driver_data(ctx);
2898 struct intel_batchbuffer *batch = i965->batch;
2900 intel_batchbuffer_start_atomic(batch, 0x1000);
2901 intel_batchbuffer_emit_mi_flush(batch);
2902 gen7_emit_invarient_states(ctx);
2903 gen7_emit_state_base_address(ctx);
2904 gen7_emit_viewport_state_pointers(ctx);
2906 gen7_emit_cc_state_pointers(ctx);
2907 gen7_emit_sampler_state_pointers(ctx);
2908 gen7_emit_bypass_state(ctx);
2909 gen7_emit_vs_state(ctx);
2910 gen7_emit_clip_state(ctx);
2911 gen7_emit_sf_state(ctx);
2912 gen7_emit_wm_state(ctx, kernel);
2913 gen7_emit_binding_table(ctx);
2914 gen7_emit_depth_buffer_state(ctx);
2915 gen7_emit_drawing_rectangle(ctx);
2916 gen7_emit_vertex_element_state(ctx);
2917 gen7_emit_vertices(ctx);
2918 intel_batchbuffer_end_atomic(batch);
2922 gen7_render_put_surface(
2923 VADriverContextP ctx,
2924 VASurfaceID surface,
2925 const VARectangle *src_rect,
2926 const VARectangle *dst_rect,
2930 struct i965_driver_data *i965 = i965_driver_data(ctx);
2931 struct intel_batchbuffer *batch = i965->batch;
2933 gen7_render_initialize(ctx);
2934 gen7_render_setup_states(ctx, surface, src_rect, dst_rect, flags);
2935 i965_clear_dest_region(ctx);
2936 gen7_render_emit_states(ctx, PS_KERNEL);
2937 intel_batchbuffer_flush(batch);
2941 gen7_subpicture_render_blend_state(VADriverContextP ctx)
2943 struct i965_driver_data *i965 = i965_driver_data(ctx);
2944 struct i965_render_state *render_state = &i965->render_state;
2945 struct gen6_blend_state *blend_state;
2947 dri_bo_unmap(render_state->cc.state);
2948 dri_bo_map(render_state->cc.blend, 1);
2949 assert(render_state->cc.blend->virtual);
2950 blend_state = render_state->cc.blend->virtual;
2951 memset(blend_state, 0, sizeof(*blend_state));
2952 blend_state->blend0.dest_blend_factor = I965_BLENDFACTOR_INV_SRC_ALPHA;
2953 blend_state->blend0.source_blend_factor = I965_BLENDFACTOR_SRC_ALPHA;
2954 blend_state->blend0.blend_func = I965_BLENDFUNCTION_ADD;
2955 blend_state->blend0.blend_enable = 1;
2956 blend_state->blend1.post_blend_clamp_enable = 1;
2957 blend_state->blend1.pre_blend_clamp_enable = 1;
2958 blend_state->blend1.clamp_range = 0; /* clamp range [0, 1] */
2959 dri_bo_unmap(render_state->cc.blend);
2963 gen7_subpicture_render_setup_states(
2964 VADriverContextP ctx,
2965 VASurfaceID surface,
2966 const VARectangle *src_rect,
2967 const VARectangle *dst_rect
2970 i965_render_dest_surface_state(ctx, 0);
2971 i965_subpic_render_src_surfaces_state(ctx, surface);
2972 i965_render_sampler(ctx);
2973 i965_render_cc_viewport(ctx);
2974 gen7_render_color_calc_state(ctx);
2975 gen7_subpicture_render_blend_state(ctx);
2976 gen7_render_depth_stencil_state(ctx);
2977 i965_subpic_render_upload_vertex(ctx, surface, dst_rect);
2981 gen7_render_put_subpicture(
2982 VADriverContextP ctx,
2983 VASurfaceID surface,
2984 const VARectangle *src_rect,
2985 const VARectangle *dst_rect
2988 struct i965_driver_data *i965 = i965_driver_data(ctx);
2989 struct intel_batchbuffer *batch = i965->batch;
2990 struct object_surface *obj_surface = SURFACE(surface);
2991 struct object_subpic *obj_subpic = SUBPIC(obj_surface->subpic);
2994 gen7_render_initialize(ctx);
2995 gen7_subpicture_render_setup_states(ctx, surface, src_rect, dst_rect);
2996 gen7_render_emit_states(ctx, PS_SUBPIC_KERNEL);
2997 i965_render_upload_image_palette(ctx, obj_subpic->image, 0xff);
2998 intel_batchbuffer_flush(batch);
3006 i965_DestroySurfaces(VADriverContextP ctx,
3007 VASurfaceID *surface_list,
3010 intel_render_put_surface(
3011 VADriverContextP ctx,
3012 VASurfaceID surface,
3013 const VARectangle *src_rect,
3014 const VARectangle *dst_rect,
3018 struct i965_driver_data *i965 = i965_driver_data(ctx);
3019 int has_done_scaling = 0;
3020 VASurfaceID in_surface_id = surface;
3021 VASurfaceID out_surface_id = i965_post_processing(ctx, surface, src_rect, dst_rect, flags, &has_done_scaling);
3023 assert((!has_done_scaling) || (out_surface_id != VA_INVALID_ID));
3025 if (out_surface_id != VA_INVALID_ID)
3026 in_surface_id = out_surface_id;
3028 if (IS_GEN7(i965->intel.device_id))
3029 gen7_render_put_surface(ctx, in_surface_id, has_done_scaling ? dst_rect : src_rect, dst_rect, flags);
3030 else if (IS_GEN6(i965->intel.device_id))
3031 gen6_render_put_surface(ctx, in_surface_id, has_done_scaling ? dst_rect : src_rect, dst_rect, flags);
3033 i965_render_put_surface(ctx, in_surface_id, has_done_scaling ? dst_rect : src_rect, dst_rect, flags);
3035 if (in_surface_id != surface)
3036 i965_DestroySurfaces(ctx, &in_surface_id, 1);
3040 intel_render_put_subpicture(
3041 VADriverContextP ctx,
3042 VASurfaceID surface,
3043 const VARectangle *src_rect,
3044 const VARectangle *dst_rect
3047 struct i965_driver_data *i965 = i965_driver_data(ctx);
3049 if (IS_GEN7(i965->intel.device_id))
3050 gen7_render_put_subpicture(ctx, surface, src_rect, dst_rect);
3051 else if (IS_GEN6(i965->intel.device_id))
3052 gen6_render_put_subpicture(ctx, surface, src_rect, dst_rect);
3054 i965_render_put_subpicture(ctx, surface, src_rect, dst_rect);
3058 i965_render_init(VADriverContextP ctx)
3060 struct i965_driver_data *i965 = i965_driver_data(ctx);
3061 struct i965_render_state *render_state = &i965->render_state;
3065 assert(NUM_RENDER_KERNEL == (sizeof(render_kernels_gen5) /
3066 sizeof(render_kernels_gen5[0])));
3067 assert(NUM_RENDER_KERNEL == (sizeof(render_kernels_gen6) /
3068 sizeof(render_kernels_gen6[0])));
3070 if (IS_GEN7(i965->intel.device_id))
3071 memcpy(render_state->render_kernels,
3072 (IS_HASWELL(i965->intel.device_id) ? render_kernels_gen7_haswell : render_kernels_gen7),
3073 sizeof(render_state->render_kernels));
3074 else if (IS_GEN6(i965->intel.device_id))
3075 memcpy(render_state->render_kernels, render_kernels_gen6, sizeof(render_state->render_kernels));
3076 else if (IS_IRONLAKE(i965->intel.device_id))
3077 memcpy(render_state->render_kernels, render_kernels_gen5, sizeof(render_state->render_kernels));
3079 memcpy(render_state->render_kernels, render_kernels_gen4, sizeof(render_state->render_kernels));
3081 for (i = 0; i < NUM_RENDER_KERNEL; i++) {
3082 struct i965_kernel *kernel = &render_state->render_kernels[i];
3087 kernel->bo = dri_bo_alloc(i965->intel.bufmgr,
3089 kernel->size, 0x1000);
3091 dri_bo_subdata(kernel->bo, 0, kernel->size, kernel->bin);
3094 /* constant buffer */
3095 render_state->curbe.bo = dri_bo_alloc(i965->intel.bufmgr,
3098 assert(render_state->curbe.bo);
3104 i965_render_terminate(VADriverContextP ctx)
3107 struct i965_driver_data *i965 = i965_driver_data(ctx);
3108 struct i965_render_state *render_state = &i965->render_state;
3110 dri_bo_unreference(render_state->curbe.bo);
3111 render_state->curbe.bo = NULL;
3113 for (i = 0; i < NUM_RENDER_KERNEL; i++) {
3114 struct i965_kernel *kernel = &render_state->render_kernels[i];
3116 dri_bo_unreference(kernel->bo);
3120 dri_bo_unreference(render_state->vb.vertex_buffer);
3121 render_state->vb.vertex_buffer = NULL;
3122 dri_bo_unreference(render_state->vs.state);
3123 render_state->vs.state = NULL;
3124 dri_bo_unreference(render_state->sf.state);
3125 render_state->sf.state = NULL;
3126 dri_bo_unreference(render_state->wm.sampler);
3127 render_state->wm.sampler = NULL;
3128 dri_bo_unreference(render_state->wm.state);
3129 render_state->wm.state = NULL;
3130 dri_bo_unreference(render_state->wm.surface_state_binding_table_bo);
3131 dri_bo_unreference(render_state->cc.viewport);
3132 render_state->cc.viewport = NULL;
3133 dri_bo_unreference(render_state->cc.state);
3134 render_state->cc.state = NULL;
3135 dri_bo_unreference(render_state->cc.blend);
3136 render_state->cc.blend = NULL;
3137 dri_bo_unreference(render_state->cc.depth_stencil);
3138 render_state->cc.depth_stencil = NULL;
3140 if (render_state->draw_region) {
3141 dri_bo_unreference(render_state->draw_region->bo);
3142 free(render_state->draw_region);
3143 render_state->draw_region = NULL;