2 * Copyright © 2010 Intel Corporation
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5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
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9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include "compiler/glsl/ir.h"
26 #include "brw_fs_surface_builder.h"
30 using namespace brw::surface_access;
33 fs_visitor::emit_nir_code()
35 /* emit the arrays used for inputs and outputs - load/store intrinsics will
36 * be converted to reads/writes of these arrays
40 nir_emit_system_values();
42 /* get the main function and emit it */
43 nir_foreach_function(function, nir) {
44 assert(strcmp(function->name, "main") == 0);
45 assert(function->impl);
46 nir_emit_impl(function->impl);
51 fs_visitor::nir_setup_outputs()
53 if (stage == MESA_SHADER_TESS_CTRL || stage == MESA_SHADER_FRAGMENT)
56 unsigned vec4s[VARYING_SLOT_TESS_MAX] = { 0, };
58 /* Calculate the size of output registers in a separate pass, before
59 * allocating them. With ARB_enhanced_layouts, multiple output variables
60 * may occupy the same slot, but have different type sizes.
62 nir_foreach_variable(var, &nir->outputs) {
63 const int loc = var->data.driver_location;
64 const unsigned var_vec4s =
65 var->data.compact ? DIV_ROUND_UP(glsl_get_length(var->type), 4)
66 : type_size_vec4(var->type);
67 vec4s[loc] = MAX2(vec4s[loc], var_vec4s);
70 nir_foreach_variable(var, &nir->outputs) {
71 const int loc = var->data.driver_location;
72 if (outputs[loc].file == BAD_FILE) {
73 fs_reg reg = bld.vgrf(BRW_REGISTER_TYPE_F, 4 * vec4s[loc]);
74 for (unsigned i = 0; i < vec4s[loc]; i++) {
75 outputs[loc + i] = offset(reg, bld, 4 * i);
82 fs_visitor::nir_setup_uniforms()
84 /* Only the first compile gets to set up uniforms. */
85 if (push_constant_loc) {
86 assert(pull_constant_loc);
90 uniforms = nir->num_uniforms / 4;
92 if (stage == MESA_SHADER_COMPUTE) {
93 /* Add a uniform for the thread local id. It must be the last uniform
96 assert(uniforms == prog_data->nr_params);
97 uint32_t *param = brw_stage_prog_data_add_params(prog_data, 1);
98 *param = BRW_PARAM_BUILTIN_SUBGROUP_ID;
99 subgroup_id = fs_reg(UNIFORM, uniforms++, BRW_REGISTER_TYPE_UD);
104 emit_system_values_block(nir_block *block, fs_visitor *v)
108 nir_foreach_instr(instr, block) {
109 if (instr->type != nir_instr_type_intrinsic)
112 nir_intrinsic_instr *intrin = nir_instr_as_intrinsic(instr);
113 switch (intrin->intrinsic) {
114 case nir_intrinsic_load_vertex_id:
115 unreachable("should be lowered by lower_vertex_id().");
117 case nir_intrinsic_load_vertex_id_zero_base:
118 case nir_intrinsic_load_base_vertex:
119 case nir_intrinsic_load_instance_id:
120 case nir_intrinsic_load_base_instance:
121 case nir_intrinsic_load_draw_id:
122 unreachable("should be lowered by brw_nir_lower_vs_inputs().");
124 case nir_intrinsic_load_invocation_id:
125 if (v->stage == MESA_SHADER_TESS_CTRL)
127 assert(v->stage == MESA_SHADER_GEOMETRY);
128 reg = &v->nir_system_values[SYSTEM_VALUE_INVOCATION_ID];
129 if (reg->file == BAD_FILE) {
130 const fs_builder abld = v->bld.annotate("gl_InvocationID", NULL);
131 fs_reg g1(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD));
132 fs_reg iid = abld.vgrf(BRW_REGISTER_TYPE_UD, 1);
133 abld.SHR(iid, g1, brw_imm_ud(27u));
138 case nir_intrinsic_load_sample_pos:
139 assert(v->stage == MESA_SHADER_FRAGMENT);
140 reg = &v->nir_system_values[SYSTEM_VALUE_SAMPLE_POS];
141 if (reg->file == BAD_FILE)
142 *reg = *v->emit_samplepos_setup();
145 case nir_intrinsic_load_sample_id:
146 assert(v->stage == MESA_SHADER_FRAGMENT);
147 reg = &v->nir_system_values[SYSTEM_VALUE_SAMPLE_ID];
148 if (reg->file == BAD_FILE)
149 *reg = *v->emit_sampleid_setup();
152 case nir_intrinsic_load_sample_mask_in:
153 assert(v->stage == MESA_SHADER_FRAGMENT);
154 assert(v->devinfo->gen >= 7);
155 reg = &v->nir_system_values[SYSTEM_VALUE_SAMPLE_MASK_IN];
156 if (reg->file == BAD_FILE)
157 *reg = *v->emit_samplemaskin_setup();
160 case nir_intrinsic_load_work_group_id:
161 assert(v->stage == MESA_SHADER_COMPUTE);
162 reg = &v->nir_system_values[SYSTEM_VALUE_WORK_GROUP_ID];
163 if (reg->file == BAD_FILE)
164 *reg = *v->emit_cs_work_group_id_setup();
167 case nir_intrinsic_load_helper_invocation:
168 assert(v->stage == MESA_SHADER_FRAGMENT);
169 reg = &v->nir_system_values[SYSTEM_VALUE_HELPER_INVOCATION];
170 if (reg->file == BAD_FILE) {
171 const fs_builder abld =
172 v->bld.annotate("gl_HelperInvocation", NULL);
174 /* On Gen6+ (gl_HelperInvocation is only exposed on Gen7+) the
175 * pixel mask is in g1.7 of the thread payload.
177 * We move the per-channel pixel enable bit to the low bit of each
178 * channel by shifting the byte containing the pixel mask by the
179 * vector immediate 0x76543210UV.
181 * The region of <1,8,0> reads only 1 byte (the pixel masks for
182 * subspans 0 and 1) in SIMD8 and an additional byte (the pixel
183 * masks for 2 and 3) in SIMD16.
185 fs_reg shifted = abld.vgrf(BRW_REGISTER_TYPE_UW, 1);
187 stride(byte_offset(retype(brw_vec1_grf(1, 0),
188 BRW_REGISTER_TYPE_UB), 28),
190 brw_imm_v(0x76543210));
192 /* A set bit in the pixel mask means the channel is enabled, but
193 * that is the opposite of gl_HelperInvocation so we need to invert
196 * The negate source-modifier bit of logical instructions on Gen8+
197 * performs 1's complement negation, so we can use that instead of
200 fs_reg inverted = negate(shifted);
201 if (v->devinfo->gen < 8) {
202 inverted = abld.vgrf(BRW_REGISTER_TYPE_UW);
203 abld.NOT(inverted, shifted);
206 /* We then resolve the 0/1 result to 0/~0 boolean values by ANDing
207 * with 1 and negating.
209 fs_reg anded = abld.vgrf(BRW_REGISTER_TYPE_UD, 1);
210 abld.AND(anded, inverted, brw_imm_uw(1));
212 fs_reg dst = abld.vgrf(BRW_REGISTER_TYPE_D, 1);
213 abld.MOV(dst, negate(retype(anded, BRW_REGISTER_TYPE_D)));
227 fs_visitor::nir_emit_system_values()
229 nir_system_values = ralloc_array(mem_ctx, fs_reg, SYSTEM_VALUE_MAX);
230 for (unsigned i = 0; i < SYSTEM_VALUE_MAX; i++) {
231 nir_system_values[i] = fs_reg();
234 /* Always emit SUBGROUP_INVOCATION. Dead code will clean it up if we
235 * never end up using it.
238 const fs_builder abld = bld.annotate("gl_SubgroupInvocation", NULL);
239 fs_reg ® = nir_system_values[SYSTEM_VALUE_SUBGROUP_INVOCATION];
240 reg = abld.vgrf(BRW_REGISTER_TYPE_UW);
242 const fs_builder allbld8 = abld.group(8, 0).exec_all();
243 allbld8.MOV(reg, brw_imm_v(0x76543210));
244 if (dispatch_width > 8)
245 allbld8.ADD(byte_offset(reg, 16), reg, brw_imm_uw(8u));
246 if (dispatch_width > 16) {
247 const fs_builder allbld16 = abld.group(16, 0).exec_all();
248 allbld16.ADD(byte_offset(reg, 32), reg, brw_imm_uw(16u));
252 nir_foreach_function(function, nir) {
253 assert(strcmp(function->name, "main") == 0);
254 assert(function->impl);
255 nir_foreach_block(block, function->impl) {
256 emit_system_values_block(block, this);
262 * Returns a type based on a reference_type (word, float, half-float) and a
265 * Reference BRW_REGISTER_TYPE are HF,F,DF,W,D,UW,UD.
267 * @FIXME: 64-bit return types are always DF on integer types to maintain
268 * compability with uses of DF previously to the introduction of int64
272 brw_reg_type_from_bit_size(const unsigned bit_size,
273 const brw_reg_type reference_type)
275 switch(reference_type) {
276 case BRW_REGISTER_TYPE_HF:
277 case BRW_REGISTER_TYPE_F:
278 case BRW_REGISTER_TYPE_DF:
281 return BRW_REGISTER_TYPE_HF;
283 return BRW_REGISTER_TYPE_F;
285 return BRW_REGISTER_TYPE_DF;
287 unreachable("Invalid bit size");
289 case BRW_REGISTER_TYPE_W:
290 case BRW_REGISTER_TYPE_D:
291 case BRW_REGISTER_TYPE_Q:
294 return BRW_REGISTER_TYPE_W;
296 return BRW_REGISTER_TYPE_D;
298 return BRW_REGISTER_TYPE_Q;
300 unreachable("Invalid bit size");
302 case BRW_REGISTER_TYPE_UW:
303 case BRW_REGISTER_TYPE_UD:
304 case BRW_REGISTER_TYPE_UQ:
307 return BRW_REGISTER_TYPE_UW;
309 return BRW_REGISTER_TYPE_UD;
311 return BRW_REGISTER_TYPE_UQ;
313 unreachable("Invalid bit size");
316 unreachable("Unknown type");
321 fs_visitor::nir_emit_impl(nir_function_impl *impl)
323 nir_locals = ralloc_array(mem_ctx, fs_reg, impl->reg_alloc);
324 for (unsigned i = 0; i < impl->reg_alloc; i++) {
325 nir_locals[i] = fs_reg();
328 foreach_list_typed(nir_register, reg, node, &impl->registers) {
329 unsigned array_elems =
330 reg->num_array_elems == 0 ? 1 : reg->num_array_elems;
331 unsigned size = array_elems * reg->num_components;
332 const brw_reg_type reg_type =
333 brw_reg_type_from_bit_size(reg->bit_size, BRW_REGISTER_TYPE_F);
334 nir_locals[reg->index] = bld.vgrf(reg_type, size);
337 nir_ssa_values = reralloc(mem_ctx, nir_ssa_values, fs_reg,
340 nir_emit_cf_list(&impl->body);
344 fs_visitor::nir_emit_cf_list(exec_list *list)
346 exec_list_validate(list);
347 foreach_list_typed(nir_cf_node, node, node, list) {
348 switch (node->type) {
350 nir_emit_if(nir_cf_node_as_if(node));
353 case nir_cf_node_loop:
354 nir_emit_loop(nir_cf_node_as_loop(node));
357 case nir_cf_node_block:
358 nir_emit_block(nir_cf_node_as_block(node));
362 unreachable("Invalid CFG node block");
368 fs_visitor::nir_emit_if(nir_if *if_stmt)
370 /* first, put the condition into f0 */
371 fs_inst *inst = bld.MOV(bld.null_reg_d(),
372 retype(get_nir_src(if_stmt->condition),
373 BRW_REGISTER_TYPE_D));
374 inst->conditional_mod = BRW_CONDITIONAL_NZ;
376 bld.IF(BRW_PREDICATE_NORMAL);
378 nir_emit_cf_list(&if_stmt->then_list);
380 /* note: if the else is empty, dead CF elimination will remove it */
381 bld.emit(BRW_OPCODE_ELSE);
383 nir_emit_cf_list(&if_stmt->else_list);
385 bld.emit(BRW_OPCODE_ENDIF);
389 fs_visitor::nir_emit_loop(nir_loop *loop)
391 bld.emit(BRW_OPCODE_DO);
393 nir_emit_cf_list(&loop->body);
395 bld.emit(BRW_OPCODE_WHILE);
399 fs_visitor::nir_emit_block(nir_block *block)
401 nir_foreach_instr(instr, block) {
402 nir_emit_instr(instr);
407 fs_visitor::nir_emit_instr(nir_instr *instr)
409 const fs_builder abld = bld.annotate(NULL, instr);
411 switch (instr->type) {
412 case nir_instr_type_alu:
413 nir_emit_alu(abld, nir_instr_as_alu(instr));
416 case nir_instr_type_intrinsic:
418 case MESA_SHADER_VERTEX:
419 nir_emit_vs_intrinsic(abld, nir_instr_as_intrinsic(instr));
421 case MESA_SHADER_TESS_CTRL:
422 nir_emit_tcs_intrinsic(abld, nir_instr_as_intrinsic(instr));
424 case MESA_SHADER_TESS_EVAL:
425 nir_emit_tes_intrinsic(abld, nir_instr_as_intrinsic(instr));
427 case MESA_SHADER_GEOMETRY:
428 nir_emit_gs_intrinsic(abld, nir_instr_as_intrinsic(instr));
430 case MESA_SHADER_FRAGMENT:
431 nir_emit_fs_intrinsic(abld, nir_instr_as_intrinsic(instr));
433 case MESA_SHADER_COMPUTE:
434 nir_emit_cs_intrinsic(abld, nir_instr_as_intrinsic(instr));
437 unreachable("unsupported shader stage");
441 case nir_instr_type_tex:
442 nir_emit_texture(abld, nir_instr_as_tex(instr));
445 case nir_instr_type_load_const:
446 nir_emit_load_const(abld, nir_instr_as_load_const(instr));
449 case nir_instr_type_ssa_undef:
450 /* We create a new VGRF for undefs on every use (by handling
451 * them in get_nir_src()), rather than for each definition.
452 * This helps register coalescing eliminate MOVs from undef.
456 case nir_instr_type_jump:
457 nir_emit_jump(abld, nir_instr_as_jump(instr));
461 unreachable("unknown instruction type");
466 * Recognizes a parent instruction of nir_op_extract_* and changes the type to
470 fs_visitor::optimize_extract_to_float(nir_alu_instr *instr,
471 const fs_reg &result)
473 if (!instr->src[0].src.is_ssa ||
474 !instr->src[0].src.ssa->parent_instr)
477 if (instr->src[0].src.ssa->parent_instr->type != nir_instr_type_alu)
480 nir_alu_instr *src0 =
481 nir_instr_as_alu(instr->src[0].src.ssa->parent_instr);
483 if (src0->op != nir_op_extract_u8 && src0->op != nir_op_extract_u16 &&
484 src0->op != nir_op_extract_i8 && src0->op != nir_op_extract_i16)
487 nir_const_value *element = nir_src_as_const_value(src0->src[1].src);
488 assert(element != NULL);
490 /* Element type to extract.*/
491 const brw_reg_type type = brw_int_type(
492 src0->op == nir_op_extract_u16 || src0->op == nir_op_extract_i16 ? 2 : 1,
493 src0->op == nir_op_extract_i16 || src0->op == nir_op_extract_i8);
495 fs_reg op0 = get_nir_src(src0->src[0].src);
496 op0.type = brw_type_for_nir_type(devinfo,
497 (nir_alu_type)(nir_op_infos[src0->op].input_types[0] |
498 nir_src_bit_size(src0->src[0].src)));
499 op0 = offset(op0, bld, src0->src[0].swizzle[0]);
501 set_saturate(instr->dest.saturate,
502 bld.MOV(result, subscript(op0, type, element->u32[0])));
507 fs_visitor::optimize_frontfacing_ternary(nir_alu_instr *instr,
508 const fs_reg &result)
510 if (!instr->src[0].src.is_ssa ||
511 instr->src[0].src.ssa->parent_instr->type != nir_instr_type_intrinsic)
514 nir_intrinsic_instr *src0 =
515 nir_instr_as_intrinsic(instr->src[0].src.ssa->parent_instr);
517 if (src0->intrinsic != nir_intrinsic_load_front_face)
520 nir_const_value *value1 = nir_src_as_const_value(instr->src[1].src);
521 if (!value1 || fabsf(value1->f32[0]) != 1.0f)
524 nir_const_value *value2 = nir_src_as_const_value(instr->src[2].src);
525 if (!value2 || fabsf(value2->f32[0]) != 1.0f)
528 fs_reg tmp = vgrf(glsl_type::int_type);
530 if (devinfo->gen >= 6) {
531 /* Bit 15 of g0.0 is 0 if the polygon is front facing. */
532 fs_reg g0 = fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_W));
534 /* For (gl_FrontFacing ? 1.0 : -1.0), emit:
536 * or(8) tmp.1<2>W g0.0<0,1,0>W 0x00003f80W
537 * and(8) dst<1>D tmp<8,8,1>D 0xbf800000D
539 * and negate g0.0<0,1,0>W for (gl_FrontFacing ? -1.0 : 1.0).
541 * This negation looks like it's safe in practice, because bits 0:4 will
542 * surely be TRIANGLES
545 if (value1->f32[0] == -1.0f) {
549 bld.OR(subscript(tmp, BRW_REGISTER_TYPE_W, 1),
550 g0, brw_imm_uw(0x3f80));
552 /* Bit 31 of g1.6 is 0 if the polygon is front facing. */
553 fs_reg g1_6 = fs_reg(retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_D));
555 /* For (gl_FrontFacing ? 1.0 : -1.0), emit:
557 * or(8) tmp<1>D g1.6<0,1,0>D 0x3f800000D
558 * and(8) dst<1>D tmp<8,8,1>D 0xbf800000D
560 * and negate g1.6<0,1,0>D for (gl_FrontFacing ? -1.0 : 1.0).
562 * This negation looks like it's safe in practice, because bits 0:4 will
563 * surely be TRIANGLES
566 if (value1->f32[0] == -1.0f) {
570 bld.OR(tmp, g1_6, brw_imm_d(0x3f800000));
572 bld.AND(retype(result, BRW_REGISTER_TYPE_D), tmp, brw_imm_d(0xbf800000));
578 emit_find_msb_using_lzd(const fs_builder &bld,
579 const fs_reg &result,
587 /* LZD of an absolute value source almost always does the right
588 * thing. There are two problem values:
590 * * 0x80000000. Since abs(0x80000000) == 0x80000000, LZD returns
591 * 0. However, findMSB(int(0x80000000)) == 30.
593 * * 0xffffffff. Since abs(0xffffffff) == 1, LZD returns
594 * 31. Section 8.8 (Integer Functions) of the GLSL 4.50 spec says:
596 * For a value of zero or negative one, -1 will be returned.
598 * * Negative powers of two. LZD(abs(-(1<<x))) returns x, but
599 * findMSB(-(1<<x)) should return x-1.
601 * For all negative number cases, including 0x80000000 and
602 * 0xffffffff, the correct value is obtained from LZD if instead of
603 * negating the (already negative) value the logical-not is used. A
604 * conditonal logical-not can be achieved in two instructions.
606 temp = bld.vgrf(BRW_REGISTER_TYPE_D);
608 bld.ASR(temp, src, brw_imm_d(31));
609 bld.XOR(temp, temp, src);
612 bld.LZD(retype(result, BRW_REGISTER_TYPE_UD),
613 retype(temp, BRW_REGISTER_TYPE_UD));
615 /* LZD counts from the MSB side, while GLSL's findMSB() wants the count
616 * from the LSB side. Subtract the result from 31 to convert the MSB
617 * count into an LSB count. If no bits are set, LZD will return 32.
618 * 31-32 = -1, which is exactly what findMSB() is supposed to return.
620 inst = bld.ADD(result, retype(result, BRW_REGISTER_TYPE_D), brw_imm_d(31));
621 inst->src[0].negate = true;
625 brw_rnd_mode_from_nir_op (const nir_op op) {
627 case nir_op_f2f16_rtz:
628 return BRW_RND_MODE_RTZ;
629 case nir_op_f2f16_rtne:
630 return BRW_RND_MODE_RTNE;
632 unreachable("Operation doesn't support rounding mode");
637 fs_visitor::nir_emit_alu(const fs_builder &bld, nir_alu_instr *instr)
639 struct brw_wm_prog_key *fs_key = (struct brw_wm_prog_key *) this->key;
642 fs_reg result = get_nir_dest(instr->dest.dest);
643 result.type = brw_type_for_nir_type(devinfo,
644 (nir_alu_type)(nir_op_infos[instr->op].output_type |
645 nir_dest_bit_size(instr->dest.dest)));
648 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++) {
649 op[i] = get_nir_src(instr->src[i].src);
650 op[i].type = brw_type_for_nir_type(devinfo,
651 (nir_alu_type)(nir_op_infos[instr->op].input_types[i] |
652 nir_src_bit_size(instr->src[i].src)));
653 op[i].abs = instr->src[i].abs;
654 op[i].negate = instr->src[i].negate;
657 /* We get a bunch of mov's out of the from_ssa pass and they may still
658 * be vectorized. We'll handle them as a special-case. We'll also
659 * handle vecN here because it's basically the same thing.
667 fs_reg temp = result;
668 bool need_extra_copy = false;
669 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++) {
670 if (!instr->src[i].src.is_ssa &&
671 instr->dest.dest.reg.reg == instr->src[i].src.reg.reg) {
672 need_extra_copy = true;
673 temp = bld.vgrf(result.type, 4);
678 for (unsigned i = 0; i < 4; i++) {
679 if (!(instr->dest.write_mask & (1 << i)))
682 if (instr->op == nir_op_imov || instr->op == nir_op_fmov) {
683 inst = bld.MOV(offset(temp, bld, i),
684 offset(op[0], bld, instr->src[0].swizzle[i]));
686 inst = bld.MOV(offset(temp, bld, i),
687 offset(op[i], bld, instr->src[i].swizzle[0]));
689 inst->saturate = instr->dest.saturate;
692 /* In this case the source and destination registers were the same,
693 * so we need to insert an extra set of moves in order to deal with
696 if (need_extra_copy) {
697 for (unsigned i = 0; i < 4; i++) {
698 if (!(instr->dest.write_mask & (1 << i)))
701 bld.MOV(offset(result, bld, i), offset(temp, bld, i));
710 /* At this point, we have dealt with any instruction that operates on
711 * more than a single channel. Therefore, we can just adjust the source
712 * and destination registers for that channel and emit the instruction.
714 unsigned channel = 0;
715 if (nir_op_infos[instr->op].output_size == 0) {
716 /* Since NIR is doing the scalarizing for us, we should only ever see
717 * vectorized operations with a single channel.
719 assert(_mesa_bitcount(instr->dest.write_mask) == 1);
720 channel = ffs(instr->dest.write_mask) - 1;
722 result = offset(result, bld, channel);
725 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++) {
726 assert(nir_op_infos[instr->op].input_sizes[i] < 2);
727 op[i] = offset(op[i], bld, instr->src[i].swizzle[channel]);
733 if (optimize_extract_to_float(instr, result))
735 inst = bld.MOV(result, op[0]);
736 inst->saturate = instr->dest.saturate;
739 case nir_op_f2f16_rtne:
740 case nir_op_f2f16_rtz:
741 bld.emit(SHADER_OPCODE_RND_MODE, bld.null_reg_ud(),
742 brw_imm_d(brw_rnd_mode_from_nir_op(instr->op)));
745 /* In theory, it would be better to use BRW_OPCODE_F32TO16. Depending
746 * on the HW gen, it is a special hw opcode or just a MOV, and
747 * brw_F32TO16 (at brw_eu_emit) would do the work to chose.
749 * But if we want to use that opcode, we need to provide support on
750 * different optimizations and lowerings. As right now HF support is
751 * only for gen8+, it will be better to use directly the MOV, and use
752 * BRW_OPCODE_F32TO16 when/if we work for HF support on gen7.
755 case nir_op_f2f16_undef:
758 /* TODO: Fixing aligment rules for conversions from 32-bits to
759 * 16-bit types should be moved to lower_conversions
761 fs_reg tmp = bld.vgrf(op[0].type, 1);
762 tmp = subscript(tmp, result.type, 0);
763 inst = bld.MOV(tmp, op[0]);
764 inst->saturate = instr->dest.saturate;
765 inst = bld.MOV(result, tmp);
766 inst->saturate = instr->dest.saturate;
777 /* CHV PRM, vol07, 3D Media GPGPU Engine, Register Region Restrictions:
779 * "When source or destination is 64b (...), regioning in Align1
780 * must follow these rules:
782 * 1. Source and destination horizontal stride must be aligned to
786 * This means that 32-bit to 64-bit conversions need to have the 32-bit
787 * data elements aligned to 64-bit. This restriction does not apply to
790 if (nir_dest_bit_size(instr->dest.dest) == 64 &&
791 nir_src_bit_size(instr->src[0].src) == 32 &&
792 (devinfo->is_cherryview || gen_device_info_is_9lp(devinfo))) {
793 fs_reg tmp = bld.vgrf(result.type, 1);
794 tmp = subscript(tmp, op[0].type, 0);
795 inst = bld.MOV(tmp, op[0]);
796 inst = bld.MOV(result, tmp);
797 inst->saturate = instr->dest.saturate;
806 inst = bld.MOV(result, op[0]);
807 inst->saturate = instr->dest.saturate;
812 /* Straightforward since the source can be assumed to be
815 set_condmod(BRW_CONDITIONAL_NZ, bld.MOV(result, op[0]));
816 set_predicate(BRW_PREDICATE_NORMAL, bld.MOV(result, brw_imm_f(1.0f)));
818 } else if (type_sz(op[0].type) < 8) {
819 /* AND(val, 0x80000000) gives the sign bit.
821 * Predicated OR ORs 1.0 (0x3f800000) with the sign bit if val is not
824 bld.CMP(bld.null_reg_f(), op[0], brw_imm_f(0.0f), BRW_CONDITIONAL_NZ);
826 fs_reg result_int = retype(result, BRW_REGISTER_TYPE_UD);
827 op[0].type = BRW_REGISTER_TYPE_UD;
828 result.type = BRW_REGISTER_TYPE_UD;
829 bld.AND(result_int, op[0], brw_imm_ud(0x80000000u));
831 inst = bld.OR(result_int, result_int, brw_imm_ud(0x3f800000u));
832 inst->predicate = BRW_PREDICATE_NORMAL;
833 if (instr->dest.saturate) {
834 inst = bld.MOV(result, result);
835 inst->saturate = true;
838 /* For doubles we do the same but we need to consider:
840 * - 2-src instructions can't operate with 64-bit immediates
841 * - The sign is encoded in the high 32-bit of each DF
842 * - We need to produce a DF result.
845 fs_reg zero = vgrf(glsl_type::double_type);
846 bld.MOV(zero, setup_imm_df(bld, 0.0));
847 bld.CMP(bld.null_reg_df(), op[0], zero, BRW_CONDITIONAL_NZ);
849 bld.MOV(result, zero);
851 fs_reg r = subscript(result, BRW_REGISTER_TYPE_UD, 1);
852 bld.AND(r, subscript(op[0], BRW_REGISTER_TYPE_UD, 1),
853 brw_imm_ud(0x80000000u));
855 set_predicate(BRW_PREDICATE_NORMAL,
856 bld.OR(r, r, brw_imm_ud(0x3ff00000u)));
858 if (instr->dest.saturate) {
859 inst = bld.MOV(result, result);
860 inst->saturate = true;
867 /* ASR(val, 31) -> negative val generates 0xffffffff (signed -1).
868 * -> non-negative val generates 0x00000000.
869 * Predicated OR sets 1 if val is positive.
871 assert(nir_dest_bit_size(instr->dest.dest) < 64);
872 bld.CMP(bld.null_reg_d(), op[0], brw_imm_d(0), BRW_CONDITIONAL_G);
873 bld.ASR(result, op[0], brw_imm_d(31));
874 inst = bld.OR(result, result, brw_imm_d(1));
875 inst->predicate = BRW_PREDICATE_NORMAL;
879 inst = bld.emit(SHADER_OPCODE_RCP, result, op[0]);
880 inst->saturate = instr->dest.saturate;
884 inst = bld.emit(SHADER_OPCODE_EXP2, result, op[0]);
885 inst->saturate = instr->dest.saturate;
889 inst = bld.emit(SHADER_OPCODE_LOG2, result, op[0]);
890 inst->saturate = instr->dest.saturate;
894 inst = bld.emit(SHADER_OPCODE_SIN, result, op[0]);
895 inst->saturate = instr->dest.saturate;
899 inst = bld.emit(SHADER_OPCODE_COS, result, op[0]);
900 inst->saturate = instr->dest.saturate;
904 if (fs_key->high_quality_derivatives) {
905 inst = bld.emit(FS_OPCODE_DDX_FINE, result, op[0]);
907 inst = bld.emit(FS_OPCODE_DDX_COARSE, result, op[0]);
909 inst->saturate = instr->dest.saturate;
911 case nir_op_fddx_fine:
912 inst = bld.emit(FS_OPCODE_DDX_FINE, result, op[0]);
913 inst->saturate = instr->dest.saturate;
915 case nir_op_fddx_coarse:
916 inst = bld.emit(FS_OPCODE_DDX_COARSE, result, op[0]);
917 inst->saturate = instr->dest.saturate;
920 if (fs_key->high_quality_derivatives) {
921 inst = bld.emit(FS_OPCODE_DDY_FINE, result, op[0]);
923 inst = bld.emit(FS_OPCODE_DDY_COARSE, result, op[0]);
925 inst->saturate = instr->dest.saturate;
927 case nir_op_fddy_fine:
928 inst = bld.emit(FS_OPCODE_DDY_FINE, result, op[0]);
929 inst->saturate = instr->dest.saturate;
931 case nir_op_fddy_coarse:
932 inst = bld.emit(FS_OPCODE_DDY_COARSE, result, op[0]);
933 inst->saturate = instr->dest.saturate;
938 inst = bld.ADD(result, op[0], op[1]);
939 inst->saturate = instr->dest.saturate;
943 inst = bld.MUL(result, op[0], op[1]);
944 inst->saturate = instr->dest.saturate;
948 assert(nir_dest_bit_size(instr->dest.dest) < 64);
949 bld.MUL(result, op[0], op[1]);
952 case nir_op_imul_high:
953 case nir_op_umul_high:
954 assert(nir_dest_bit_size(instr->dest.dest) < 64);
955 bld.emit(SHADER_OPCODE_MULH, result, op[0], op[1]);
960 assert(nir_dest_bit_size(instr->dest.dest) < 64);
961 bld.emit(SHADER_OPCODE_INT_QUOTIENT, result, op[0], op[1]);
964 case nir_op_uadd_carry:
965 unreachable("Should have been lowered by carry_to_arith().");
967 case nir_op_usub_borrow:
968 unreachable("Should have been lowered by borrow_to_arith().");
972 /* According to the sign table for INT DIV in the Ivy Bridge PRM, it
973 * appears that our hardware just does the right thing for signed
976 assert(nir_dest_bit_size(instr->dest.dest) < 64);
977 bld.emit(SHADER_OPCODE_INT_REMAINDER, result, op[0], op[1]);
981 /* Get a regular C-style remainder. If a % b == 0, set the predicate. */
982 bld.emit(SHADER_OPCODE_INT_REMAINDER, result, op[0], op[1]);
984 /* Math instructions don't support conditional mod */
985 inst = bld.MOV(bld.null_reg_d(), result);
986 inst->conditional_mod = BRW_CONDITIONAL_NZ;
988 /* Now, we need to determine if signs of the sources are different.
989 * When we XOR the sources, the top bit is 0 if they are the same and 1
990 * if they are different. We can then use a conditional modifier to
991 * turn that into a predicate. This leads us to an XOR.l instruction.
993 * Technically, according to the PRM, you're not allowed to use .l on a
994 * XOR instruction. However, emperical experiments and Curro's reading
995 * of the simulator source both indicate that it's safe.
997 fs_reg tmp = bld.vgrf(BRW_REGISTER_TYPE_D);
998 inst = bld.XOR(tmp, op[0], op[1]);
999 inst->predicate = BRW_PREDICATE_NORMAL;
1000 inst->conditional_mod = BRW_CONDITIONAL_L;
1002 /* If the result of the initial remainder operation is non-zero and the
1003 * two sources have different signs, add in a copy of op[1] to get the
1004 * final integer modulus value.
1006 inst = bld.ADD(result, result, op[1]);
1007 inst->predicate = BRW_PREDICATE_NORMAL;
1015 fs_reg dest = result;
1016 if (nir_src_bit_size(instr->src[0].src) > 32) {
1017 dest = bld.vgrf(BRW_REGISTER_TYPE_DF, 1);
1019 brw_conditional_mod cond;
1020 switch (instr->op) {
1022 cond = BRW_CONDITIONAL_L;
1025 cond = BRW_CONDITIONAL_GE;
1028 cond = BRW_CONDITIONAL_Z;
1031 cond = BRW_CONDITIONAL_NZ;
1034 unreachable("bad opcode");
1036 bld.CMP(dest, op[0], op[1], cond);
1037 if (nir_src_bit_size(instr->src[0].src) > 32) {
1038 bld.MOV(result, subscript(dest, BRW_REGISTER_TYPE_UD, 0));
1049 fs_reg dest = result;
1050 if (nir_src_bit_size(instr->src[0].src) > 32) {
1051 dest = bld.vgrf(BRW_REGISTER_TYPE_UQ, 1);
1054 brw_conditional_mod cond;
1055 switch (instr->op) {
1058 cond = BRW_CONDITIONAL_L;
1062 cond = BRW_CONDITIONAL_GE;
1065 cond = BRW_CONDITIONAL_Z;
1068 cond = BRW_CONDITIONAL_NZ;
1071 unreachable("bad opcode");
1073 bld.CMP(dest, op[0], op[1], cond);
1074 if (nir_src_bit_size(instr->src[0].src) > 32) {
1075 bld.MOV(result, subscript(dest, BRW_REGISTER_TYPE_UD, 0));
1081 if (devinfo->gen >= 8) {
1082 op[0] = resolve_source_modifiers(op[0]);
1084 bld.NOT(result, op[0]);
1087 if (devinfo->gen >= 8) {
1088 op[0] = resolve_source_modifiers(op[0]);
1089 op[1] = resolve_source_modifiers(op[1]);
1091 bld.XOR(result, op[0], op[1]);
1094 if (devinfo->gen >= 8) {
1095 op[0] = resolve_source_modifiers(op[0]);
1096 op[1] = resolve_source_modifiers(op[1]);
1098 bld.OR(result, op[0], op[1]);
1101 if (devinfo->gen >= 8) {
1102 op[0] = resolve_source_modifiers(op[0]);
1103 op[1] = resolve_source_modifiers(op[1]);
1105 bld.AND(result, op[0], op[1]);
1111 case nir_op_ball_fequal2:
1112 case nir_op_ball_iequal2:
1113 case nir_op_ball_fequal3:
1114 case nir_op_ball_iequal3:
1115 case nir_op_ball_fequal4:
1116 case nir_op_ball_iequal4:
1117 case nir_op_bany_fnequal2:
1118 case nir_op_bany_inequal2:
1119 case nir_op_bany_fnequal3:
1120 case nir_op_bany_inequal3:
1121 case nir_op_bany_fnequal4:
1122 case nir_op_bany_inequal4:
1123 unreachable("Lowered by nir_lower_alu_reductions");
1125 case nir_op_fnoise1_1:
1126 case nir_op_fnoise1_2:
1127 case nir_op_fnoise1_3:
1128 case nir_op_fnoise1_4:
1129 case nir_op_fnoise2_1:
1130 case nir_op_fnoise2_2:
1131 case nir_op_fnoise2_3:
1132 case nir_op_fnoise2_4:
1133 case nir_op_fnoise3_1:
1134 case nir_op_fnoise3_2:
1135 case nir_op_fnoise3_3:
1136 case nir_op_fnoise3_4:
1137 case nir_op_fnoise4_1:
1138 case nir_op_fnoise4_2:
1139 case nir_op_fnoise4_3:
1140 case nir_op_fnoise4_4:
1141 unreachable("not reached: should be handled by lower_noise");
1144 unreachable("not reached: should be handled by ldexp_to_arith()");
1147 inst = bld.emit(SHADER_OPCODE_SQRT, result, op[0]);
1148 inst->saturate = instr->dest.saturate;
1152 inst = bld.emit(SHADER_OPCODE_RSQ, result, op[0]);
1153 inst->saturate = instr->dest.saturate;
1158 bld.MOV(result, negate(op[0]));
1163 if (nir_src_bit_size(instr->src[0].src) == 64) {
1164 /* two-argument instructions can't take 64-bit immediates */
1168 if (instr->op == nir_op_f2b) {
1169 zero = vgrf(glsl_type::double_type);
1170 tmp = vgrf(glsl_type::double_type);
1171 bld.MOV(zero, setup_imm_df(bld, 0.0));
1173 zero = vgrf(glsl_type::int64_t_type);
1174 tmp = vgrf(glsl_type::int64_t_type);
1175 bld.MOV(zero, brw_imm_q(0));
1178 /* A SIMD16 execution needs to be split in two instructions, so use
1179 * a vgrf instead of the flag register as dst so instruction splitting
1182 bld.CMP(tmp, op[0], zero, BRW_CONDITIONAL_NZ);
1183 bld.MOV(result, subscript(tmp, BRW_REGISTER_TYPE_UD, 0));
1185 if (instr->op == nir_op_f2b) {
1186 bld.CMP(result, op[0], brw_imm_f(0.0f), BRW_CONDITIONAL_NZ);
1188 bld.CMP(result, op[0], brw_imm_d(0), BRW_CONDITIONAL_NZ);
1194 inst = bld.RNDZ(result, op[0]);
1195 inst->saturate = instr->dest.saturate;
1198 case nir_op_fceil: {
1199 op[0].negate = !op[0].negate;
1200 fs_reg temp = vgrf(glsl_type::float_type);
1201 bld.RNDD(temp, op[0]);
1203 inst = bld.MOV(result, temp);
1204 inst->saturate = instr->dest.saturate;
1208 inst = bld.RNDD(result, op[0]);
1209 inst->saturate = instr->dest.saturate;
1212 inst = bld.FRC(result, op[0]);
1213 inst->saturate = instr->dest.saturate;
1215 case nir_op_fround_even:
1216 inst = bld.RNDE(result, op[0]);
1217 inst->saturate = instr->dest.saturate;
1220 case nir_op_fquantize2f16: {
1221 fs_reg tmp16 = bld.vgrf(BRW_REGISTER_TYPE_D);
1222 fs_reg tmp32 = bld.vgrf(BRW_REGISTER_TYPE_F);
1223 fs_reg zero = bld.vgrf(BRW_REGISTER_TYPE_F);
1225 /* The destination stride must be at least as big as the source stride. */
1226 tmp16.type = BRW_REGISTER_TYPE_W;
1229 /* Check for denormal */
1230 fs_reg abs_src0 = op[0];
1231 abs_src0.abs = true;
1232 bld.CMP(bld.null_reg_f(), abs_src0, brw_imm_f(ldexpf(1.0, -14)),
1234 /* Get the appropriately signed zero */
1235 bld.AND(retype(zero, BRW_REGISTER_TYPE_UD),
1236 retype(op[0], BRW_REGISTER_TYPE_UD),
1237 brw_imm_ud(0x80000000));
1238 /* Do the actual F32 -> F16 -> F32 conversion */
1239 bld.emit(BRW_OPCODE_F32TO16, tmp16, op[0]);
1240 bld.emit(BRW_OPCODE_F16TO32, tmp32, tmp16);
1241 /* Select that or zero based on normal status */
1242 inst = bld.SEL(result, zero, tmp32);
1243 inst->predicate = BRW_PREDICATE_NORMAL;
1244 inst->saturate = instr->dest.saturate;
1251 inst = bld.emit_minmax(result, op[0], op[1], BRW_CONDITIONAL_L);
1252 inst->saturate = instr->dest.saturate;
1258 inst = bld.emit_minmax(result, op[0], op[1], BRW_CONDITIONAL_GE);
1259 inst->saturate = instr->dest.saturate;
1262 case nir_op_pack_snorm_2x16:
1263 case nir_op_pack_snorm_4x8:
1264 case nir_op_pack_unorm_2x16:
1265 case nir_op_pack_unorm_4x8:
1266 case nir_op_unpack_snorm_2x16:
1267 case nir_op_unpack_snorm_4x8:
1268 case nir_op_unpack_unorm_2x16:
1269 case nir_op_unpack_unorm_4x8:
1270 case nir_op_unpack_half_2x16:
1271 case nir_op_pack_half_2x16:
1272 unreachable("not reached: should be handled by lower_packing_builtins");
1274 case nir_op_unpack_half_2x16_split_x:
1275 inst = bld.emit(FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X, result, op[0]);
1276 inst->saturate = instr->dest.saturate;
1278 case nir_op_unpack_half_2x16_split_y:
1279 inst = bld.emit(FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y, result, op[0]);
1280 inst->saturate = instr->dest.saturate;
1283 case nir_op_pack_64_2x32_split:
1284 bld.emit(FS_OPCODE_PACK, result, op[0], op[1]);
1287 case nir_op_unpack_64_2x32_split_x:
1288 case nir_op_unpack_64_2x32_split_y: {
1289 if (instr->op == nir_op_unpack_64_2x32_split_x)
1290 bld.MOV(result, subscript(op[0], BRW_REGISTER_TYPE_UD, 0));
1292 bld.MOV(result, subscript(op[0], BRW_REGISTER_TYPE_UD, 1));
1297 inst = bld.emit(SHADER_OPCODE_POW, result, op[0], op[1]);
1298 inst->saturate = instr->dest.saturate;
1301 case nir_op_bitfield_reverse:
1302 assert(nir_dest_bit_size(instr->dest.dest) < 64);
1303 bld.BFREV(result, op[0]);
1306 case nir_op_bit_count:
1307 assert(nir_dest_bit_size(instr->dest.dest) < 64);
1308 bld.CBIT(result, op[0]);
1311 case nir_op_ufind_msb: {
1312 assert(nir_dest_bit_size(instr->dest.dest) < 64);
1313 emit_find_msb_using_lzd(bld, result, op[0], false);
1317 case nir_op_ifind_msb: {
1318 assert(nir_dest_bit_size(instr->dest.dest) < 64);
1320 if (devinfo->gen < 7) {
1321 emit_find_msb_using_lzd(bld, result, op[0], true);
1323 bld.FBH(retype(result, BRW_REGISTER_TYPE_UD), op[0]);
1325 /* FBH counts from the MSB side, while GLSL's findMSB() wants the
1326 * count from the LSB side. If FBH didn't return an error
1327 * (0xFFFFFFFF), then subtract the result from 31 to convert the MSB
1328 * count into an LSB count.
1330 bld.CMP(bld.null_reg_d(), result, brw_imm_d(-1), BRW_CONDITIONAL_NZ);
1332 inst = bld.ADD(result, result, brw_imm_d(31));
1333 inst->predicate = BRW_PREDICATE_NORMAL;
1334 inst->src[0].negate = true;
1339 case nir_op_find_lsb:
1340 assert(nir_dest_bit_size(instr->dest.dest) < 64);
1342 if (devinfo->gen < 7) {
1343 fs_reg temp = vgrf(glsl_type::int_type);
1345 /* (x & -x) generates a value that consists of only the LSB of x.
1346 * For all powers of 2, findMSB(y) == findLSB(y).
1348 fs_reg src = retype(op[0], BRW_REGISTER_TYPE_D);
1349 fs_reg negated_src = src;
1351 /* One must be negated, and the other must be non-negated. It
1352 * doesn't matter which is which.
1354 negated_src.negate = true;
1357 bld.AND(temp, src, negated_src);
1358 emit_find_msb_using_lzd(bld, result, temp, false);
1360 bld.FBL(result, op[0]);
1364 case nir_op_ubitfield_extract:
1365 case nir_op_ibitfield_extract:
1366 unreachable("should have been lowered");
1369 assert(nir_dest_bit_size(instr->dest.dest) < 64);
1370 bld.BFE(result, op[2], op[1], op[0]);
1373 assert(nir_dest_bit_size(instr->dest.dest) < 64);
1374 bld.BFI1(result, op[0], op[1]);
1377 assert(nir_dest_bit_size(instr->dest.dest) < 64);
1378 bld.BFI2(result, op[0], op[1], op[2]);
1381 case nir_op_bitfield_insert:
1382 unreachable("not reached: should have been lowered");
1387 fs_reg shift_count = op[1];
1389 if (devinfo->is_cherryview || gen_device_info_is_9lp(devinfo)) {
1390 if (op[1].file == VGRF &&
1391 (result.type == BRW_REGISTER_TYPE_Q ||
1392 result.type == BRW_REGISTER_TYPE_UQ)) {
1393 shift_count = fs_reg(VGRF, alloc.allocate(dispatch_width / 4),
1394 BRW_REGISTER_TYPE_UD);
1395 shift_count.stride = 2;
1396 bld.MOV(shift_count, op[1]);
1400 switch (instr->op) {
1402 bld.SHL(result, op[0], shift_count);
1405 bld.ASR(result, op[0], shift_count);
1408 bld.SHR(result, op[0], shift_count);
1411 unreachable("not reached");
1416 case nir_op_pack_half_2x16_split:
1417 bld.emit(FS_OPCODE_PACK_HALF_2x16_SPLIT, result, op[0], op[1]);
1421 inst = bld.MAD(result, op[2], op[1], op[0]);
1422 inst->saturate = instr->dest.saturate;
1426 inst = bld.LRP(result, op[0], op[1], op[2]);
1427 inst->saturate = instr->dest.saturate;
1431 if (optimize_frontfacing_ternary(instr, result))
1434 bld.CMP(bld.null_reg_d(), op[0], brw_imm_d(0), BRW_CONDITIONAL_NZ);
1435 inst = bld.SEL(result, op[1], op[2]);
1436 inst->predicate = BRW_PREDICATE_NORMAL;
1439 case nir_op_extract_u8:
1440 case nir_op_extract_i8: {
1441 nir_const_value *byte = nir_src_as_const_value(instr->src[1].src);
1442 assert(byte != NULL);
1447 * There is no direct conversion from B/UB to Q/UQ or Q/UQ to B/UB.
1448 * Use two instructions and a word or DWord intermediate integer type.
1450 if (nir_dest_bit_size(instr->dest.dest) == 64) {
1451 const brw_reg_type type = brw_int_type(2, instr->op == nir_op_extract_i8);
1453 if (instr->op == nir_op_extract_i8) {
1454 /* If we need to sign extend, extract to a word first */
1455 fs_reg w_temp = bld.vgrf(BRW_REGISTER_TYPE_W);
1456 bld.MOV(w_temp, subscript(op[0], type, byte->u32[0]));
1457 bld.MOV(result, w_temp);
1459 /* Otherwise use an AND with 0xff and a word type */
1460 bld.AND(result, subscript(op[0], type, byte->u32[0] / 2), brw_imm_uw(0xff));
1463 const brw_reg_type type = brw_int_type(1, instr->op == nir_op_extract_i8);
1464 bld.MOV(result, subscript(op[0], type, byte->u32[0]));
1469 case nir_op_extract_u16:
1470 case nir_op_extract_i16: {
1471 const brw_reg_type type = brw_int_type(2, instr->op == nir_op_extract_i16);
1472 nir_const_value *word = nir_src_as_const_value(instr->src[1].src);
1473 assert(word != NULL);
1474 bld.MOV(result, subscript(op[0], type, word->u32[0]));
1479 unreachable("unhandled instruction");
1482 /* If we need to do a boolean resolve, replace the result with -(x & 1)
1483 * to sign extend the low bit to 0/~0
1485 if (devinfo->gen <= 5 &&
1486 (instr->instr.pass_flags & BRW_NIR_BOOLEAN_MASK) == BRW_NIR_BOOLEAN_NEEDS_RESOLVE) {
1487 fs_reg masked = vgrf(glsl_type::int_type);
1488 bld.AND(masked, result, brw_imm_d(1));
1489 masked.negate = true;
1490 bld.MOV(retype(result, BRW_REGISTER_TYPE_D), masked);
1495 fs_visitor::nir_emit_load_const(const fs_builder &bld,
1496 nir_load_const_instr *instr)
1498 const brw_reg_type reg_type =
1499 brw_reg_type_from_bit_size(instr->def.bit_size, BRW_REGISTER_TYPE_D);
1500 fs_reg reg = bld.vgrf(reg_type, instr->def.num_components);
1502 switch (instr->def.bit_size) {
1504 for (unsigned i = 0; i < instr->def.num_components; i++)
1505 bld.MOV(offset(reg, bld, i), brw_imm_d(instr->value.i32[i]));
1509 assert(devinfo->gen >= 7);
1510 if (devinfo->gen == 7) {
1511 /* We don't get 64-bit integer types until gen8 */
1512 for (unsigned i = 0; i < instr->def.num_components; i++) {
1513 bld.MOV(retype(offset(reg, bld, i), BRW_REGISTER_TYPE_DF),
1514 setup_imm_df(bld, instr->value.f64[i]));
1517 for (unsigned i = 0; i < instr->def.num_components; i++)
1518 bld.MOV(offset(reg, bld, i), brw_imm_q(instr->value.i64[i]));
1523 unreachable("Invalid bit size");
1526 nir_ssa_values[instr->def.index] = reg;
1530 fs_visitor::get_nir_src(const nir_src &src)
1534 if (src.ssa->parent_instr->type == nir_instr_type_ssa_undef) {
1535 const brw_reg_type reg_type =
1536 brw_reg_type_from_bit_size(src.ssa->bit_size, BRW_REGISTER_TYPE_D);
1537 reg = bld.vgrf(reg_type, src.ssa->num_components);
1539 reg = nir_ssa_values[src.ssa->index];
1542 /* We don't handle indirects on locals */
1543 assert(src.reg.indirect == NULL);
1544 reg = offset(nir_locals[src.reg.reg->index], bld,
1545 src.reg.base_offset * src.reg.reg->num_components);
1548 if (nir_src_bit_size(src) == 64 && devinfo->gen == 7) {
1549 /* The only 64-bit type available on gen7 is DF, so use that. */
1550 reg.type = BRW_REGISTER_TYPE_DF;
1552 /* To avoid floating-point denorm flushing problems, set the type by
1553 * default to an integer type - instructions that need floating point
1554 * semantics will set this to F if they need to
1556 reg.type = brw_reg_type_from_bit_size(nir_src_bit_size(src),
1557 BRW_REGISTER_TYPE_D);
1564 * Return an IMM for constants; otherwise call get_nir_src() as normal.
1566 * This function should not be called on any value which may be 64 bits.
1567 * We could theoretically support 64-bit on gen8+ but we choose not to
1568 * because it wouldn't work in general (no gen7 support) and there are
1569 * enough restrictions in 64-bit immediates that you can't take the return
1570 * value and treat it the same as the result of get_nir_src().
1573 fs_visitor::get_nir_src_imm(const nir_src &src)
1575 nir_const_value *val = nir_src_as_const_value(src);
1576 assert(nir_src_bit_size(src) == 32);
1577 return val ? fs_reg(brw_imm_d(val->i32[0])) : get_nir_src(src);
1581 fs_visitor::get_nir_dest(const nir_dest &dest)
1584 const brw_reg_type reg_type =
1585 brw_reg_type_from_bit_size(dest.ssa.bit_size, BRW_REGISTER_TYPE_F);
1586 nir_ssa_values[dest.ssa.index] =
1587 bld.vgrf(reg_type, dest.ssa.num_components);
1588 return nir_ssa_values[dest.ssa.index];
1590 /* We don't handle indirects on locals */
1591 assert(dest.reg.indirect == NULL);
1592 return offset(nir_locals[dest.reg.reg->index], bld,
1593 dest.reg.base_offset * dest.reg.reg->num_components);
1598 fs_visitor::get_nir_image_deref(const nir_deref_var *deref)
1600 fs_reg image(UNIFORM, deref->var->data.driver_location / 4,
1601 BRW_REGISTER_TYPE_UD);
1603 unsigned indirect_max = 0;
1605 for (const nir_deref *tail = &deref->deref; tail->child;
1606 tail = tail->child) {
1607 const nir_deref_array *deref_array = nir_deref_as_array(tail->child);
1608 assert(tail->child->deref_type == nir_deref_type_array);
1609 const unsigned size = glsl_get_length(tail->type);
1610 const unsigned element_size = type_size_scalar(deref_array->deref.type);
1611 const unsigned base = MIN2(deref_array->base_offset, size - 1);
1612 image = offset(image, bld, base * element_size);
1614 if (deref_array->deref_array_type == nir_deref_array_type_indirect) {
1615 fs_reg tmp = vgrf(glsl_type::uint_type);
1617 /* Accessing an invalid surface index with the dataport can result
1618 * in a hang. According to the spec "if the index used to
1619 * select an individual element is negative or greater than or
1620 * equal to the size of the array, the results of the operation
1621 * are undefined but may not lead to termination" -- which is one
1622 * of the possible outcomes of the hang. Clamp the index to
1623 * prevent access outside of the array bounds.
1625 bld.emit_minmax(tmp, retype(get_nir_src(deref_array->indirect),
1626 BRW_REGISTER_TYPE_UD),
1627 brw_imm_ud(size - base - 1), BRW_CONDITIONAL_L);
1629 indirect_max += element_size * (tail->type->length - 1);
1631 bld.MUL(tmp, tmp, brw_imm_ud(element_size * 4));
1632 if (indirect.file == BAD_FILE) {
1635 bld.ADD(indirect, indirect, tmp);
1640 if (indirect.file == BAD_FILE) {
1643 /* Emit a pile of MOVs to load the uniform into a temporary. The
1644 * dead-code elimination pass will get rid of what we don't use.
1646 fs_reg tmp = bld.vgrf(BRW_REGISTER_TYPE_UD, BRW_IMAGE_PARAM_SIZE);
1647 for (unsigned j = 0; j < BRW_IMAGE_PARAM_SIZE; j++) {
1648 bld.emit(SHADER_OPCODE_MOV_INDIRECT,
1649 offset(tmp, bld, j), offset(image, bld, j),
1650 indirect, brw_imm_ud((indirect_max + 1) * 4));
1657 fs_visitor::emit_percomp(const fs_builder &bld, const fs_inst &inst,
1660 for (unsigned i = 0; i < 4; i++) {
1661 if (!((wr_mask >> i) & 1))
1664 fs_inst *new_inst = new(mem_ctx) fs_inst(inst);
1665 new_inst->dst = offset(new_inst->dst, bld, i);
1666 for (unsigned j = 0; j < new_inst->sources; j++)
1667 if (new_inst->src[j].file == VGRF)
1668 new_inst->src[j] = offset(new_inst->src[j], bld, i);
1675 * Get the matching channel register datatype for an image intrinsic of the
1676 * specified GLSL image type.
1679 get_image_base_type(const glsl_type *type)
1681 switch ((glsl_base_type)type->sampled_type) {
1682 case GLSL_TYPE_UINT:
1683 return BRW_REGISTER_TYPE_UD;
1685 return BRW_REGISTER_TYPE_D;
1686 case GLSL_TYPE_FLOAT:
1687 return BRW_REGISTER_TYPE_F;
1689 unreachable("Not reached.");
1694 * Get the appropriate atomic op for an image atomic intrinsic.
1697 get_image_atomic_op(nir_intrinsic_op op, const glsl_type *type)
1700 case nir_intrinsic_image_var_atomic_add:
1702 case nir_intrinsic_image_var_atomic_min:
1703 return (get_image_base_type(type) == BRW_REGISTER_TYPE_D ?
1704 BRW_AOP_IMIN : BRW_AOP_UMIN);
1705 case nir_intrinsic_image_var_atomic_max:
1706 return (get_image_base_type(type) == BRW_REGISTER_TYPE_D ?
1707 BRW_AOP_IMAX : BRW_AOP_UMAX);
1708 case nir_intrinsic_image_var_atomic_and:
1710 case nir_intrinsic_image_var_atomic_or:
1712 case nir_intrinsic_image_var_atomic_xor:
1714 case nir_intrinsic_image_var_atomic_exchange:
1716 case nir_intrinsic_image_var_atomic_comp_swap:
1717 return BRW_AOP_CMPWR;
1719 unreachable("Not reachable.");
1724 emit_pixel_interpolater_send(const fs_builder &bld,
1729 glsl_interp_mode interpolation)
1731 struct brw_wm_prog_data *wm_prog_data =
1732 brw_wm_prog_data(bld.shader->stage_prog_data);
1737 if (src.file == BAD_FILE) {
1739 payload = bld.vgrf(BRW_REGISTER_TYPE_F, 1);
1743 mlen = 2 * bld.dispatch_width() / 8;
1746 inst = bld.emit(opcode, dst, payload, desc);
1748 /* 2 floats per slot returned */
1749 inst->size_written = 2 * dst.component_size(inst->exec_size);
1750 inst->pi_noperspective = interpolation == INTERP_MODE_NOPERSPECTIVE;
1752 wm_prog_data->pulls_bary = true;
1758 * Computes 1 << x, given a D/UD register containing some value x.
1761 intexp2(const fs_builder &bld, const fs_reg &x)
1763 assert(x.type == BRW_REGISTER_TYPE_UD || x.type == BRW_REGISTER_TYPE_D);
1765 fs_reg result = bld.vgrf(x.type, 1);
1766 fs_reg one = bld.vgrf(x.type, 1);
1768 bld.MOV(one, retype(brw_imm_d(1), one.type));
1769 bld.SHL(result, one, x);
1774 fs_visitor::emit_gs_end_primitive(const nir_src &vertex_count_nir_src)
1776 assert(stage == MESA_SHADER_GEOMETRY);
1778 struct brw_gs_prog_data *gs_prog_data = brw_gs_prog_data(prog_data);
1780 if (gs_compile->control_data_header_size_bits == 0)
1783 /* We can only do EndPrimitive() functionality when the control data
1784 * consists of cut bits. Fortunately, the only time it isn't is when the
1785 * output type is points, in which case EndPrimitive() is a no-op.
1787 if (gs_prog_data->control_data_format !=
1788 GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_CUT) {
1792 /* Cut bits use one bit per vertex. */
1793 assert(gs_compile->control_data_bits_per_vertex == 1);
1795 fs_reg vertex_count = get_nir_src(vertex_count_nir_src);
1796 vertex_count.type = BRW_REGISTER_TYPE_UD;
1798 /* Cut bit n should be set to 1 if EndPrimitive() was called after emitting
1799 * vertex n, 0 otherwise. So all we need to do here is mark bit
1800 * (vertex_count - 1) % 32 in the cut_bits register to indicate that
1801 * EndPrimitive() was called after emitting vertex (vertex_count - 1);
1802 * vec4_gs_visitor::emit_control_data_bits() will take care of the rest.
1804 * Note that if EndPrimitive() is called before emitting any vertices, this
1805 * will cause us to set bit 31 of the control_data_bits register to 1.
1806 * That's fine because:
1808 * - If max_vertices < 32, then vertex number 31 (zero-based) will never be
1809 * output, so the hardware will ignore cut bit 31.
1811 * - If max_vertices == 32, then vertex number 31 is guaranteed to be the
1812 * last vertex, so setting cut bit 31 has no effect (since the primitive
1813 * is automatically ended when the GS terminates).
1815 * - If max_vertices > 32, then the ir_emit_vertex visitor will reset the
1816 * control_data_bits register to 0 when the first vertex is emitted.
1819 const fs_builder abld = bld.annotate("end primitive");
1821 /* control_data_bits |= 1 << ((vertex_count - 1) % 32) */
1822 fs_reg prev_count = bld.vgrf(BRW_REGISTER_TYPE_UD, 1);
1823 abld.ADD(prev_count, vertex_count, brw_imm_ud(0xffffffffu));
1824 fs_reg mask = intexp2(abld, prev_count);
1825 /* Note: we're relying on the fact that the GEN SHL instruction only pays
1826 * attention to the lower 5 bits of its second source argument, so on this
1827 * architecture, 1 << (vertex_count - 1) is equivalent to 1 <<
1828 * ((vertex_count - 1) % 32).
1830 abld.OR(this->control_data_bits, this->control_data_bits, mask);
1834 fs_visitor::emit_gs_control_data_bits(const fs_reg &vertex_count)
1836 assert(stage == MESA_SHADER_GEOMETRY);
1837 assert(gs_compile->control_data_bits_per_vertex != 0);
1839 struct brw_gs_prog_data *gs_prog_data = brw_gs_prog_data(prog_data);
1841 const fs_builder abld = bld.annotate("emit control data bits");
1842 const fs_builder fwa_bld = bld.exec_all();
1844 /* We use a single UD register to accumulate control data bits (32 bits
1845 * for each of the SIMD8 channels). So we need to write a DWord (32 bits)
1848 * Unfortunately, the URB_WRITE_SIMD8 message uses 128-bit (OWord) offsets.
1849 * We have select a 128-bit group via the Global and Per-Slot Offsets, then
1850 * use the Channel Mask phase to enable/disable which DWord within that
1851 * group to write. (Remember, different SIMD8 channels may have emitted
1852 * different numbers of vertices, so we may need per-slot offsets.)
1854 * Channel masking presents an annoying problem: we may have to replicate
1855 * the data up to 4 times:
1857 * Msg = Handles, Per-Slot Offsets, Channel Masks, Data, Data, Data, Data.
1859 * To avoid penalizing shaders that emit a small number of vertices, we
1860 * can avoid these sometimes: if the size of the control data header is
1861 * <= 128 bits, then there is only 1 OWord. All SIMD8 channels will land
1862 * land in the same 128-bit group, so we can skip per-slot offsets.
1864 * Similarly, if the control data header is <= 32 bits, there is only one
1865 * DWord, so we can skip channel masks.
1867 enum opcode opcode = SHADER_OPCODE_URB_WRITE_SIMD8;
1869 fs_reg channel_mask, per_slot_offset;
1871 if (gs_compile->control_data_header_size_bits > 32) {
1872 opcode = SHADER_OPCODE_URB_WRITE_SIMD8_MASKED;
1873 channel_mask = vgrf(glsl_type::uint_type);
1876 if (gs_compile->control_data_header_size_bits > 128) {
1877 opcode = SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT;
1878 per_slot_offset = vgrf(glsl_type::uint_type);
1881 /* Figure out which DWord we're trying to write to using the formula:
1883 * dword_index = (vertex_count - 1) * bits_per_vertex / 32
1885 * Since bits_per_vertex is a power of two, and is known at compile
1886 * time, this can be optimized to:
1888 * dword_index = (vertex_count - 1) >> (6 - log2(bits_per_vertex))
1890 if (opcode != SHADER_OPCODE_URB_WRITE_SIMD8) {
1891 fs_reg dword_index = bld.vgrf(BRW_REGISTER_TYPE_UD, 1);
1892 fs_reg prev_count = bld.vgrf(BRW_REGISTER_TYPE_UD, 1);
1893 abld.ADD(prev_count, vertex_count, brw_imm_ud(0xffffffffu));
1894 unsigned log2_bits_per_vertex =
1895 util_last_bit(gs_compile->control_data_bits_per_vertex);
1896 abld.SHR(dword_index, prev_count, brw_imm_ud(6u - log2_bits_per_vertex));
1898 if (per_slot_offset.file != BAD_FILE) {
1899 /* Set the per-slot offset to dword_index / 4, so that we'll write to
1900 * the appropriate OWord within the control data header.
1902 abld.SHR(per_slot_offset, dword_index, brw_imm_ud(2u));
1905 /* Set the channel masks to 1 << (dword_index % 4), so that we'll
1906 * write to the appropriate DWORD within the OWORD.
1908 fs_reg channel = bld.vgrf(BRW_REGISTER_TYPE_UD, 1);
1909 fwa_bld.AND(channel, dword_index, brw_imm_ud(3u));
1910 channel_mask = intexp2(fwa_bld, channel);
1911 /* Then the channel masks need to be in bits 23:16. */
1912 fwa_bld.SHL(channel_mask, channel_mask, brw_imm_ud(16u));
1915 /* Store the control data bits in the message payload and send it. */
1917 if (channel_mask.file != BAD_FILE)
1918 mlen += 4; /* channel masks, plus 3 extra copies of the data */
1919 if (per_slot_offset.file != BAD_FILE)
1922 fs_reg payload = bld.vgrf(BRW_REGISTER_TYPE_UD, mlen);
1923 fs_reg *sources = ralloc_array(mem_ctx, fs_reg, mlen);
1925 sources[i++] = fs_reg(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD));
1926 if (per_slot_offset.file != BAD_FILE)
1927 sources[i++] = per_slot_offset;
1928 if (channel_mask.file != BAD_FILE)
1929 sources[i++] = channel_mask;
1931 sources[i++] = this->control_data_bits;
1934 abld.LOAD_PAYLOAD(payload, sources, mlen, mlen);
1935 fs_inst *inst = abld.emit(opcode, reg_undef, payload);
1937 /* We need to increment Global Offset by 256-bits to make room for
1938 * Broadwell's extra "Vertex Count" payload at the beginning of the
1939 * URB entry. Since this is an OWord message, Global Offset is counted
1940 * in 128-bit units, so we must set it to 2.
1942 if (gs_prog_data->static_vertex_count == -1)
1947 fs_visitor::set_gs_stream_control_data_bits(const fs_reg &vertex_count,
1950 /* control_data_bits |= stream_id << ((2 * (vertex_count - 1)) % 32) */
1952 /* Note: we are calling this *before* increasing vertex_count, so
1953 * this->vertex_count == vertex_count - 1 in the formula above.
1956 /* Stream mode uses 2 bits per vertex */
1957 assert(gs_compile->control_data_bits_per_vertex == 2);
1959 /* Must be a valid stream */
1960 assert(stream_id < MAX_VERTEX_STREAMS);
1962 /* Control data bits are initialized to 0 so we don't have to set any
1963 * bits when sending vertices to stream 0.
1968 const fs_builder abld = bld.annotate("set stream control data bits", NULL);
1970 /* reg::sid = stream_id */
1971 fs_reg sid = bld.vgrf(BRW_REGISTER_TYPE_UD, 1);
1972 abld.MOV(sid, brw_imm_ud(stream_id));
1974 /* reg:shift_count = 2 * (vertex_count - 1) */
1975 fs_reg shift_count = bld.vgrf(BRW_REGISTER_TYPE_UD, 1);
1976 abld.SHL(shift_count, vertex_count, brw_imm_ud(1u));
1978 /* Note: we're relying on the fact that the GEN SHL instruction only pays
1979 * attention to the lower 5 bits of its second source argument, so on this
1980 * architecture, stream_id << 2 * (vertex_count - 1) is equivalent to
1981 * stream_id << ((2 * (vertex_count - 1)) % 32).
1983 fs_reg mask = bld.vgrf(BRW_REGISTER_TYPE_UD, 1);
1984 abld.SHL(mask, sid, shift_count);
1985 abld.OR(this->control_data_bits, this->control_data_bits, mask);
1989 fs_visitor::emit_gs_vertex(const nir_src &vertex_count_nir_src,
1992 assert(stage == MESA_SHADER_GEOMETRY);
1994 struct brw_gs_prog_data *gs_prog_data = brw_gs_prog_data(prog_data);
1996 fs_reg vertex_count = get_nir_src(vertex_count_nir_src);
1997 vertex_count.type = BRW_REGISTER_TYPE_UD;
1999 /* Haswell and later hardware ignores the "Render Stream Select" bits
2000 * from the 3DSTATE_STREAMOUT packet when the SOL stage is disabled,
2001 * and instead sends all primitives down the pipeline for rasterization.
2002 * If the SOL stage is enabled, "Render Stream Select" is honored and
2003 * primitives bound to non-zero streams are discarded after stream output.
2005 * Since the only purpose of primives sent to non-zero streams is to
2006 * be recorded by transform feedback, we can simply discard all geometry
2007 * bound to these streams when transform feedback is disabled.
2009 if (stream_id > 0 && !nir->info.has_transform_feedback_varyings)
2012 /* If we're outputting 32 control data bits or less, then we can wait
2013 * until the shader is over to output them all. Otherwise we need to
2014 * output them as we go. Now is the time to do it, since we're about to
2015 * output the vertex_count'th vertex, so it's guaranteed that the
2016 * control data bits associated with the (vertex_count - 1)th vertex are
2019 if (gs_compile->control_data_header_size_bits > 32) {
2020 const fs_builder abld =
2021 bld.annotate("emit vertex: emit control data bits");
2023 /* Only emit control data bits if we've finished accumulating a batch
2024 * of 32 bits. This is the case when:
2026 * (vertex_count * bits_per_vertex) % 32 == 0
2028 * (in other words, when the last 5 bits of vertex_count *
2029 * bits_per_vertex are 0). Assuming bits_per_vertex == 2^n for some
2030 * integer n (which is always the case, since bits_per_vertex is
2031 * always 1 or 2), this is equivalent to requiring that the last 5-n
2032 * bits of vertex_count are 0:
2034 * vertex_count & (2^(5-n) - 1) == 0
2036 * 2^(5-n) == 2^5 / 2^n == 32 / bits_per_vertex, so this is
2039 * vertex_count & (32 / bits_per_vertex - 1) == 0
2041 * TODO: If vertex_count is an immediate, we could do some of this math
2042 * at compile time...
2045 abld.AND(bld.null_reg_d(), vertex_count,
2046 brw_imm_ud(32u / gs_compile->control_data_bits_per_vertex - 1u));
2047 inst->conditional_mod = BRW_CONDITIONAL_Z;
2049 abld.IF(BRW_PREDICATE_NORMAL);
2050 /* If vertex_count is 0, then no control data bits have been
2051 * accumulated yet, so we can skip emitting them.
2053 abld.CMP(bld.null_reg_d(), vertex_count, brw_imm_ud(0u),
2054 BRW_CONDITIONAL_NEQ);
2055 abld.IF(BRW_PREDICATE_NORMAL);
2056 emit_gs_control_data_bits(vertex_count);
2057 abld.emit(BRW_OPCODE_ENDIF);
2059 /* Reset control_data_bits to 0 so we can start accumulating a new
2062 * Note: in the case where vertex_count == 0, this neutralizes the
2063 * effect of any call to EndPrimitive() that the shader may have
2064 * made before outputting its first vertex.
2066 inst = abld.MOV(this->control_data_bits, brw_imm_ud(0u));
2067 inst->force_writemask_all = true;
2068 abld.emit(BRW_OPCODE_ENDIF);
2071 emit_urb_writes(vertex_count);
2073 /* In stream mode we have to set control data bits for all vertices
2074 * unless we have disabled control data bits completely (which we do
2075 * do for GL_POINTS outputs that don't use streams).
2077 if (gs_compile->control_data_header_size_bits > 0 &&
2078 gs_prog_data->control_data_format ==
2079 GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_SID) {
2080 set_gs_stream_control_data_bits(vertex_count, stream_id);
2085 fs_visitor::emit_gs_input_load(const fs_reg &dst,
2086 const nir_src &vertex_src,
2087 unsigned base_offset,
2088 const nir_src &offset_src,
2089 unsigned num_components,
2090 unsigned first_component)
2092 struct brw_gs_prog_data *gs_prog_data = brw_gs_prog_data(prog_data);
2094 nir_const_value *vertex_const = nir_src_as_const_value(vertex_src);
2095 nir_const_value *offset_const = nir_src_as_const_value(offset_src);
2096 const unsigned push_reg_count = gs_prog_data->base.urb_read_length * 8;
2098 /* TODO: figure out push input layout for invocations == 1 */
2099 /* TODO: make this work with 64-bit inputs */
2100 if (gs_prog_data->invocations == 1 &&
2101 type_sz(dst.type) <= 4 &&
2102 offset_const != NULL && vertex_const != NULL &&
2103 4 * (base_offset + offset_const->u32[0]) < push_reg_count) {
2104 int imm_offset = (base_offset + offset_const->u32[0]) * 4 +
2105 vertex_const->u32[0] * push_reg_count;
2106 for (unsigned i = 0; i < num_components; i++) {
2107 bld.MOV(offset(dst, bld, i),
2108 fs_reg(ATTR, imm_offset + i + first_component, dst.type));
2113 /* Resort to the pull model. Ensure the VUE handles are provided. */
2114 assert(gs_prog_data->base.include_vue_handles);
2116 unsigned first_icp_handle = gs_prog_data->include_primitive_id ? 3 : 2;
2117 fs_reg icp_handle = bld.vgrf(BRW_REGISTER_TYPE_UD, 1);
2119 if (gs_prog_data->invocations == 1) {
2121 /* The vertex index is constant; just select the proper URB handle. */
2123 retype(brw_vec8_grf(first_icp_handle + vertex_const->i32[0], 0),
2124 BRW_REGISTER_TYPE_UD);
2126 /* The vertex index is non-constant. We need to use indirect
2127 * addressing to fetch the proper URB handle.
2129 * First, we start with the sequence <7, 6, 5, 4, 3, 2, 1, 0>
2130 * indicating that channel <n> should read the handle from
2131 * DWord <n>. We convert that to bytes by multiplying by 4.
2133 * Next, we convert the vertex index to bytes by multiplying
2134 * by 32 (shifting by 5), and add the two together. This is
2135 * the final indirect byte offset.
2137 fs_reg sequence = bld.vgrf(BRW_REGISTER_TYPE_UW, 1);
2138 fs_reg channel_offsets = bld.vgrf(BRW_REGISTER_TYPE_UD, 1);
2139 fs_reg vertex_offset_bytes = bld.vgrf(BRW_REGISTER_TYPE_UD, 1);
2140 fs_reg icp_offset_bytes = bld.vgrf(BRW_REGISTER_TYPE_UD, 1);
2142 /* sequence = <7, 6, 5, 4, 3, 2, 1, 0> */
2143 bld.MOV(sequence, fs_reg(brw_imm_v(0x76543210)));
2144 /* channel_offsets = 4 * sequence = <28, 24, 20, 16, 12, 8, 4, 0> */
2145 bld.SHL(channel_offsets, sequence, brw_imm_ud(2u));
2146 /* Convert vertex_index to bytes (multiply by 32) */
2147 bld.SHL(vertex_offset_bytes,
2148 retype(get_nir_src(vertex_src), BRW_REGISTER_TYPE_UD),
2150 bld.ADD(icp_offset_bytes, vertex_offset_bytes, channel_offsets);
2152 /* Use first_icp_handle as the base offset. There is one register
2153 * of URB handles per vertex, so inform the register allocator that
2154 * we might read up to nir->info.gs.vertices_in registers.
2156 bld.emit(SHADER_OPCODE_MOV_INDIRECT, icp_handle,
2157 retype(brw_vec8_grf(first_icp_handle, 0), icp_handle.type),
2158 fs_reg(icp_offset_bytes),
2159 brw_imm_ud(nir->info.gs.vertices_in * REG_SIZE));
2162 assert(gs_prog_data->invocations > 1);
2165 assert(devinfo->gen >= 9 || vertex_const->i32[0] <= 5);
2167 retype(brw_vec1_grf(first_icp_handle +
2168 vertex_const->i32[0] / 8,
2169 vertex_const->i32[0] % 8),
2170 BRW_REGISTER_TYPE_UD));
2172 /* The vertex index is non-constant. We need to use indirect
2173 * addressing to fetch the proper URB handle.
2176 fs_reg icp_offset_bytes = bld.vgrf(BRW_REGISTER_TYPE_UD, 1);
2178 /* Convert vertex_index to bytes (multiply by 4) */
2179 bld.SHL(icp_offset_bytes,
2180 retype(get_nir_src(vertex_src), BRW_REGISTER_TYPE_UD),
2183 /* Use first_icp_handle as the base offset. There is one DWord
2184 * of URB handles per vertex, so inform the register allocator that
2185 * we might read up to ceil(nir->info.gs.vertices_in / 8) registers.
2187 bld.emit(SHADER_OPCODE_MOV_INDIRECT, icp_handle,
2188 retype(brw_vec8_grf(first_icp_handle, 0), icp_handle.type),
2189 fs_reg(icp_offset_bytes),
2190 brw_imm_ud(DIV_ROUND_UP(nir->info.gs.vertices_in, 8) *
2197 fs_reg tmp_dst = dst;
2198 fs_reg indirect_offset = get_nir_src(offset_src);
2199 unsigned num_iterations = 1;
2200 unsigned orig_num_components = num_components;
2202 if (type_sz(dst.type) == 8) {
2203 if (num_components > 2) {
2207 fs_reg tmp = fs_reg(VGRF, alloc.allocate(4), dst.type);
2209 first_component = first_component / 2;
2212 for (unsigned iter = 0; iter < num_iterations; iter++) {
2214 /* Constant indexing - use global offset. */
2215 if (first_component != 0) {
2216 unsigned read_components = num_components + first_component;
2217 fs_reg tmp = bld.vgrf(dst.type, read_components);
2218 inst = bld.emit(SHADER_OPCODE_URB_READ_SIMD8, tmp, icp_handle);
2219 inst->size_written = read_components *
2220 tmp.component_size(inst->exec_size);
2221 for (unsigned i = 0; i < num_components; i++) {
2222 bld.MOV(offset(tmp_dst, bld, i),
2223 offset(tmp, bld, i + first_component));
2226 inst = bld.emit(SHADER_OPCODE_URB_READ_SIMD8, tmp_dst,
2228 inst->size_written = num_components *
2229 tmp_dst.component_size(inst->exec_size);
2231 inst->offset = base_offset + offset_const->u32[0];
2234 /* Indirect indexing - use per-slot offsets as well. */
2235 const fs_reg srcs[] = { icp_handle, indirect_offset };
2236 unsigned read_components = num_components + first_component;
2237 fs_reg tmp = bld.vgrf(dst.type, read_components);
2238 fs_reg payload = bld.vgrf(BRW_REGISTER_TYPE_UD, 2);
2239 bld.LOAD_PAYLOAD(payload, srcs, ARRAY_SIZE(srcs), 0);
2240 if (first_component != 0) {
2241 inst = bld.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT, tmp,
2243 inst->size_written = read_components *
2244 tmp.component_size(inst->exec_size);
2245 for (unsigned i = 0; i < num_components; i++) {
2246 bld.MOV(offset(tmp_dst, bld, i),
2247 offset(tmp, bld, i + first_component));
2250 inst = bld.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT, tmp_dst,
2252 inst->size_written = num_components *
2253 tmp_dst.component_size(inst->exec_size);
2255 inst->offset = base_offset;
2259 if (type_sz(dst.type) == 8) {
2260 shuffle_32bit_load_result_to_64bit_data(
2261 bld, tmp_dst, retype(tmp_dst, BRW_REGISTER_TYPE_F), num_components);
2263 for (unsigned c = 0; c < num_components; c++)
2264 bld.MOV(offset(dst, bld, iter * 2 + c), offset(tmp_dst, bld, c));
2267 if (num_iterations > 1) {
2268 num_components = orig_num_components - 2;
2272 fs_reg new_indirect = bld.vgrf(BRW_REGISTER_TYPE_UD, 1);
2273 bld.ADD(new_indirect, indirect_offset, brw_imm_ud(1u));
2274 indirect_offset = new_indirect;
2281 fs_visitor::get_indirect_offset(nir_intrinsic_instr *instr)
2283 nir_src *offset_src = nir_get_io_offset_src(instr);
2284 nir_const_value *const_value = nir_src_as_const_value(*offset_src);
2287 /* The only constant offset we should find is 0. brw_nir.c's
2288 * add_const_offset_to_base() will fold other constant offsets
2289 * into instr->const_index[0].
2291 assert(const_value->u32[0] == 0);
2295 return get_nir_src(*offset_src);
2299 do_untyped_vector_read(const fs_builder &bld,
2301 const fs_reg surf_index,
2302 const fs_reg offset_reg,
2303 unsigned num_components)
2305 if (type_sz(dest.type) <= 2) {
2306 assert(dest.stride == 1);
2307 boolean is_const_offset = offset_reg.file == BRW_IMMEDIATE_VALUE;
2309 if (is_const_offset) {
2310 uint32_t start = offset_reg.ud & ~3;
2311 uint32_t end = offset_reg.ud + num_components * type_sz(dest.type);
2312 end = ALIGN(end, 4);
2313 assert (end - start <= 16);
2315 /* At this point we have 16-bit component/s that have constant
2316 * offset aligned to 4-bytes that can be read with untyped_reads.
2317 * untyped_read message requires 32-bit aligned offsets.
2319 unsigned first_component = (offset_reg.ud & 3) / type_sz(dest.type);
2320 unsigned num_components_32bit = (end - start) / 4;
2322 fs_reg read_result =
2323 emit_untyped_read(bld, surf_index, brw_imm_ud(start),
2325 num_components_32bit,
2326 BRW_PREDICATE_NONE);
2327 shuffle_32bit_load_result_to_16bit_data(bld,
2328 retype(dest, BRW_REGISTER_TYPE_W),
2329 retype(read_result, BRW_REGISTER_TYPE_D),
2330 first_component, num_components);
2332 fs_reg read_offset = bld.vgrf(BRW_REGISTER_TYPE_UD);
2333 for (unsigned i = 0; i < num_components; i++) {
2335 bld.MOV(read_offset, offset_reg);
2337 bld.ADD(read_offset, offset_reg,
2338 brw_imm_ud(i * type_sz(dest.type)));
2340 /* Non constant offsets are not guaranteed to be aligned 32-bits
2341 * so they are read using one byte_scattered_read message
2342 * for each component.
2344 fs_reg read_result =
2345 emit_byte_scattered_read(bld, surf_index, read_offset,
2347 type_sz(dest.type) * 8 /* bit_size */,
2348 BRW_PREDICATE_NONE);
2349 bld.MOV(offset(dest, bld, i),
2350 subscript (read_result, dest.type, 0));
2353 } else if (type_sz(dest.type) == 4) {
2354 fs_reg read_result = emit_untyped_read(bld, surf_index, offset_reg,
2357 BRW_PREDICATE_NONE);
2358 read_result.type = dest.type;
2359 for (unsigned i = 0; i < num_components; i++)
2360 bld.MOV(offset(dest, bld, i), offset(read_result, bld, i));
2361 } else if (type_sz(dest.type) == 8) {
2362 /* Reading a dvec, so we need to:
2364 * 1. Multiply num_components by 2, to account for the fact that we
2365 * need to read 64-bit components.
2366 * 2. Shuffle the result of the load to form valid 64-bit elements
2367 * 3. Emit a second load (for components z/w) if needed.
2369 fs_reg read_offset = bld.vgrf(BRW_REGISTER_TYPE_UD);
2370 bld.MOV(read_offset, offset_reg);
2372 int iters = num_components <= 2 ? 1 : 2;
2374 /* Load the dvec, the first iteration loads components x/y, the second
2375 * iteration, if needed, loads components z/w
2377 for (int it = 0; it < iters; it++) {
2378 /* Compute number of components to read in this iteration */
2379 int iter_components = MIN2(2, num_components);
2380 num_components -= iter_components;
2382 /* Read. Since this message reads 32-bit components, we need to
2383 * read twice as many components.
2385 fs_reg read_result = emit_untyped_read(bld, surf_index, read_offset,
2387 iter_components * 2,
2388 BRW_PREDICATE_NONE);
2390 /* Shuffle the 32-bit load result into valid 64-bit data */
2391 const fs_reg packed_result = bld.vgrf(dest.type, iter_components);
2392 shuffle_32bit_load_result_to_64bit_data(
2393 bld, packed_result, read_result, iter_components);
2395 /* Move each component to its destination */
2396 read_result = retype(read_result, BRW_REGISTER_TYPE_DF);
2397 for (int c = 0; c < iter_components; c++) {
2398 bld.MOV(offset(dest, bld, it * 2 + c),
2399 offset(packed_result, bld, c));
2402 bld.ADD(read_offset, read_offset, brw_imm_ud(16));
2405 unreachable("Unsupported type");
2410 fs_visitor::nir_emit_vs_intrinsic(const fs_builder &bld,
2411 nir_intrinsic_instr *instr)
2413 assert(stage == MESA_SHADER_VERTEX);
2416 if (nir_intrinsic_infos[instr->intrinsic].has_dest)
2417 dest = get_nir_dest(instr->dest);
2419 switch (instr->intrinsic) {
2420 case nir_intrinsic_load_vertex_id:
2421 unreachable("should be lowered by lower_vertex_id()");
2423 case nir_intrinsic_load_vertex_id_zero_base:
2424 case nir_intrinsic_load_base_vertex:
2425 case nir_intrinsic_load_instance_id:
2426 case nir_intrinsic_load_base_instance:
2427 case nir_intrinsic_load_draw_id: {
2428 gl_system_value sv = nir_system_value_from_intrinsic(instr->intrinsic);
2429 fs_reg val = nir_system_values[sv];
2430 assert(val.file != BAD_FILE);
2431 dest.type = val.type;
2436 case nir_intrinsic_load_input: {
2437 fs_reg src = fs_reg(ATTR, nir_intrinsic_base(instr) * 4, dest.type);
2438 unsigned first_component = nir_intrinsic_component(instr);
2439 unsigned num_components = instr->num_components;
2441 nir_const_value *const_offset = nir_src_as_const_value(instr->src[0]);
2442 assert(const_offset && "Indirect input loads not allowed");
2443 src = offset(src, bld, const_offset->u32[0]);
2445 if (type_sz(dest.type) == 8)
2446 first_component /= 2;
2448 for (unsigned j = 0; j < num_components; j++) {
2449 bld.MOV(offset(dest, bld, j), offset(src, bld, j + first_component));
2452 if (type_sz(dest.type) == 8) {
2453 shuffle_32bit_load_result_to_64bit_data(bld,
2455 retype(dest, BRW_REGISTER_TYPE_F),
2456 instr->num_components);
2462 nir_emit_intrinsic(bld, instr);
2468 fs_visitor::nir_emit_tcs_intrinsic(const fs_builder &bld,
2469 nir_intrinsic_instr *instr)
2471 assert(stage == MESA_SHADER_TESS_CTRL);
2472 struct brw_tcs_prog_key *tcs_key = (struct brw_tcs_prog_key *) key;
2473 struct brw_tcs_prog_data *tcs_prog_data = brw_tcs_prog_data(prog_data);
2476 if (nir_intrinsic_infos[instr->intrinsic].has_dest)
2477 dst = get_nir_dest(instr->dest);
2479 switch (instr->intrinsic) {
2480 case nir_intrinsic_load_primitive_id:
2481 bld.MOV(dst, fs_reg(brw_vec1_grf(0, 1)));
2483 case nir_intrinsic_load_invocation_id:
2484 bld.MOV(retype(dst, invocation_id.type), invocation_id);
2486 case nir_intrinsic_load_patch_vertices_in:
2487 bld.MOV(retype(dst, BRW_REGISTER_TYPE_D),
2488 brw_imm_d(tcs_key->input_vertices));
2491 case nir_intrinsic_barrier: {
2492 if (tcs_prog_data->instances == 1)
2495 fs_reg m0 = bld.vgrf(BRW_REGISTER_TYPE_UD, 1);
2496 fs_reg m0_2 = component(m0, 2);
2498 const fs_builder chanbld = bld.exec_all().group(1, 0);
2500 /* Zero the message header */
2501 bld.exec_all().MOV(m0, brw_imm_ud(0u));
2503 /* Copy "Barrier ID" from r0.2, bits 16:13 */
2504 chanbld.AND(m0_2, retype(brw_vec1_grf(0, 2), BRW_REGISTER_TYPE_UD),
2505 brw_imm_ud(INTEL_MASK(16, 13)));
2507 /* Shift it up to bits 27:24. */
2508 chanbld.SHL(m0_2, m0_2, brw_imm_ud(11));
2510 /* Set the Barrier Count and the enable bit */
2511 chanbld.OR(m0_2, m0_2,
2512 brw_imm_ud(tcs_prog_data->instances << 9 | (1 << 15)));
2514 bld.emit(SHADER_OPCODE_BARRIER, bld.null_reg_ud(), m0);
2518 case nir_intrinsic_load_input:
2519 unreachable("nir_lower_io should never give us these.");
2522 case nir_intrinsic_load_per_vertex_input: {
2523 fs_reg indirect_offset = get_indirect_offset(instr);
2524 unsigned imm_offset = instr->const_index[0];
2526 const nir_src &vertex_src = instr->src[0];
2527 nir_const_value *vertex_const = nir_src_as_const_value(vertex_src);
2534 /* Emit a MOV to resolve <0,1,0> regioning. */
2535 icp_handle = bld.vgrf(BRW_REGISTER_TYPE_UD, 1);
2537 retype(brw_vec1_grf(1 + (vertex_const->i32[0] >> 3),
2538 vertex_const->i32[0] & 7),
2539 BRW_REGISTER_TYPE_UD));
2540 } else if (tcs_prog_data->instances == 1 &&
2541 vertex_src.is_ssa &&
2542 vertex_src.ssa->parent_instr->type == nir_instr_type_intrinsic &&
2543 nir_instr_as_intrinsic(vertex_src.ssa->parent_instr)->intrinsic == nir_intrinsic_load_invocation_id) {
2544 /* For the common case of only 1 instance, an array index of
2545 * gl_InvocationID means reading g1. Skip all the indirect work.
2547 icp_handle = retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD);
2549 /* The vertex index is non-constant. We need to use indirect
2550 * addressing to fetch the proper URB handle.
2552 icp_handle = bld.vgrf(BRW_REGISTER_TYPE_UD, 1);
2554 /* Each ICP handle is a single DWord (4 bytes) */
2555 fs_reg vertex_offset_bytes = bld.vgrf(BRW_REGISTER_TYPE_UD, 1);
2556 bld.SHL(vertex_offset_bytes,
2557 retype(get_nir_src(vertex_src), BRW_REGISTER_TYPE_UD),
2560 /* Start at g1. We might read up to 4 registers. */
2561 bld.emit(SHADER_OPCODE_MOV_INDIRECT, icp_handle,
2562 retype(brw_vec8_grf(1, 0), icp_handle.type), vertex_offset_bytes,
2563 brw_imm_ud(4 * REG_SIZE));
2566 /* We can only read two double components with each URB read, so
2567 * we send two read messages in that case, each one loading up to
2568 * two double components.
2570 unsigned num_iterations = 1;
2571 unsigned num_components = instr->num_components;
2572 unsigned first_component = nir_intrinsic_component(instr);
2573 fs_reg orig_dst = dst;
2574 if (type_sz(dst.type) == 8) {
2575 first_component = first_component / 2;
2576 if (instr->num_components > 2) {
2581 fs_reg tmp = fs_reg(VGRF, alloc.allocate(4), dst.type);
2585 for (unsigned iter = 0; iter < num_iterations; iter++) {
2586 if (indirect_offset.file == BAD_FILE) {
2587 /* Constant indexing - use global offset. */
2588 if (first_component != 0) {
2589 unsigned read_components = num_components + first_component;
2590 fs_reg tmp = bld.vgrf(dst.type, read_components);
2591 inst = bld.emit(SHADER_OPCODE_URB_READ_SIMD8, tmp, icp_handle);
2592 for (unsigned i = 0; i < num_components; i++) {
2593 bld.MOV(offset(dst, bld, i),
2594 offset(tmp, bld, i + first_component));
2597 inst = bld.emit(SHADER_OPCODE_URB_READ_SIMD8, dst, icp_handle);
2599 inst->offset = imm_offset;
2602 /* Indirect indexing - use per-slot offsets as well. */
2603 const fs_reg srcs[] = { icp_handle, indirect_offset };
2604 fs_reg payload = bld.vgrf(BRW_REGISTER_TYPE_UD, 2);
2605 bld.LOAD_PAYLOAD(payload, srcs, ARRAY_SIZE(srcs), 0);
2606 if (first_component != 0) {
2607 unsigned read_components = num_components + first_component;
2608 fs_reg tmp = bld.vgrf(dst.type, read_components);
2609 inst = bld.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT, tmp,
2611 for (unsigned i = 0; i < num_components; i++) {
2612 bld.MOV(offset(dst, bld, i),
2613 offset(tmp, bld, i + first_component));
2616 inst = bld.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT, dst,
2619 inst->offset = imm_offset;
2622 inst->size_written = (num_components + first_component) *
2623 inst->dst.component_size(inst->exec_size);
2625 /* If we are reading 64-bit data using 32-bit read messages we need
2626 * build proper 64-bit data elements by shuffling the low and high
2627 * 32-bit components around like we do for other things like UBOs
2630 if (type_sz(dst.type) == 8) {
2631 shuffle_32bit_load_result_to_64bit_data(
2632 bld, dst, retype(dst, BRW_REGISTER_TYPE_F), num_components);
2634 for (unsigned c = 0; c < num_components; c++) {
2635 bld.MOV(offset(orig_dst, bld, iter * 2 + c),
2636 offset(dst, bld, c));
2640 /* Copy the temporary to the destination to deal with writemasking.
2642 * Also attempt to deal with gl_PointSize being in the .w component.
2644 if (inst->offset == 0 && indirect_offset.file == BAD_FILE) {
2645 assert(type_sz(dst.type) < 8);
2646 inst->dst = bld.vgrf(dst.type, 4);
2647 inst->size_written = 4 * REG_SIZE;
2648 bld.MOV(dst, offset(inst->dst, bld, 3));
2651 /* If we are loading double data and we need a second read message
2652 * adjust the write offset
2654 if (num_iterations > 1) {
2655 num_components = instr->num_components - 2;
2662 case nir_intrinsic_load_output:
2663 case nir_intrinsic_load_per_vertex_output: {
2664 fs_reg indirect_offset = get_indirect_offset(instr);
2665 unsigned imm_offset = instr->const_index[0];
2666 unsigned first_component = nir_intrinsic_component(instr);
2669 if (indirect_offset.file == BAD_FILE) {
2670 /* Replicate the patch handle to all enabled channels */
2671 fs_reg patch_handle = bld.vgrf(BRW_REGISTER_TYPE_UD, 1);
2672 bld.MOV(patch_handle,
2673 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD));
2676 if (first_component != 0) {
2677 unsigned read_components =
2678 instr->num_components + first_component;
2679 fs_reg tmp = bld.vgrf(dst.type, read_components);
2680 inst = bld.emit(SHADER_OPCODE_URB_READ_SIMD8, tmp,
2682 inst->size_written = read_components * REG_SIZE;
2683 for (unsigned i = 0; i < instr->num_components; i++) {
2684 bld.MOV(offset(dst, bld, i),
2685 offset(tmp, bld, i + first_component));
2688 inst = bld.emit(SHADER_OPCODE_URB_READ_SIMD8, dst,
2690 inst->size_written = instr->num_components * REG_SIZE;
2692 inst->offset = imm_offset;
2696 /* Indirect indexing - use per-slot offsets as well. */
2697 const fs_reg srcs[] = {
2698 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD),
2701 fs_reg payload = bld.vgrf(BRW_REGISTER_TYPE_UD, 2);
2702 bld.LOAD_PAYLOAD(payload, srcs, ARRAY_SIZE(srcs), 0);
2703 if (first_component != 0) {
2704 unsigned read_components =
2705 instr->num_components + first_component;
2706 fs_reg tmp = bld.vgrf(dst.type, read_components);
2707 inst = bld.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT, tmp,
2709 inst->size_written = read_components * REG_SIZE;
2710 for (unsigned i = 0; i < instr->num_components; i++) {
2711 bld.MOV(offset(dst, bld, i),
2712 offset(tmp, bld, i + first_component));
2715 inst = bld.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT, dst,
2717 inst->size_written = instr->num_components * REG_SIZE;
2719 inst->offset = imm_offset;
2725 case nir_intrinsic_store_output:
2726 case nir_intrinsic_store_per_vertex_output: {
2727 fs_reg value = get_nir_src(instr->src[0]);
2728 bool is_64bit = (instr->src[0].is_ssa ?
2729 instr->src[0].ssa->bit_size : instr->src[0].reg.reg->bit_size) == 64;
2730 fs_reg indirect_offset = get_indirect_offset(instr);
2731 unsigned imm_offset = instr->const_index[0];
2732 unsigned mask = instr->const_index[1];
2733 unsigned header_regs = 0;
2735 srcs[header_regs++] = retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD);
2737 if (indirect_offset.file != BAD_FILE) {
2738 srcs[header_regs++] = indirect_offset;
2744 unsigned num_components = util_last_bit(mask);
2747 /* We can only pack two 64-bit components in a single message, so send
2748 * 2 messages if we have more components
2750 unsigned num_iterations = 1;
2751 unsigned iter_components = num_components;
2752 unsigned first_component = nir_intrinsic_component(instr);
2754 first_component = first_component / 2;
2755 if (instr->num_components > 2) {
2757 iter_components = 2;
2761 mask = mask << first_component;
2763 for (unsigned iter = 0; iter < num_iterations; iter++) {
2764 if (!is_64bit && mask != WRITEMASK_XYZW) {
2765 srcs[header_regs++] = brw_imm_ud(mask << 16);
2766 opcode = indirect_offset.file != BAD_FILE ?
2767 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT :
2768 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED;
2769 } else if (is_64bit && ((mask & WRITEMASK_XY) != WRITEMASK_XY)) {
2770 /* Expand the 64-bit mask to 32-bit channels. We only handle
2771 * two channels in each iteration, so we only care about X/Y.
2773 unsigned mask32 = 0;
2774 if (mask & WRITEMASK_X)
2775 mask32 |= WRITEMASK_XY;
2776 if (mask & WRITEMASK_Y)
2777 mask32 |= WRITEMASK_ZW;
2779 /* If the mask does not include any of the channels X or Y there
2780 * is nothing to do in this iteration. Move on to the next couple
2781 * of 64-bit channels.
2789 srcs[header_regs++] = brw_imm_ud(mask32 << 16);
2790 opcode = indirect_offset.file != BAD_FILE ?
2791 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT :
2792 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED;
2794 opcode = indirect_offset.file != BAD_FILE ?
2795 SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT :
2796 SHADER_OPCODE_URB_WRITE_SIMD8;
2799 for (unsigned i = 0; i < iter_components; i++) {
2800 if (!(mask & (1 << (i + first_component))))
2804 srcs[header_regs + i + first_component] = offset(value, bld, i);
2806 /* We need to shuffle the 64-bit data to match the layout
2807 * expected by our 32-bit URB write messages. We use a temporary
2810 unsigned channel = iter * 2 + i;
2811 fs_reg dest = shuffle_64bit_data_for_32bit_write(bld,
2812 offset(value, bld, channel), 1);
2814 srcs[header_regs + (i + first_component) * 2] = dest;
2815 srcs[header_regs + (i + first_component) * 2 + 1] =
2816 offset(dest, bld, 1);
2821 header_regs + (is_64bit ? 2 * iter_components : iter_components) +
2822 (is_64bit ? 2 * first_component : first_component);
2824 bld.vgrf(BRW_REGISTER_TYPE_UD, mlen);
2825 bld.LOAD_PAYLOAD(payload, srcs, mlen, header_regs);
2827 fs_inst *inst = bld.emit(opcode, bld.null_reg_ud(), payload);
2828 inst->offset = imm_offset;
2831 /* If this is a 64-bit attribute, select the next two 64-bit channels
2832 * to be handled in the next iteration.
2843 nir_emit_intrinsic(bld, instr);
2849 fs_visitor::nir_emit_tes_intrinsic(const fs_builder &bld,
2850 nir_intrinsic_instr *instr)
2852 assert(stage == MESA_SHADER_TESS_EVAL);
2853 struct brw_tes_prog_data *tes_prog_data = brw_tes_prog_data(prog_data);
2856 if (nir_intrinsic_infos[instr->intrinsic].has_dest)
2857 dest = get_nir_dest(instr->dest);
2859 switch (instr->intrinsic) {
2860 case nir_intrinsic_load_primitive_id:
2861 bld.MOV(dest, fs_reg(brw_vec1_grf(0, 1)));
2863 case nir_intrinsic_load_tess_coord:
2864 /* gl_TessCoord is part of the payload in g1-3 */
2865 for (unsigned i = 0; i < 3; i++) {
2866 bld.MOV(offset(dest, bld, i), fs_reg(brw_vec8_grf(1 + i, 0)));
2870 case nir_intrinsic_load_input:
2871 case nir_intrinsic_load_per_vertex_input: {
2872 fs_reg indirect_offset = get_indirect_offset(instr);
2873 unsigned imm_offset = instr->const_index[0];
2874 unsigned first_component = nir_intrinsic_component(instr);
2876 if (type_sz(dest.type) == 8) {
2877 first_component = first_component / 2;
2881 if (indirect_offset.file == BAD_FILE) {
2882 /* Arbitrarily only push up to 32 vec4 slots worth of data,
2883 * which is 16 registers (since each holds 2 vec4 slots).
2885 unsigned slot_count = 1;
2886 if (type_sz(dest.type) == 8 && instr->num_components > 2)
2889 const unsigned max_push_slots = 32;
2890 if (imm_offset + slot_count <= max_push_slots) {
2891 fs_reg src = fs_reg(ATTR, imm_offset / 2, dest.type);
2892 for (int i = 0; i < instr->num_components; i++) {
2893 unsigned comp = 16 / type_sz(dest.type) * (imm_offset % 2) +
2894 i + first_component;
2895 bld.MOV(offset(dest, bld, i), component(src, comp));
2898 tes_prog_data->base.urb_read_length =
2899 MAX2(tes_prog_data->base.urb_read_length,
2900 DIV_ROUND_UP(imm_offset + slot_count, 2));
2902 /* Replicate the patch handle to all enabled channels */
2903 const fs_reg srcs[] = {
2904 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD)
2906 fs_reg patch_handle = bld.vgrf(BRW_REGISTER_TYPE_UD, 1);
2907 bld.LOAD_PAYLOAD(patch_handle, srcs, ARRAY_SIZE(srcs), 0);
2909 if (first_component != 0) {
2910 unsigned read_components =
2911 instr->num_components + first_component;
2912 fs_reg tmp = bld.vgrf(dest.type, read_components);
2913 inst = bld.emit(SHADER_OPCODE_URB_READ_SIMD8, tmp,
2915 inst->size_written = read_components * REG_SIZE;
2916 for (unsigned i = 0; i < instr->num_components; i++) {
2917 bld.MOV(offset(dest, bld, i),
2918 offset(tmp, bld, i + first_component));
2921 inst = bld.emit(SHADER_OPCODE_URB_READ_SIMD8, dest,
2923 inst->size_written = instr->num_components * REG_SIZE;
2926 inst->offset = imm_offset;
2929 /* Indirect indexing - use per-slot offsets as well. */
2931 /* We can only read two double components with each URB read, so
2932 * we send two read messages in that case, each one loading up to
2933 * two double components.
2935 unsigned num_iterations = 1;
2936 unsigned num_components = instr->num_components;
2937 fs_reg orig_dest = dest;
2938 if (type_sz(dest.type) == 8) {
2939 if (instr->num_components > 2) {
2943 fs_reg tmp = fs_reg(VGRF, alloc.allocate(4), dest.type);
2947 for (unsigned iter = 0; iter < num_iterations; iter++) {
2948 const fs_reg srcs[] = {
2949 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD),
2952 fs_reg payload = bld.vgrf(BRW_REGISTER_TYPE_UD, 2);
2953 bld.LOAD_PAYLOAD(payload, srcs, ARRAY_SIZE(srcs), 0);
2955 if (first_component != 0) {
2956 unsigned read_components =
2957 num_components + first_component;
2958 fs_reg tmp = bld.vgrf(dest.type, read_components);
2959 inst = bld.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT, tmp,
2961 for (unsigned i = 0; i < num_components; i++) {
2962 bld.MOV(offset(dest, bld, i),
2963 offset(tmp, bld, i + first_component));
2966 inst = bld.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT, dest,
2970 inst->offset = imm_offset;
2971 inst->size_written = (num_components + first_component) *
2972 inst->dst.component_size(inst->exec_size);
2974 /* If we are reading 64-bit data using 32-bit read messages we need
2975 * build proper 64-bit data elements by shuffling the low and high
2976 * 32-bit components around like we do for other things like UBOs
2979 if (type_sz(dest.type) == 8) {
2980 shuffle_32bit_load_result_to_64bit_data(
2981 bld, dest, retype(dest, BRW_REGISTER_TYPE_F), num_components);
2983 for (unsigned c = 0; c < num_components; c++) {
2984 bld.MOV(offset(orig_dest, bld, iter * 2 + c),
2985 offset(dest, bld, c));
2989 /* If we are loading double data and we need a second read message
2992 if (num_iterations > 1) {
2993 num_components = instr->num_components - 2;
3001 nir_emit_intrinsic(bld, instr);
3007 fs_visitor::nir_emit_gs_intrinsic(const fs_builder &bld,
3008 nir_intrinsic_instr *instr)
3010 assert(stage == MESA_SHADER_GEOMETRY);
3011 fs_reg indirect_offset;
3014 if (nir_intrinsic_infos[instr->intrinsic].has_dest)
3015 dest = get_nir_dest(instr->dest);
3017 switch (instr->intrinsic) {
3018 case nir_intrinsic_load_primitive_id:
3019 assert(stage == MESA_SHADER_GEOMETRY);
3020 assert(brw_gs_prog_data(prog_data)->include_primitive_id);
3021 bld.MOV(retype(dest, BRW_REGISTER_TYPE_UD),
3022 retype(fs_reg(brw_vec8_grf(2, 0)), BRW_REGISTER_TYPE_UD));
3025 case nir_intrinsic_load_input:
3026 unreachable("load_input intrinsics are invalid for the GS stage");
3028 case nir_intrinsic_load_per_vertex_input:
3029 emit_gs_input_load(dest, instr->src[0], instr->const_index[0],
3030 instr->src[1], instr->num_components,
3031 nir_intrinsic_component(instr));
3034 case nir_intrinsic_emit_vertex_with_counter:
3035 emit_gs_vertex(instr->src[0], instr->const_index[0]);
3038 case nir_intrinsic_end_primitive_with_counter:
3039 emit_gs_end_primitive(instr->src[0]);
3042 case nir_intrinsic_set_vertex_count:
3043 bld.MOV(this->final_gs_vertex_count, get_nir_src(instr->src[0]));
3046 case nir_intrinsic_load_invocation_id: {
3047 fs_reg val = nir_system_values[SYSTEM_VALUE_INVOCATION_ID];
3048 assert(val.file != BAD_FILE);
3049 dest.type = val.type;
3055 nir_emit_intrinsic(bld, instr);
3061 * Fetch the current render target layer index.
3064 fetch_render_target_array_index(const fs_builder &bld)
3066 if (bld.shader->devinfo->gen >= 6) {
3067 /* The render target array index is provided in the thread payload as
3068 * bits 26:16 of r0.0.
3070 const fs_reg idx = bld.vgrf(BRW_REGISTER_TYPE_UD);
3071 bld.AND(idx, brw_uw1_reg(BRW_GENERAL_REGISTER_FILE, 0, 1),
3075 /* Pre-SNB we only ever render into the first layer of the framebuffer
3076 * since layered rendering is not implemented.
3078 return brw_imm_ud(0);
3083 * Fake non-coherent framebuffer read implemented using TXF to fetch from the
3084 * framebuffer at the current fragment coordinates and sample index.
3087 fs_visitor::emit_non_coherent_fb_read(const fs_builder &bld, const fs_reg &dst,
3090 const struct gen_device_info *devinfo = bld.shader->devinfo;
3092 assert(bld.shader->stage == MESA_SHADER_FRAGMENT);
3093 const brw_wm_prog_key *wm_key =
3094 reinterpret_cast<const brw_wm_prog_key *>(key);
3095 assert(!wm_key->coherent_fb_fetch);
3096 const struct brw_wm_prog_data *wm_prog_data =
3097 brw_wm_prog_data(stage_prog_data);
3099 /* Calculate the surface index relative to the start of the texture binding
3100 * table block, since that's what the texturing messages expect.
3102 const unsigned surface = target +
3103 wm_prog_data->binding_table.render_target_read_start -
3104 wm_prog_data->base.binding_table.texture_start;
3106 brw_mark_surface_used(
3107 bld.shader->stage_prog_data,
3108 wm_prog_data->binding_table.render_target_read_start + target);
3110 /* Calculate the fragment coordinates. */
3111 const fs_reg coords = bld.vgrf(BRW_REGISTER_TYPE_UD, 3);
3112 bld.MOV(offset(coords, bld, 0), pixel_x);
3113 bld.MOV(offset(coords, bld, 1), pixel_y);
3114 bld.MOV(offset(coords, bld, 2), fetch_render_target_array_index(bld));
3116 /* Calculate the sample index and MCS payload when multisampling. Luckily
3117 * the MCS fetch message behaves deterministically for UMS surfaces, so it
3118 * shouldn't be necessary to recompile based on whether the framebuffer is
3121 if (wm_key->multisample_fbo &&
3122 nir_system_values[SYSTEM_VALUE_SAMPLE_ID].file == BAD_FILE)
3123 nir_system_values[SYSTEM_VALUE_SAMPLE_ID] = *emit_sampleid_setup();
3125 const fs_reg sample = nir_system_values[SYSTEM_VALUE_SAMPLE_ID];
3126 const fs_reg mcs = wm_key->multisample_fbo ?
3127 emit_mcs_fetch(coords, 3, brw_imm_ud(surface)) : fs_reg();
3129 /* Use either a normal or a CMS texel fetch message depending on whether
3130 * the framebuffer is single or multisample. On SKL+ use the wide CMS
3131 * message just in case the framebuffer uses 16x multisampling, it should
3132 * be equivalent to the normal CMS fetch for lower multisampling modes.
3134 const opcode op = !wm_key->multisample_fbo ? SHADER_OPCODE_TXF_LOGICAL :
3135 devinfo->gen >= 9 ? SHADER_OPCODE_TXF_CMS_W_LOGICAL :
3136 SHADER_OPCODE_TXF_CMS_LOGICAL;
3138 /* Emit the instruction. */
3139 const fs_reg srcs[] = { coords, fs_reg(), brw_imm_ud(0), fs_reg(),
3141 brw_imm_ud(surface), brw_imm_ud(0),
3142 fs_reg(), brw_imm_ud(3), brw_imm_ud(0) };
3143 STATIC_ASSERT(ARRAY_SIZE(srcs) == TEX_LOGICAL_NUM_SRCS);
3145 fs_inst *inst = bld.emit(op, dst, srcs, ARRAY_SIZE(srcs));
3146 inst->size_written = 4 * inst->dst.component_size(inst->exec_size);
3152 * Actual coherent framebuffer read implemented using the native render target
3153 * read message. Requires SKL+.
3156 emit_coherent_fb_read(const fs_builder &bld, const fs_reg &dst, unsigned target)
3158 assert(bld.shader->devinfo->gen >= 9);
3159 fs_inst *inst = bld.emit(FS_OPCODE_FB_READ_LOGICAL, dst);
3160 inst->target = target;
3161 inst->size_written = 4 * inst->dst.component_size(inst->exec_size);
3167 alloc_temporary(const fs_builder &bld, unsigned size, fs_reg *regs, unsigned n)
3169 if (n && regs[0].file != BAD_FILE) {
3173 const fs_reg tmp = bld.vgrf(BRW_REGISTER_TYPE_F, size);
3175 for (unsigned i = 0; i < n; i++)
3183 alloc_frag_output(fs_visitor *v, unsigned location)
3185 assert(v->stage == MESA_SHADER_FRAGMENT);
3186 const brw_wm_prog_key *const key =
3187 reinterpret_cast<const brw_wm_prog_key *>(v->key);
3188 const unsigned l = GET_FIELD(location, BRW_NIR_FRAG_OUTPUT_LOCATION);
3189 const unsigned i = GET_FIELD(location, BRW_NIR_FRAG_OUTPUT_INDEX);
3191 if (i > 0 || (key->force_dual_color_blend && l == FRAG_RESULT_DATA1))
3192 return alloc_temporary(v->bld, 4, &v->dual_src_output, 1);
3194 else if (l == FRAG_RESULT_COLOR)
3195 return alloc_temporary(v->bld, 4, v->outputs,
3196 MAX2(key->nr_color_regions, 1));
3198 else if (l == FRAG_RESULT_DEPTH)
3199 return alloc_temporary(v->bld, 1, &v->frag_depth, 1);
3201 else if (l == FRAG_RESULT_STENCIL)
3202 return alloc_temporary(v->bld, 1, &v->frag_stencil, 1);
3204 else if (l == FRAG_RESULT_SAMPLE_MASK)
3205 return alloc_temporary(v->bld, 1, &v->sample_mask, 1);
3207 else if (l >= FRAG_RESULT_DATA0 &&
3208 l < FRAG_RESULT_DATA0 + BRW_MAX_DRAW_BUFFERS)
3209 return alloc_temporary(v->bld, 4,
3210 &v->outputs[l - FRAG_RESULT_DATA0], 1);
3213 unreachable("Invalid location");
3217 fs_visitor::nir_emit_fs_intrinsic(const fs_builder &bld,
3218 nir_intrinsic_instr *instr)
3220 assert(stage == MESA_SHADER_FRAGMENT);
3223 if (nir_intrinsic_infos[instr->intrinsic].has_dest)
3224 dest = get_nir_dest(instr->dest);
3226 switch (instr->intrinsic) {
3227 case nir_intrinsic_load_front_face:
3228 bld.MOV(retype(dest, BRW_REGISTER_TYPE_D),
3229 *emit_frontfacing_interpolation());
3232 case nir_intrinsic_load_sample_pos: {
3233 fs_reg sample_pos = nir_system_values[SYSTEM_VALUE_SAMPLE_POS];
3234 assert(sample_pos.file != BAD_FILE);
3235 dest.type = sample_pos.type;
3236 bld.MOV(dest, sample_pos);
3237 bld.MOV(offset(dest, bld, 1), offset(sample_pos, bld, 1));
3241 case nir_intrinsic_load_layer_id:
3242 dest.type = BRW_REGISTER_TYPE_UD;
3243 bld.MOV(dest, fetch_render_target_array_index(bld));
3246 case nir_intrinsic_load_helper_invocation:
3247 case nir_intrinsic_load_sample_mask_in:
3248 case nir_intrinsic_load_sample_id: {
3249 gl_system_value sv = nir_system_value_from_intrinsic(instr->intrinsic);
3250 fs_reg val = nir_system_values[sv];
3251 assert(val.file != BAD_FILE);
3252 dest.type = val.type;
3257 case nir_intrinsic_store_output: {
3258 const fs_reg src = get_nir_src(instr->src[0]);
3259 const nir_const_value *const_offset = nir_src_as_const_value(instr->src[1]);
3260 assert(const_offset && "Indirect output stores not allowed");
3261 const unsigned location = nir_intrinsic_base(instr) +
3262 SET_FIELD(const_offset->u32[0], BRW_NIR_FRAG_OUTPUT_LOCATION);
3263 const fs_reg new_dest = retype(alloc_frag_output(this, location),
3266 for (unsigned j = 0; j < instr->num_components; j++)
3267 bld.MOV(offset(new_dest, bld, nir_intrinsic_component(instr) + j),
3268 offset(src, bld, j));
3273 case nir_intrinsic_load_output: {
3274 const unsigned l = GET_FIELD(nir_intrinsic_base(instr),
3275 BRW_NIR_FRAG_OUTPUT_LOCATION);
3276 assert(l >= FRAG_RESULT_DATA0);
3277 nir_const_value *const_offset = nir_src_as_const_value(instr->src[0]);
3278 assert(const_offset && "Indirect output loads not allowed");
3279 const unsigned target = l - FRAG_RESULT_DATA0 + const_offset->u32[0];
3280 const fs_reg tmp = bld.vgrf(dest.type, 4);
3282 if (reinterpret_cast<const brw_wm_prog_key *>(key)->coherent_fb_fetch)
3283 emit_coherent_fb_read(bld, tmp, target);
3285 emit_non_coherent_fb_read(bld, tmp, target);
3287 for (unsigned j = 0; j < instr->num_components; j++) {
3288 bld.MOV(offset(dest, bld, j),
3289 offset(tmp, bld, nir_intrinsic_component(instr) + j));
3295 case nir_intrinsic_discard:
3296 case nir_intrinsic_discard_if: {
3297 /* We track our discarded pixels in f0.1. By predicating on it, we can
3298 * update just the flag bits that aren't yet discarded. If there's no
3299 * condition, we emit a CMP of g0 != g0, so all currently executing
3300 * channels will get turned off.
3303 if (instr->intrinsic == nir_intrinsic_discard_if) {
3304 cmp = bld.CMP(bld.null_reg_f(), get_nir_src(instr->src[0]),
3305 brw_imm_d(0), BRW_CONDITIONAL_Z);
3307 fs_reg some_reg = fs_reg(retype(brw_vec8_grf(0, 0),
3308 BRW_REGISTER_TYPE_UW));
3309 cmp = bld.CMP(bld.null_reg_f(), some_reg, some_reg, BRW_CONDITIONAL_NZ);
3311 cmp->predicate = BRW_PREDICATE_NORMAL;
3312 cmp->flag_subreg = 1;
3314 if (devinfo->gen >= 6) {
3315 emit_discard_jump();
3320 case nir_intrinsic_load_input: {
3321 /* load_input is only used for flat inputs */
3322 unsigned base = nir_intrinsic_base(instr);
3323 unsigned component = nir_intrinsic_component(instr);
3324 unsigned num_components = instr->num_components;
3325 enum brw_reg_type type = dest.type;
3327 /* Special case fields in the VUE header */
3328 if (base == VARYING_SLOT_LAYER)
3330 else if (base == VARYING_SLOT_VIEWPORT)
3333 if (nir_dest_bit_size(instr->dest) == 64) {
3334 /* const_index is in 32-bit type size units that could not be aligned
3335 * with DF. We need to read the double vector as if it was a float
3336 * vector of twice the number of components to fetch the right data.
3338 type = BRW_REGISTER_TYPE_F;
3339 num_components *= 2;
3342 for (unsigned int i = 0; i < num_components; i++) {
3343 struct brw_reg interp = interp_reg(base, component + i);
3344 interp = suboffset(interp, 3);
3345 bld.emit(FS_OPCODE_CINTERP, offset(retype(dest, type), bld, i),
3346 retype(fs_reg(interp), type));
3349 if (nir_dest_bit_size(instr->dest) == 64) {
3350 shuffle_32bit_load_result_to_64bit_data(bld,
3353 instr->num_components);
3358 case nir_intrinsic_load_barycentric_pixel:
3359 case nir_intrinsic_load_barycentric_centroid:
3360 case nir_intrinsic_load_barycentric_sample:
3361 /* Do nothing - load_interpolated_input handling will handle it later. */
3364 case nir_intrinsic_load_barycentric_at_sample: {
3365 const glsl_interp_mode interpolation =
3366 (enum glsl_interp_mode) nir_intrinsic_interp_mode(instr);
3368 nir_const_value *const_sample = nir_src_as_const_value(instr->src[0]);
3371 unsigned msg_data = const_sample->i32[0] << 4;
3373 emit_pixel_interpolater_send(bld,
3374 FS_OPCODE_INTERPOLATE_AT_SAMPLE,
3377 brw_imm_ud(msg_data),
3380 const fs_reg sample_src = retype(get_nir_src(instr->src[0]),
3381 BRW_REGISTER_TYPE_UD);
3383 if (nir_src_is_dynamically_uniform(instr->src[0])) {
3384 const fs_reg sample_id = bld.emit_uniformize(sample_src);
3385 const fs_reg msg_data = vgrf(glsl_type::uint_type);
3386 bld.exec_all().group(1, 0)
3387 .SHL(msg_data, sample_id, brw_imm_ud(4u));
3388 emit_pixel_interpolater_send(bld,
3389 FS_OPCODE_INTERPOLATE_AT_SAMPLE,
3395 /* Make a loop that sends a message to the pixel interpolater
3396 * for the sample number in each live channel. If there are
3397 * multiple channels with the same sample number then these
3398 * will be handled simultaneously with a single interation of
3401 bld.emit(BRW_OPCODE_DO);
3403 /* Get the next live sample number into sample_id_reg */
3404 const fs_reg sample_id = bld.emit_uniformize(sample_src);
3406 /* Set the flag register so that we can perform the send
3407 * message on all channels that have the same sample number
3409 bld.CMP(bld.null_reg_ud(),
3410 sample_src, sample_id,
3411 BRW_CONDITIONAL_EQ);
3412 const fs_reg msg_data = vgrf(glsl_type::uint_type);
3413 bld.exec_all().group(1, 0)
3414 .SHL(msg_data, sample_id, brw_imm_ud(4u));
3416 emit_pixel_interpolater_send(bld,
3417 FS_OPCODE_INTERPOLATE_AT_SAMPLE,
3422 set_predicate(BRW_PREDICATE_NORMAL, inst);
3424 /* Continue the loop if there are any live channels left */
3425 set_predicate_inv(BRW_PREDICATE_NORMAL,
3427 bld.emit(BRW_OPCODE_WHILE));
3433 case nir_intrinsic_load_barycentric_at_offset: {
3434 const glsl_interp_mode interpolation =
3435 (enum glsl_interp_mode) nir_intrinsic_interp_mode(instr);
3437 nir_const_value *const_offset = nir_src_as_const_value(instr->src[0]);
3440 unsigned off_x = MIN2((int)(const_offset->f32[0] * 16), 7) & 0xf;
3441 unsigned off_y = MIN2((int)(const_offset->f32[1] * 16), 7) & 0xf;
3443 emit_pixel_interpolater_send(bld,
3444 FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET,
3447 brw_imm_ud(off_x | (off_y << 4)),
3450 fs_reg src = vgrf(glsl_type::ivec2_type);
3451 fs_reg offset_src = retype(get_nir_src(instr->src[0]),
3452 BRW_REGISTER_TYPE_F);
3453 for (int i = 0; i < 2; i++) {
3454 fs_reg temp = vgrf(glsl_type::float_type);
3455 bld.MUL(temp, offset(offset_src, bld, i), brw_imm_f(16.0f));
3456 fs_reg itemp = vgrf(glsl_type::int_type);
3458 bld.MOV(itemp, temp);
3460 /* Clamp the upper end of the range to +7/16.
3461 * ARB_gpu_shader5 requires that we support a maximum offset
3462 * of +0.5, which isn't representable in a S0.4 value -- if
3463 * we didn't clamp it, we'd end up with -8/16, which is the
3464 * opposite of what the shader author wanted.
3466 * This is legal due to ARB_gpu_shader5's quantization
3469 * "Not all values of <offset> may be supported; x and y
3470 * offsets may be rounded to fixed-point values with the
3471 * number of fraction bits given by the
3472 * implementation-dependent constant
3473 * FRAGMENT_INTERPOLATION_OFFSET_BITS"
3475 set_condmod(BRW_CONDITIONAL_L,
3476 bld.SEL(offset(src, bld, i), itemp, brw_imm_d(7)));
3479 const enum opcode opcode = FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET;
3480 emit_pixel_interpolater_send(bld,
3490 case nir_intrinsic_load_interpolated_input: {
3491 if (nir_intrinsic_base(instr) == VARYING_SLOT_POS) {
3492 emit_fragcoord_interpolation(dest);
3496 assert(instr->src[0].ssa &&
3497 instr->src[0].ssa->parent_instr->type == nir_instr_type_intrinsic);
3498 nir_intrinsic_instr *bary_intrinsic =
3499 nir_instr_as_intrinsic(instr->src[0].ssa->parent_instr);
3500 nir_intrinsic_op bary_intrin = bary_intrinsic->intrinsic;
3501 enum glsl_interp_mode interp_mode =
3502 (enum glsl_interp_mode) nir_intrinsic_interp_mode(bary_intrinsic);
3505 if (bary_intrin == nir_intrinsic_load_barycentric_at_offset ||
3506 bary_intrin == nir_intrinsic_load_barycentric_at_sample) {
3507 /* Use the result of the PI message */
3508 dst_xy = retype(get_nir_src(instr->src[0]), BRW_REGISTER_TYPE_F);
3510 /* Use the delta_xy values computed from the payload */
3511 enum brw_barycentric_mode bary =
3512 brw_barycentric_mode(interp_mode, bary_intrin);
3514 dst_xy = this->delta_xy[bary];
3517 for (unsigned int i = 0; i < instr->num_components; i++) {
3519 fs_reg(interp_reg(nir_intrinsic_base(instr),
3520 nir_intrinsic_component(instr) + i));
3521 interp.type = BRW_REGISTER_TYPE_F;
3522 dest.type = BRW_REGISTER_TYPE_F;
3524 if (devinfo->gen < 6 && interp_mode == INTERP_MODE_SMOOTH) {
3525 fs_reg tmp = vgrf(glsl_type::float_type);
3526 bld.emit(FS_OPCODE_LINTERP, tmp, dst_xy, interp);
3527 bld.MUL(offset(dest, bld, i), tmp, this->pixel_w);
3529 bld.emit(FS_OPCODE_LINTERP, offset(dest, bld, i), dst_xy, interp);
3536 nir_emit_intrinsic(bld, instr);
3542 fs_visitor::nir_emit_cs_intrinsic(const fs_builder &bld,
3543 nir_intrinsic_instr *instr)
3545 assert(stage == MESA_SHADER_COMPUTE);
3546 struct brw_cs_prog_data *cs_prog_data = brw_cs_prog_data(prog_data);
3549 if (nir_intrinsic_infos[instr->intrinsic].has_dest)
3550 dest = get_nir_dest(instr->dest);
3552 switch (instr->intrinsic) {
3553 case nir_intrinsic_barrier:
3555 cs_prog_data->uses_barrier = true;
3558 case nir_intrinsic_load_subgroup_id:
3559 bld.MOV(retype(dest, BRW_REGISTER_TYPE_UD), subgroup_id);
3562 case nir_intrinsic_load_local_invocation_id:
3563 case nir_intrinsic_load_work_group_id: {
3564 gl_system_value sv = nir_system_value_from_intrinsic(instr->intrinsic);
3565 fs_reg val = nir_system_values[sv];
3566 assert(val.file != BAD_FILE);
3567 dest.type = val.type;
3568 for (unsigned i = 0; i < 3; i++)
3569 bld.MOV(offset(dest, bld, i), offset(val, bld, i));
3573 case nir_intrinsic_load_num_work_groups: {
3574 const unsigned surface =
3575 cs_prog_data->binding_table.work_groups_start;
3577 cs_prog_data->uses_num_work_groups = true;
3579 fs_reg surf_index = brw_imm_ud(surface);
3580 brw_mark_surface_used(prog_data, surface);
3582 /* Read the 3 GLuint components of gl_NumWorkGroups */
3583 for (unsigned i = 0; i < 3; i++) {
3584 fs_reg read_result =
3585 emit_untyped_read(bld, surf_index,
3587 1 /* dims */, 1 /* size */,
3588 BRW_PREDICATE_NONE);
3589 read_result.type = dest.type;
3590 bld.MOV(dest, read_result);
3591 dest = offset(dest, bld, 1);
3596 case nir_intrinsic_shared_atomic_add:
3597 nir_emit_shared_atomic(bld, BRW_AOP_ADD, instr);
3599 case nir_intrinsic_shared_atomic_imin:
3600 nir_emit_shared_atomic(bld, BRW_AOP_IMIN, instr);
3602 case nir_intrinsic_shared_atomic_umin:
3603 nir_emit_shared_atomic(bld, BRW_AOP_UMIN, instr);
3605 case nir_intrinsic_shared_atomic_imax:
3606 nir_emit_shared_atomic(bld, BRW_AOP_IMAX, instr);
3608 case nir_intrinsic_shared_atomic_umax:
3609 nir_emit_shared_atomic(bld, BRW_AOP_UMAX, instr);
3611 case nir_intrinsic_shared_atomic_and:
3612 nir_emit_shared_atomic(bld, BRW_AOP_AND, instr);
3614 case nir_intrinsic_shared_atomic_or:
3615 nir_emit_shared_atomic(bld, BRW_AOP_OR, instr);
3617 case nir_intrinsic_shared_atomic_xor:
3618 nir_emit_shared_atomic(bld, BRW_AOP_XOR, instr);
3620 case nir_intrinsic_shared_atomic_exchange:
3621 nir_emit_shared_atomic(bld, BRW_AOP_MOV, instr);
3623 case nir_intrinsic_shared_atomic_comp_swap:
3624 nir_emit_shared_atomic(bld, BRW_AOP_CMPWR, instr);
3627 case nir_intrinsic_load_shared: {
3628 assert(devinfo->gen >= 7);
3630 fs_reg surf_index = brw_imm_ud(GEN7_BTI_SLM);
3632 /* Get the offset to read from */
3634 nir_const_value *const_offset = nir_src_as_const_value(instr->src[0]);
3636 offset_reg = brw_imm_ud(instr->const_index[0] + const_offset->u32[0]);
3638 offset_reg = vgrf(glsl_type::uint_type);
3640 retype(get_nir_src(instr->src[0]), BRW_REGISTER_TYPE_UD),
3641 brw_imm_ud(instr->const_index[0]));
3644 /* Read the vector */
3645 do_untyped_vector_read(bld, dest, surf_index, offset_reg,
3646 instr->num_components);
3650 case nir_intrinsic_store_shared: {
3651 assert(devinfo->gen >= 7);
3654 fs_reg surf_index = brw_imm_ud(GEN7_BTI_SLM);
3657 fs_reg val_reg = get_nir_src(instr->src[0]);
3660 unsigned writemask = instr->const_index[1];
3662 /* get_nir_src() retypes to integer. Be wary of 64-bit types though
3663 * since the untyped writes below operate in units of 32-bits, which
3664 * means that we need to write twice as many components each time.
3665 * Also, we have to suffle 64-bit data to be in the appropriate layout
3666 * expected by our 32-bit write messages.
3668 unsigned type_size = 4;
3669 if (nir_src_bit_size(instr->src[0]) == 64) {
3671 val_reg = shuffle_64bit_data_for_32bit_write(bld,
3672 val_reg, instr->num_components);
3675 unsigned type_slots = type_size / 4;
3677 /* Combine groups of consecutive enabled channels in one write
3678 * message. We use ffs to find the first enabled channel and then ffs on
3679 * the bit-inverse, down-shifted writemask to determine the length of
3680 * the block of enabled bits.
3683 unsigned first_component = ffs(writemask) - 1;
3684 unsigned length = ffs(~(writemask >> first_component)) - 1;
3686 /* We can't write more than 2 64-bit components at once. Limit the
3687 * length of the write to what we can do and let the next iteration
3691 length = MIN2(2, length);
3694 nir_const_value *const_offset = nir_src_as_const_value(instr->src[1]);
3696 offset_reg = brw_imm_ud(instr->const_index[0] + const_offset->u32[0] +
3697 type_size * first_component);
3699 offset_reg = vgrf(glsl_type::uint_type);
3701 retype(get_nir_src(instr->src[1]), BRW_REGISTER_TYPE_UD),
3702 brw_imm_ud(instr->const_index[0] + type_size * first_component));
3705 emit_untyped_write(bld, surf_index, offset_reg,
3706 offset(val_reg, bld, first_component * type_slots),
3707 1 /* dims */, length * type_slots,
3708 BRW_PREDICATE_NONE);
3710 /* Clear the bits in the writemask that we just wrote, then try
3711 * again to see if more channels are left.
3713 writemask &= (15 << (first_component + length));
3720 nir_emit_intrinsic(bld, instr);
3726 brw_nir_reduction_op_identity(const fs_builder &bld,
3727 nir_op op, brw_reg_type type)
3729 nir_const_value value = nir_alu_binop_identity(op, type_sz(type) * 8);
3730 switch (type_sz(type)) {
3732 assert(type != BRW_REGISTER_TYPE_HF);
3733 return retype(brw_imm_uw(value.u16[0]), type);
3735 return retype(brw_imm_ud(value.u32[0]), type);
3737 if (type == BRW_REGISTER_TYPE_DF)
3738 return setup_imm_df(bld, value.f64[0]);
3740 return retype(brw_imm_u64(value.u64[0]), type);
3742 unreachable("Invalid type size");
3747 brw_op_for_nir_reduction_op(nir_op op)
3750 case nir_op_iadd: return BRW_OPCODE_ADD;
3751 case nir_op_fadd: return BRW_OPCODE_ADD;
3752 case nir_op_imul: return BRW_OPCODE_MUL;
3753 case nir_op_fmul: return BRW_OPCODE_MUL;
3754 case nir_op_imin: return BRW_OPCODE_SEL;
3755 case nir_op_umin: return BRW_OPCODE_SEL;
3756 case nir_op_fmin: return BRW_OPCODE_SEL;
3757 case nir_op_imax: return BRW_OPCODE_SEL;
3758 case nir_op_umax: return BRW_OPCODE_SEL;
3759 case nir_op_fmax: return BRW_OPCODE_SEL;
3760 case nir_op_iand: return BRW_OPCODE_AND;
3761 case nir_op_ior: return BRW_OPCODE_OR;
3762 case nir_op_ixor: return BRW_OPCODE_XOR;
3764 unreachable("Invalid reduction operation");
3768 static brw_conditional_mod
3769 brw_cond_mod_for_nir_reduction_op(nir_op op)
3772 case nir_op_iadd: return BRW_CONDITIONAL_NONE;
3773 case nir_op_fadd: return BRW_CONDITIONAL_NONE;
3774 case nir_op_imul: return BRW_CONDITIONAL_NONE;
3775 case nir_op_fmul: return BRW_CONDITIONAL_NONE;
3776 case nir_op_imin: return BRW_CONDITIONAL_L;
3777 case nir_op_umin: return BRW_CONDITIONAL_L;
3778 case nir_op_fmin: return BRW_CONDITIONAL_L;
3779 case nir_op_imax: return BRW_CONDITIONAL_GE;
3780 case nir_op_umax: return BRW_CONDITIONAL_GE;
3781 case nir_op_fmax: return BRW_CONDITIONAL_GE;
3782 case nir_op_iand: return BRW_CONDITIONAL_NONE;
3783 case nir_op_ior: return BRW_CONDITIONAL_NONE;
3784 case nir_op_ixor: return BRW_CONDITIONAL_NONE;
3786 unreachable("Invalid reduction operation");
3791 fs_visitor::nir_emit_intrinsic(const fs_builder &bld, nir_intrinsic_instr *instr)
3794 if (nir_intrinsic_infos[instr->intrinsic].has_dest)
3795 dest = get_nir_dest(instr->dest);
3797 switch (instr->intrinsic) {
3798 case nir_intrinsic_image_var_load:
3799 case nir_intrinsic_image_var_store:
3800 case nir_intrinsic_image_var_atomic_add:
3801 case nir_intrinsic_image_var_atomic_min:
3802 case nir_intrinsic_image_var_atomic_max:
3803 case nir_intrinsic_image_var_atomic_and:
3804 case nir_intrinsic_image_var_atomic_or:
3805 case nir_intrinsic_image_var_atomic_xor:
3806 case nir_intrinsic_image_var_atomic_exchange:
3807 case nir_intrinsic_image_var_atomic_comp_swap: {
3808 using namespace image_access;
3810 if (stage == MESA_SHADER_FRAGMENT &&
3811 instr->intrinsic != nir_intrinsic_image_var_load)
3812 brw_wm_prog_data(prog_data)->has_side_effects = true;
3814 /* Get the referenced image variable and type. */
3815 const nir_variable *var = instr->variables[0]->var;
3816 const glsl_type *type = var->type->without_array();
3817 const brw_reg_type base_type = get_image_base_type(type);
3819 /* Get some metadata from the image intrinsic. */
3820 const nir_intrinsic_info *info = &nir_intrinsic_infos[instr->intrinsic];
3821 const unsigned arr_dims = type->sampler_array ? 1 : 0;
3822 const unsigned surf_dims = type->coordinate_components() - arr_dims;
3823 const unsigned format = var->data.image.format;
3825 /* Get the arguments of the image intrinsic. */
3826 const fs_reg image = get_nir_image_deref(instr->variables[0]);
3827 const fs_reg addr = retype(get_nir_src(instr->src[0]),
3828 BRW_REGISTER_TYPE_UD);
3829 const fs_reg src0 = (info->num_srcs >= 3 ?
3830 retype(get_nir_src(instr->src[2]), base_type) :
3832 const fs_reg src1 = (info->num_srcs >= 4 ?
3833 retype(get_nir_src(instr->src[3]), base_type) :
3837 /* Emit an image load, store or atomic op. */
3838 if (instr->intrinsic == nir_intrinsic_image_var_load)
3839 tmp = emit_image_load(bld, image, addr, surf_dims, arr_dims, format);
3841 else if (instr->intrinsic == nir_intrinsic_image_var_store)
3842 emit_image_store(bld, image, addr, src0, surf_dims, arr_dims,
3843 var->data.image.write_only ? GL_NONE : format);
3846 tmp = emit_image_atomic(bld, image, addr, src0, src1,
3847 surf_dims, arr_dims, info->dest_components,
3848 get_image_atomic_op(instr->intrinsic, type));
3850 /* Assign the result. */
3851 for (unsigned c = 0; c < info->dest_components; ++c)
3852 bld.MOV(offset(retype(dest, base_type), bld, c),
3853 offset(tmp, bld, c));
3857 case nir_intrinsic_memory_barrier_atomic_counter:
3858 case nir_intrinsic_memory_barrier_buffer:
3859 case nir_intrinsic_memory_barrier_image:
3860 case nir_intrinsic_memory_barrier: {
3861 const fs_builder ubld = bld.group(8, 0);
3862 const fs_reg tmp = ubld.vgrf(BRW_REGISTER_TYPE_UD, 2);
3863 ubld.emit(SHADER_OPCODE_MEMORY_FENCE, tmp)
3864 ->size_written = 2 * REG_SIZE;
3868 case nir_intrinsic_group_memory_barrier:
3869 case nir_intrinsic_memory_barrier_shared:
3870 /* We treat these workgroup-level barriers as no-ops. This should be
3871 * safe at present and as long as:
3873 * - Memory access instructions are not subsequently reordered by the
3874 * compiler back-end.
3876 * - All threads from a given compute shader workgroup fit within a
3877 * single subslice and therefore talk to the same HDC shared unit
3878 * what supposedly guarantees ordering and coherency between threads
3879 * from the same workgroup. This may change in the future when we
3880 * start splitting workgroups across multiple subslices.
3882 * - The context is not in fault-and-stream mode, which could cause
3883 * memory transactions (including to SLM) prior to the barrier to be
3884 * replayed after the barrier if a pagefault occurs. This shouldn't
3885 * be a problem up to and including SKL because fault-and-stream is
3886 * not usable due to hardware issues, but that's likely to change in
3891 case nir_intrinsic_shader_clock: {
3892 /* We cannot do anything if there is an event, so ignore it for now */
3893 const fs_reg shader_clock = get_timestamp(bld);
3894 const fs_reg srcs[] = { component(shader_clock, 0),
3895 component(shader_clock, 1) };
3896 bld.LOAD_PAYLOAD(dest, srcs, ARRAY_SIZE(srcs), 0);
3900 case nir_intrinsic_image_var_size: {
3901 /* Get the referenced image variable and type. */
3902 const nir_variable *var = instr->variables[0]->var;
3903 const glsl_type *type = var->type->without_array();
3905 /* Get the size of the image. */
3906 const fs_reg image = get_nir_image_deref(instr->variables[0]);
3907 const fs_reg size = offset(image, bld, BRW_IMAGE_PARAM_SIZE_OFFSET);
3909 /* For 1DArray image types, the array index is stored in the Z component.
3910 * Fix this by swizzling the Z component to the Y component.
3912 const bool is_1d_array_image =
3913 type->sampler_dimensionality == GLSL_SAMPLER_DIM_1D &&
3914 type->sampler_array;
3916 /* For CubeArray images, we should count the number of cubes instead
3917 * of the number of faces. Fix it by dividing the (Z component) by 6.
3919 const bool is_cube_array_image =
3920 type->sampler_dimensionality == GLSL_SAMPLER_DIM_CUBE &&
3921 type->sampler_array;
3923 /* Copy all the components. */
3924 for (unsigned c = 0; c < instr->dest.ssa.num_components; ++c) {
3925 if ((int)c >= type->coordinate_components()) {
3926 bld.MOV(offset(retype(dest, BRW_REGISTER_TYPE_D), bld, c),
3928 } else if (c == 1 && is_1d_array_image) {
3929 bld.MOV(offset(retype(dest, BRW_REGISTER_TYPE_D), bld, c),
3930 offset(size, bld, 2));
3931 } else if (c == 2 && is_cube_array_image) {
3932 bld.emit(SHADER_OPCODE_INT_QUOTIENT,
3933 offset(retype(dest, BRW_REGISTER_TYPE_D), bld, c),
3934 offset(size, bld, c), brw_imm_d(6));
3936 bld.MOV(offset(retype(dest, BRW_REGISTER_TYPE_D), bld, c),
3937 offset(size, bld, c));
3944 case nir_intrinsic_image_var_samples:
3945 /* The driver does not support multi-sampled images. */
3946 bld.MOV(retype(dest, BRW_REGISTER_TYPE_D), brw_imm_d(1));
3949 case nir_intrinsic_load_uniform: {
3950 /* Offsets are in bytes but they should always aligned to
3953 assert(instr->const_index[0] % 4 == 0 ||
3954 instr->const_index[0] % type_sz(dest.type) == 0);
3956 fs_reg src(UNIFORM, instr->const_index[0] / 4, dest.type);
3958 nir_const_value *const_offset = nir_src_as_const_value(instr->src[0]);
3960 assert(const_offset->u32[0] % type_sz(dest.type) == 0);
3961 /* For 16-bit types we add the module of the const_index[0]
3962 * offset to access to not 32-bit aligned element
3964 src.offset = const_offset->u32[0] + instr->const_index[0] % 4;
3966 for (unsigned j = 0; j < instr->num_components; j++) {
3967 bld.MOV(offset(dest, bld, j), offset(src, bld, j));
3970 fs_reg indirect = retype(get_nir_src(instr->src[0]),
3971 BRW_REGISTER_TYPE_UD);
3973 /* We need to pass a size to the MOV_INDIRECT but we don't want it to
3974 * go past the end of the uniform. In order to keep the n'th
3975 * component from running past, we subtract off the size of all but
3976 * one component of the vector.
3978 assert(instr->const_index[1] >=
3979 instr->num_components * (int) type_sz(dest.type));
3980 unsigned read_size = instr->const_index[1] -
3981 (instr->num_components - 1) * type_sz(dest.type);
3983 bool supports_64bit_indirects =
3984 !devinfo->is_cherryview && !gen_device_info_is_9lp(devinfo);
3986 if (type_sz(dest.type) != 8 || supports_64bit_indirects) {
3987 for (unsigned j = 0; j < instr->num_components; j++) {
3988 bld.emit(SHADER_OPCODE_MOV_INDIRECT,
3989 offset(dest, bld, j), offset(src, bld, j),
3990 indirect, brw_imm_ud(read_size));
3993 const unsigned num_mov_indirects =
3994 type_sz(dest.type) / type_sz(BRW_REGISTER_TYPE_UD);
3995 /* We read a little bit less per MOV INDIRECT, as they are now
3996 * 32-bits ones instead of 64-bit. Fix read_size then.
3998 const unsigned read_size_32bit = read_size -
3999 (num_mov_indirects - 1) * type_sz(BRW_REGISTER_TYPE_UD);
4000 for (unsigned j = 0; j < instr->num_components; j++) {
4001 for (unsigned i = 0; i < num_mov_indirects; i++) {
4002 bld.emit(SHADER_OPCODE_MOV_INDIRECT,
4003 subscript(offset(dest, bld, j), BRW_REGISTER_TYPE_UD, i),
4004 subscript(offset(src, bld, j), BRW_REGISTER_TYPE_UD, i),
4005 indirect, brw_imm_ud(read_size_32bit));
4013 case nir_intrinsic_load_ubo: {
4014 nir_const_value *const_index = nir_src_as_const_value(instr->src[0]);
4018 const unsigned index = stage_prog_data->binding_table.ubo_start +
4019 const_index->u32[0];
4020 surf_index = brw_imm_ud(index);
4021 brw_mark_surface_used(prog_data, index);
4023 /* The block index is not a constant. Evaluate the index expression
4024 * per-channel and add the base UBO index; we have to select a value
4025 * from any live channel.
4027 surf_index = vgrf(glsl_type::uint_type);
4028 bld.ADD(surf_index, get_nir_src(instr->src[0]),
4029 brw_imm_ud(stage_prog_data->binding_table.ubo_start));
4030 surf_index = bld.emit_uniformize(surf_index);
4032 /* Assume this may touch any UBO. It would be nice to provide
4033 * a tighter bound, but the array information is already lowered away.
4035 brw_mark_surface_used(prog_data,
4036 stage_prog_data->binding_table.ubo_start +
4037 nir->info.num_ubos - 1);
4040 nir_const_value *const_offset = nir_src_as_const_value(instr->src[1]);
4041 if (const_offset == NULL) {
4042 fs_reg base_offset = retype(get_nir_src(instr->src[1]),
4043 BRW_REGISTER_TYPE_UD);
4045 for (int i = 0; i < instr->num_components; i++)
4046 VARYING_PULL_CONSTANT_LOAD(bld, offset(dest, bld, i), surf_index,
4047 base_offset, i * type_sz(dest.type));
4049 /* Even if we are loading doubles, a pull constant load will load
4050 * a 32-bit vec4, so should only reserve vgrf space for that. If we
4051 * need to load a full dvec4 we will have to emit 2 loads. This is
4052 * similar to demote_pull_constants(), except that in that case we
4053 * see individual accesses to each component of the vector and then
4054 * we let CSE deal with duplicate loads. Here we see a vector access
4055 * and we have to split it if necessary.
4057 const unsigned type_size = type_sz(dest.type);
4059 /* See if we've selected this as a push constant candidate */
4061 const unsigned ubo_block = const_index->u32[0];
4062 const unsigned offset_256b = const_offset->u32[0] / 32;
4065 for (int i = 0; i < 4; i++) {
4066 const struct brw_ubo_range *range = &prog_data->ubo_ranges[i];
4067 if (range->block == ubo_block &&
4068 offset_256b >= range->start &&
4069 offset_256b < range->start + range->length) {
4071 push_reg = fs_reg(UNIFORM, UBO_START + i, dest.type);
4072 push_reg.offset = const_offset->u32[0] - 32 * range->start;
4077 if (push_reg.file != BAD_FILE) {
4078 for (unsigned i = 0; i < instr->num_components; i++) {
4079 bld.MOV(offset(dest, bld, i),
4080 byte_offset(push_reg, i * type_size));
4086 const unsigned block_sz = 64; /* Fetch one cacheline at a time. */
4087 const fs_builder ubld = bld.exec_all().group(block_sz / 4, 0);
4088 const fs_reg packed_consts = ubld.vgrf(BRW_REGISTER_TYPE_UD);
4090 for (unsigned c = 0; c < instr->num_components;) {
4091 const unsigned base = const_offset->u32[0] + c * type_size;
4092 /* Number of usable components in the next block-aligned load. */
4093 const unsigned count = MIN2(instr->num_components - c,
4094 (block_sz - base % block_sz) / type_size);
4096 ubld.emit(FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD,
4097 packed_consts, surf_index,
4098 brw_imm_ud(base & ~(block_sz - 1)));
4100 const fs_reg consts =
4101 retype(byte_offset(packed_consts, base & (block_sz - 1)),
4104 for (unsigned d = 0; d < count; d++)
4105 bld.MOV(offset(dest, bld, c + d), component(consts, d));
4113 case nir_intrinsic_load_ssbo: {
4114 assert(devinfo->gen >= 7);
4116 nir_const_value *const_uniform_block =
4117 nir_src_as_const_value(instr->src[0]);
4120 if (const_uniform_block) {
4121 unsigned index = stage_prog_data->binding_table.ssbo_start +
4122 const_uniform_block->u32[0];
4123 surf_index = brw_imm_ud(index);
4124 brw_mark_surface_used(prog_data, index);
4126 surf_index = vgrf(glsl_type::uint_type);
4127 bld.ADD(surf_index, get_nir_src(instr->src[0]),
4128 brw_imm_ud(stage_prog_data->binding_table.ssbo_start));
4130 /* Assume this may touch any UBO. It would be nice to provide
4131 * a tighter bound, but the array information is already lowered away.
4133 brw_mark_surface_used(prog_data,
4134 stage_prog_data->binding_table.ssbo_start +
4135 nir->info.num_ssbos - 1);
4139 nir_const_value *const_offset = nir_src_as_const_value(instr->src[1]);
4141 offset_reg = brw_imm_ud(const_offset->u32[0]);
4143 offset_reg = get_nir_src(instr->src[1]);
4146 /* Read the vector */
4147 do_untyped_vector_read(bld, dest, surf_index, offset_reg,
4148 instr->num_components);
4153 case nir_intrinsic_store_ssbo: {
4154 assert(devinfo->gen >= 7);
4156 if (stage == MESA_SHADER_FRAGMENT)
4157 brw_wm_prog_data(prog_data)->has_side_effects = true;
4161 nir_const_value *const_uniform_block =
4162 nir_src_as_const_value(instr->src[1]);
4163 if (const_uniform_block) {
4164 unsigned index = stage_prog_data->binding_table.ssbo_start +
4165 const_uniform_block->u32[0];
4166 surf_index = brw_imm_ud(index);
4167 brw_mark_surface_used(prog_data, index);
4169 surf_index = vgrf(glsl_type::uint_type);
4170 bld.ADD(surf_index, get_nir_src(instr->src[1]),
4171 brw_imm_ud(stage_prog_data->binding_table.ssbo_start));
4173 brw_mark_surface_used(prog_data,
4174 stage_prog_data->binding_table.ssbo_start +
4175 nir->info.num_ssbos - 1);
4179 fs_reg val_reg = get_nir_src(instr->src[0]);
4182 unsigned writemask = instr->const_index[0];
4184 /* get_nir_src() retypes to integer. Be wary of 64-bit types though
4185 * since the untyped writes below operate in units of 32-bits, which
4186 * means that we need to write twice as many components each time.
4187 * Also, we have to suffle 64-bit data to be in the appropriate layout
4188 * expected by our 32-bit write messages.
4190 unsigned bit_size = nir_src_bit_size(instr->src[0]);
4191 unsigned type_size = bit_size / 8;
4193 /* Combine groups of consecutive enabled channels in one write
4194 * message. We use ffs to find the first enabled channel and then ffs on
4195 * the bit-inverse, down-shifted writemask to determine the num_components
4196 * of the block of enabled bits.
4199 unsigned first_component = ffs(writemask) - 1;
4200 unsigned num_components = ffs(~(writemask >> first_component)) - 1;
4201 fs_reg write_src = offset(val_reg, bld, first_component);
4203 nir_const_value *const_offset = nir_src_as_const_value(instr->src[2]);
4205 if (type_size > 4) {
4206 /* We can't write more than 2 64-bit components at once. Limit
4207 * the num_components of the write to what we can do and let the next
4208 * iteration handle the rest.
4210 num_components = MIN2(2, num_components);
4211 write_src = shuffle_64bit_data_for_32bit_write(bld, write_src,
4213 } else if (type_size < 4) {
4214 assert(type_size == 2);
4215 /* For 16-bit types we pack two consecutive values into a 32-bit
4216 * word and use an untyped write message. For single values or not
4217 * 32-bit-aligned we need to use byte-scattered writes because
4218 * untyped writes works with 32-bit components with 32-bit
4219 * alignment. byte_scattered_write messages only support one
4220 * 16-bit component at a time. As VK_KHR_relaxed_block_layout
4221 * could be enabled we can not guarantee that not constant offsets
4222 * to be 32-bit aligned for 16-bit types. For example an array, of
4223 * 16-bit vec3 with array element stride of 6.
4225 * In the case of 32-bit aligned constant offsets if there is
4226 * a 3-components vector we submit one untyped-write message
4227 * of 32-bit (first two components), and one byte-scattered
4228 * write message (the last component).
4231 if ( !const_offset || ((const_offset->u32[0] +
4232 type_size * first_component) % 4)) {
4233 /* If we use a .yz writemask we also need to emit 2
4234 * byte-scattered write messages because of y-component not
4235 * being aligned to 32-bit.
4238 } else if (num_components > 2 && (num_components % 2)) {
4239 /* If there is an odd number of consecutive components we left
4240 * the not paired component for a following emit of length == 1
4241 * with byte_scattered_write.
4245 /* For num_components == 1 we are also shuffling the component
4246 * because byte scattered writes of 16-bit need values to be dword
4247 * aligned. Shuffling only one component would be the same as
4250 fs_reg tmp = bld.vgrf(BRW_REGISTER_TYPE_D,
4251 DIV_ROUND_UP(num_components, 2));
4252 shuffle_16bit_data_for_32bit_write(bld, tmp, write_src,
4260 offset_reg = brw_imm_ud(const_offset->u32[0] +
4261 type_size * first_component);
4263 offset_reg = vgrf(glsl_type::uint_type);
4265 retype(get_nir_src(instr->src[2]), BRW_REGISTER_TYPE_UD),
4266 brw_imm_ud(type_size * first_component));
4269 if (type_size < 4 && num_components == 1) {
4270 assert(type_size == 2);
4271 /* Untyped Surface messages have a fixed 32-bit size, so we need
4272 * to rely on byte scattered in order to write 16-bit elements.
4273 * The byte_scattered_write message needs that every written 16-bit
4274 * type to be aligned 32-bits (stride=2).
4276 emit_byte_scattered_write(bld, surf_index, offset_reg,
4280 BRW_PREDICATE_NONE);
4282 assert(num_components * type_size <= 16);
4283 assert((num_components * type_size) % 4 == 0);
4284 assert(offset_reg.file != BRW_IMMEDIATE_VALUE ||
4285 offset_reg.ud % 4 == 0);
4286 unsigned num_slots = (num_components * type_size) / 4;
4288 emit_untyped_write(bld, surf_index, offset_reg,
4290 1 /* dims */, num_slots,
4291 BRW_PREDICATE_NONE);
4294 /* Clear the bits in the writemask that we just wrote, then try
4295 * again to see if more channels are left.
4297 writemask &= (15 << (first_component + num_components));
4302 case nir_intrinsic_store_output: {
4303 fs_reg src = get_nir_src(instr->src[0]);
4305 nir_const_value *const_offset = nir_src_as_const_value(instr->src[1]);
4306 assert(const_offset && "Indirect output stores not allowed");
4308 unsigned num_components = instr->num_components;
4309 unsigned first_component = nir_intrinsic_component(instr);
4310 if (nir_src_bit_size(instr->src[0]) == 64) {
4311 src = shuffle_64bit_data_for_32bit_write(bld, src, num_components);
4312 num_components *= 2;
4315 fs_reg new_dest = retype(offset(outputs[instr->const_index[0]], bld,
4316 4 * const_offset->u32[0]), src.type);
4317 for (unsigned j = 0; j < num_components; j++) {
4318 bld.MOV(offset(new_dest, bld, j + first_component),
4319 offset(src, bld, j));
4324 case nir_intrinsic_ssbo_atomic_add:
4325 nir_emit_ssbo_atomic(bld, BRW_AOP_ADD, instr);
4327 case nir_intrinsic_ssbo_atomic_imin:
4328 nir_emit_ssbo_atomic(bld, BRW_AOP_IMIN, instr);
4330 case nir_intrinsic_ssbo_atomic_umin:
4331 nir_emit_ssbo_atomic(bld, BRW_AOP_UMIN, instr);
4333 case nir_intrinsic_ssbo_atomic_imax:
4334 nir_emit_ssbo_atomic(bld, BRW_AOP_IMAX, instr);
4336 case nir_intrinsic_ssbo_atomic_umax:
4337 nir_emit_ssbo_atomic(bld, BRW_AOP_UMAX, instr);
4339 case nir_intrinsic_ssbo_atomic_and:
4340 nir_emit_ssbo_atomic(bld, BRW_AOP_AND, instr);
4342 case nir_intrinsic_ssbo_atomic_or:
4343 nir_emit_ssbo_atomic(bld, BRW_AOP_OR, instr);
4345 case nir_intrinsic_ssbo_atomic_xor:
4346 nir_emit_ssbo_atomic(bld, BRW_AOP_XOR, instr);
4348 case nir_intrinsic_ssbo_atomic_exchange:
4349 nir_emit_ssbo_atomic(bld, BRW_AOP_MOV, instr);
4351 case nir_intrinsic_ssbo_atomic_comp_swap:
4352 nir_emit_ssbo_atomic(bld, BRW_AOP_CMPWR, instr);
4355 case nir_intrinsic_get_buffer_size: {
4356 nir_const_value *const_uniform_block = nir_src_as_const_value(instr->src[0]);
4357 unsigned ssbo_index = const_uniform_block ? const_uniform_block->u32[0] : 0;
4359 /* A resinfo's sampler message is used to get the buffer size. The
4360 * SIMD8's writeback message consists of four registers and SIMD16's
4361 * writeback message consists of 8 destination registers (two per each
4362 * component). Because we are only interested on the first channel of
4363 * the first returned component, where resinfo returns the buffer size
4364 * for SURFTYPE_BUFFER, we can just use the SIMD8 variant regardless of
4365 * the dispatch width.
4367 const fs_builder ubld = bld.exec_all().group(8, 0);
4368 fs_reg src_payload = ubld.vgrf(BRW_REGISTER_TYPE_UD);
4369 fs_reg ret_payload = ubld.vgrf(BRW_REGISTER_TYPE_UD, 4);
4372 ubld.MOV(src_payload, brw_imm_d(0));
4374 const unsigned index = prog_data->binding_table.ssbo_start + ssbo_index;
4375 fs_inst *inst = ubld.emit(SHADER_OPCODE_GET_BUFFER_SIZE, ret_payload,
4376 src_payload, brw_imm_ud(index));
4377 inst->header_size = 0;
4379 inst->size_written = 4 * REG_SIZE;
4381 /* SKL PRM, vol07, 3D Media GPGPU Engine, Bounds Checking and Faulting:
4383 * "Out-of-bounds checking is always performed at a DWord granularity. If
4384 * any part of the DWord is out-of-bounds then the whole DWord is
4385 * considered out-of-bounds."
4387 * This implies that types with size smaller than 4-bytes need to be
4388 * padded if they don't complete the last dword of the buffer. But as we
4389 * need to maintain the original size we need to reverse the padding
4390 * calculation to return the correct size to know the number of elements
4391 * of an unsized array. As we stored in the last two bits of the surface
4392 * size the needed padding for the buffer, we calculate here the
4393 * original buffer_size reversing the surface_size calculation:
4395 * surface_size = isl_align(buffer_size, 4) +
4396 * (isl_align(buffer_size) - buffer_size)
4398 * buffer_size = surface_size & ~3 - surface_size & 3
4401 fs_reg size_aligned4 = ubld.vgrf(BRW_REGISTER_TYPE_UD);
4402 fs_reg size_padding = ubld.vgrf(BRW_REGISTER_TYPE_UD);
4403 fs_reg buffer_size = ubld.vgrf(BRW_REGISTER_TYPE_UD);
4405 ubld.AND(size_padding, ret_payload, brw_imm_ud(3));
4406 ubld.AND(size_aligned4, ret_payload, brw_imm_ud(~3));
4407 ubld.ADD(buffer_size, size_aligned4, negate(size_padding));
4409 bld.MOV(retype(dest, ret_payload.type), component(buffer_size, 0));
4411 brw_mark_surface_used(prog_data, index);
4415 case nir_intrinsic_load_subgroup_invocation:
4416 bld.MOV(retype(dest, BRW_REGISTER_TYPE_D),
4417 nir_system_values[SYSTEM_VALUE_SUBGROUP_INVOCATION]);
4420 case nir_intrinsic_load_subgroup_eq_mask:
4421 case nir_intrinsic_load_subgroup_ge_mask:
4422 case nir_intrinsic_load_subgroup_gt_mask:
4423 case nir_intrinsic_load_subgroup_le_mask:
4424 case nir_intrinsic_load_subgroup_lt_mask:
4425 unreachable("not reached");
4427 case nir_intrinsic_vote_any: {
4428 const fs_builder ubld = bld.exec_all().group(1, 0);
4430 /* The any/all predicates do not consider channel enables. To prevent
4431 * dead channels from affecting the result, we initialize the flag with
4432 * with the identity value for the logical operation.
4434 if (dispatch_width == 32) {
4435 /* For SIMD32, we use a UD type so we fill both f0.0 and f0.1. */
4436 ubld.MOV(retype(brw_flag_reg(0, 0), BRW_REGISTER_TYPE_UD),
4439 ubld.MOV(brw_flag_reg(0, 0), brw_imm_uw(0));
4441 bld.CMP(bld.null_reg_d(), get_nir_src(instr->src[0]), brw_imm_d(0), BRW_CONDITIONAL_NZ);
4443 /* For some reason, the any/all predicates don't work properly with
4444 * SIMD32. In particular, it appears that a SEL with a QtrCtrl of 2H
4445 * doesn't read the correct subset of the flag register and you end up
4446 * getting garbage in the second half. Work around this by using a pair
4447 * of 1-wide MOVs and scattering the result.
4449 fs_reg res1 = ubld.vgrf(BRW_REGISTER_TYPE_D);
4450 ubld.MOV(res1, brw_imm_d(0));
4451 set_predicate(dispatch_width == 8 ? BRW_PREDICATE_ALIGN1_ANY8H :
4452 dispatch_width == 16 ? BRW_PREDICATE_ALIGN1_ANY16H :
4453 BRW_PREDICATE_ALIGN1_ANY32H,
4454 ubld.MOV(res1, brw_imm_d(-1)));
4456 bld.MOV(retype(dest, BRW_REGISTER_TYPE_D), component(res1, 0));
4459 case nir_intrinsic_vote_all: {
4460 const fs_builder ubld = bld.exec_all().group(1, 0);
4462 /* The any/all predicates do not consider channel enables. To prevent
4463 * dead channels from affecting the result, we initialize the flag with
4464 * with the identity value for the logical operation.
4466 if (dispatch_width == 32) {
4467 /* For SIMD32, we use a UD type so we fill both f0.0 and f0.1. */
4468 ubld.MOV(retype(brw_flag_reg(0, 0), BRW_REGISTER_TYPE_UD),
4469 brw_imm_ud(0xffffffff));
4471 ubld.MOV(brw_flag_reg(0, 0), brw_imm_uw(0xffff));
4473 bld.CMP(bld.null_reg_d(), get_nir_src(instr->src[0]), brw_imm_d(0), BRW_CONDITIONAL_NZ);
4475 /* For some reason, the any/all predicates don't work properly with
4476 * SIMD32. In particular, it appears that a SEL with a QtrCtrl of 2H
4477 * doesn't read the correct subset of the flag register and you end up
4478 * getting garbage in the second half. Work around this by using a pair
4479 * of 1-wide MOVs and scattering the result.
4481 fs_reg res1 = ubld.vgrf(BRW_REGISTER_TYPE_D);
4482 ubld.MOV(res1, brw_imm_d(0));
4483 set_predicate(dispatch_width == 8 ? BRW_PREDICATE_ALIGN1_ALL8H :
4484 dispatch_width == 16 ? BRW_PREDICATE_ALIGN1_ALL16H :
4485 BRW_PREDICATE_ALIGN1_ALL32H,
4486 ubld.MOV(res1, brw_imm_d(-1)));
4488 bld.MOV(retype(dest, BRW_REGISTER_TYPE_D), component(res1, 0));
4491 case nir_intrinsic_vote_feq:
4492 case nir_intrinsic_vote_ieq: {
4493 fs_reg value = get_nir_src(instr->src[0]);
4494 if (instr->intrinsic == nir_intrinsic_vote_feq) {
4495 const unsigned bit_size = nir_src_bit_size(instr->src[0]);
4496 value.type = brw_reg_type_from_bit_size(bit_size, BRW_REGISTER_TYPE_F);
4499 fs_reg uniformized = bld.emit_uniformize(value);
4500 const fs_builder ubld = bld.exec_all().group(1, 0);
4502 /* The any/all predicates do not consider channel enables. To prevent
4503 * dead channels from affecting the result, we initialize the flag with
4504 * with the identity value for the logical operation.
4506 if (dispatch_width == 32) {
4507 /* For SIMD32, we use a UD type so we fill both f0.0 and f0.1. */
4508 ubld.MOV(retype(brw_flag_reg(0, 0), BRW_REGISTER_TYPE_UD),
4509 brw_imm_ud(0xffffffff));
4511 ubld.MOV(brw_flag_reg(0, 0), brw_imm_uw(0xffff));
4513 bld.CMP(bld.null_reg_d(), value, uniformized, BRW_CONDITIONAL_Z);
4515 /* For some reason, the any/all predicates don't work properly with
4516 * SIMD32. In particular, it appears that a SEL with a QtrCtrl of 2H
4517 * doesn't read the correct subset of the flag register and you end up
4518 * getting garbage in the second half. Work around this by using a pair
4519 * of 1-wide MOVs and scattering the result.
4521 fs_reg res1 = ubld.vgrf(BRW_REGISTER_TYPE_D);
4522 ubld.MOV(res1, brw_imm_d(0));
4523 set_predicate(dispatch_width == 8 ? BRW_PREDICATE_ALIGN1_ALL8H :
4524 dispatch_width == 16 ? BRW_PREDICATE_ALIGN1_ALL16H :
4525 BRW_PREDICATE_ALIGN1_ALL32H,
4526 ubld.MOV(res1, brw_imm_d(-1)));
4528 bld.MOV(retype(dest, BRW_REGISTER_TYPE_D), component(res1, 0));
4532 case nir_intrinsic_ballot: {
4533 const fs_reg value = retype(get_nir_src(instr->src[0]),
4534 BRW_REGISTER_TYPE_UD);
4535 struct brw_reg flag = brw_flag_reg(0, 0);
4536 /* FIXME: For SIMD32 programs, this causes us to stomp on f0.1 as well
4537 * as f0.0. This is a problem for fragment programs as we currently use
4538 * f0.1 for discards. Fortunately, we don't support SIMD32 fragment
4539 * programs yet so this isn't a problem. When we do, something will
4542 if (dispatch_width == 32)
4543 flag.type = BRW_REGISTER_TYPE_UD;
4545 bld.exec_all().group(1, 0).MOV(flag, brw_imm_ud(0u));
4546 bld.CMP(bld.null_reg_ud(), value, brw_imm_ud(0u), BRW_CONDITIONAL_NZ);
4548 if (instr->dest.ssa.bit_size > 32) {
4549 dest.type = BRW_REGISTER_TYPE_UQ;
4551 dest.type = BRW_REGISTER_TYPE_UD;
4553 bld.MOV(dest, flag);
4557 case nir_intrinsic_read_invocation: {
4558 const fs_reg value = get_nir_src(instr->src[0]);
4559 const fs_reg invocation = get_nir_src(instr->src[1]);
4560 fs_reg tmp = bld.vgrf(value.type);
4562 bld.exec_all().emit(SHADER_OPCODE_BROADCAST, tmp, value,
4563 bld.emit_uniformize(invocation));
4565 bld.MOV(retype(dest, value.type), fs_reg(component(tmp, 0)));
4569 case nir_intrinsic_read_first_invocation: {
4570 const fs_reg value = get_nir_src(instr->src[0]);
4571 bld.MOV(retype(dest, value.type), bld.emit_uniformize(value));
4575 case nir_intrinsic_shuffle: {
4576 const fs_reg value = get_nir_src(instr->src[0]);
4577 const fs_reg index = get_nir_src(instr->src[1]);
4579 bld.emit(SHADER_OPCODE_SHUFFLE, retype(dest, value.type), value, index);
4583 case nir_intrinsic_first_invocation: {
4584 fs_reg tmp = bld.vgrf(BRW_REGISTER_TYPE_UD);
4585 bld.exec_all().emit(SHADER_OPCODE_FIND_LIVE_CHANNEL, tmp);
4586 bld.MOV(retype(dest, BRW_REGISTER_TYPE_UD),
4587 fs_reg(component(tmp, 0)));
4591 case nir_intrinsic_quad_broadcast: {
4592 const fs_reg value = get_nir_src(instr->src[0]);
4593 nir_const_value *index = nir_src_as_const_value(instr->src[1]);
4594 assert(nir_src_bit_size(instr->src[1]) == 32);
4596 bld.emit(SHADER_OPCODE_CLUSTER_BROADCAST, retype(dest, value.type),
4597 value, brw_imm_ud(index->u32[0]), brw_imm_ud(4));
4601 case nir_intrinsic_quad_swap_horizontal: {
4602 const fs_reg value = get_nir_src(instr->src[0]);
4603 const fs_reg tmp = bld.vgrf(value.type);
4604 const fs_builder ubld = bld.exec_all().group(dispatch_width / 2, 0);
4606 const fs_reg src_left = horiz_stride(value, 2);
4607 const fs_reg src_right = horiz_stride(horiz_offset(value, 1), 2);
4608 const fs_reg tmp_left = horiz_stride(tmp, 2);
4609 const fs_reg tmp_right = horiz_stride(horiz_offset(tmp, 1), 2);
4611 /* From the Cherryview PRM Vol. 7, "Register Region Restrictiosn":
4613 * "When source or destination datatype is 64b or operation is
4614 * integer DWord multiply, regioning in Align1 must follow
4619 * 3. Source and Destination offset must be the same, except
4620 * the case of scalar source."
4622 * In order to work around this, we have to emit two 32-bit MOVs instead
4623 * of a single 64-bit MOV to do the shuffle.
4625 if (type_sz(value.type) > 4 &&
4626 (devinfo->is_cherryview || gen_device_info_is_9lp(devinfo))) {
4627 ubld.MOV(subscript(tmp_left, BRW_REGISTER_TYPE_D, 0),
4628 subscript(src_right, BRW_REGISTER_TYPE_D, 0));
4629 ubld.MOV(subscript(tmp_left, BRW_REGISTER_TYPE_D, 1),
4630 subscript(src_right, BRW_REGISTER_TYPE_D, 1));
4631 ubld.MOV(subscript(tmp_right, BRW_REGISTER_TYPE_D, 0),
4632 subscript(src_left, BRW_REGISTER_TYPE_D, 0));
4633 ubld.MOV(subscript(tmp_right, BRW_REGISTER_TYPE_D, 1),
4634 subscript(src_left, BRW_REGISTER_TYPE_D, 1));
4636 ubld.MOV(tmp_left, src_right);
4637 ubld.MOV(tmp_right, src_left);
4639 bld.MOV(retype(dest, value.type), tmp);
4643 case nir_intrinsic_quad_swap_vertical: {
4644 const fs_reg value = get_nir_src(instr->src[0]);
4645 if (nir_src_bit_size(instr->src[0]) == 32) {
4646 /* For 32-bit, we can use a SIMD4x2 instruction to do this easily */
4647 const fs_reg tmp = bld.vgrf(value.type);
4648 const fs_builder ubld = bld.exec_all();
4649 ubld.emit(SHADER_OPCODE_QUAD_SWIZZLE, tmp, value,
4650 brw_imm_ud(BRW_SWIZZLE4(2,3,0,1)));
4651 bld.MOV(retype(dest, value.type), tmp);
4653 /* For larger data types, we have to either emit dispatch_width many
4654 * MOVs or else fall back to doing indirects.
4656 fs_reg idx = bld.vgrf(BRW_REGISTER_TYPE_W);
4657 bld.XOR(idx, nir_system_values[SYSTEM_VALUE_SUBGROUP_INVOCATION],
4659 bld.emit(SHADER_OPCODE_SHUFFLE, retype(dest, value.type), value, idx);
4664 case nir_intrinsic_quad_swap_diagonal: {
4665 const fs_reg value = get_nir_src(instr->src[0]);
4666 if (nir_src_bit_size(instr->src[0]) == 32) {
4667 /* For 32-bit, we can use a SIMD4x2 instruction to do this easily */
4668 const fs_reg tmp = bld.vgrf(value.type);
4669 const fs_builder ubld = bld.exec_all();
4670 ubld.emit(SHADER_OPCODE_QUAD_SWIZZLE, tmp, value,
4671 brw_imm_ud(BRW_SWIZZLE4(3,2,1,0)));
4672 bld.MOV(retype(dest, value.type), tmp);
4674 /* For larger data types, we have to either emit dispatch_width many
4675 * MOVs or else fall back to doing indirects.
4677 fs_reg idx = bld.vgrf(BRW_REGISTER_TYPE_W);
4678 bld.XOR(idx, nir_system_values[SYSTEM_VALUE_SUBGROUP_INVOCATION],
4680 bld.emit(SHADER_OPCODE_SHUFFLE, retype(dest, value.type), value, idx);
4685 case nir_intrinsic_reduce: {
4686 fs_reg src = get_nir_src(instr->src[0]);
4687 nir_op redop = (nir_op)nir_intrinsic_reduction_op(instr);
4688 unsigned cluster_size = nir_intrinsic_cluster_size(instr);
4689 if (cluster_size == 0 || cluster_size > dispatch_width)
4690 cluster_size = dispatch_width;
4692 /* Figure out the source type */
4693 src.type = brw_type_for_nir_type(devinfo,
4694 (nir_alu_type)(nir_op_infos[redop].input_types[0] |
4695 nir_src_bit_size(instr->src[0])));
4697 fs_reg identity = brw_nir_reduction_op_identity(bld, redop, src.type);
4698 opcode brw_op = brw_op_for_nir_reduction_op(redop);
4699 brw_conditional_mod cond_mod = brw_cond_mod_for_nir_reduction_op(redop);
4701 /* Set up a register for all of our scratching around and initialize it
4702 * to reduction operation's identity value.
4704 fs_reg scan = bld.vgrf(src.type);
4705 bld.exec_all().emit(SHADER_OPCODE_SEL_EXEC, scan, src, identity);
4707 bld.emit_scan(brw_op, scan, cluster_size, cond_mod);
4709 dest.type = src.type;
4710 if (cluster_size * type_sz(src.type) >= REG_SIZE * 2) {
4711 /* In this case, CLUSTER_BROADCAST instruction isn't needed because
4712 * the distance between clusters is at least 2 GRFs. In this case,
4713 * we don't need the weird striding of the CLUSTER_BROADCAST
4714 * instruction and can just do regular MOVs.
4716 assert((cluster_size * type_sz(src.type)) % (REG_SIZE * 2) == 0);
4717 const unsigned groups =
4718 (dispatch_width * type_sz(src.type)) / (REG_SIZE * 2);
4719 const unsigned group_size = dispatch_width / groups;
4720 for (unsigned i = 0; i < groups; i++) {
4721 const unsigned cluster = (i * group_size) / cluster_size;
4722 const unsigned comp = cluster * cluster_size + (cluster_size - 1);
4723 bld.group(group_size, i).MOV(horiz_offset(dest, i * group_size),
4724 component(scan, comp));
4727 bld.emit(SHADER_OPCODE_CLUSTER_BROADCAST, dest, scan,
4728 brw_imm_ud(cluster_size - 1), brw_imm_ud(cluster_size));
4733 case nir_intrinsic_inclusive_scan:
4734 case nir_intrinsic_exclusive_scan: {
4735 fs_reg src = get_nir_src(instr->src[0]);
4736 nir_op redop = (nir_op)nir_intrinsic_reduction_op(instr);
4738 /* Figure out the source type */
4739 src.type = brw_type_for_nir_type(devinfo,
4740 (nir_alu_type)(nir_op_infos[redop].input_types[0] |
4741 nir_src_bit_size(instr->src[0])));
4743 fs_reg identity = brw_nir_reduction_op_identity(bld, redop, src.type);
4744 opcode brw_op = brw_op_for_nir_reduction_op(redop);
4745 brw_conditional_mod cond_mod = brw_cond_mod_for_nir_reduction_op(redop);
4747 /* Set up a register for all of our scratching around and initialize it
4748 * to reduction operation's identity value.
4750 fs_reg scan = bld.vgrf(src.type);
4751 const fs_builder allbld = bld.exec_all();
4752 allbld.emit(SHADER_OPCODE_SEL_EXEC, scan, src, identity);
4754 if (instr->intrinsic == nir_intrinsic_exclusive_scan) {
4755 /* Exclusive scan is a bit harder because we have to do an annoying
4756 * shift of the contents before we can begin. To make things worse,
4757 * we can't do this with a normal stride; we have to use indirects.
4759 fs_reg shifted = bld.vgrf(src.type);
4760 fs_reg idx = bld.vgrf(BRW_REGISTER_TYPE_W);
4761 allbld.ADD(idx, nir_system_values[SYSTEM_VALUE_SUBGROUP_INVOCATION],
4763 allbld.emit(SHADER_OPCODE_SHUFFLE, shifted, scan, idx);
4764 allbld.group(1, 0).MOV(component(shifted, 0), identity);
4768 bld.emit_scan(brw_op, scan, dispatch_width, cond_mod);
4770 bld.MOV(retype(dest, src.type), scan);
4775 unreachable("unknown intrinsic");
4780 fs_visitor::nir_emit_ssbo_atomic(const fs_builder &bld,
4781 int op, nir_intrinsic_instr *instr)
4783 if (stage == MESA_SHADER_FRAGMENT)
4784 brw_wm_prog_data(prog_data)->has_side_effects = true;
4787 if (nir_intrinsic_infos[instr->intrinsic].has_dest)
4788 dest = get_nir_dest(instr->dest);
4791 nir_const_value *const_surface = nir_src_as_const_value(instr->src[0]);
4792 if (const_surface) {
4793 unsigned surf_index = stage_prog_data->binding_table.ssbo_start +
4794 const_surface->u32[0];
4795 surface = brw_imm_ud(surf_index);
4796 brw_mark_surface_used(prog_data, surf_index);
4798 surface = vgrf(glsl_type::uint_type);
4799 bld.ADD(surface, get_nir_src(instr->src[0]),
4800 brw_imm_ud(stage_prog_data->binding_table.ssbo_start));
4802 /* Assume this may touch any SSBO. This is the same we do for other
4803 * UBO/SSBO accesses with non-constant surface.
4805 brw_mark_surface_used(prog_data,
4806 stage_prog_data->binding_table.ssbo_start +
4807 nir->info.num_ssbos - 1);
4810 fs_reg offset = get_nir_src(instr->src[1]);
4811 fs_reg data1 = get_nir_src(instr->src[2]);
4813 if (op == BRW_AOP_CMPWR)
4814 data2 = get_nir_src(instr->src[3]);
4816 /* Emit the actual atomic operation */
4818 fs_reg atomic_result = emit_untyped_atomic(bld, surface, offset,
4820 1 /* dims */, 1 /* rsize */,
4822 BRW_PREDICATE_NONE);
4823 dest.type = atomic_result.type;
4824 bld.MOV(dest, atomic_result);
4828 fs_visitor::nir_emit_shared_atomic(const fs_builder &bld,
4829 int op, nir_intrinsic_instr *instr)
4832 if (nir_intrinsic_infos[instr->intrinsic].has_dest)
4833 dest = get_nir_dest(instr->dest);
4835 fs_reg surface = brw_imm_ud(GEN7_BTI_SLM);
4837 fs_reg data1 = get_nir_src(instr->src[1]);
4839 if (op == BRW_AOP_CMPWR)
4840 data2 = get_nir_src(instr->src[2]);
4842 /* Get the offset */
4843 nir_const_value *const_offset = nir_src_as_const_value(instr->src[0]);
4845 offset = brw_imm_ud(instr->const_index[0] + const_offset->u32[0]);
4847 offset = vgrf(glsl_type::uint_type);
4849 retype(get_nir_src(instr->src[0]), BRW_REGISTER_TYPE_UD),
4850 brw_imm_ud(instr->const_index[0]));
4853 /* Emit the actual atomic operation operation */
4855 fs_reg atomic_result = emit_untyped_atomic(bld, surface, offset,
4857 1 /* dims */, 1 /* rsize */,
4859 BRW_PREDICATE_NONE);
4860 dest.type = atomic_result.type;
4861 bld.MOV(dest, atomic_result);
4865 fs_visitor::nir_emit_texture(const fs_builder &bld, nir_tex_instr *instr)
4867 unsigned texture = instr->texture_index;
4868 unsigned sampler = instr->sampler_index;
4870 fs_reg srcs[TEX_LOGICAL_NUM_SRCS];
4872 srcs[TEX_LOGICAL_SRC_SURFACE] = brw_imm_ud(texture);
4873 srcs[TEX_LOGICAL_SRC_SAMPLER] = brw_imm_ud(sampler);
4875 int lod_components = 0;
4877 /* The hardware requires a LOD for buffer textures */
4878 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF)
4879 srcs[TEX_LOGICAL_SRC_LOD] = brw_imm_d(0);
4881 uint32_t header_bits = 0;
4882 for (unsigned i = 0; i < instr->num_srcs; i++) {
4883 fs_reg src = get_nir_src(instr->src[i].src);
4884 switch (instr->src[i].src_type) {
4885 case nir_tex_src_bias:
4886 srcs[TEX_LOGICAL_SRC_LOD] =
4887 retype(get_nir_src_imm(instr->src[i].src), BRW_REGISTER_TYPE_F);
4889 case nir_tex_src_comparator:
4890 srcs[TEX_LOGICAL_SRC_SHADOW_C] = retype(src, BRW_REGISTER_TYPE_F);
4892 case nir_tex_src_coord:
4893 switch (instr->op) {
4895 case nir_texop_txf_ms:
4896 case nir_texop_txf_ms_mcs:
4897 case nir_texop_samples_identical:
4898 srcs[TEX_LOGICAL_SRC_COORDINATE] = retype(src, BRW_REGISTER_TYPE_D);
4901 srcs[TEX_LOGICAL_SRC_COORDINATE] = retype(src, BRW_REGISTER_TYPE_F);
4905 case nir_tex_src_ddx:
4906 srcs[TEX_LOGICAL_SRC_LOD] = retype(src, BRW_REGISTER_TYPE_F);
4907 lod_components = nir_tex_instr_src_size(instr, i);
4909 case nir_tex_src_ddy:
4910 srcs[TEX_LOGICAL_SRC_LOD2] = retype(src, BRW_REGISTER_TYPE_F);
4912 case nir_tex_src_lod:
4913 switch (instr->op) {
4915 srcs[TEX_LOGICAL_SRC_LOD] =
4916 retype(get_nir_src_imm(instr->src[i].src), BRW_REGISTER_TYPE_UD);
4919 srcs[TEX_LOGICAL_SRC_LOD] =
4920 retype(get_nir_src_imm(instr->src[i].src), BRW_REGISTER_TYPE_D);
4923 srcs[TEX_LOGICAL_SRC_LOD] =
4924 retype(get_nir_src_imm(instr->src[i].src), BRW_REGISTER_TYPE_F);
4928 case nir_tex_src_ms_index:
4929 srcs[TEX_LOGICAL_SRC_SAMPLE_INDEX] = retype(src, BRW_REGISTER_TYPE_UD);
4932 case nir_tex_src_offset: {
4933 nir_const_value *const_offset =
4934 nir_src_as_const_value(instr->src[i].src);
4935 unsigned offset_bits = 0;
4937 brw_texture_offset(const_offset->i32,
4938 nir_tex_instr_src_size(instr, i),
4940 header_bits |= offset_bits;
4942 srcs[TEX_LOGICAL_SRC_TG4_OFFSET] =
4943 retype(src, BRW_REGISTER_TYPE_D);
4948 case nir_tex_src_projector:
4949 unreachable("should be lowered");
4951 case nir_tex_src_texture_offset: {
4952 /* Figure out the highest possible texture index and mark it as used */
4953 uint32_t max_used = texture + instr->texture_array_size - 1;
4954 if (instr->op == nir_texop_tg4 && devinfo->gen < 8) {
4955 max_used += stage_prog_data->binding_table.gather_texture_start;
4957 max_used += stage_prog_data->binding_table.texture_start;
4959 brw_mark_surface_used(prog_data, max_used);
4961 /* Emit code to evaluate the actual indexing expression */
4962 fs_reg tmp = vgrf(glsl_type::uint_type);
4963 bld.ADD(tmp, src, brw_imm_ud(texture));
4964 srcs[TEX_LOGICAL_SRC_SURFACE] = bld.emit_uniformize(tmp);
4968 case nir_tex_src_sampler_offset: {
4969 /* Emit code to evaluate the actual indexing expression */
4970 fs_reg tmp = vgrf(glsl_type::uint_type);
4971 bld.ADD(tmp, src, brw_imm_ud(sampler));
4972 srcs[TEX_LOGICAL_SRC_SAMPLER] = bld.emit_uniformize(tmp);
4976 case nir_tex_src_ms_mcs:
4977 assert(instr->op == nir_texop_txf_ms);
4978 srcs[TEX_LOGICAL_SRC_MCS] = retype(src, BRW_REGISTER_TYPE_D);
4981 case nir_tex_src_plane: {
4982 nir_const_value *const_plane =
4983 nir_src_as_const_value(instr->src[i].src);
4984 const uint32_t plane = const_plane->u32[0];
4985 const uint32_t texture_index =
4986 instr->texture_index +
4987 stage_prog_data->binding_table.plane_start[plane] -
4988 stage_prog_data->binding_table.texture_start;
4990 srcs[TEX_LOGICAL_SRC_SURFACE] = brw_imm_ud(texture_index);
4995 unreachable("unknown texture source");
4999 if (srcs[TEX_LOGICAL_SRC_MCS].file == BAD_FILE &&
5000 (instr->op == nir_texop_txf_ms ||
5001 instr->op == nir_texop_samples_identical)) {
5002 if (devinfo->gen >= 7 &&
5003 key_tex->compressed_multisample_layout_mask & (1 << texture)) {
5004 srcs[TEX_LOGICAL_SRC_MCS] =
5005 emit_mcs_fetch(srcs[TEX_LOGICAL_SRC_COORDINATE],
5006 instr->coord_components,
5007 srcs[TEX_LOGICAL_SRC_SURFACE]);
5009 srcs[TEX_LOGICAL_SRC_MCS] = brw_imm_ud(0u);
5013 srcs[TEX_LOGICAL_SRC_COORD_COMPONENTS] = brw_imm_d(instr->coord_components);
5014 srcs[TEX_LOGICAL_SRC_GRAD_COMPONENTS] = brw_imm_d(lod_components);
5017 switch (instr->op) {
5019 opcode = (stage == MESA_SHADER_FRAGMENT ? SHADER_OPCODE_TEX_LOGICAL :
5020 SHADER_OPCODE_TXL_LOGICAL);
5023 opcode = FS_OPCODE_TXB_LOGICAL;
5026 opcode = SHADER_OPCODE_TXL_LOGICAL;
5029 opcode = SHADER_OPCODE_TXD_LOGICAL;
5032 opcode = SHADER_OPCODE_TXF_LOGICAL;
5034 case nir_texop_txf_ms:
5035 if ((key_tex->msaa_16 & (1 << sampler)))
5036 opcode = SHADER_OPCODE_TXF_CMS_W_LOGICAL;
5038 opcode = SHADER_OPCODE_TXF_CMS_LOGICAL;
5040 case nir_texop_txf_ms_mcs:
5041 opcode = SHADER_OPCODE_TXF_MCS_LOGICAL;
5043 case nir_texop_query_levels:
5045 opcode = SHADER_OPCODE_TXS_LOGICAL;
5048 opcode = SHADER_OPCODE_LOD_LOGICAL;
5051 if (srcs[TEX_LOGICAL_SRC_TG4_OFFSET].file != BAD_FILE)
5052 opcode = SHADER_OPCODE_TG4_OFFSET_LOGICAL;
5054 opcode = SHADER_OPCODE_TG4_LOGICAL;
5056 case nir_texop_texture_samples:
5057 opcode = SHADER_OPCODE_SAMPLEINFO_LOGICAL;
5059 case nir_texop_samples_identical: {
5060 fs_reg dst = retype(get_nir_dest(instr->dest), BRW_REGISTER_TYPE_D);
5062 /* If mcs is an immediate value, it means there is no MCS. In that case
5063 * just return false.
5065 if (srcs[TEX_LOGICAL_SRC_MCS].file == BRW_IMMEDIATE_VALUE) {
5066 bld.MOV(dst, brw_imm_ud(0u));
5067 } else if ((key_tex->msaa_16 & (1 << sampler))) {
5068 fs_reg tmp = vgrf(glsl_type::uint_type);
5069 bld.OR(tmp, srcs[TEX_LOGICAL_SRC_MCS],
5070 offset(srcs[TEX_LOGICAL_SRC_MCS], bld, 1));
5071 bld.CMP(dst, tmp, brw_imm_ud(0u), BRW_CONDITIONAL_EQ);
5073 bld.CMP(dst, srcs[TEX_LOGICAL_SRC_MCS], brw_imm_ud(0u),
5074 BRW_CONDITIONAL_EQ);
5079 unreachable("unknown texture opcode");
5082 if (instr->op == nir_texop_tg4) {
5083 if (instr->component == 1 &&
5084 key_tex->gather_channel_quirk_mask & (1 << texture)) {
5085 /* gather4 sampler is broken for green channel on RG32F --
5086 * we must ask for blue instead.
5088 header_bits |= 2 << 16;
5090 header_bits |= instr->component << 16;
5094 fs_reg dst = bld.vgrf(brw_type_for_nir_type(devinfo, instr->dest_type), 4);
5095 fs_inst *inst = bld.emit(opcode, dst, srcs, ARRAY_SIZE(srcs));
5096 inst->offset = header_bits;
5098 const unsigned dest_size = nir_tex_instr_dest_size(instr);
5099 if (devinfo->gen >= 9 &&
5100 instr->op != nir_texop_tg4 && instr->op != nir_texop_query_levels) {
5101 unsigned write_mask = instr->dest.is_ssa ?
5102 nir_ssa_def_components_read(&instr->dest.ssa):
5103 (1 << dest_size) - 1;
5104 assert(write_mask != 0); /* dead code should have been eliminated */
5105 inst->size_written = util_last_bit(write_mask) *
5106 inst->dst.component_size(inst->exec_size);
5108 inst->size_written = 4 * inst->dst.component_size(inst->exec_size);
5111 if (srcs[TEX_LOGICAL_SRC_SHADOW_C].file != BAD_FILE)
5112 inst->shadow_compare = true;
5114 if (instr->op == nir_texop_tg4 && devinfo->gen == 6)
5115 emit_gen6_gather_wa(key_tex->gen6_gather_wa[texture], dst);
5118 for (unsigned i = 0; i < dest_size; i++)
5119 nir_dest[i] = offset(dst, bld, i);
5121 if (instr->op == nir_texop_query_levels) {
5122 /* # levels is in .w */
5123 nir_dest[0] = offset(dst, bld, 3);
5124 } else if (instr->op == nir_texop_txs &&
5125 dest_size >= 3 && devinfo->gen < 7) {
5126 /* Gen4-6 return 0 instead of 1 for single layer surfaces. */
5127 fs_reg depth = offset(dst, bld, 2);
5128 nir_dest[2] = vgrf(glsl_type::int_type);
5129 bld.emit_minmax(nir_dest[2], depth, brw_imm_d(1), BRW_CONDITIONAL_GE);
5132 bld.LOAD_PAYLOAD(get_nir_dest(instr->dest), nir_dest, dest_size, 0);
5136 fs_visitor::nir_emit_jump(const fs_builder &bld, nir_jump_instr *instr)
5138 switch (instr->type) {
5139 case nir_jump_break:
5140 bld.emit(BRW_OPCODE_BREAK);
5142 case nir_jump_continue:
5143 bld.emit(BRW_OPCODE_CONTINUE);
5145 case nir_jump_return:
5147 unreachable("unknown jump");
5152 * This helper takes the result of a load operation that reads 32-bit elements
5160 * and shuffles the data to get this:
5167 * Which is exactly what we want if the load is reading 64-bit components
5168 * like doubles, where x represents the low 32-bit of the x double component
5169 * and y represents the high 32-bit of the x double component (likewise with
5170 * z and w for double component y). The parameter @components represents
5171 * the number of 64-bit components present in @src. This would typically be
5172 * 2 at most, since we can only fit 2 double elements in the result of a
5175 * Notice that @dst and @src can be the same register.
5178 shuffle_32bit_load_result_to_64bit_data(const fs_builder &bld,
5181 uint32_t components)
5183 assert(type_sz(src.type) == 4);
5184 assert(type_sz(dst.type) == 8);
5186 /* A temporary that we will use to shuffle the 32-bit data of each
5187 * component in the vector into valid 64-bit data. We can't write directly
5188 * to dst because dst can be (and would usually be) the same as src
5189 * and in that case the first MOV in the loop below would overwrite the
5190 * data read in the second MOV.
5192 fs_reg tmp = bld.vgrf(dst.type);
5194 for (unsigned i = 0; i < components; i++) {
5195 const fs_reg component_i = offset(src, bld, 2 * i);
5197 bld.MOV(subscript(tmp, src.type, 0), component_i);
5198 bld.MOV(subscript(tmp, src.type, 1), offset(component_i, bld, 1));
5200 bld.MOV(offset(dst, bld, i), tmp);
5205 shuffle_32bit_load_result_to_16bit_data(const fs_builder &bld,
5208 uint32_t first_component,
5209 uint32_t components)
5211 assert(type_sz(src.type) == 4);
5212 assert(type_sz(dst.type) == 2);
5214 /* A temporary is used to un-shuffle the 32-bit data of each component in
5215 * into a valid 16-bit vector. We can't write directly to dst because it
5216 * can be the same register as src and in that case the first MOV in the
5217 * loop below would overwrite the data read in the second MOV.
5219 fs_reg tmp = retype(bld.vgrf(src.type), dst.type);
5221 for (unsigned i = 0; i < components; i++) {
5222 const fs_reg component_i =
5223 subscript(offset(src, bld, (first_component + i) / 2), dst.type,
5224 (first_component + i) % 2);
5226 bld.MOV(offset(tmp, bld, i % 2), component_i);
5229 bld.MOV(offset(dst, bld, i -1), offset(tmp, bld, 0));
5230 bld.MOV(offset(dst, bld, i), offset(tmp, bld, 1));
5233 if (components % 2) {
5234 bld.MOV(offset(dst, bld, components - 1), tmp);
5239 * This helper does the inverse operation of
5240 * SHUFFLE_32BIT_LOAD_RESULT_TO_64BIT_DATA.
5242 * We need to do this when we are going to use untyped write messsages that
5243 * operate with 32-bit components in order to arrange our 64-bit data to be
5244 * in the expected layout.
5246 * Notice that callers of this function, unlike in the case of the inverse
5247 * operation, would typically need to call this with dst and src being
5248 * different registers, since they would otherwise corrupt the original
5249 * 64-bit data they are about to write. Because of this the function checks
5250 * that the src and dst regions involved in the operation do not overlap.
5253 shuffle_64bit_data_for_32bit_write(const fs_builder &bld,
5255 uint32_t components)
5257 assert(type_sz(src.type) == 8);
5259 fs_reg dst = bld.vgrf(BRW_REGISTER_TYPE_D, 2 * components);
5261 for (unsigned i = 0; i < components; i++) {
5262 const fs_reg component_i = offset(src, bld, i);
5263 bld.MOV(offset(dst, bld, 2 * i), subscript(component_i, dst.type, 0));
5264 bld.MOV(offset(dst, bld, 2 * i + 1), subscript(component_i, dst.type, 1));
5271 shuffle_16bit_data_for_32bit_write(const fs_builder &bld,
5274 uint32_t components)
5276 assert(type_sz(src.type) == 2);
5277 assert(type_sz(dst.type) == 4);
5279 /* A temporary is used to shuffle the 16-bit data of each component in the
5280 * 32-bit data vector. We can't write directly to dst because it can be the
5281 * same register as src and in that case the first MOV in the loop below
5282 * would overwrite the data read in the second MOV.
5284 fs_reg tmp = bld.vgrf(dst.type);
5286 for (unsigned i = 0; i < components; i++) {
5287 const fs_reg component_i = offset(src, bld, i);
5288 bld.MOV(subscript(tmp, src.type, i % 2), component_i);
5290 bld.MOV(offset(dst, bld, i / 2), tmp);
5293 if (components % 2) {
5294 bld.MOV(offset(dst, bld, components / 2), tmp);
5299 setup_imm_df(const fs_builder &bld, double v)
5301 const struct gen_device_info *devinfo = bld.shader->devinfo;
5302 assert(devinfo->gen >= 7);
5304 if (devinfo->gen >= 8)
5305 return brw_imm_df(v);
5307 /* gen7.5 does not support DF immediates straighforward but the DIM
5308 * instruction allows to set the 64-bit immediate value.
5310 if (devinfo->is_haswell) {
5311 const fs_builder ubld = bld.exec_all().group(1, 0);
5312 fs_reg dst = ubld.vgrf(BRW_REGISTER_TYPE_DF, 1);
5313 ubld.DIM(dst, brw_imm_df(v));
5314 return component(dst, 0);
5317 /* gen7 does not support DF immediates, so we generate a 64-bit constant by
5318 * writing the low 32-bit of the constant to suboffset 0 of a VGRF and
5319 * the high 32-bit to suboffset 4 and then applying a stride of 0.
5321 * Alternatively, we could also produce a normal VGRF (without stride 0)
5322 * by writing to all the channels in the VGRF, however, that would hit the
5323 * gen7 bug where we have to split writes that span more than 1 register
5324 * into instructions with a width of 4 (otherwise the write to the second
5325 * register written runs into an execmask hardware bug) which isn't very
5338 const fs_builder ubld = bld.exec_all().group(1, 0);
5339 const fs_reg tmp = ubld.vgrf(BRW_REGISTER_TYPE_UD, 2);
5340 ubld.MOV(tmp, brw_imm_ud(di.i1));
5341 ubld.MOV(horiz_offset(tmp, 1), brw_imm_ud(di.i2));
5343 return component(retype(tmp, BRW_REGISTER_TYPE_DF), 0);