2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
30 #include "anv_private.h"
32 #include "vk_format_info.h"
34 /** \file anv_cmd_buffer.c
36 * This file contains all of the stuff for emitting commands into a command
37 * buffer. This includes implementations of most of the vkCmd*
38 * entrypoints. This file is concerned entirely with state emission and
39 * not with the command buffer data structure itself. As far as this file
40 * is concerned, most of anv_cmd_buffer is magic.
43 /* TODO: These are taken from GLES. We should check the Vulkan spec */
44 const struct anv_dynamic_state default_dynamic_state = {
57 .blend_constants = { 0.0f, 0.0f, 0.0f, 0.0f },
62 .stencil_compare_mask = {
66 .stencil_write_mask = {
70 .stencil_reference = {
77 anv_dynamic_state_copy(struct anv_dynamic_state *dest,
78 const struct anv_dynamic_state *src,
81 if (copy_mask & (1 << VK_DYNAMIC_STATE_VIEWPORT)) {
82 dest->viewport.count = src->viewport.count;
83 typed_memcpy(dest->viewport.viewports, src->viewport.viewports,
87 if (copy_mask & (1 << VK_DYNAMIC_STATE_SCISSOR)) {
88 dest->scissor.count = src->scissor.count;
89 typed_memcpy(dest->scissor.scissors, src->scissor.scissors,
93 if (copy_mask & (1 << VK_DYNAMIC_STATE_LINE_WIDTH))
94 dest->line_width = src->line_width;
96 if (copy_mask & (1 << VK_DYNAMIC_STATE_DEPTH_BIAS))
97 dest->depth_bias = src->depth_bias;
99 if (copy_mask & (1 << VK_DYNAMIC_STATE_BLEND_CONSTANTS))
100 typed_memcpy(dest->blend_constants, src->blend_constants, 4);
102 if (copy_mask & (1 << VK_DYNAMIC_STATE_DEPTH_BOUNDS))
103 dest->depth_bounds = src->depth_bounds;
105 if (copy_mask & (1 << VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK))
106 dest->stencil_compare_mask = src->stencil_compare_mask;
108 if (copy_mask & (1 << VK_DYNAMIC_STATE_STENCIL_WRITE_MASK))
109 dest->stencil_write_mask = src->stencil_write_mask;
111 if (copy_mask & (1 << VK_DYNAMIC_STATE_STENCIL_REFERENCE))
112 dest->stencil_reference = src->stencil_reference;
116 anv_cmd_state_reset(struct anv_cmd_buffer *cmd_buffer)
118 struct anv_cmd_state *state = &cmd_buffer->state;
120 cmd_buffer->batch.status = VK_SUCCESS;
122 memset(&state->descriptors, 0, sizeof(state->descriptors));
123 for (uint32_t i = 0; i < ARRAY_SIZE(state->push_descriptors); i++) {
124 vk_free(&cmd_buffer->pool->alloc, state->push_descriptors[i]);
125 state->push_descriptors[i] = NULL;
127 for (uint32_t i = 0; i < MESA_SHADER_STAGES; i++) {
128 vk_free(&cmd_buffer->pool->alloc, state->push_constants[i]);
129 state->push_constants[i] = NULL;
131 memset(state->binding_tables, 0, sizeof(state->binding_tables));
132 memset(state->samplers, 0, sizeof(state->samplers));
134 /* 0 isn't a valid config. This ensures that we always configure L3$. */
135 cmd_buffer->state.current_l3_config = 0;
139 state->pending_pipe_bits = 0;
140 state->descriptors_dirty = 0;
141 state->push_constants_dirty = 0;
142 state->pipeline = NULL;
143 state->framebuffer = NULL;
145 state->subpass = NULL;
146 state->push_constant_stages = 0;
147 state->restart_index = UINT32_MAX;
148 state->dynamic = default_dynamic_state;
149 state->need_query_wa = true;
150 state->pma_fix_enabled = false;
151 state->hiz_enabled = false;
153 vk_free(&cmd_buffer->pool->alloc, state->attachments);
154 state->attachments = NULL;
156 state->gen7.index_buffer = NULL;
160 anv_cmd_buffer_ensure_push_constants_size(struct anv_cmd_buffer *cmd_buffer,
161 gl_shader_stage stage, uint32_t size)
163 struct anv_push_constants **ptr = &cmd_buffer->state.push_constants[stage];
166 *ptr = vk_alloc(&cmd_buffer->pool->alloc, size, 8,
167 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
169 anv_batch_set_error(&cmd_buffer->batch, VK_ERROR_OUT_OF_HOST_MEMORY);
170 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
172 } else if ((*ptr)->size < size) {
173 *ptr = vk_realloc(&cmd_buffer->pool->alloc, *ptr, size, 8,
174 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
176 anv_batch_set_error(&cmd_buffer->batch, VK_ERROR_OUT_OF_HOST_MEMORY);
177 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
185 static VkResult anv_create_cmd_buffer(
186 struct anv_device * device,
187 struct anv_cmd_pool * pool,
188 VkCommandBufferLevel level,
189 VkCommandBuffer* pCommandBuffer)
191 struct anv_cmd_buffer *cmd_buffer;
194 cmd_buffer = vk_alloc(&pool->alloc, sizeof(*cmd_buffer), 8,
195 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
196 if (cmd_buffer == NULL)
197 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
199 cmd_buffer->batch.status = VK_SUCCESS;
201 for (uint32_t i = 0; i < MESA_SHADER_STAGES; i++) {
202 cmd_buffer->state.push_constants[i] = NULL;
204 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
205 cmd_buffer->device = device;
206 cmd_buffer->pool = pool;
207 cmd_buffer->level = level;
208 cmd_buffer->state.attachments = NULL;
210 result = anv_cmd_buffer_init_batch_bo_chain(cmd_buffer);
211 if (result != VK_SUCCESS)
214 anv_state_stream_init(&cmd_buffer->surface_state_stream,
215 &device->surface_state_pool, 4096);
216 anv_state_stream_init(&cmd_buffer->dynamic_state_stream,
217 &device->dynamic_state_pool, 16384);
219 memset(cmd_buffer->state.push_descriptors, 0,
220 sizeof(cmd_buffer->state.push_descriptors));
223 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
225 /* Init the pool_link so we can safefly call list_del when we destroy
228 list_inithead(&cmd_buffer->pool_link);
231 *pCommandBuffer = anv_cmd_buffer_to_handle(cmd_buffer);
236 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
241 VkResult anv_AllocateCommandBuffers(
243 const VkCommandBufferAllocateInfo* pAllocateInfo,
244 VkCommandBuffer* pCommandBuffers)
246 ANV_FROM_HANDLE(anv_device, device, _device);
247 ANV_FROM_HANDLE(anv_cmd_pool, pool, pAllocateInfo->commandPool);
249 VkResult result = VK_SUCCESS;
252 for (i = 0; i < pAllocateInfo->commandBufferCount; i++) {
253 result = anv_create_cmd_buffer(device, pool, pAllocateInfo->level,
254 &pCommandBuffers[i]);
255 if (result != VK_SUCCESS)
259 if (result != VK_SUCCESS) {
260 anv_FreeCommandBuffers(_device, pAllocateInfo->commandPool,
262 for (i = 0; i < pAllocateInfo->commandBufferCount; i++)
263 pCommandBuffers[i] = VK_NULL_HANDLE;
270 anv_cmd_buffer_destroy(struct anv_cmd_buffer *cmd_buffer)
272 list_del(&cmd_buffer->pool_link);
274 anv_cmd_buffer_fini_batch_bo_chain(cmd_buffer);
276 anv_state_stream_finish(&cmd_buffer->surface_state_stream);
277 anv_state_stream_finish(&cmd_buffer->dynamic_state_stream);
279 anv_cmd_state_reset(cmd_buffer);
281 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
284 void anv_FreeCommandBuffers(
286 VkCommandPool commandPool,
287 uint32_t commandBufferCount,
288 const VkCommandBuffer* pCommandBuffers)
290 for (uint32_t i = 0; i < commandBufferCount; i++) {
291 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, pCommandBuffers[i]);
296 anv_cmd_buffer_destroy(cmd_buffer);
301 anv_cmd_buffer_reset(struct anv_cmd_buffer *cmd_buffer)
303 cmd_buffer->usage_flags = 0;
304 cmd_buffer->state.current_pipeline = UINT32_MAX;
305 anv_cmd_buffer_reset_batch_bo_chain(cmd_buffer);
306 anv_cmd_state_reset(cmd_buffer);
308 anv_state_stream_finish(&cmd_buffer->surface_state_stream);
309 anv_state_stream_init(&cmd_buffer->surface_state_stream,
310 &cmd_buffer->device->surface_state_pool, 4096);
312 anv_state_stream_finish(&cmd_buffer->dynamic_state_stream);
313 anv_state_stream_init(&cmd_buffer->dynamic_state_stream,
314 &cmd_buffer->device->dynamic_state_pool, 16384);
318 VkResult anv_ResetCommandBuffer(
319 VkCommandBuffer commandBuffer,
320 VkCommandBufferResetFlags flags)
322 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
323 return anv_cmd_buffer_reset(cmd_buffer);
327 anv_cmd_buffer_emit_state_base_address(struct anv_cmd_buffer *cmd_buffer)
329 switch (cmd_buffer->device->info.gen) {
331 if (cmd_buffer->device->info.is_haswell)
332 return gen75_cmd_buffer_emit_state_base_address(cmd_buffer);
334 return gen7_cmd_buffer_emit_state_base_address(cmd_buffer);
336 return gen8_cmd_buffer_emit_state_base_address(cmd_buffer);
338 return gen9_cmd_buffer_emit_state_base_address(cmd_buffer);
340 return gen10_cmd_buffer_emit_state_base_address(cmd_buffer);
342 unreachable("unsupported gen\n");
346 void anv_CmdBindPipeline(
347 VkCommandBuffer commandBuffer,
348 VkPipelineBindPoint pipelineBindPoint,
349 VkPipeline _pipeline)
351 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
352 ANV_FROM_HANDLE(anv_pipeline, pipeline, _pipeline);
354 switch (pipelineBindPoint) {
355 case VK_PIPELINE_BIND_POINT_COMPUTE:
356 cmd_buffer->state.compute_pipeline = pipeline;
357 cmd_buffer->state.compute_dirty |= ANV_CMD_DIRTY_PIPELINE;
358 cmd_buffer->state.push_constants_dirty |= VK_SHADER_STAGE_COMPUTE_BIT;
359 cmd_buffer->state.descriptors_dirty |= VK_SHADER_STAGE_COMPUTE_BIT;
362 case VK_PIPELINE_BIND_POINT_GRAPHICS:
363 cmd_buffer->state.pipeline = pipeline;
364 cmd_buffer->state.vb_dirty |= pipeline->vb_used;
365 cmd_buffer->state.dirty |= ANV_CMD_DIRTY_PIPELINE;
366 cmd_buffer->state.push_constants_dirty |= pipeline->active_stages;
367 cmd_buffer->state.descriptors_dirty |= pipeline->active_stages;
369 /* Apply the dynamic state from the pipeline */
370 cmd_buffer->state.dirty |= pipeline->dynamic_state_mask;
371 anv_dynamic_state_copy(&cmd_buffer->state.dynamic,
372 &pipeline->dynamic_state,
373 pipeline->dynamic_state_mask);
377 assert(!"invalid bind point");
382 void anv_CmdSetViewport(
383 VkCommandBuffer commandBuffer,
384 uint32_t firstViewport,
385 uint32_t viewportCount,
386 const VkViewport* pViewports)
388 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
390 const uint32_t total_count = firstViewport + viewportCount;
391 if (cmd_buffer->state.dynamic.viewport.count < total_count)
392 cmd_buffer->state.dynamic.viewport.count = total_count;
394 memcpy(cmd_buffer->state.dynamic.viewport.viewports + firstViewport,
395 pViewports, viewportCount * sizeof(*pViewports));
397 cmd_buffer->state.dirty |= ANV_CMD_DIRTY_DYNAMIC_VIEWPORT;
400 void anv_CmdSetScissor(
401 VkCommandBuffer commandBuffer,
402 uint32_t firstScissor,
403 uint32_t scissorCount,
404 const VkRect2D* pScissors)
406 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
408 const uint32_t total_count = firstScissor + scissorCount;
409 if (cmd_buffer->state.dynamic.scissor.count < total_count)
410 cmd_buffer->state.dynamic.scissor.count = total_count;
412 memcpy(cmd_buffer->state.dynamic.scissor.scissors + firstScissor,
413 pScissors, scissorCount * sizeof(*pScissors));
415 cmd_buffer->state.dirty |= ANV_CMD_DIRTY_DYNAMIC_SCISSOR;
418 void anv_CmdSetLineWidth(
419 VkCommandBuffer commandBuffer,
422 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
424 cmd_buffer->state.dynamic.line_width = lineWidth;
425 cmd_buffer->state.dirty |= ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH;
428 void anv_CmdSetDepthBias(
429 VkCommandBuffer commandBuffer,
430 float depthBiasConstantFactor,
431 float depthBiasClamp,
432 float depthBiasSlopeFactor)
434 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
436 cmd_buffer->state.dynamic.depth_bias.bias = depthBiasConstantFactor;
437 cmd_buffer->state.dynamic.depth_bias.clamp = depthBiasClamp;
438 cmd_buffer->state.dynamic.depth_bias.slope = depthBiasSlopeFactor;
440 cmd_buffer->state.dirty |= ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
443 void anv_CmdSetBlendConstants(
444 VkCommandBuffer commandBuffer,
445 const float blendConstants[4])
447 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
449 memcpy(cmd_buffer->state.dynamic.blend_constants,
450 blendConstants, sizeof(float) * 4);
452 cmd_buffer->state.dirty |= ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS;
455 void anv_CmdSetDepthBounds(
456 VkCommandBuffer commandBuffer,
457 float minDepthBounds,
458 float maxDepthBounds)
460 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
462 cmd_buffer->state.dynamic.depth_bounds.min = minDepthBounds;
463 cmd_buffer->state.dynamic.depth_bounds.max = maxDepthBounds;
465 cmd_buffer->state.dirty |= ANV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS;
468 void anv_CmdSetStencilCompareMask(
469 VkCommandBuffer commandBuffer,
470 VkStencilFaceFlags faceMask,
471 uint32_t compareMask)
473 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
475 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
476 cmd_buffer->state.dynamic.stencil_compare_mask.front = compareMask;
477 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
478 cmd_buffer->state.dynamic.stencil_compare_mask.back = compareMask;
480 cmd_buffer->state.dirty |= ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK;
483 void anv_CmdSetStencilWriteMask(
484 VkCommandBuffer commandBuffer,
485 VkStencilFaceFlags faceMask,
488 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
490 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
491 cmd_buffer->state.dynamic.stencil_write_mask.front = writeMask;
492 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
493 cmd_buffer->state.dynamic.stencil_write_mask.back = writeMask;
495 cmd_buffer->state.dirty |= ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK;
498 void anv_CmdSetStencilReference(
499 VkCommandBuffer commandBuffer,
500 VkStencilFaceFlags faceMask,
503 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
505 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
506 cmd_buffer->state.dynamic.stencil_reference.front = reference;
507 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
508 cmd_buffer->state.dynamic.stencil_reference.back = reference;
510 cmd_buffer->state.dirty |= ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE;
513 void anv_CmdBindDescriptorSets(
514 VkCommandBuffer commandBuffer,
515 VkPipelineBindPoint pipelineBindPoint,
516 VkPipelineLayout _layout,
518 uint32_t descriptorSetCount,
519 const VkDescriptorSet* pDescriptorSets,
520 uint32_t dynamicOffsetCount,
521 const uint32_t* pDynamicOffsets)
523 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
524 ANV_FROM_HANDLE(anv_pipeline_layout, layout, _layout);
525 struct anv_descriptor_set_layout *set_layout;
527 assert(firstSet + descriptorSetCount < MAX_SETS);
529 uint32_t dynamic_slot = 0;
530 for (uint32_t i = 0; i < descriptorSetCount; i++) {
531 ANV_FROM_HANDLE(anv_descriptor_set, set, pDescriptorSets[i]);
532 set_layout = layout->set[firstSet + i].layout;
534 cmd_buffer->state.descriptors[firstSet + i] = set;
536 if (set_layout->dynamic_offset_count > 0) {
537 uint32_t dynamic_offset_start =
538 layout->set[firstSet + i].dynamic_offset_start;
540 /* Assert that everything is in range */
541 assert(dynamic_offset_start + set_layout->dynamic_offset_count <=
542 ARRAY_SIZE(cmd_buffer->state.dynamic_offsets));
543 assert(dynamic_slot + set_layout->dynamic_offset_count <=
546 typed_memcpy(&cmd_buffer->state.dynamic_offsets[dynamic_offset_start],
547 &pDynamicOffsets[dynamic_slot],
548 set_layout->dynamic_offset_count);
550 dynamic_slot += set_layout->dynamic_offset_count;
553 cmd_buffer->state.descriptors_dirty |= set_layout->shader_stages;
557 void anv_CmdBindVertexBuffers(
558 VkCommandBuffer commandBuffer,
559 uint32_t firstBinding,
560 uint32_t bindingCount,
561 const VkBuffer* pBuffers,
562 const VkDeviceSize* pOffsets)
564 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
565 struct anv_vertex_binding *vb = cmd_buffer->state.vertex_bindings;
567 /* We have to defer setting up vertex buffer since we need the buffer
568 * stride from the pipeline. */
570 assert(firstBinding + bindingCount <= MAX_VBS);
571 for (uint32_t i = 0; i < bindingCount; i++) {
572 vb[firstBinding + i].buffer = anv_buffer_from_handle(pBuffers[i]);
573 vb[firstBinding + i].offset = pOffsets[i];
574 cmd_buffer->state.vb_dirty |= 1 << (firstBinding + i);
579 anv_isl_format_for_descriptor_type(VkDescriptorType type)
582 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER:
583 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC:
584 return ISL_FORMAT_R32G32B32A32_FLOAT;
586 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER:
587 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC:
588 return ISL_FORMAT_RAW;
591 unreachable("Invalid descriptor type");
596 anv_cmd_buffer_emit_dynamic(struct anv_cmd_buffer *cmd_buffer,
597 const void *data, uint32_t size, uint32_t alignment)
599 struct anv_state state;
601 state = anv_cmd_buffer_alloc_dynamic_state(cmd_buffer, size, alignment);
602 memcpy(state.map, data, size);
604 anv_state_flush(cmd_buffer->device, state);
606 VG(VALGRIND_CHECK_MEM_IS_DEFINED(state.map, size));
612 anv_cmd_buffer_merge_dynamic(struct anv_cmd_buffer *cmd_buffer,
613 uint32_t *a, uint32_t *b,
614 uint32_t dwords, uint32_t alignment)
616 struct anv_state state;
619 state = anv_cmd_buffer_alloc_dynamic_state(cmd_buffer,
620 dwords * 4, alignment);
622 for (uint32_t i = 0; i < dwords; i++)
625 anv_state_flush(cmd_buffer->device, state);
627 VG(VALGRIND_CHECK_MEM_IS_DEFINED(p, dwords * 4));
633 anv_push_constant_value(struct anv_push_constants *data, uint32_t param)
635 if (BRW_PARAM_IS_BUILTIN(param)) {
637 case BRW_PARAM_BUILTIN_ZERO:
640 unreachable("Invalid param builtin");
643 uint32_t offset = ANV_PARAM_PUSH_OFFSET(param);
644 assert(offset % sizeof(uint32_t) == 0);
645 if (offset < data->size)
646 return *(uint32_t *)((uint8_t *)data + offset);
653 anv_cmd_buffer_push_constants(struct anv_cmd_buffer *cmd_buffer,
654 gl_shader_stage stage)
656 /* If we don't have this stage, bail. */
657 if (!anv_pipeline_has_stage(cmd_buffer->state.pipeline, stage))
658 return (struct anv_state) { .offset = 0 };
660 struct anv_push_constants *data =
661 cmd_buffer->state.push_constants[stage];
662 const struct brw_stage_prog_data *prog_data =
663 cmd_buffer->state.pipeline->shaders[stage]->prog_data;
665 /* If we don't actually have any push constants, bail. */
666 if (data == NULL || prog_data == NULL || prog_data->nr_params == 0)
667 return (struct anv_state) { .offset = 0 };
669 struct anv_state state =
670 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer,
671 prog_data->nr_params * sizeof(float),
672 32 /* bottom 5 bits MBZ */);
674 /* Walk through the param array and fill the buffer with data */
675 uint32_t *u32_map = state.map;
676 for (unsigned i = 0; i < prog_data->nr_params; i++)
677 u32_map[i] = anv_push_constant_value(data, prog_data->param[i]);
679 anv_state_flush(cmd_buffer->device, state);
685 anv_cmd_buffer_cs_push_constants(struct anv_cmd_buffer *cmd_buffer)
687 struct anv_push_constants *data =
688 cmd_buffer->state.push_constants[MESA_SHADER_COMPUTE];
689 struct anv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
690 const struct brw_cs_prog_data *cs_prog_data = get_cs_prog_data(pipeline);
691 const struct brw_stage_prog_data *prog_data = &cs_prog_data->base;
693 /* If we don't actually have any push constants, bail. */
694 if (cs_prog_data->push.total.size == 0)
695 return (struct anv_state) { .offset = 0 };
697 const unsigned push_constant_alignment =
698 cmd_buffer->device->info.gen < 8 ? 32 : 64;
699 const unsigned aligned_total_push_constants_size =
700 ALIGN(cs_prog_data->push.total.size, push_constant_alignment);
701 struct anv_state state =
702 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer,
703 aligned_total_push_constants_size,
704 push_constant_alignment);
706 /* Walk through the param array and fill the buffer with data */
707 uint32_t *u32_map = state.map;
709 if (cs_prog_data->push.cross_thread.size > 0) {
711 i < cs_prog_data->push.cross_thread.dwords;
713 assert(prog_data->param[i] != BRW_PARAM_BUILTIN_SUBGROUP_ID);
714 u32_map[i] = anv_push_constant_value(data, prog_data->param[i]);
718 if (cs_prog_data->push.per_thread.size > 0) {
719 for (unsigned t = 0; t < cs_prog_data->threads; t++) {
721 8 * (cs_prog_data->push.per_thread.regs * t +
722 cs_prog_data->push.cross_thread.regs);
723 unsigned src = cs_prog_data->push.cross_thread.dwords;
724 for ( ; src < prog_data->nr_params; src++, dst++) {
725 if (prog_data->param[src] == BRW_PARAM_BUILTIN_SUBGROUP_ID) {
729 anv_push_constant_value(data, prog_data->param[src]);
735 anv_state_flush(cmd_buffer->device, state);
740 void anv_CmdPushConstants(
741 VkCommandBuffer commandBuffer,
742 VkPipelineLayout layout,
743 VkShaderStageFlags stageFlags,
748 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
750 anv_foreach_stage(stage, stageFlags) {
752 anv_cmd_buffer_ensure_push_constant_field(cmd_buffer,
754 if (result != VK_SUCCESS)
757 memcpy(cmd_buffer->state.push_constants[stage]->client_data + offset,
761 cmd_buffer->state.push_constants_dirty |= stageFlags;
764 VkResult anv_CreateCommandPool(
766 const VkCommandPoolCreateInfo* pCreateInfo,
767 const VkAllocationCallbacks* pAllocator,
768 VkCommandPool* pCmdPool)
770 ANV_FROM_HANDLE(anv_device, device, _device);
771 struct anv_cmd_pool *pool;
773 pool = vk_alloc2(&device->alloc, pAllocator, sizeof(*pool), 8,
774 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
776 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
779 pool->alloc = *pAllocator;
781 pool->alloc = device->alloc;
783 list_inithead(&pool->cmd_buffers);
785 *pCmdPool = anv_cmd_pool_to_handle(pool);
790 void anv_DestroyCommandPool(
792 VkCommandPool commandPool,
793 const VkAllocationCallbacks* pAllocator)
795 ANV_FROM_HANDLE(anv_device, device, _device);
796 ANV_FROM_HANDLE(anv_cmd_pool, pool, commandPool);
801 list_for_each_entry_safe(struct anv_cmd_buffer, cmd_buffer,
802 &pool->cmd_buffers, pool_link) {
803 anv_cmd_buffer_destroy(cmd_buffer);
806 vk_free2(&device->alloc, pAllocator, pool);
809 VkResult anv_ResetCommandPool(
811 VkCommandPool commandPool,
812 VkCommandPoolResetFlags flags)
814 ANV_FROM_HANDLE(anv_cmd_pool, pool, commandPool);
816 list_for_each_entry(struct anv_cmd_buffer, cmd_buffer,
817 &pool->cmd_buffers, pool_link) {
818 anv_cmd_buffer_reset(cmd_buffer);
824 void anv_TrimCommandPoolKHR(
826 VkCommandPool commandPool,
827 VkCommandPoolTrimFlagsKHR flags)
829 /* Nothing for us to do here. Our pools stay pretty tidy. */
833 * Return NULL if the current subpass has no depthstencil attachment.
835 const struct anv_image_view *
836 anv_cmd_buffer_get_depth_stencil_view(const struct anv_cmd_buffer *cmd_buffer)
838 const struct anv_subpass *subpass = cmd_buffer->state.subpass;
839 const struct anv_framebuffer *fb = cmd_buffer->state.framebuffer;
841 if (subpass->depth_stencil_attachment.attachment == VK_ATTACHMENT_UNUSED)
844 const struct anv_image_view *iview =
845 fb->attachments[subpass->depth_stencil_attachment.attachment];
847 assert(iview->aspect_mask & (VK_IMAGE_ASPECT_DEPTH_BIT |
848 VK_IMAGE_ASPECT_STENCIL_BIT));
854 anv_cmd_buffer_ensure_push_descriptor_set(struct anv_cmd_buffer *cmd_buffer,
857 struct anv_push_descriptor_set **push_set =
858 &cmd_buffer->state.push_descriptors[set];
860 if (*push_set == NULL) {
861 *push_set = vk_alloc(&cmd_buffer->pool->alloc,
862 sizeof(struct anv_push_descriptor_set), 8,
863 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
864 if (*push_set == NULL) {
865 anv_batch_set_error(&cmd_buffer->batch, VK_ERROR_OUT_OF_HOST_MEMORY);
866 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
873 void anv_CmdPushDescriptorSetKHR(
874 VkCommandBuffer commandBuffer,
875 VkPipelineBindPoint pipelineBindPoint,
876 VkPipelineLayout _layout,
878 uint32_t descriptorWriteCount,
879 const VkWriteDescriptorSet* pDescriptorWrites)
881 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
882 ANV_FROM_HANDLE(anv_pipeline_layout, layout, _layout);
884 assert(pipelineBindPoint == VK_PIPELINE_BIND_POINT_GRAPHICS ||
885 pipelineBindPoint == VK_PIPELINE_BIND_POINT_COMPUTE);
886 assert(_set < MAX_SETS);
888 const struct anv_descriptor_set_layout *set_layout =
889 layout->set[_set].layout;
891 if (anv_cmd_buffer_ensure_push_descriptor_set(cmd_buffer, _set) != VK_SUCCESS)
893 struct anv_push_descriptor_set *push_set =
894 cmd_buffer->state.push_descriptors[_set];
895 struct anv_descriptor_set *set = &push_set->set;
897 set->layout = set_layout;
898 set->size = anv_descriptor_set_layout_size(set_layout);
899 set->buffer_count = set_layout->buffer_count;
900 set->buffer_views = push_set->buffer_views;
902 /* Go through the user supplied descriptors. */
903 for (uint32_t i = 0; i < descriptorWriteCount; i++) {
904 const VkWriteDescriptorSet *write = &pDescriptorWrites[i];
906 switch (write->descriptorType) {
907 case VK_DESCRIPTOR_TYPE_SAMPLER:
908 case VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER:
909 case VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE:
910 case VK_DESCRIPTOR_TYPE_STORAGE_IMAGE:
911 case VK_DESCRIPTOR_TYPE_INPUT_ATTACHMENT:
912 for (uint32_t j = 0; j < write->descriptorCount; j++) {
913 anv_descriptor_set_write_image_view(set, &cmd_buffer->device->info,
914 write->pImageInfo + j,
915 write->descriptorType,
917 write->dstArrayElement + j);
921 case VK_DESCRIPTOR_TYPE_UNIFORM_TEXEL_BUFFER:
922 case VK_DESCRIPTOR_TYPE_STORAGE_TEXEL_BUFFER:
923 for (uint32_t j = 0; j < write->descriptorCount; j++) {
924 ANV_FROM_HANDLE(anv_buffer_view, bview,
925 write->pTexelBufferView[j]);
927 anv_descriptor_set_write_buffer_view(set,
928 write->descriptorType,
931 write->dstArrayElement + j);
935 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER:
936 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER:
937 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC:
938 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC:
939 for (uint32_t j = 0; j < write->descriptorCount; j++) {
940 assert(write->pBufferInfo[j].buffer);
941 ANV_FROM_HANDLE(anv_buffer, buffer, write->pBufferInfo[j].buffer);
944 anv_descriptor_set_write_buffer(set,
946 &cmd_buffer->surface_state_stream,
947 write->descriptorType,
950 write->dstArrayElement + j,
951 write->pBufferInfo[j].offset,
952 write->pBufferInfo[j].range);
961 cmd_buffer->state.descriptors[_set] = set;
962 cmd_buffer->state.descriptors_dirty |= set_layout->shader_stages;
965 void anv_CmdPushDescriptorSetWithTemplateKHR(
966 VkCommandBuffer commandBuffer,
967 VkDescriptorUpdateTemplateKHR descriptorUpdateTemplate,
968 VkPipelineLayout _layout,
972 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
973 ANV_FROM_HANDLE(anv_descriptor_update_template, template,
974 descriptorUpdateTemplate);
975 ANV_FROM_HANDLE(anv_pipeline_layout, layout, _layout);
977 assert(_set < MAX_PUSH_DESCRIPTORS);
979 const struct anv_descriptor_set_layout *set_layout =
980 layout->set[_set].layout;
982 if (anv_cmd_buffer_ensure_push_descriptor_set(cmd_buffer, _set) != VK_SUCCESS)
984 struct anv_push_descriptor_set *push_set =
985 cmd_buffer->state.push_descriptors[_set];
986 struct anv_descriptor_set *set = &push_set->set;
988 set->layout = set_layout;
989 set->size = anv_descriptor_set_layout_size(set_layout);
990 set->buffer_count = set_layout->buffer_count;
991 set->buffer_views = push_set->buffer_views;
993 anv_descriptor_set_write_template(set,
995 &cmd_buffer->surface_state_stream,
999 cmd_buffer->state.descriptors[_set] = set;
1000 cmd_buffer->state.descriptors_dirty |= set_layout->shader_stages;