2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
30 #include "anv_private.h"
32 #include "vk_format_info.h"
34 /** \file anv_cmd_buffer.c
36 * This file contains all of the stuff for emitting commands into a command
37 * buffer. This includes implementations of most of the vkCmd*
38 * entrypoints. This file is concerned entirely with state emission and
39 * not with the command buffer data structure itself. As far as this file
40 * is concerned, most of anv_cmd_buffer is magic.
43 /* TODO: These are taken from GLES. We should check the Vulkan spec */
44 const struct anv_dynamic_state default_dynamic_state = {
57 .blend_constants = { 0.0f, 0.0f, 0.0f, 0.0f },
62 .stencil_compare_mask = {
66 .stencil_write_mask = {
70 .stencil_reference = {
77 anv_dynamic_state_copy(struct anv_dynamic_state *dest,
78 const struct anv_dynamic_state *src,
81 if (copy_mask & (1 << VK_DYNAMIC_STATE_VIEWPORT)) {
82 dest->viewport.count = src->viewport.count;
83 typed_memcpy(dest->viewport.viewports, src->viewport.viewports,
87 if (copy_mask & (1 << VK_DYNAMIC_STATE_SCISSOR)) {
88 dest->scissor.count = src->scissor.count;
89 typed_memcpy(dest->scissor.scissors, src->scissor.scissors,
93 if (copy_mask & (1 << VK_DYNAMIC_STATE_LINE_WIDTH))
94 dest->line_width = src->line_width;
96 if (copy_mask & (1 << VK_DYNAMIC_STATE_DEPTH_BIAS))
97 dest->depth_bias = src->depth_bias;
99 if (copy_mask & (1 << VK_DYNAMIC_STATE_BLEND_CONSTANTS))
100 typed_memcpy(dest->blend_constants, src->blend_constants, 4);
102 if (copy_mask & (1 << VK_DYNAMIC_STATE_DEPTH_BOUNDS))
103 dest->depth_bounds = src->depth_bounds;
105 if (copy_mask & (1 << VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK))
106 dest->stencil_compare_mask = src->stencil_compare_mask;
108 if (copy_mask & (1 << VK_DYNAMIC_STATE_STENCIL_WRITE_MASK))
109 dest->stencil_write_mask = src->stencil_write_mask;
111 if (copy_mask & (1 << VK_DYNAMIC_STATE_STENCIL_REFERENCE))
112 dest->stencil_reference = src->stencil_reference;
116 anv_cmd_state_init(struct anv_cmd_buffer *cmd_buffer)
118 struct anv_cmd_state *state = &cmd_buffer->state;
120 memset(state, 0, sizeof(*state));
122 state->current_pipeline = UINT32_MAX;
123 state->restart_index = UINT32_MAX;
124 state->gfx.dynamic = default_dynamic_state;
128 anv_cmd_pipeline_state_finish(struct anv_cmd_buffer *cmd_buffer,
129 struct anv_cmd_pipeline_state *pipe_state)
131 for (uint32_t i = 0; i < ARRAY_SIZE(pipe_state->push_descriptors); i++)
132 vk_free(&cmd_buffer->pool->alloc, pipe_state->push_descriptors[i]);
136 anv_cmd_state_finish(struct anv_cmd_buffer *cmd_buffer)
138 struct anv_cmd_state *state = &cmd_buffer->state;
140 anv_cmd_pipeline_state_finish(cmd_buffer, &state->gfx.base);
141 anv_cmd_pipeline_state_finish(cmd_buffer, &state->compute.base);
143 for (uint32_t i = 0; i < MESA_SHADER_STAGES; i++)
144 vk_free(&cmd_buffer->pool->alloc, state->push_constants[i]);
146 vk_free(&cmd_buffer->pool->alloc, state->attachments);
150 anv_cmd_state_reset(struct anv_cmd_buffer *cmd_buffer)
152 anv_cmd_state_finish(cmd_buffer);
153 anv_cmd_state_init(cmd_buffer);
157 * This function updates the size of the push constant buffer we need to emit.
158 * This is called in various parts of the driver to ensure that different
159 * pieces of push constant data get emitted as needed. However, it is important
160 * that we never shrink the size of the buffer. For example, a compute shader
161 * dispatch will always call this for the base group id, which has an
162 * offset in the push constant buffer that is smaller than the offset for
163 * storage image data. If the compute shader has storage images, we will call
164 * this again with a larger size during binding table emission. However,
165 * if we dispatch the compute shader again without dirtying our descriptors,
166 * we would still call this function with a smaller size for the base group
167 * id, and not for the images, which would incorrectly shrink the size of the
168 * push constant data we emit with that dispatch, making us drop the image data.
171 anv_cmd_buffer_ensure_push_constants_size(struct anv_cmd_buffer *cmd_buffer,
172 gl_shader_stage stage, uint32_t size)
174 struct anv_push_constants **ptr = &cmd_buffer->state.push_constants[stage];
177 *ptr = vk_alloc(&cmd_buffer->pool->alloc, size, 8,
178 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
180 anv_batch_set_error(&cmd_buffer->batch, VK_ERROR_OUT_OF_HOST_MEMORY);
181 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
184 } else if ((*ptr)->size < size) {
185 *ptr = vk_realloc(&cmd_buffer->pool->alloc, *ptr, size, 8,
186 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
188 anv_batch_set_error(&cmd_buffer->batch, VK_ERROR_OUT_OF_HOST_MEMORY);
189 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
197 static VkResult anv_create_cmd_buffer(
198 struct anv_device * device,
199 struct anv_cmd_pool * pool,
200 VkCommandBufferLevel level,
201 VkCommandBuffer* pCommandBuffer)
203 struct anv_cmd_buffer *cmd_buffer;
206 cmd_buffer = vk_alloc(&pool->alloc, sizeof(*cmd_buffer), 8,
207 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
208 if (cmd_buffer == NULL)
209 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
211 cmd_buffer->batch.status = VK_SUCCESS;
213 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
214 cmd_buffer->device = device;
215 cmd_buffer->pool = pool;
216 cmd_buffer->level = level;
218 result = anv_cmd_buffer_init_batch_bo_chain(cmd_buffer);
219 if (result != VK_SUCCESS)
222 anv_state_stream_init(&cmd_buffer->surface_state_stream,
223 &device->surface_state_pool, 4096);
224 anv_state_stream_init(&cmd_buffer->dynamic_state_stream,
225 &device->dynamic_state_pool, 16384);
227 anv_cmd_state_init(cmd_buffer);
230 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
232 /* Init the pool_link so we can safefly call list_del when we destroy
235 list_inithead(&cmd_buffer->pool_link);
238 *pCommandBuffer = anv_cmd_buffer_to_handle(cmd_buffer);
243 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
248 VkResult anv_AllocateCommandBuffers(
250 const VkCommandBufferAllocateInfo* pAllocateInfo,
251 VkCommandBuffer* pCommandBuffers)
253 ANV_FROM_HANDLE(anv_device, device, _device);
254 ANV_FROM_HANDLE(anv_cmd_pool, pool, pAllocateInfo->commandPool);
256 VkResult result = VK_SUCCESS;
259 for (i = 0; i < pAllocateInfo->commandBufferCount; i++) {
260 result = anv_create_cmd_buffer(device, pool, pAllocateInfo->level,
261 &pCommandBuffers[i]);
262 if (result != VK_SUCCESS)
266 if (result != VK_SUCCESS) {
267 anv_FreeCommandBuffers(_device, pAllocateInfo->commandPool,
269 for (i = 0; i < pAllocateInfo->commandBufferCount; i++)
270 pCommandBuffers[i] = VK_NULL_HANDLE;
277 anv_cmd_buffer_destroy(struct anv_cmd_buffer *cmd_buffer)
279 list_del(&cmd_buffer->pool_link);
281 anv_cmd_buffer_fini_batch_bo_chain(cmd_buffer);
283 anv_state_stream_finish(&cmd_buffer->surface_state_stream);
284 anv_state_stream_finish(&cmd_buffer->dynamic_state_stream);
286 anv_cmd_state_finish(cmd_buffer);
288 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
291 void anv_FreeCommandBuffers(
293 VkCommandPool commandPool,
294 uint32_t commandBufferCount,
295 const VkCommandBuffer* pCommandBuffers)
297 for (uint32_t i = 0; i < commandBufferCount; i++) {
298 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, pCommandBuffers[i]);
303 anv_cmd_buffer_destroy(cmd_buffer);
308 anv_cmd_buffer_reset(struct anv_cmd_buffer *cmd_buffer)
310 cmd_buffer->usage_flags = 0;
311 anv_cmd_buffer_reset_batch_bo_chain(cmd_buffer);
312 anv_cmd_state_reset(cmd_buffer);
314 anv_state_stream_finish(&cmd_buffer->surface_state_stream);
315 anv_state_stream_init(&cmd_buffer->surface_state_stream,
316 &cmd_buffer->device->surface_state_pool, 4096);
318 anv_state_stream_finish(&cmd_buffer->dynamic_state_stream);
319 anv_state_stream_init(&cmd_buffer->dynamic_state_stream,
320 &cmd_buffer->device->dynamic_state_pool, 16384);
324 VkResult anv_ResetCommandBuffer(
325 VkCommandBuffer commandBuffer,
326 VkCommandBufferResetFlags flags)
328 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
329 return anv_cmd_buffer_reset(cmd_buffer);
332 #define anv_genX_call(devinfo, func, ...) \
333 switch ((devinfo)->gen) { \
335 if ((devinfo)->is_haswell) { \
336 gen75_##func(__VA_ARGS__); \
338 gen7_##func(__VA_ARGS__); \
342 gen8_##func(__VA_ARGS__); \
345 gen9_##func(__VA_ARGS__); \
348 gen10_##func(__VA_ARGS__); \
351 gen11_##func(__VA_ARGS__); \
354 assert(!"Unknown hardware generation"); \
358 anv_cmd_buffer_emit_state_base_address(struct anv_cmd_buffer *cmd_buffer)
360 anv_genX_call(&cmd_buffer->device->info,
361 cmd_buffer_emit_state_base_address,
366 anv_cmd_buffer_mark_image_written(struct anv_cmd_buffer *cmd_buffer,
367 const struct anv_image *image,
368 VkImageAspectFlagBits aspect,
369 enum isl_aux_usage aux_usage,
372 uint32_t layer_count)
374 anv_genX_call(&cmd_buffer->device->info,
375 cmd_buffer_mark_image_written,
376 cmd_buffer, image, aspect, aux_usage,
377 level, base_layer, layer_count);
380 void anv_CmdBindPipeline(
381 VkCommandBuffer commandBuffer,
382 VkPipelineBindPoint pipelineBindPoint,
383 VkPipeline _pipeline)
385 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
386 ANV_FROM_HANDLE(anv_pipeline, pipeline, _pipeline);
388 switch (pipelineBindPoint) {
389 case VK_PIPELINE_BIND_POINT_COMPUTE:
390 cmd_buffer->state.compute.base.pipeline = pipeline;
391 cmd_buffer->state.compute.pipeline_dirty = true;
392 cmd_buffer->state.push_constants_dirty |= VK_SHADER_STAGE_COMPUTE_BIT;
393 cmd_buffer->state.descriptors_dirty |= VK_SHADER_STAGE_COMPUTE_BIT;
396 case VK_PIPELINE_BIND_POINT_GRAPHICS:
397 cmd_buffer->state.gfx.base.pipeline = pipeline;
398 cmd_buffer->state.gfx.vb_dirty |= pipeline->vb_used;
399 cmd_buffer->state.gfx.dirty |= ANV_CMD_DIRTY_PIPELINE;
400 cmd_buffer->state.push_constants_dirty |= pipeline->active_stages;
401 cmd_buffer->state.descriptors_dirty |= pipeline->active_stages;
403 /* Apply the dynamic state from the pipeline */
404 cmd_buffer->state.gfx.dirty |= pipeline->dynamic_state_mask;
405 anv_dynamic_state_copy(&cmd_buffer->state.gfx.dynamic,
406 &pipeline->dynamic_state,
407 pipeline->dynamic_state_mask);
411 assert(!"invalid bind point");
416 void anv_CmdSetViewport(
417 VkCommandBuffer commandBuffer,
418 uint32_t firstViewport,
419 uint32_t viewportCount,
420 const VkViewport* pViewports)
422 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
424 const uint32_t total_count = firstViewport + viewportCount;
425 if (cmd_buffer->state.gfx.dynamic.viewport.count < total_count)
426 cmd_buffer->state.gfx.dynamic.viewport.count = total_count;
428 memcpy(cmd_buffer->state.gfx.dynamic.viewport.viewports + firstViewport,
429 pViewports, viewportCount * sizeof(*pViewports));
431 cmd_buffer->state.gfx.dirty |= ANV_CMD_DIRTY_DYNAMIC_VIEWPORT;
434 void anv_CmdSetScissor(
435 VkCommandBuffer commandBuffer,
436 uint32_t firstScissor,
437 uint32_t scissorCount,
438 const VkRect2D* pScissors)
440 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
442 const uint32_t total_count = firstScissor + scissorCount;
443 if (cmd_buffer->state.gfx.dynamic.scissor.count < total_count)
444 cmd_buffer->state.gfx.dynamic.scissor.count = total_count;
446 memcpy(cmd_buffer->state.gfx.dynamic.scissor.scissors + firstScissor,
447 pScissors, scissorCount * sizeof(*pScissors));
449 cmd_buffer->state.gfx.dirty |= ANV_CMD_DIRTY_DYNAMIC_SCISSOR;
452 void anv_CmdSetLineWidth(
453 VkCommandBuffer commandBuffer,
456 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
458 cmd_buffer->state.gfx.dynamic.line_width = lineWidth;
459 cmd_buffer->state.gfx.dirty |= ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH;
462 void anv_CmdSetDepthBias(
463 VkCommandBuffer commandBuffer,
464 float depthBiasConstantFactor,
465 float depthBiasClamp,
466 float depthBiasSlopeFactor)
468 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
470 cmd_buffer->state.gfx.dynamic.depth_bias.bias = depthBiasConstantFactor;
471 cmd_buffer->state.gfx.dynamic.depth_bias.clamp = depthBiasClamp;
472 cmd_buffer->state.gfx.dynamic.depth_bias.slope = depthBiasSlopeFactor;
474 cmd_buffer->state.gfx.dirty |= ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
477 void anv_CmdSetBlendConstants(
478 VkCommandBuffer commandBuffer,
479 const float blendConstants[4])
481 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
483 memcpy(cmd_buffer->state.gfx.dynamic.blend_constants,
484 blendConstants, sizeof(float) * 4);
486 cmd_buffer->state.gfx.dirty |= ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS;
489 void anv_CmdSetDepthBounds(
490 VkCommandBuffer commandBuffer,
491 float minDepthBounds,
492 float maxDepthBounds)
494 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
496 cmd_buffer->state.gfx.dynamic.depth_bounds.min = minDepthBounds;
497 cmd_buffer->state.gfx.dynamic.depth_bounds.max = maxDepthBounds;
499 cmd_buffer->state.gfx.dirty |= ANV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS;
502 void anv_CmdSetStencilCompareMask(
503 VkCommandBuffer commandBuffer,
504 VkStencilFaceFlags faceMask,
505 uint32_t compareMask)
507 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
509 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
510 cmd_buffer->state.gfx.dynamic.stencil_compare_mask.front = compareMask;
511 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
512 cmd_buffer->state.gfx.dynamic.stencil_compare_mask.back = compareMask;
514 cmd_buffer->state.gfx.dirty |= ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK;
517 void anv_CmdSetStencilWriteMask(
518 VkCommandBuffer commandBuffer,
519 VkStencilFaceFlags faceMask,
522 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
524 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
525 cmd_buffer->state.gfx.dynamic.stencil_write_mask.front = writeMask;
526 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
527 cmd_buffer->state.gfx.dynamic.stencil_write_mask.back = writeMask;
529 cmd_buffer->state.gfx.dirty |= ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK;
532 void anv_CmdSetStencilReference(
533 VkCommandBuffer commandBuffer,
534 VkStencilFaceFlags faceMask,
537 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
539 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
540 cmd_buffer->state.gfx.dynamic.stencil_reference.front = reference;
541 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
542 cmd_buffer->state.gfx.dynamic.stencil_reference.back = reference;
544 cmd_buffer->state.gfx.dirty |= ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE;
548 anv_cmd_buffer_bind_descriptor_set(struct anv_cmd_buffer *cmd_buffer,
549 VkPipelineBindPoint bind_point,
550 struct anv_pipeline_layout *layout,
552 struct anv_descriptor_set *set,
553 uint32_t *dynamic_offset_count,
554 const uint32_t **dynamic_offsets)
556 struct anv_descriptor_set_layout *set_layout =
557 layout->set[set_index].layout;
559 struct anv_cmd_pipeline_state *pipe_state;
560 if (bind_point == VK_PIPELINE_BIND_POINT_COMPUTE) {
561 pipe_state = &cmd_buffer->state.compute.base;
563 assert(bind_point == VK_PIPELINE_BIND_POINT_GRAPHICS);
564 pipe_state = &cmd_buffer->state.gfx.base;
566 pipe_state->descriptors[set_index] = set;
568 if (dynamic_offsets) {
569 if (set_layout->dynamic_offset_count > 0) {
570 uint32_t dynamic_offset_start =
571 layout->set[set_index].dynamic_offset_start;
573 /* Assert that everything is in range */
574 assert(set_layout->dynamic_offset_count <= *dynamic_offset_count);
575 assert(dynamic_offset_start + set_layout->dynamic_offset_count <=
576 ARRAY_SIZE(pipe_state->dynamic_offsets));
578 typed_memcpy(&pipe_state->dynamic_offsets[dynamic_offset_start],
579 *dynamic_offsets, set_layout->dynamic_offset_count);
581 *dynamic_offsets += set_layout->dynamic_offset_count;
582 *dynamic_offset_count -= set_layout->dynamic_offset_count;
586 if (bind_point == VK_PIPELINE_BIND_POINT_COMPUTE) {
587 cmd_buffer->state.descriptors_dirty |= VK_SHADER_STAGE_COMPUTE_BIT;
589 assert(bind_point == VK_PIPELINE_BIND_POINT_GRAPHICS);
590 cmd_buffer->state.descriptors_dirty |=
591 set_layout->shader_stages & VK_SHADER_STAGE_ALL_GRAPHICS;
594 /* Pipeline layout objects are required to live at least while any command
595 * buffers that use them are in recording state. We need to grab a reference
596 * to the pipeline layout being bound here so we can compute correct dynamic
597 * offsets for VK_DESCRIPTOR_TYPE_*_DYNAMIC in dynamic_offset_for_binding()
598 * when we record draw commands that come after this.
600 pipe_state->layout = layout;
603 void anv_CmdBindDescriptorSets(
604 VkCommandBuffer commandBuffer,
605 VkPipelineBindPoint pipelineBindPoint,
606 VkPipelineLayout _layout,
608 uint32_t descriptorSetCount,
609 const VkDescriptorSet* pDescriptorSets,
610 uint32_t dynamicOffsetCount,
611 const uint32_t* pDynamicOffsets)
613 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
614 ANV_FROM_HANDLE(anv_pipeline_layout, layout, _layout);
616 assert(firstSet + descriptorSetCount <= MAX_SETS);
618 for (uint32_t i = 0; i < descriptorSetCount; i++) {
619 ANV_FROM_HANDLE(anv_descriptor_set, set, pDescriptorSets[i]);
620 anv_cmd_buffer_bind_descriptor_set(cmd_buffer, pipelineBindPoint,
621 layout, firstSet + i, set,
627 void anv_CmdBindVertexBuffers(
628 VkCommandBuffer commandBuffer,
629 uint32_t firstBinding,
630 uint32_t bindingCount,
631 const VkBuffer* pBuffers,
632 const VkDeviceSize* pOffsets)
634 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
635 struct anv_vertex_binding *vb = cmd_buffer->state.vertex_bindings;
637 /* We have to defer setting up vertex buffer since we need the buffer
638 * stride from the pipeline. */
640 assert(firstBinding + bindingCount <= MAX_VBS);
641 for (uint32_t i = 0; i < bindingCount; i++) {
642 vb[firstBinding + i].buffer = anv_buffer_from_handle(pBuffers[i]);
643 vb[firstBinding + i].offset = pOffsets[i];
644 cmd_buffer->state.gfx.vb_dirty |= 1 << (firstBinding + i);
649 anv_isl_format_for_descriptor_type(VkDescriptorType type)
652 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER:
653 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC:
654 return ISL_FORMAT_R32G32B32A32_FLOAT;
656 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER:
657 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC:
658 return ISL_FORMAT_RAW;
661 unreachable("Invalid descriptor type");
666 anv_cmd_buffer_emit_dynamic(struct anv_cmd_buffer *cmd_buffer,
667 const void *data, uint32_t size, uint32_t alignment)
669 struct anv_state state;
671 state = anv_cmd_buffer_alloc_dynamic_state(cmd_buffer, size, alignment);
672 memcpy(state.map, data, size);
674 VG(VALGRIND_CHECK_MEM_IS_DEFINED(state.map, size));
680 anv_cmd_buffer_merge_dynamic(struct anv_cmd_buffer *cmd_buffer,
681 uint32_t *a, uint32_t *b,
682 uint32_t dwords, uint32_t alignment)
684 struct anv_state state;
687 state = anv_cmd_buffer_alloc_dynamic_state(cmd_buffer,
688 dwords * 4, alignment);
690 for (uint32_t i = 0; i < dwords; i++)
693 VG(VALGRIND_CHECK_MEM_IS_DEFINED(p, dwords * 4));
699 anv_push_constant_value(struct anv_push_constants *data, uint32_t param)
701 if (BRW_PARAM_IS_BUILTIN(param)) {
703 case BRW_PARAM_BUILTIN_ZERO:
705 case BRW_PARAM_BUILTIN_BASE_WORK_GROUP_ID_X:
706 return data->base_work_group_id[0];
707 case BRW_PARAM_BUILTIN_BASE_WORK_GROUP_ID_Y:
708 return data->base_work_group_id[1];
709 case BRW_PARAM_BUILTIN_BASE_WORK_GROUP_ID_Z:
710 return data->base_work_group_id[2];
712 unreachable("Invalid param builtin");
715 uint32_t offset = ANV_PARAM_PUSH_OFFSET(param);
716 assert(offset % sizeof(uint32_t) == 0);
717 if (offset < data->size)
718 return *(uint32_t *)((uint8_t *)data + offset);
725 anv_cmd_buffer_push_constants(struct anv_cmd_buffer *cmd_buffer,
726 gl_shader_stage stage)
728 struct anv_pipeline *pipeline = cmd_buffer->state.gfx.base.pipeline;
730 /* If we don't have this stage, bail. */
731 if (!anv_pipeline_has_stage(pipeline, stage))
732 return (struct anv_state) { .offset = 0 };
734 struct anv_push_constants *data =
735 cmd_buffer->state.push_constants[stage];
736 const struct brw_stage_prog_data *prog_data =
737 pipeline->shaders[stage]->prog_data;
739 /* If we don't actually have any push constants, bail. */
740 if (data == NULL || prog_data == NULL || prog_data->nr_params == 0)
741 return (struct anv_state) { .offset = 0 };
743 struct anv_state state =
744 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer,
745 prog_data->nr_params * sizeof(float),
746 32 /* bottom 5 bits MBZ */);
748 /* Walk through the param array and fill the buffer with data */
749 uint32_t *u32_map = state.map;
750 for (unsigned i = 0; i < prog_data->nr_params; i++)
751 u32_map[i] = anv_push_constant_value(data, prog_data->param[i]);
757 anv_cmd_buffer_cs_push_constants(struct anv_cmd_buffer *cmd_buffer)
759 struct anv_push_constants *data =
760 cmd_buffer->state.push_constants[MESA_SHADER_COMPUTE];
761 struct anv_pipeline *pipeline = cmd_buffer->state.compute.base.pipeline;
762 const struct brw_cs_prog_data *cs_prog_data = get_cs_prog_data(pipeline);
763 const struct brw_stage_prog_data *prog_data = &cs_prog_data->base;
765 /* If we don't actually have any push constants, bail. */
766 if (cs_prog_data->push.total.size == 0)
767 return (struct anv_state) { .offset = 0 };
769 const unsigned push_constant_alignment =
770 cmd_buffer->device->info.gen < 8 ? 32 : 64;
771 const unsigned aligned_total_push_constants_size =
772 ALIGN(cs_prog_data->push.total.size, push_constant_alignment);
773 struct anv_state state =
774 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer,
775 aligned_total_push_constants_size,
776 push_constant_alignment);
778 /* Walk through the param array and fill the buffer with data */
779 uint32_t *u32_map = state.map;
781 if (cs_prog_data->push.cross_thread.size > 0) {
783 i < cs_prog_data->push.cross_thread.dwords;
785 assert(prog_data->param[i] != BRW_PARAM_BUILTIN_SUBGROUP_ID);
786 u32_map[i] = anv_push_constant_value(data, prog_data->param[i]);
790 if (cs_prog_data->push.per_thread.size > 0) {
791 for (unsigned t = 0; t < cs_prog_data->threads; t++) {
793 8 * (cs_prog_data->push.per_thread.regs * t +
794 cs_prog_data->push.cross_thread.regs);
795 unsigned src = cs_prog_data->push.cross_thread.dwords;
796 for ( ; src < prog_data->nr_params; src++, dst++) {
797 if (prog_data->param[src] == BRW_PARAM_BUILTIN_SUBGROUP_ID) {
801 anv_push_constant_value(data, prog_data->param[src]);
810 void anv_CmdPushConstants(
811 VkCommandBuffer commandBuffer,
812 VkPipelineLayout layout,
813 VkShaderStageFlags stageFlags,
818 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
820 anv_foreach_stage(stage, stageFlags) {
822 anv_cmd_buffer_ensure_push_constant_field(cmd_buffer,
824 if (result != VK_SUCCESS)
827 memcpy(cmd_buffer->state.push_constants[stage]->client_data + offset,
831 cmd_buffer->state.push_constants_dirty |= stageFlags;
834 VkResult anv_CreateCommandPool(
836 const VkCommandPoolCreateInfo* pCreateInfo,
837 const VkAllocationCallbacks* pAllocator,
838 VkCommandPool* pCmdPool)
840 ANV_FROM_HANDLE(anv_device, device, _device);
841 struct anv_cmd_pool *pool;
843 pool = vk_alloc2(&device->alloc, pAllocator, sizeof(*pool), 8,
844 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
846 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
849 pool->alloc = *pAllocator;
851 pool->alloc = device->alloc;
853 list_inithead(&pool->cmd_buffers);
855 *pCmdPool = anv_cmd_pool_to_handle(pool);
860 void anv_DestroyCommandPool(
862 VkCommandPool commandPool,
863 const VkAllocationCallbacks* pAllocator)
865 ANV_FROM_HANDLE(anv_device, device, _device);
866 ANV_FROM_HANDLE(anv_cmd_pool, pool, commandPool);
871 list_for_each_entry_safe(struct anv_cmd_buffer, cmd_buffer,
872 &pool->cmd_buffers, pool_link) {
873 anv_cmd_buffer_destroy(cmd_buffer);
876 vk_free2(&device->alloc, pAllocator, pool);
879 VkResult anv_ResetCommandPool(
881 VkCommandPool commandPool,
882 VkCommandPoolResetFlags flags)
884 ANV_FROM_HANDLE(anv_cmd_pool, pool, commandPool);
886 list_for_each_entry(struct anv_cmd_buffer, cmd_buffer,
887 &pool->cmd_buffers, pool_link) {
888 anv_cmd_buffer_reset(cmd_buffer);
894 void anv_TrimCommandPool(
896 VkCommandPool commandPool,
897 VkCommandPoolTrimFlags flags)
899 /* Nothing for us to do here. Our pools stay pretty tidy. */
903 * Return NULL if the current subpass has no depthstencil attachment.
905 const struct anv_image_view *
906 anv_cmd_buffer_get_depth_stencil_view(const struct anv_cmd_buffer *cmd_buffer)
908 const struct anv_subpass *subpass = cmd_buffer->state.subpass;
909 const struct anv_framebuffer *fb = cmd_buffer->state.framebuffer;
911 if (subpass->depth_stencil_attachment == NULL)
914 const struct anv_image_view *iview =
915 fb->attachments[subpass->depth_stencil_attachment->attachment];
917 assert(iview->aspect_mask & (VK_IMAGE_ASPECT_DEPTH_BIT |
918 VK_IMAGE_ASPECT_STENCIL_BIT));
923 static struct anv_push_descriptor_set *
924 anv_cmd_buffer_get_push_descriptor_set(struct anv_cmd_buffer *cmd_buffer,
925 VkPipelineBindPoint bind_point,
928 struct anv_cmd_pipeline_state *pipe_state;
929 if (bind_point == VK_PIPELINE_BIND_POINT_COMPUTE) {
930 pipe_state = &cmd_buffer->state.compute.base;
932 assert(bind_point == VK_PIPELINE_BIND_POINT_GRAPHICS);
933 pipe_state = &cmd_buffer->state.gfx.base;
936 struct anv_push_descriptor_set **push_set =
937 &pipe_state->push_descriptors[set];
939 if (*push_set == NULL) {
940 *push_set = vk_alloc(&cmd_buffer->pool->alloc,
941 sizeof(struct anv_push_descriptor_set), 8,
942 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
943 if (*push_set == NULL) {
944 anv_batch_set_error(&cmd_buffer->batch, VK_ERROR_OUT_OF_HOST_MEMORY);
952 void anv_CmdPushDescriptorSetKHR(
953 VkCommandBuffer commandBuffer,
954 VkPipelineBindPoint pipelineBindPoint,
955 VkPipelineLayout _layout,
957 uint32_t descriptorWriteCount,
958 const VkWriteDescriptorSet* pDescriptorWrites)
960 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
961 ANV_FROM_HANDLE(anv_pipeline_layout, layout, _layout);
963 assert(_set < MAX_SETS);
965 struct anv_descriptor_set_layout *set_layout = layout->set[_set].layout;
967 struct anv_push_descriptor_set *push_set =
968 anv_cmd_buffer_get_push_descriptor_set(cmd_buffer,
969 pipelineBindPoint, _set);
973 struct anv_descriptor_set *set = &push_set->set;
975 set->layout = set_layout;
976 set->size = anv_descriptor_set_layout_size(set_layout);
977 set->buffer_count = set_layout->buffer_count;
978 set->buffer_views = push_set->buffer_views;
980 /* Go through the user supplied descriptors. */
981 for (uint32_t i = 0; i < descriptorWriteCount; i++) {
982 const VkWriteDescriptorSet *write = &pDescriptorWrites[i];
984 switch (write->descriptorType) {
985 case VK_DESCRIPTOR_TYPE_SAMPLER:
986 case VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER:
987 case VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE:
988 case VK_DESCRIPTOR_TYPE_STORAGE_IMAGE:
989 case VK_DESCRIPTOR_TYPE_INPUT_ATTACHMENT:
990 for (uint32_t j = 0; j < write->descriptorCount; j++) {
991 anv_descriptor_set_write_image_view(set, &cmd_buffer->device->info,
992 write->pImageInfo + j,
993 write->descriptorType,
995 write->dstArrayElement + j);
999 case VK_DESCRIPTOR_TYPE_UNIFORM_TEXEL_BUFFER:
1000 case VK_DESCRIPTOR_TYPE_STORAGE_TEXEL_BUFFER:
1001 for (uint32_t j = 0; j < write->descriptorCount; j++) {
1002 ANV_FROM_HANDLE(anv_buffer_view, bview,
1003 write->pTexelBufferView[j]);
1005 anv_descriptor_set_write_buffer_view(set,
1006 write->descriptorType,
1009 write->dstArrayElement + j);
1013 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER:
1014 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER:
1015 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC:
1016 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC:
1017 for (uint32_t j = 0; j < write->descriptorCount; j++) {
1018 assert(write->pBufferInfo[j].buffer);
1019 ANV_FROM_HANDLE(anv_buffer, buffer, write->pBufferInfo[j].buffer);
1022 anv_descriptor_set_write_buffer(set,
1024 &cmd_buffer->surface_state_stream,
1025 write->descriptorType,
1028 write->dstArrayElement + j,
1029 write->pBufferInfo[j].offset,
1030 write->pBufferInfo[j].range);
1039 anv_cmd_buffer_bind_descriptor_set(cmd_buffer, pipelineBindPoint,
1040 layout, _set, set, NULL, NULL);
1043 void anv_CmdPushDescriptorSetWithTemplateKHR(
1044 VkCommandBuffer commandBuffer,
1045 VkDescriptorUpdateTemplate descriptorUpdateTemplate,
1046 VkPipelineLayout _layout,
1050 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
1051 ANV_FROM_HANDLE(anv_descriptor_update_template, template,
1052 descriptorUpdateTemplate);
1053 ANV_FROM_HANDLE(anv_pipeline_layout, layout, _layout);
1055 assert(_set < MAX_PUSH_DESCRIPTORS);
1057 struct anv_descriptor_set_layout *set_layout = layout->set[_set].layout;
1059 struct anv_push_descriptor_set *push_set =
1060 anv_cmd_buffer_get_push_descriptor_set(cmd_buffer,
1061 template->bind_point, _set);
1065 struct anv_descriptor_set *set = &push_set->set;
1067 set->layout = set_layout;
1068 set->size = anv_descriptor_set_layout_size(set_layout);
1069 set->buffer_count = set_layout->buffer_count;
1070 set->buffer_views = push_set->buffer_views;
1072 anv_descriptor_set_write_template(set,
1074 &cmd_buffer->surface_state_stream,
1078 anv_cmd_buffer_bind_descriptor_set(cmd_buffer, template->bind_point,
1079 layout, _set, set, NULL, NULL);
1082 void anv_CmdSetDeviceMask(
1083 VkCommandBuffer commandBuffer,
1084 uint32_t deviceMask)