2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
30 #include "anv_private.h"
32 #include "vk_format_info.h"
34 /** \file anv_cmd_buffer.c
36 * This file contains all of the stuff for emitting commands into a command
37 * buffer. This includes implementations of most of the vkCmd*
38 * entrypoints. This file is concerned entirely with state emission and
39 * not with the command buffer data structure itself. As far as this file
40 * is concerned, most of anv_cmd_buffer is magic.
43 /* TODO: These are taken from GLES. We should check the Vulkan spec */
44 const struct anv_dynamic_state default_dynamic_state = {
57 .blend_constants = { 0.0f, 0.0f, 0.0f, 0.0f },
62 .stencil_compare_mask = {
66 .stencil_write_mask = {
70 .stencil_reference = {
77 anv_dynamic_state_copy(struct anv_dynamic_state *dest,
78 const struct anv_dynamic_state *src,
81 if (copy_mask & (1 << VK_DYNAMIC_STATE_VIEWPORT)) {
82 dest->viewport.count = src->viewport.count;
83 typed_memcpy(dest->viewport.viewports, src->viewport.viewports,
87 if (copy_mask & (1 << VK_DYNAMIC_STATE_SCISSOR)) {
88 dest->scissor.count = src->scissor.count;
89 typed_memcpy(dest->scissor.scissors, src->scissor.scissors,
93 if (copy_mask & (1 << VK_DYNAMIC_STATE_LINE_WIDTH))
94 dest->line_width = src->line_width;
96 if (copy_mask & (1 << VK_DYNAMIC_STATE_DEPTH_BIAS))
97 dest->depth_bias = src->depth_bias;
99 if (copy_mask & (1 << VK_DYNAMIC_STATE_BLEND_CONSTANTS))
100 typed_memcpy(dest->blend_constants, src->blend_constants, 4);
102 if (copy_mask & (1 << VK_DYNAMIC_STATE_DEPTH_BOUNDS))
103 dest->depth_bounds = src->depth_bounds;
105 if (copy_mask & (1 << VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK))
106 dest->stencil_compare_mask = src->stencil_compare_mask;
108 if (copy_mask & (1 << VK_DYNAMIC_STATE_STENCIL_WRITE_MASK))
109 dest->stencil_write_mask = src->stencil_write_mask;
111 if (copy_mask & (1 << VK_DYNAMIC_STATE_STENCIL_REFERENCE))
112 dest->stencil_reference = src->stencil_reference;
116 anv_cmd_state_init(struct anv_cmd_buffer *cmd_buffer)
118 struct anv_cmd_state *state = &cmd_buffer->state;
120 memset(state, 0, sizeof(*state));
122 state->current_pipeline = UINT32_MAX;
123 state->restart_index = UINT32_MAX;
124 state->gfx.dynamic = default_dynamic_state;
128 anv_cmd_pipeline_state_finish(struct anv_cmd_buffer *cmd_buffer,
129 struct anv_cmd_pipeline_state *pipe_state)
131 for (uint32_t i = 0; i < ARRAY_SIZE(pipe_state->push_descriptors); i++)
132 vk_free(&cmd_buffer->pool->alloc, pipe_state->push_descriptors[i]);
136 anv_cmd_state_finish(struct anv_cmd_buffer *cmd_buffer)
138 struct anv_cmd_state *state = &cmd_buffer->state;
140 anv_cmd_pipeline_state_finish(cmd_buffer, &state->gfx.base);
141 anv_cmd_pipeline_state_finish(cmd_buffer, &state->compute.base);
143 for (uint32_t i = 0; i < MESA_SHADER_STAGES; i++)
144 vk_free(&cmd_buffer->pool->alloc, state->push_constants[i]);
146 vk_free(&cmd_buffer->pool->alloc, state->attachments);
150 anv_cmd_state_reset(struct anv_cmd_buffer *cmd_buffer)
152 anv_cmd_state_finish(cmd_buffer);
153 anv_cmd_state_init(cmd_buffer);
157 anv_cmd_buffer_ensure_push_constants_size(struct anv_cmd_buffer *cmd_buffer,
158 gl_shader_stage stage, uint32_t size)
160 struct anv_push_constants **ptr = &cmd_buffer->state.push_constants[stage];
163 *ptr = vk_alloc(&cmd_buffer->pool->alloc, size, 8,
164 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
166 anv_batch_set_error(&cmd_buffer->batch, VK_ERROR_OUT_OF_HOST_MEMORY);
167 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
169 } else if ((*ptr)->size < size) {
170 *ptr = vk_realloc(&cmd_buffer->pool->alloc, *ptr, size, 8,
171 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
173 anv_batch_set_error(&cmd_buffer->batch, VK_ERROR_OUT_OF_HOST_MEMORY);
174 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
182 static VkResult anv_create_cmd_buffer(
183 struct anv_device * device,
184 struct anv_cmd_pool * pool,
185 VkCommandBufferLevel level,
186 VkCommandBuffer* pCommandBuffer)
188 struct anv_cmd_buffer *cmd_buffer;
191 cmd_buffer = vk_alloc(&pool->alloc, sizeof(*cmd_buffer), 8,
192 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
193 if (cmd_buffer == NULL)
194 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
196 cmd_buffer->batch.status = VK_SUCCESS;
198 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
199 cmd_buffer->device = device;
200 cmd_buffer->pool = pool;
201 cmd_buffer->level = level;
203 result = anv_cmd_buffer_init_batch_bo_chain(cmd_buffer);
204 if (result != VK_SUCCESS)
207 anv_state_stream_init(&cmd_buffer->surface_state_stream,
208 &device->surface_state_pool, 4096);
209 anv_state_stream_init(&cmd_buffer->dynamic_state_stream,
210 &device->dynamic_state_pool, 16384);
212 anv_cmd_state_init(cmd_buffer);
215 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
217 /* Init the pool_link so we can safefly call list_del when we destroy
220 list_inithead(&cmd_buffer->pool_link);
223 *pCommandBuffer = anv_cmd_buffer_to_handle(cmd_buffer);
228 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
233 VkResult anv_AllocateCommandBuffers(
235 const VkCommandBufferAllocateInfo* pAllocateInfo,
236 VkCommandBuffer* pCommandBuffers)
238 ANV_FROM_HANDLE(anv_device, device, _device);
239 ANV_FROM_HANDLE(anv_cmd_pool, pool, pAllocateInfo->commandPool);
241 VkResult result = VK_SUCCESS;
244 for (i = 0; i < pAllocateInfo->commandBufferCount; i++) {
245 result = anv_create_cmd_buffer(device, pool, pAllocateInfo->level,
246 &pCommandBuffers[i]);
247 if (result != VK_SUCCESS)
251 if (result != VK_SUCCESS) {
252 anv_FreeCommandBuffers(_device, pAllocateInfo->commandPool,
254 for (i = 0; i < pAllocateInfo->commandBufferCount; i++)
255 pCommandBuffers[i] = VK_NULL_HANDLE;
262 anv_cmd_buffer_destroy(struct anv_cmd_buffer *cmd_buffer)
264 list_del(&cmd_buffer->pool_link);
266 anv_cmd_buffer_fini_batch_bo_chain(cmd_buffer);
268 anv_state_stream_finish(&cmd_buffer->surface_state_stream);
269 anv_state_stream_finish(&cmd_buffer->dynamic_state_stream);
271 anv_cmd_state_finish(cmd_buffer);
273 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
276 void anv_FreeCommandBuffers(
278 VkCommandPool commandPool,
279 uint32_t commandBufferCount,
280 const VkCommandBuffer* pCommandBuffers)
282 for (uint32_t i = 0; i < commandBufferCount; i++) {
283 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, pCommandBuffers[i]);
288 anv_cmd_buffer_destroy(cmd_buffer);
293 anv_cmd_buffer_reset(struct anv_cmd_buffer *cmd_buffer)
295 cmd_buffer->usage_flags = 0;
296 anv_cmd_buffer_reset_batch_bo_chain(cmd_buffer);
297 anv_cmd_state_reset(cmd_buffer);
299 anv_state_stream_finish(&cmd_buffer->surface_state_stream);
300 anv_state_stream_init(&cmd_buffer->surface_state_stream,
301 &cmd_buffer->device->surface_state_pool, 4096);
303 anv_state_stream_finish(&cmd_buffer->dynamic_state_stream);
304 anv_state_stream_init(&cmd_buffer->dynamic_state_stream,
305 &cmd_buffer->device->dynamic_state_pool, 16384);
309 VkResult anv_ResetCommandBuffer(
310 VkCommandBuffer commandBuffer,
311 VkCommandBufferResetFlags flags)
313 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
314 return anv_cmd_buffer_reset(cmd_buffer);
317 #define anv_genX_call(devinfo, func, ...) \
318 switch ((devinfo)->gen) { \
320 if ((devinfo)->is_haswell) { \
321 gen75_##func(__VA_ARGS__); \
323 gen7_##func(__VA_ARGS__); \
327 gen8_##func(__VA_ARGS__); \
330 gen9_##func(__VA_ARGS__); \
333 gen10_##func(__VA_ARGS__); \
336 assert(!"Unknown hardware generation"); \
340 anv_cmd_buffer_emit_state_base_address(struct anv_cmd_buffer *cmd_buffer)
342 anv_genX_call(&cmd_buffer->device->info,
343 cmd_buffer_emit_state_base_address,
348 anv_cmd_buffer_mark_image_written(struct anv_cmd_buffer *cmd_buffer,
349 const struct anv_image *image,
350 VkImageAspectFlagBits aspect,
351 enum isl_aux_usage aux_usage,
354 uint32_t layer_count)
356 anv_genX_call(&cmd_buffer->device->info,
357 cmd_buffer_mark_image_written,
358 cmd_buffer, image, aspect, aux_usage,
359 level, base_layer, layer_count);
362 void anv_CmdBindPipeline(
363 VkCommandBuffer commandBuffer,
364 VkPipelineBindPoint pipelineBindPoint,
365 VkPipeline _pipeline)
367 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
368 ANV_FROM_HANDLE(anv_pipeline, pipeline, _pipeline);
370 switch (pipelineBindPoint) {
371 case VK_PIPELINE_BIND_POINT_COMPUTE:
372 cmd_buffer->state.compute.base.pipeline = pipeline;
373 cmd_buffer->state.compute.pipeline_dirty = true;
374 cmd_buffer->state.push_constants_dirty |= VK_SHADER_STAGE_COMPUTE_BIT;
375 cmd_buffer->state.descriptors_dirty |= VK_SHADER_STAGE_COMPUTE_BIT;
378 case VK_PIPELINE_BIND_POINT_GRAPHICS:
379 cmd_buffer->state.gfx.base.pipeline = pipeline;
380 cmd_buffer->state.gfx.vb_dirty |= pipeline->vb_used;
381 cmd_buffer->state.gfx.dirty |= ANV_CMD_DIRTY_PIPELINE;
382 cmd_buffer->state.push_constants_dirty |= pipeline->active_stages;
383 cmd_buffer->state.descriptors_dirty |= pipeline->active_stages;
385 /* Apply the dynamic state from the pipeline */
386 cmd_buffer->state.gfx.dirty |= pipeline->dynamic_state_mask;
387 anv_dynamic_state_copy(&cmd_buffer->state.gfx.dynamic,
388 &pipeline->dynamic_state,
389 pipeline->dynamic_state_mask);
393 assert(!"invalid bind point");
398 void anv_CmdSetViewport(
399 VkCommandBuffer commandBuffer,
400 uint32_t firstViewport,
401 uint32_t viewportCount,
402 const VkViewport* pViewports)
404 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
406 const uint32_t total_count = firstViewport + viewportCount;
407 if (cmd_buffer->state.gfx.dynamic.viewport.count < total_count)
408 cmd_buffer->state.gfx.dynamic.viewport.count = total_count;
410 memcpy(cmd_buffer->state.gfx.dynamic.viewport.viewports + firstViewport,
411 pViewports, viewportCount * sizeof(*pViewports));
413 cmd_buffer->state.gfx.dirty |= ANV_CMD_DIRTY_DYNAMIC_VIEWPORT;
416 void anv_CmdSetScissor(
417 VkCommandBuffer commandBuffer,
418 uint32_t firstScissor,
419 uint32_t scissorCount,
420 const VkRect2D* pScissors)
422 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
424 const uint32_t total_count = firstScissor + scissorCount;
425 if (cmd_buffer->state.gfx.dynamic.scissor.count < total_count)
426 cmd_buffer->state.gfx.dynamic.scissor.count = total_count;
428 memcpy(cmd_buffer->state.gfx.dynamic.scissor.scissors + firstScissor,
429 pScissors, scissorCount * sizeof(*pScissors));
431 cmd_buffer->state.gfx.dirty |= ANV_CMD_DIRTY_DYNAMIC_SCISSOR;
434 void anv_CmdSetLineWidth(
435 VkCommandBuffer commandBuffer,
438 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
440 cmd_buffer->state.gfx.dynamic.line_width = lineWidth;
441 cmd_buffer->state.gfx.dirty |= ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH;
444 void anv_CmdSetDepthBias(
445 VkCommandBuffer commandBuffer,
446 float depthBiasConstantFactor,
447 float depthBiasClamp,
448 float depthBiasSlopeFactor)
450 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
452 cmd_buffer->state.gfx.dynamic.depth_bias.bias = depthBiasConstantFactor;
453 cmd_buffer->state.gfx.dynamic.depth_bias.clamp = depthBiasClamp;
454 cmd_buffer->state.gfx.dynamic.depth_bias.slope = depthBiasSlopeFactor;
456 cmd_buffer->state.gfx.dirty |= ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
459 void anv_CmdSetBlendConstants(
460 VkCommandBuffer commandBuffer,
461 const float blendConstants[4])
463 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
465 memcpy(cmd_buffer->state.gfx.dynamic.blend_constants,
466 blendConstants, sizeof(float) * 4);
468 cmd_buffer->state.gfx.dirty |= ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS;
471 void anv_CmdSetDepthBounds(
472 VkCommandBuffer commandBuffer,
473 float minDepthBounds,
474 float maxDepthBounds)
476 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
478 cmd_buffer->state.gfx.dynamic.depth_bounds.min = minDepthBounds;
479 cmd_buffer->state.gfx.dynamic.depth_bounds.max = maxDepthBounds;
481 cmd_buffer->state.gfx.dirty |= ANV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS;
484 void anv_CmdSetStencilCompareMask(
485 VkCommandBuffer commandBuffer,
486 VkStencilFaceFlags faceMask,
487 uint32_t compareMask)
489 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
491 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
492 cmd_buffer->state.gfx.dynamic.stencil_compare_mask.front = compareMask;
493 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
494 cmd_buffer->state.gfx.dynamic.stencil_compare_mask.back = compareMask;
496 cmd_buffer->state.gfx.dirty |= ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK;
499 void anv_CmdSetStencilWriteMask(
500 VkCommandBuffer commandBuffer,
501 VkStencilFaceFlags faceMask,
504 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
506 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
507 cmd_buffer->state.gfx.dynamic.stencil_write_mask.front = writeMask;
508 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
509 cmd_buffer->state.gfx.dynamic.stencil_write_mask.back = writeMask;
511 cmd_buffer->state.gfx.dirty |= ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK;
514 void anv_CmdSetStencilReference(
515 VkCommandBuffer commandBuffer,
516 VkStencilFaceFlags faceMask,
519 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
521 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
522 cmd_buffer->state.gfx.dynamic.stencil_reference.front = reference;
523 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
524 cmd_buffer->state.gfx.dynamic.stencil_reference.back = reference;
526 cmd_buffer->state.gfx.dirty |= ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE;
530 anv_cmd_buffer_bind_descriptor_set(struct anv_cmd_buffer *cmd_buffer,
531 VkPipelineBindPoint bind_point,
532 struct anv_pipeline_layout *layout,
534 struct anv_descriptor_set *set,
535 uint32_t *dynamic_offset_count,
536 const uint32_t **dynamic_offsets)
538 struct anv_descriptor_set_layout *set_layout =
539 layout->set[set_index].layout;
541 struct anv_cmd_pipeline_state *pipe_state;
542 if (bind_point == VK_PIPELINE_BIND_POINT_COMPUTE) {
543 pipe_state = &cmd_buffer->state.compute.base;
545 assert(bind_point == VK_PIPELINE_BIND_POINT_GRAPHICS);
546 pipe_state = &cmd_buffer->state.gfx.base;
548 pipe_state->descriptors[set_index] = set;
550 if (dynamic_offsets) {
551 if (set_layout->dynamic_offset_count > 0) {
552 uint32_t dynamic_offset_start =
553 layout->set[set_index].dynamic_offset_start;
555 /* Assert that everything is in range */
556 assert(set_layout->dynamic_offset_count <= *dynamic_offset_count);
557 assert(dynamic_offset_start + set_layout->dynamic_offset_count <=
558 ARRAY_SIZE(pipe_state->dynamic_offsets));
560 typed_memcpy(&pipe_state->dynamic_offsets[dynamic_offset_start],
561 *dynamic_offsets, set_layout->dynamic_offset_count);
563 *dynamic_offsets += set_layout->dynamic_offset_count;
564 *dynamic_offset_count -= set_layout->dynamic_offset_count;
568 if (bind_point == VK_PIPELINE_BIND_POINT_COMPUTE) {
569 cmd_buffer->state.descriptors_dirty |= VK_SHADER_STAGE_COMPUTE_BIT;
571 assert(bind_point == VK_PIPELINE_BIND_POINT_GRAPHICS);
572 cmd_buffer->state.descriptors_dirty |=
573 set_layout->shader_stages & VK_SHADER_STAGE_ALL_GRAPHICS;
576 /* Pipeline layout objects are required to live at least while any command
577 * buffers that use them are in recording state. We need to grab a reference
578 * to the pipeline layout being bound here so we can compute correct dynamic
579 * offsets for VK_DESCRIPTOR_TYPE_*_DYNAMIC in dynamic_offset_for_binding()
580 * when we record draw commands that come after this.
582 pipe_state->layout = layout;
585 void anv_CmdBindDescriptorSets(
586 VkCommandBuffer commandBuffer,
587 VkPipelineBindPoint pipelineBindPoint,
588 VkPipelineLayout _layout,
590 uint32_t descriptorSetCount,
591 const VkDescriptorSet* pDescriptorSets,
592 uint32_t dynamicOffsetCount,
593 const uint32_t* pDynamicOffsets)
595 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
596 ANV_FROM_HANDLE(anv_pipeline_layout, layout, _layout);
598 assert(firstSet + descriptorSetCount < MAX_SETS);
600 for (uint32_t i = 0; i < descriptorSetCount; i++) {
601 ANV_FROM_HANDLE(anv_descriptor_set, set, pDescriptorSets[i]);
602 anv_cmd_buffer_bind_descriptor_set(cmd_buffer, pipelineBindPoint,
603 layout, firstSet + i, set,
609 void anv_CmdBindVertexBuffers(
610 VkCommandBuffer commandBuffer,
611 uint32_t firstBinding,
612 uint32_t bindingCount,
613 const VkBuffer* pBuffers,
614 const VkDeviceSize* pOffsets)
616 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
617 struct anv_vertex_binding *vb = cmd_buffer->state.vertex_bindings;
619 /* We have to defer setting up vertex buffer since we need the buffer
620 * stride from the pipeline. */
622 assert(firstBinding + bindingCount <= MAX_VBS);
623 for (uint32_t i = 0; i < bindingCount; i++) {
624 vb[firstBinding + i].buffer = anv_buffer_from_handle(pBuffers[i]);
625 vb[firstBinding + i].offset = pOffsets[i];
626 cmd_buffer->state.gfx.vb_dirty |= 1 << (firstBinding + i);
631 anv_isl_format_for_descriptor_type(VkDescriptorType type)
634 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER:
635 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC:
636 return ISL_FORMAT_R32G32B32A32_FLOAT;
638 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER:
639 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC:
640 return ISL_FORMAT_RAW;
643 unreachable("Invalid descriptor type");
648 anv_cmd_buffer_emit_dynamic(struct anv_cmd_buffer *cmd_buffer,
649 const void *data, uint32_t size, uint32_t alignment)
651 struct anv_state state;
653 state = anv_cmd_buffer_alloc_dynamic_state(cmd_buffer, size, alignment);
654 memcpy(state.map, data, size);
656 anv_state_flush(cmd_buffer->device, state);
658 VG(VALGRIND_CHECK_MEM_IS_DEFINED(state.map, size));
664 anv_cmd_buffer_merge_dynamic(struct anv_cmd_buffer *cmd_buffer,
665 uint32_t *a, uint32_t *b,
666 uint32_t dwords, uint32_t alignment)
668 struct anv_state state;
671 state = anv_cmd_buffer_alloc_dynamic_state(cmd_buffer,
672 dwords * 4, alignment);
674 for (uint32_t i = 0; i < dwords; i++)
677 anv_state_flush(cmd_buffer->device, state);
679 VG(VALGRIND_CHECK_MEM_IS_DEFINED(p, dwords * 4));
685 anv_push_constant_value(struct anv_push_constants *data, uint32_t param)
687 if (BRW_PARAM_IS_BUILTIN(param)) {
689 case BRW_PARAM_BUILTIN_ZERO:
691 case BRW_PARAM_BUILTIN_BASE_WORK_GROUP_ID_X:
692 return data->base_work_group_id[0];
693 case BRW_PARAM_BUILTIN_BASE_WORK_GROUP_ID_Y:
694 return data->base_work_group_id[1];
695 case BRW_PARAM_BUILTIN_BASE_WORK_GROUP_ID_Z:
696 return data->base_work_group_id[2];
698 unreachable("Invalid param builtin");
701 uint32_t offset = ANV_PARAM_PUSH_OFFSET(param);
702 assert(offset % sizeof(uint32_t) == 0);
703 if (offset < data->size)
704 return *(uint32_t *)((uint8_t *)data + offset);
711 anv_cmd_buffer_push_constants(struct anv_cmd_buffer *cmd_buffer,
712 gl_shader_stage stage)
714 struct anv_pipeline *pipeline = cmd_buffer->state.gfx.base.pipeline;
716 /* If we don't have this stage, bail. */
717 if (!anv_pipeline_has_stage(pipeline, stage))
718 return (struct anv_state) { .offset = 0 };
720 struct anv_push_constants *data =
721 cmd_buffer->state.push_constants[stage];
722 const struct brw_stage_prog_data *prog_data =
723 pipeline->shaders[stage]->prog_data;
725 /* If we don't actually have any push constants, bail. */
726 if (data == NULL || prog_data == NULL || prog_data->nr_params == 0)
727 return (struct anv_state) { .offset = 0 };
729 struct anv_state state =
730 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer,
731 prog_data->nr_params * sizeof(float),
732 32 /* bottom 5 bits MBZ */);
734 /* Walk through the param array and fill the buffer with data */
735 uint32_t *u32_map = state.map;
736 for (unsigned i = 0; i < prog_data->nr_params; i++)
737 u32_map[i] = anv_push_constant_value(data, prog_data->param[i]);
739 anv_state_flush(cmd_buffer->device, state);
745 anv_cmd_buffer_cs_push_constants(struct anv_cmd_buffer *cmd_buffer)
747 struct anv_push_constants *data =
748 cmd_buffer->state.push_constants[MESA_SHADER_COMPUTE];
749 struct anv_pipeline *pipeline = cmd_buffer->state.compute.base.pipeline;
750 const struct brw_cs_prog_data *cs_prog_data = get_cs_prog_data(pipeline);
751 const struct brw_stage_prog_data *prog_data = &cs_prog_data->base;
753 /* If we don't actually have any push constants, bail. */
754 if (cs_prog_data->push.total.size == 0)
755 return (struct anv_state) { .offset = 0 };
757 const unsigned push_constant_alignment =
758 cmd_buffer->device->info.gen < 8 ? 32 : 64;
759 const unsigned aligned_total_push_constants_size =
760 ALIGN(cs_prog_data->push.total.size, push_constant_alignment);
761 struct anv_state state =
762 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer,
763 aligned_total_push_constants_size,
764 push_constant_alignment);
766 /* Walk through the param array and fill the buffer with data */
767 uint32_t *u32_map = state.map;
769 if (cs_prog_data->push.cross_thread.size > 0) {
771 i < cs_prog_data->push.cross_thread.dwords;
773 assert(prog_data->param[i] != BRW_PARAM_BUILTIN_SUBGROUP_ID);
774 u32_map[i] = anv_push_constant_value(data, prog_data->param[i]);
778 if (cs_prog_data->push.per_thread.size > 0) {
779 for (unsigned t = 0; t < cs_prog_data->threads; t++) {
781 8 * (cs_prog_data->push.per_thread.regs * t +
782 cs_prog_data->push.cross_thread.regs);
783 unsigned src = cs_prog_data->push.cross_thread.dwords;
784 for ( ; src < prog_data->nr_params; src++, dst++) {
785 if (prog_data->param[src] == BRW_PARAM_BUILTIN_SUBGROUP_ID) {
789 anv_push_constant_value(data, prog_data->param[src]);
795 anv_state_flush(cmd_buffer->device, state);
800 void anv_CmdPushConstants(
801 VkCommandBuffer commandBuffer,
802 VkPipelineLayout layout,
803 VkShaderStageFlags stageFlags,
808 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
810 anv_foreach_stage(stage, stageFlags) {
812 anv_cmd_buffer_ensure_push_constant_field(cmd_buffer,
814 if (result != VK_SUCCESS)
817 memcpy(cmd_buffer->state.push_constants[stage]->client_data + offset,
821 cmd_buffer->state.push_constants_dirty |= stageFlags;
824 VkResult anv_CreateCommandPool(
826 const VkCommandPoolCreateInfo* pCreateInfo,
827 const VkAllocationCallbacks* pAllocator,
828 VkCommandPool* pCmdPool)
830 ANV_FROM_HANDLE(anv_device, device, _device);
831 struct anv_cmd_pool *pool;
833 pool = vk_alloc2(&device->alloc, pAllocator, sizeof(*pool), 8,
834 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
836 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
839 pool->alloc = *pAllocator;
841 pool->alloc = device->alloc;
843 list_inithead(&pool->cmd_buffers);
845 *pCmdPool = anv_cmd_pool_to_handle(pool);
850 void anv_DestroyCommandPool(
852 VkCommandPool commandPool,
853 const VkAllocationCallbacks* pAllocator)
855 ANV_FROM_HANDLE(anv_device, device, _device);
856 ANV_FROM_HANDLE(anv_cmd_pool, pool, commandPool);
861 list_for_each_entry_safe(struct anv_cmd_buffer, cmd_buffer,
862 &pool->cmd_buffers, pool_link) {
863 anv_cmd_buffer_destroy(cmd_buffer);
866 vk_free2(&device->alloc, pAllocator, pool);
869 VkResult anv_ResetCommandPool(
871 VkCommandPool commandPool,
872 VkCommandPoolResetFlags flags)
874 ANV_FROM_HANDLE(anv_cmd_pool, pool, commandPool);
876 list_for_each_entry(struct anv_cmd_buffer, cmd_buffer,
877 &pool->cmd_buffers, pool_link) {
878 anv_cmd_buffer_reset(cmd_buffer);
884 void anv_TrimCommandPool(
886 VkCommandPool commandPool,
887 VkCommandPoolTrimFlags flags)
889 /* Nothing for us to do here. Our pools stay pretty tidy. */
893 * Return NULL if the current subpass has no depthstencil attachment.
895 const struct anv_image_view *
896 anv_cmd_buffer_get_depth_stencil_view(const struct anv_cmd_buffer *cmd_buffer)
898 const struct anv_subpass *subpass = cmd_buffer->state.subpass;
899 const struct anv_framebuffer *fb = cmd_buffer->state.framebuffer;
901 if (subpass->depth_stencil_attachment.attachment == VK_ATTACHMENT_UNUSED)
904 const struct anv_image_view *iview =
905 fb->attachments[subpass->depth_stencil_attachment.attachment];
907 assert(iview->aspect_mask & (VK_IMAGE_ASPECT_DEPTH_BIT |
908 VK_IMAGE_ASPECT_STENCIL_BIT));
913 static struct anv_push_descriptor_set *
914 anv_cmd_buffer_get_push_descriptor_set(struct anv_cmd_buffer *cmd_buffer,
915 VkPipelineBindPoint bind_point,
918 struct anv_cmd_pipeline_state *pipe_state;
919 if (bind_point == VK_PIPELINE_BIND_POINT_COMPUTE) {
920 pipe_state = &cmd_buffer->state.compute.base;
922 assert(bind_point == VK_PIPELINE_BIND_POINT_GRAPHICS);
923 pipe_state = &cmd_buffer->state.gfx.base;
926 struct anv_push_descriptor_set **push_set =
927 &pipe_state->push_descriptors[set];
929 if (*push_set == NULL) {
930 *push_set = vk_alloc(&cmd_buffer->pool->alloc,
931 sizeof(struct anv_push_descriptor_set), 8,
932 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
933 if (*push_set == NULL) {
934 anv_batch_set_error(&cmd_buffer->batch, VK_ERROR_OUT_OF_HOST_MEMORY);
942 void anv_CmdPushDescriptorSetKHR(
943 VkCommandBuffer commandBuffer,
944 VkPipelineBindPoint pipelineBindPoint,
945 VkPipelineLayout _layout,
947 uint32_t descriptorWriteCount,
948 const VkWriteDescriptorSet* pDescriptorWrites)
950 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
951 ANV_FROM_HANDLE(anv_pipeline_layout, layout, _layout);
953 assert(_set < MAX_SETS);
955 struct anv_descriptor_set_layout *set_layout = layout->set[_set].layout;
957 struct anv_push_descriptor_set *push_set =
958 anv_cmd_buffer_get_push_descriptor_set(cmd_buffer,
959 pipelineBindPoint, _set);
963 struct anv_descriptor_set *set = &push_set->set;
965 set->layout = set_layout;
966 set->size = anv_descriptor_set_layout_size(set_layout);
967 set->buffer_count = set_layout->buffer_count;
968 set->buffer_views = push_set->buffer_views;
970 /* Go through the user supplied descriptors. */
971 for (uint32_t i = 0; i < descriptorWriteCount; i++) {
972 const VkWriteDescriptorSet *write = &pDescriptorWrites[i];
974 switch (write->descriptorType) {
975 case VK_DESCRIPTOR_TYPE_SAMPLER:
976 case VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER:
977 case VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE:
978 case VK_DESCRIPTOR_TYPE_STORAGE_IMAGE:
979 case VK_DESCRIPTOR_TYPE_INPUT_ATTACHMENT:
980 for (uint32_t j = 0; j < write->descriptorCount; j++) {
981 anv_descriptor_set_write_image_view(set, &cmd_buffer->device->info,
982 write->pImageInfo + j,
983 write->descriptorType,
985 write->dstArrayElement + j);
989 case VK_DESCRIPTOR_TYPE_UNIFORM_TEXEL_BUFFER:
990 case VK_DESCRIPTOR_TYPE_STORAGE_TEXEL_BUFFER:
991 for (uint32_t j = 0; j < write->descriptorCount; j++) {
992 ANV_FROM_HANDLE(anv_buffer_view, bview,
993 write->pTexelBufferView[j]);
995 anv_descriptor_set_write_buffer_view(set,
996 write->descriptorType,
999 write->dstArrayElement + j);
1003 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER:
1004 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER:
1005 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC:
1006 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC:
1007 for (uint32_t j = 0; j < write->descriptorCount; j++) {
1008 assert(write->pBufferInfo[j].buffer);
1009 ANV_FROM_HANDLE(anv_buffer, buffer, write->pBufferInfo[j].buffer);
1012 anv_descriptor_set_write_buffer(set,
1014 &cmd_buffer->surface_state_stream,
1015 write->descriptorType,
1018 write->dstArrayElement + j,
1019 write->pBufferInfo[j].offset,
1020 write->pBufferInfo[j].range);
1029 anv_cmd_buffer_bind_descriptor_set(cmd_buffer, pipelineBindPoint,
1030 layout, _set, set, NULL, NULL);
1033 void anv_CmdPushDescriptorSetWithTemplateKHR(
1034 VkCommandBuffer commandBuffer,
1035 VkDescriptorUpdateTemplate descriptorUpdateTemplate,
1036 VkPipelineLayout _layout,
1040 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
1041 ANV_FROM_HANDLE(anv_descriptor_update_template, template,
1042 descriptorUpdateTemplate);
1043 ANV_FROM_HANDLE(anv_pipeline_layout, layout, _layout);
1045 assert(_set < MAX_PUSH_DESCRIPTORS);
1047 struct anv_descriptor_set_layout *set_layout = layout->set[_set].layout;
1049 struct anv_push_descriptor_set *push_set =
1050 anv_cmd_buffer_get_push_descriptor_set(cmd_buffer,
1051 template->bind_point, _set);
1055 struct anv_descriptor_set *set = &push_set->set;
1057 set->layout = set_layout;
1058 set->size = anv_descriptor_set_layout_size(set_layout);
1059 set->buffer_count = set_layout->buffer_count;
1060 set->buffer_views = push_set->buffer_views;
1062 anv_descriptor_set_write_template(set,
1064 &cmd_buffer->surface_state_stream,
1068 anv_cmd_buffer_bind_descriptor_set(cmd_buffer, template->bind_point,
1069 layout, _set, set, NULL, NULL);
1072 void anv_CmdSetDeviceMask(
1073 VkCommandBuffer commandBuffer,
1074 uint32_t deviceMask)