2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
30 #include "anv_private.h"
32 #include "vk_format_info.h"
34 /** \file anv_cmd_buffer.c
36 * This file contains all of the stuff for emitting commands into a command
37 * buffer. This includes implementations of most of the vkCmd*
38 * entrypoints. This file is concerned entirely with state emission and
39 * not with the command buffer data structure itself. As far as this file
40 * is concerned, most of anv_cmd_buffer is magic.
43 /* TODO: These are taken from GLES. We should check the Vulkan spec */
44 const struct anv_dynamic_state default_dynamic_state = {
57 .blend_constants = { 0.0f, 0.0f, 0.0f, 0.0f },
62 .stencil_compare_mask = {
66 .stencil_write_mask = {
70 .stencil_reference = {
77 anv_dynamic_state_copy(struct anv_dynamic_state *dest,
78 const struct anv_dynamic_state *src,
81 if (copy_mask & (1 << VK_DYNAMIC_STATE_VIEWPORT)) {
82 dest->viewport.count = src->viewport.count;
83 typed_memcpy(dest->viewport.viewports, src->viewport.viewports,
87 if (copy_mask & (1 << VK_DYNAMIC_STATE_SCISSOR)) {
88 dest->scissor.count = src->scissor.count;
89 typed_memcpy(dest->scissor.scissors, src->scissor.scissors,
93 if (copy_mask & (1 << VK_DYNAMIC_STATE_LINE_WIDTH))
94 dest->line_width = src->line_width;
96 if (copy_mask & (1 << VK_DYNAMIC_STATE_DEPTH_BIAS))
97 dest->depth_bias = src->depth_bias;
99 if (copy_mask & (1 << VK_DYNAMIC_STATE_BLEND_CONSTANTS))
100 typed_memcpy(dest->blend_constants, src->blend_constants, 4);
102 if (copy_mask & (1 << VK_DYNAMIC_STATE_DEPTH_BOUNDS))
103 dest->depth_bounds = src->depth_bounds;
105 if (copy_mask & (1 << VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK))
106 dest->stencil_compare_mask = src->stencil_compare_mask;
108 if (copy_mask & (1 << VK_DYNAMIC_STATE_STENCIL_WRITE_MASK))
109 dest->stencil_write_mask = src->stencil_write_mask;
111 if (copy_mask & (1 << VK_DYNAMIC_STATE_STENCIL_REFERENCE))
112 dest->stencil_reference = src->stencil_reference;
116 anv_cmd_state_init(struct anv_cmd_buffer *cmd_buffer)
118 struct anv_cmd_state *state = &cmd_buffer->state;
120 memset(state, 0, sizeof(*state));
122 state->restart_index = UINT32_MAX;
123 state->gfx.dynamic = default_dynamic_state;
127 anv_cmd_pipeline_state_finish(struct anv_cmd_buffer *cmd_buffer,
128 struct anv_cmd_pipeline_state *pipe_state)
130 for (uint32_t i = 0; i < ARRAY_SIZE(pipe_state->push_descriptors); i++)
131 vk_free(&cmd_buffer->pool->alloc, pipe_state->push_descriptors[i]);
135 anv_cmd_state_finish(struct anv_cmd_buffer *cmd_buffer)
137 struct anv_cmd_state *state = &cmd_buffer->state;
139 anv_cmd_pipeline_state_finish(cmd_buffer, &state->gfx.base);
140 anv_cmd_pipeline_state_finish(cmd_buffer, &state->compute.base);
142 for (uint32_t i = 0; i < MESA_SHADER_STAGES; i++)
143 vk_free(&cmd_buffer->pool->alloc, state->push_constants[i]);
145 vk_free(&cmd_buffer->pool->alloc, state->attachments);
149 anv_cmd_state_reset(struct anv_cmd_buffer *cmd_buffer)
151 anv_cmd_state_finish(cmd_buffer);
152 anv_cmd_state_init(cmd_buffer);
156 anv_cmd_buffer_ensure_push_constants_size(struct anv_cmd_buffer *cmd_buffer,
157 gl_shader_stage stage, uint32_t size)
159 struct anv_push_constants **ptr = &cmd_buffer->state.push_constants[stage];
162 *ptr = vk_alloc(&cmd_buffer->pool->alloc, size, 8,
163 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
165 anv_batch_set_error(&cmd_buffer->batch, VK_ERROR_OUT_OF_HOST_MEMORY);
166 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
168 } else if ((*ptr)->size < size) {
169 *ptr = vk_realloc(&cmd_buffer->pool->alloc, *ptr, size, 8,
170 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
172 anv_batch_set_error(&cmd_buffer->batch, VK_ERROR_OUT_OF_HOST_MEMORY);
173 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
181 static VkResult anv_create_cmd_buffer(
182 struct anv_device * device,
183 struct anv_cmd_pool * pool,
184 VkCommandBufferLevel level,
185 VkCommandBuffer* pCommandBuffer)
187 struct anv_cmd_buffer *cmd_buffer;
190 cmd_buffer = vk_alloc(&pool->alloc, sizeof(*cmd_buffer), 8,
191 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
192 if (cmd_buffer == NULL)
193 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
195 cmd_buffer->batch.status = VK_SUCCESS;
197 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
198 cmd_buffer->device = device;
199 cmd_buffer->pool = pool;
200 cmd_buffer->level = level;
202 result = anv_cmd_buffer_init_batch_bo_chain(cmd_buffer);
203 if (result != VK_SUCCESS)
206 anv_state_stream_init(&cmd_buffer->surface_state_stream,
207 &device->surface_state_pool, 4096);
208 anv_state_stream_init(&cmd_buffer->dynamic_state_stream,
209 &device->dynamic_state_pool, 16384);
211 anv_cmd_state_init(cmd_buffer);
214 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
216 /* Init the pool_link so we can safefly call list_del when we destroy
219 list_inithead(&cmd_buffer->pool_link);
222 *pCommandBuffer = anv_cmd_buffer_to_handle(cmd_buffer);
227 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
232 VkResult anv_AllocateCommandBuffers(
234 const VkCommandBufferAllocateInfo* pAllocateInfo,
235 VkCommandBuffer* pCommandBuffers)
237 ANV_FROM_HANDLE(anv_device, device, _device);
238 ANV_FROM_HANDLE(anv_cmd_pool, pool, pAllocateInfo->commandPool);
240 VkResult result = VK_SUCCESS;
243 for (i = 0; i < pAllocateInfo->commandBufferCount; i++) {
244 result = anv_create_cmd_buffer(device, pool, pAllocateInfo->level,
245 &pCommandBuffers[i]);
246 if (result != VK_SUCCESS)
250 if (result != VK_SUCCESS) {
251 anv_FreeCommandBuffers(_device, pAllocateInfo->commandPool,
253 for (i = 0; i < pAllocateInfo->commandBufferCount; i++)
254 pCommandBuffers[i] = VK_NULL_HANDLE;
261 anv_cmd_buffer_destroy(struct anv_cmd_buffer *cmd_buffer)
263 list_del(&cmd_buffer->pool_link);
265 anv_cmd_buffer_fini_batch_bo_chain(cmd_buffer);
267 anv_state_stream_finish(&cmd_buffer->surface_state_stream);
268 anv_state_stream_finish(&cmd_buffer->dynamic_state_stream);
270 anv_cmd_state_finish(cmd_buffer);
272 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
275 void anv_FreeCommandBuffers(
277 VkCommandPool commandPool,
278 uint32_t commandBufferCount,
279 const VkCommandBuffer* pCommandBuffers)
281 for (uint32_t i = 0; i < commandBufferCount; i++) {
282 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, pCommandBuffers[i]);
287 anv_cmd_buffer_destroy(cmd_buffer);
292 anv_cmd_buffer_reset(struct anv_cmd_buffer *cmd_buffer)
294 cmd_buffer->usage_flags = 0;
295 cmd_buffer->state.current_pipeline = UINT32_MAX;
296 anv_cmd_buffer_reset_batch_bo_chain(cmd_buffer);
297 anv_cmd_state_reset(cmd_buffer);
299 anv_state_stream_finish(&cmd_buffer->surface_state_stream);
300 anv_state_stream_init(&cmd_buffer->surface_state_stream,
301 &cmd_buffer->device->surface_state_pool, 4096);
303 anv_state_stream_finish(&cmd_buffer->dynamic_state_stream);
304 anv_state_stream_init(&cmd_buffer->dynamic_state_stream,
305 &cmd_buffer->device->dynamic_state_pool, 16384);
309 VkResult anv_ResetCommandBuffer(
310 VkCommandBuffer commandBuffer,
311 VkCommandBufferResetFlags flags)
313 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
314 return anv_cmd_buffer_reset(cmd_buffer);
318 anv_cmd_buffer_emit_state_base_address(struct anv_cmd_buffer *cmd_buffer)
320 switch (cmd_buffer->device->info.gen) {
322 if (cmd_buffer->device->info.is_haswell)
323 return gen75_cmd_buffer_emit_state_base_address(cmd_buffer);
325 return gen7_cmd_buffer_emit_state_base_address(cmd_buffer);
327 return gen8_cmd_buffer_emit_state_base_address(cmd_buffer);
329 return gen9_cmd_buffer_emit_state_base_address(cmd_buffer);
331 return gen10_cmd_buffer_emit_state_base_address(cmd_buffer);
333 unreachable("unsupported gen\n");
337 void anv_CmdBindPipeline(
338 VkCommandBuffer commandBuffer,
339 VkPipelineBindPoint pipelineBindPoint,
340 VkPipeline _pipeline)
342 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
343 ANV_FROM_HANDLE(anv_pipeline, pipeline, _pipeline);
345 switch (pipelineBindPoint) {
346 case VK_PIPELINE_BIND_POINT_COMPUTE:
347 cmd_buffer->state.compute.base.pipeline = pipeline;
348 cmd_buffer->state.compute.pipeline_dirty = true;
349 cmd_buffer->state.push_constants_dirty |= VK_SHADER_STAGE_COMPUTE_BIT;
350 cmd_buffer->state.descriptors_dirty |= VK_SHADER_STAGE_COMPUTE_BIT;
353 case VK_PIPELINE_BIND_POINT_GRAPHICS:
354 cmd_buffer->state.gfx.base.pipeline = pipeline;
355 cmd_buffer->state.gfx.vb_dirty |= pipeline->vb_used;
356 cmd_buffer->state.gfx.dirty |= ANV_CMD_DIRTY_PIPELINE;
357 cmd_buffer->state.push_constants_dirty |= pipeline->active_stages;
358 cmd_buffer->state.descriptors_dirty |= pipeline->active_stages;
360 /* Apply the dynamic state from the pipeline */
361 cmd_buffer->state.gfx.dirty |= pipeline->dynamic_state_mask;
362 anv_dynamic_state_copy(&cmd_buffer->state.gfx.dynamic,
363 &pipeline->dynamic_state,
364 pipeline->dynamic_state_mask);
368 assert(!"invalid bind point");
373 void anv_CmdSetViewport(
374 VkCommandBuffer commandBuffer,
375 uint32_t firstViewport,
376 uint32_t viewportCount,
377 const VkViewport* pViewports)
379 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
381 const uint32_t total_count = firstViewport + viewportCount;
382 if (cmd_buffer->state.gfx.dynamic.viewport.count < total_count)
383 cmd_buffer->state.gfx.dynamic.viewport.count = total_count;
385 memcpy(cmd_buffer->state.gfx.dynamic.viewport.viewports + firstViewport,
386 pViewports, viewportCount * sizeof(*pViewports));
388 cmd_buffer->state.gfx.dirty |= ANV_CMD_DIRTY_DYNAMIC_VIEWPORT;
391 void anv_CmdSetScissor(
392 VkCommandBuffer commandBuffer,
393 uint32_t firstScissor,
394 uint32_t scissorCount,
395 const VkRect2D* pScissors)
397 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
399 const uint32_t total_count = firstScissor + scissorCount;
400 if (cmd_buffer->state.gfx.dynamic.scissor.count < total_count)
401 cmd_buffer->state.gfx.dynamic.scissor.count = total_count;
403 memcpy(cmd_buffer->state.gfx.dynamic.scissor.scissors + firstScissor,
404 pScissors, scissorCount * sizeof(*pScissors));
406 cmd_buffer->state.gfx.dirty |= ANV_CMD_DIRTY_DYNAMIC_SCISSOR;
409 void anv_CmdSetLineWidth(
410 VkCommandBuffer commandBuffer,
413 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
415 cmd_buffer->state.gfx.dynamic.line_width = lineWidth;
416 cmd_buffer->state.gfx.dirty |= ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH;
419 void anv_CmdSetDepthBias(
420 VkCommandBuffer commandBuffer,
421 float depthBiasConstantFactor,
422 float depthBiasClamp,
423 float depthBiasSlopeFactor)
425 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
427 cmd_buffer->state.gfx.dynamic.depth_bias.bias = depthBiasConstantFactor;
428 cmd_buffer->state.gfx.dynamic.depth_bias.clamp = depthBiasClamp;
429 cmd_buffer->state.gfx.dynamic.depth_bias.slope = depthBiasSlopeFactor;
431 cmd_buffer->state.gfx.dirty |= ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
434 void anv_CmdSetBlendConstants(
435 VkCommandBuffer commandBuffer,
436 const float blendConstants[4])
438 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
440 memcpy(cmd_buffer->state.gfx.dynamic.blend_constants,
441 blendConstants, sizeof(float) * 4);
443 cmd_buffer->state.gfx.dirty |= ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS;
446 void anv_CmdSetDepthBounds(
447 VkCommandBuffer commandBuffer,
448 float minDepthBounds,
449 float maxDepthBounds)
451 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
453 cmd_buffer->state.gfx.dynamic.depth_bounds.min = minDepthBounds;
454 cmd_buffer->state.gfx.dynamic.depth_bounds.max = maxDepthBounds;
456 cmd_buffer->state.gfx.dirty |= ANV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS;
459 void anv_CmdSetStencilCompareMask(
460 VkCommandBuffer commandBuffer,
461 VkStencilFaceFlags faceMask,
462 uint32_t compareMask)
464 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
466 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
467 cmd_buffer->state.gfx.dynamic.stencil_compare_mask.front = compareMask;
468 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
469 cmd_buffer->state.gfx.dynamic.stencil_compare_mask.back = compareMask;
471 cmd_buffer->state.gfx.dirty |= ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK;
474 void anv_CmdSetStencilWriteMask(
475 VkCommandBuffer commandBuffer,
476 VkStencilFaceFlags faceMask,
479 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
481 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
482 cmd_buffer->state.gfx.dynamic.stencil_write_mask.front = writeMask;
483 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
484 cmd_buffer->state.gfx.dynamic.stencil_write_mask.back = writeMask;
486 cmd_buffer->state.gfx.dirty |= ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK;
489 void anv_CmdSetStencilReference(
490 VkCommandBuffer commandBuffer,
491 VkStencilFaceFlags faceMask,
494 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
496 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
497 cmd_buffer->state.gfx.dynamic.stencil_reference.front = reference;
498 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
499 cmd_buffer->state.gfx.dynamic.stencil_reference.back = reference;
501 cmd_buffer->state.gfx.dirty |= ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE;
505 anv_cmd_buffer_bind_descriptor_set(struct anv_cmd_buffer *cmd_buffer,
506 VkPipelineBindPoint bind_point,
507 struct anv_pipeline_layout *layout,
509 struct anv_descriptor_set *set,
510 uint32_t *dynamic_offset_count,
511 const uint32_t **dynamic_offsets)
513 struct anv_descriptor_set_layout *set_layout =
514 layout->set[set_index].layout;
516 struct anv_cmd_pipeline_state *pipe_state;
517 if (bind_point == VK_PIPELINE_BIND_POINT_COMPUTE) {
518 pipe_state = &cmd_buffer->state.compute.base;
520 assert(bind_point == VK_PIPELINE_BIND_POINT_GRAPHICS);
521 pipe_state = &cmd_buffer->state.gfx.base;
523 pipe_state->descriptors[set_index] = set;
525 if (dynamic_offsets) {
526 if (set_layout->dynamic_offset_count > 0) {
527 uint32_t dynamic_offset_start =
528 layout->set[set_index].dynamic_offset_start;
530 /* Assert that everything is in range */
531 assert(set_layout->dynamic_offset_count <= *dynamic_offset_count);
532 assert(dynamic_offset_start + set_layout->dynamic_offset_count <=
533 ARRAY_SIZE(pipe_state->dynamic_offsets));
535 typed_memcpy(&pipe_state->dynamic_offsets[dynamic_offset_start],
536 *dynamic_offsets, set_layout->dynamic_offset_count);
538 *dynamic_offsets += set_layout->dynamic_offset_count;
539 *dynamic_offset_count -= set_layout->dynamic_offset_count;
543 if (bind_point == VK_PIPELINE_BIND_POINT_COMPUTE) {
544 cmd_buffer->state.descriptors_dirty |= VK_SHADER_STAGE_COMPUTE_BIT;
546 assert(bind_point == VK_PIPELINE_BIND_POINT_GRAPHICS);
547 cmd_buffer->state.descriptors_dirty |=
548 set_layout->shader_stages & VK_SHADER_STAGE_ALL_GRAPHICS;
552 void anv_CmdBindDescriptorSets(
553 VkCommandBuffer commandBuffer,
554 VkPipelineBindPoint pipelineBindPoint,
555 VkPipelineLayout _layout,
557 uint32_t descriptorSetCount,
558 const VkDescriptorSet* pDescriptorSets,
559 uint32_t dynamicOffsetCount,
560 const uint32_t* pDynamicOffsets)
562 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
563 ANV_FROM_HANDLE(anv_pipeline_layout, layout, _layout);
565 assert(firstSet + descriptorSetCount < MAX_SETS);
567 for (uint32_t i = 0; i < descriptorSetCount; i++) {
568 ANV_FROM_HANDLE(anv_descriptor_set, set, pDescriptorSets[i]);
569 anv_cmd_buffer_bind_descriptor_set(cmd_buffer, pipelineBindPoint,
570 layout, firstSet + i, set,
576 void anv_CmdBindVertexBuffers(
577 VkCommandBuffer commandBuffer,
578 uint32_t firstBinding,
579 uint32_t bindingCount,
580 const VkBuffer* pBuffers,
581 const VkDeviceSize* pOffsets)
583 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
584 struct anv_vertex_binding *vb = cmd_buffer->state.vertex_bindings;
586 /* We have to defer setting up vertex buffer since we need the buffer
587 * stride from the pipeline. */
589 assert(firstBinding + bindingCount <= MAX_VBS);
590 for (uint32_t i = 0; i < bindingCount; i++) {
591 vb[firstBinding + i].buffer = anv_buffer_from_handle(pBuffers[i]);
592 vb[firstBinding + i].offset = pOffsets[i];
593 cmd_buffer->state.gfx.vb_dirty |= 1 << (firstBinding + i);
598 anv_isl_format_for_descriptor_type(VkDescriptorType type)
601 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER:
602 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC:
603 return ISL_FORMAT_R32G32B32A32_FLOAT;
605 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER:
606 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC:
607 return ISL_FORMAT_RAW;
610 unreachable("Invalid descriptor type");
615 anv_cmd_buffer_emit_dynamic(struct anv_cmd_buffer *cmd_buffer,
616 const void *data, uint32_t size, uint32_t alignment)
618 struct anv_state state;
620 state = anv_cmd_buffer_alloc_dynamic_state(cmd_buffer, size, alignment);
621 memcpy(state.map, data, size);
623 anv_state_flush(cmd_buffer->device, state);
625 VG(VALGRIND_CHECK_MEM_IS_DEFINED(state.map, size));
631 anv_cmd_buffer_merge_dynamic(struct anv_cmd_buffer *cmd_buffer,
632 uint32_t *a, uint32_t *b,
633 uint32_t dwords, uint32_t alignment)
635 struct anv_state state;
638 state = anv_cmd_buffer_alloc_dynamic_state(cmd_buffer,
639 dwords * 4, alignment);
641 for (uint32_t i = 0; i < dwords; i++)
644 anv_state_flush(cmd_buffer->device, state);
646 VG(VALGRIND_CHECK_MEM_IS_DEFINED(p, dwords * 4));
652 anv_push_constant_value(struct anv_push_constants *data, uint32_t param)
654 if (BRW_PARAM_IS_BUILTIN(param)) {
656 case BRW_PARAM_BUILTIN_ZERO:
659 unreachable("Invalid param builtin");
662 uint32_t offset = ANV_PARAM_PUSH_OFFSET(param);
663 assert(offset % sizeof(uint32_t) == 0);
664 if (offset < data->size)
665 return *(uint32_t *)((uint8_t *)data + offset);
672 anv_cmd_buffer_push_constants(struct anv_cmd_buffer *cmd_buffer,
673 gl_shader_stage stage)
675 struct anv_pipeline *pipeline = cmd_buffer->state.gfx.base.pipeline;
677 /* If we don't have this stage, bail. */
678 if (!anv_pipeline_has_stage(pipeline, stage))
679 return (struct anv_state) { .offset = 0 };
681 struct anv_push_constants *data =
682 cmd_buffer->state.push_constants[stage];
683 const struct brw_stage_prog_data *prog_data =
684 pipeline->shaders[stage]->prog_data;
686 /* If we don't actually have any push constants, bail. */
687 if (data == NULL || prog_data == NULL || prog_data->nr_params == 0)
688 return (struct anv_state) { .offset = 0 };
690 struct anv_state state =
691 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer,
692 prog_data->nr_params * sizeof(float),
693 32 /* bottom 5 bits MBZ */);
695 /* Walk through the param array and fill the buffer with data */
696 uint32_t *u32_map = state.map;
697 for (unsigned i = 0; i < prog_data->nr_params; i++)
698 u32_map[i] = anv_push_constant_value(data, prog_data->param[i]);
700 anv_state_flush(cmd_buffer->device, state);
706 anv_cmd_buffer_cs_push_constants(struct anv_cmd_buffer *cmd_buffer)
708 struct anv_push_constants *data =
709 cmd_buffer->state.push_constants[MESA_SHADER_COMPUTE];
710 struct anv_pipeline *pipeline = cmd_buffer->state.compute.base.pipeline;
711 const struct brw_cs_prog_data *cs_prog_data = get_cs_prog_data(pipeline);
712 const struct brw_stage_prog_data *prog_data = &cs_prog_data->base;
714 /* If we don't actually have any push constants, bail. */
715 if (cs_prog_data->push.total.size == 0)
716 return (struct anv_state) { .offset = 0 };
718 const unsigned push_constant_alignment =
719 cmd_buffer->device->info.gen < 8 ? 32 : 64;
720 const unsigned aligned_total_push_constants_size =
721 ALIGN(cs_prog_data->push.total.size, push_constant_alignment);
722 struct anv_state state =
723 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer,
724 aligned_total_push_constants_size,
725 push_constant_alignment);
727 /* Walk through the param array and fill the buffer with data */
728 uint32_t *u32_map = state.map;
730 if (cs_prog_data->push.cross_thread.size > 0) {
732 i < cs_prog_data->push.cross_thread.dwords;
734 assert(prog_data->param[i] != BRW_PARAM_BUILTIN_SUBGROUP_ID);
735 u32_map[i] = anv_push_constant_value(data, prog_data->param[i]);
739 if (cs_prog_data->push.per_thread.size > 0) {
740 for (unsigned t = 0; t < cs_prog_data->threads; t++) {
742 8 * (cs_prog_data->push.per_thread.regs * t +
743 cs_prog_data->push.cross_thread.regs);
744 unsigned src = cs_prog_data->push.cross_thread.dwords;
745 for ( ; src < prog_data->nr_params; src++, dst++) {
746 if (prog_data->param[src] == BRW_PARAM_BUILTIN_SUBGROUP_ID) {
750 anv_push_constant_value(data, prog_data->param[src]);
756 anv_state_flush(cmd_buffer->device, state);
761 void anv_CmdPushConstants(
762 VkCommandBuffer commandBuffer,
763 VkPipelineLayout layout,
764 VkShaderStageFlags stageFlags,
769 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
771 anv_foreach_stage(stage, stageFlags) {
773 anv_cmd_buffer_ensure_push_constant_field(cmd_buffer,
775 if (result != VK_SUCCESS)
778 memcpy(cmd_buffer->state.push_constants[stage]->client_data + offset,
782 cmd_buffer->state.push_constants_dirty |= stageFlags;
785 VkResult anv_CreateCommandPool(
787 const VkCommandPoolCreateInfo* pCreateInfo,
788 const VkAllocationCallbacks* pAllocator,
789 VkCommandPool* pCmdPool)
791 ANV_FROM_HANDLE(anv_device, device, _device);
792 struct anv_cmd_pool *pool;
794 pool = vk_alloc2(&device->alloc, pAllocator, sizeof(*pool), 8,
795 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
797 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
800 pool->alloc = *pAllocator;
802 pool->alloc = device->alloc;
804 list_inithead(&pool->cmd_buffers);
806 *pCmdPool = anv_cmd_pool_to_handle(pool);
811 void anv_DestroyCommandPool(
813 VkCommandPool commandPool,
814 const VkAllocationCallbacks* pAllocator)
816 ANV_FROM_HANDLE(anv_device, device, _device);
817 ANV_FROM_HANDLE(anv_cmd_pool, pool, commandPool);
822 list_for_each_entry_safe(struct anv_cmd_buffer, cmd_buffer,
823 &pool->cmd_buffers, pool_link) {
824 anv_cmd_buffer_destroy(cmd_buffer);
827 vk_free2(&device->alloc, pAllocator, pool);
830 VkResult anv_ResetCommandPool(
832 VkCommandPool commandPool,
833 VkCommandPoolResetFlags flags)
835 ANV_FROM_HANDLE(anv_cmd_pool, pool, commandPool);
837 list_for_each_entry(struct anv_cmd_buffer, cmd_buffer,
838 &pool->cmd_buffers, pool_link) {
839 anv_cmd_buffer_reset(cmd_buffer);
845 void anv_TrimCommandPoolKHR(
847 VkCommandPool commandPool,
848 VkCommandPoolTrimFlagsKHR flags)
850 /* Nothing for us to do here. Our pools stay pretty tidy. */
854 * Return NULL if the current subpass has no depthstencil attachment.
856 const struct anv_image_view *
857 anv_cmd_buffer_get_depth_stencil_view(const struct anv_cmd_buffer *cmd_buffer)
859 const struct anv_subpass *subpass = cmd_buffer->state.subpass;
860 const struct anv_framebuffer *fb = cmd_buffer->state.framebuffer;
862 if (subpass->depth_stencil_attachment.attachment == VK_ATTACHMENT_UNUSED)
865 const struct anv_image_view *iview =
866 fb->attachments[subpass->depth_stencil_attachment.attachment];
868 assert(iview->aspect_mask & (VK_IMAGE_ASPECT_DEPTH_BIT |
869 VK_IMAGE_ASPECT_STENCIL_BIT));
874 static struct anv_push_descriptor_set *
875 anv_cmd_buffer_get_push_descriptor_set(struct anv_cmd_buffer *cmd_buffer,
876 VkPipelineBindPoint bind_point,
879 struct anv_cmd_pipeline_state *pipe_state;
880 if (bind_point == VK_PIPELINE_BIND_POINT_COMPUTE) {
881 pipe_state = &cmd_buffer->state.compute.base;
883 assert(bind_point == VK_PIPELINE_BIND_POINT_GRAPHICS);
884 pipe_state = &cmd_buffer->state.gfx.base;
887 struct anv_push_descriptor_set **push_set =
888 &pipe_state->push_descriptors[set];
890 if (*push_set == NULL) {
891 *push_set = vk_alloc(&cmd_buffer->pool->alloc,
892 sizeof(struct anv_push_descriptor_set), 8,
893 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
894 if (*push_set == NULL) {
895 anv_batch_set_error(&cmd_buffer->batch, VK_ERROR_OUT_OF_HOST_MEMORY);
903 void anv_CmdPushDescriptorSetKHR(
904 VkCommandBuffer commandBuffer,
905 VkPipelineBindPoint pipelineBindPoint,
906 VkPipelineLayout _layout,
908 uint32_t descriptorWriteCount,
909 const VkWriteDescriptorSet* pDescriptorWrites)
911 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
912 ANV_FROM_HANDLE(anv_pipeline_layout, layout, _layout);
914 assert(_set < MAX_SETS);
916 const struct anv_descriptor_set_layout *set_layout =
917 layout->set[_set].layout;
919 struct anv_push_descriptor_set *push_set =
920 anv_cmd_buffer_get_push_descriptor_set(cmd_buffer,
921 pipelineBindPoint, _set);
925 struct anv_descriptor_set *set = &push_set->set;
927 set->layout = set_layout;
928 set->size = anv_descriptor_set_layout_size(set_layout);
929 set->buffer_count = set_layout->buffer_count;
930 set->buffer_views = push_set->buffer_views;
932 /* Go through the user supplied descriptors. */
933 for (uint32_t i = 0; i < descriptorWriteCount; i++) {
934 const VkWriteDescriptorSet *write = &pDescriptorWrites[i];
936 switch (write->descriptorType) {
937 case VK_DESCRIPTOR_TYPE_SAMPLER:
938 case VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER:
939 case VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE:
940 case VK_DESCRIPTOR_TYPE_STORAGE_IMAGE:
941 case VK_DESCRIPTOR_TYPE_INPUT_ATTACHMENT:
942 for (uint32_t j = 0; j < write->descriptorCount; j++) {
943 anv_descriptor_set_write_image_view(set, &cmd_buffer->device->info,
944 write->pImageInfo + j,
945 write->descriptorType,
947 write->dstArrayElement + j);
951 case VK_DESCRIPTOR_TYPE_UNIFORM_TEXEL_BUFFER:
952 case VK_DESCRIPTOR_TYPE_STORAGE_TEXEL_BUFFER:
953 for (uint32_t j = 0; j < write->descriptorCount; j++) {
954 ANV_FROM_HANDLE(anv_buffer_view, bview,
955 write->pTexelBufferView[j]);
957 anv_descriptor_set_write_buffer_view(set,
958 write->descriptorType,
961 write->dstArrayElement + j);
965 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER:
966 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER:
967 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC:
968 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC:
969 for (uint32_t j = 0; j < write->descriptorCount; j++) {
970 assert(write->pBufferInfo[j].buffer);
971 ANV_FROM_HANDLE(anv_buffer, buffer, write->pBufferInfo[j].buffer);
974 anv_descriptor_set_write_buffer(set,
976 &cmd_buffer->surface_state_stream,
977 write->descriptorType,
980 write->dstArrayElement + j,
981 write->pBufferInfo[j].offset,
982 write->pBufferInfo[j].range);
991 anv_cmd_buffer_bind_descriptor_set(cmd_buffer, pipelineBindPoint,
992 layout, _set, set, NULL, NULL);
995 void anv_CmdPushDescriptorSetWithTemplateKHR(
996 VkCommandBuffer commandBuffer,
997 VkDescriptorUpdateTemplateKHR descriptorUpdateTemplate,
998 VkPipelineLayout _layout,
1002 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
1003 ANV_FROM_HANDLE(anv_descriptor_update_template, template,
1004 descriptorUpdateTemplate);
1005 ANV_FROM_HANDLE(anv_pipeline_layout, layout, _layout);
1007 assert(_set < MAX_PUSH_DESCRIPTORS);
1009 const struct anv_descriptor_set_layout *set_layout =
1010 layout->set[_set].layout;
1012 struct anv_push_descriptor_set *push_set =
1013 anv_cmd_buffer_get_push_descriptor_set(cmd_buffer,
1014 template->bind_point, _set);
1018 struct anv_descriptor_set *set = &push_set->set;
1020 set->layout = set_layout;
1021 set->size = anv_descriptor_set_layout_size(set_layout);
1022 set->buffer_count = set_layout->buffer_count;
1023 set->buffer_views = push_set->buffer_views;
1025 anv_descriptor_set_write_template(set,
1027 &cmd_buffer->surface_state_stream,
1031 anv_cmd_buffer_bind_descriptor_set(cmd_buffer, template->bind_point,
1032 layout, _set, set, NULL, NULL);