2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
30 #include "anv_private.h"
32 #include "vk_format_info.h"
34 /** \file anv_cmd_buffer.c
36 * This file contains all of the stuff for emitting commands into a command
37 * buffer. This includes implementations of most of the vkCmd*
38 * entrypoints. This file is concerned entirely with state emission and
39 * not with the command buffer data structure itself. As far as this file
40 * is concerned, most of anv_cmd_buffer is magic.
43 /* TODO: These are taken from GLES. We should check the Vulkan spec */
44 const struct anv_dynamic_state default_dynamic_state = {
57 .blend_constants = { 0.0f, 0.0f, 0.0f, 0.0f },
62 .stencil_compare_mask = {
66 .stencil_write_mask = {
70 .stencil_reference = {
77 anv_dynamic_state_copy(struct anv_dynamic_state *dest,
78 const struct anv_dynamic_state *src,
81 if (copy_mask & (1 << VK_DYNAMIC_STATE_VIEWPORT)) {
82 dest->viewport.count = src->viewport.count;
83 typed_memcpy(dest->viewport.viewports, src->viewport.viewports,
87 if (copy_mask & (1 << VK_DYNAMIC_STATE_SCISSOR)) {
88 dest->scissor.count = src->scissor.count;
89 typed_memcpy(dest->scissor.scissors, src->scissor.scissors,
93 if (copy_mask & (1 << VK_DYNAMIC_STATE_LINE_WIDTH))
94 dest->line_width = src->line_width;
96 if (copy_mask & (1 << VK_DYNAMIC_STATE_DEPTH_BIAS))
97 dest->depth_bias = src->depth_bias;
99 if (copy_mask & (1 << VK_DYNAMIC_STATE_BLEND_CONSTANTS))
100 typed_memcpy(dest->blend_constants, src->blend_constants, 4);
102 if (copy_mask & (1 << VK_DYNAMIC_STATE_DEPTH_BOUNDS))
103 dest->depth_bounds = src->depth_bounds;
105 if (copy_mask & (1 << VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK))
106 dest->stencil_compare_mask = src->stencil_compare_mask;
108 if (copy_mask & (1 << VK_DYNAMIC_STATE_STENCIL_WRITE_MASK))
109 dest->stencil_write_mask = src->stencil_write_mask;
111 if (copy_mask & (1 << VK_DYNAMIC_STATE_STENCIL_REFERENCE))
112 dest->stencil_reference = src->stencil_reference;
116 anv_cmd_state_init(struct anv_cmd_buffer *cmd_buffer)
118 struct anv_cmd_state *state = &cmd_buffer->state;
120 memset(state, 0, sizeof(*state));
122 state->current_pipeline = UINT32_MAX;
123 state->restart_index = UINT32_MAX;
124 state->gfx.dynamic = default_dynamic_state;
128 anv_cmd_pipeline_state_finish(struct anv_cmd_buffer *cmd_buffer,
129 struct anv_cmd_pipeline_state *pipe_state)
131 for (uint32_t i = 0; i < ARRAY_SIZE(pipe_state->push_descriptors); i++)
132 vk_free(&cmd_buffer->pool->alloc, pipe_state->push_descriptors[i]);
136 anv_cmd_state_finish(struct anv_cmd_buffer *cmd_buffer)
138 struct anv_cmd_state *state = &cmd_buffer->state;
140 anv_cmd_pipeline_state_finish(cmd_buffer, &state->gfx.base);
141 anv_cmd_pipeline_state_finish(cmd_buffer, &state->compute.base);
143 for (uint32_t i = 0; i < MESA_SHADER_STAGES; i++)
144 vk_free(&cmd_buffer->pool->alloc, state->push_constants[i]);
146 vk_free(&cmd_buffer->pool->alloc, state->attachments);
150 anv_cmd_state_reset(struct anv_cmd_buffer *cmd_buffer)
152 anv_cmd_state_finish(cmd_buffer);
153 anv_cmd_state_init(cmd_buffer);
157 anv_cmd_buffer_ensure_push_constants_size(struct anv_cmd_buffer *cmd_buffer,
158 gl_shader_stage stage, uint32_t size)
160 struct anv_push_constants **ptr = &cmd_buffer->state.push_constants[stage];
163 *ptr = vk_alloc(&cmd_buffer->pool->alloc, size, 8,
164 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
166 anv_batch_set_error(&cmd_buffer->batch, VK_ERROR_OUT_OF_HOST_MEMORY);
167 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
169 } else if ((*ptr)->size < size) {
170 *ptr = vk_realloc(&cmd_buffer->pool->alloc, *ptr, size, 8,
171 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
173 anv_batch_set_error(&cmd_buffer->batch, VK_ERROR_OUT_OF_HOST_MEMORY);
174 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
182 static VkResult anv_create_cmd_buffer(
183 struct anv_device * device,
184 struct anv_cmd_pool * pool,
185 VkCommandBufferLevel level,
186 VkCommandBuffer* pCommandBuffer)
188 struct anv_cmd_buffer *cmd_buffer;
191 cmd_buffer = vk_alloc(&pool->alloc, sizeof(*cmd_buffer), 8,
192 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
193 if (cmd_buffer == NULL)
194 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
196 cmd_buffer->batch.status = VK_SUCCESS;
198 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
199 cmd_buffer->device = device;
200 cmd_buffer->pool = pool;
201 cmd_buffer->level = level;
203 result = anv_cmd_buffer_init_batch_bo_chain(cmd_buffer);
204 if (result != VK_SUCCESS)
207 anv_state_stream_init(&cmd_buffer->surface_state_stream,
208 &device->surface_state_pool, 4096);
209 anv_state_stream_init(&cmd_buffer->dynamic_state_stream,
210 &device->dynamic_state_pool, 16384);
212 anv_cmd_state_init(cmd_buffer);
215 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
217 /* Init the pool_link so we can safefly call list_del when we destroy
220 list_inithead(&cmd_buffer->pool_link);
223 *pCommandBuffer = anv_cmd_buffer_to_handle(cmd_buffer);
228 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
233 VkResult anv_AllocateCommandBuffers(
235 const VkCommandBufferAllocateInfo* pAllocateInfo,
236 VkCommandBuffer* pCommandBuffers)
238 ANV_FROM_HANDLE(anv_device, device, _device);
239 ANV_FROM_HANDLE(anv_cmd_pool, pool, pAllocateInfo->commandPool);
241 VkResult result = VK_SUCCESS;
244 for (i = 0; i < pAllocateInfo->commandBufferCount; i++) {
245 result = anv_create_cmd_buffer(device, pool, pAllocateInfo->level,
246 &pCommandBuffers[i]);
247 if (result != VK_SUCCESS)
251 if (result != VK_SUCCESS) {
252 anv_FreeCommandBuffers(_device, pAllocateInfo->commandPool,
254 for (i = 0; i < pAllocateInfo->commandBufferCount; i++)
255 pCommandBuffers[i] = VK_NULL_HANDLE;
262 anv_cmd_buffer_destroy(struct anv_cmd_buffer *cmd_buffer)
264 list_del(&cmd_buffer->pool_link);
266 anv_cmd_buffer_fini_batch_bo_chain(cmd_buffer);
268 anv_state_stream_finish(&cmd_buffer->surface_state_stream);
269 anv_state_stream_finish(&cmd_buffer->dynamic_state_stream);
271 anv_cmd_state_finish(cmd_buffer);
273 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
276 void anv_FreeCommandBuffers(
278 VkCommandPool commandPool,
279 uint32_t commandBufferCount,
280 const VkCommandBuffer* pCommandBuffers)
282 for (uint32_t i = 0; i < commandBufferCount; i++) {
283 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, pCommandBuffers[i]);
288 anv_cmd_buffer_destroy(cmd_buffer);
293 anv_cmd_buffer_reset(struct anv_cmd_buffer *cmd_buffer)
295 cmd_buffer->usage_flags = 0;
296 anv_cmd_buffer_reset_batch_bo_chain(cmd_buffer);
297 anv_cmd_state_reset(cmd_buffer);
299 anv_state_stream_finish(&cmd_buffer->surface_state_stream);
300 anv_state_stream_init(&cmd_buffer->surface_state_stream,
301 &cmd_buffer->device->surface_state_pool, 4096);
303 anv_state_stream_finish(&cmd_buffer->dynamic_state_stream);
304 anv_state_stream_init(&cmd_buffer->dynamic_state_stream,
305 &cmd_buffer->device->dynamic_state_pool, 16384);
309 VkResult anv_ResetCommandBuffer(
310 VkCommandBuffer commandBuffer,
311 VkCommandBufferResetFlags flags)
313 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
314 return anv_cmd_buffer_reset(cmd_buffer);
317 #define anv_genX_call(devinfo, func, ...) \
318 switch ((devinfo)->gen) { \
320 if ((devinfo)->is_haswell) { \
321 gen75_##func(__VA_ARGS__); \
323 gen7_##func(__VA_ARGS__); \
327 gen8_##func(__VA_ARGS__); \
330 gen9_##func(__VA_ARGS__); \
333 gen10_##func(__VA_ARGS__); \
336 gen11_##func(__VA_ARGS__); \
339 assert(!"Unknown hardware generation"); \
343 anv_cmd_buffer_emit_state_base_address(struct anv_cmd_buffer *cmd_buffer)
345 anv_genX_call(&cmd_buffer->device->info,
346 cmd_buffer_emit_state_base_address,
351 anv_cmd_buffer_mark_image_written(struct anv_cmd_buffer *cmd_buffer,
352 const struct anv_image *image,
353 VkImageAspectFlagBits aspect,
354 enum isl_aux_usage aux_usage,
357 uint32_t layer_count)
359 anv_genX_call(&cmd_buffer->device->info,
360 cmd_buffer_mark_image_written,
361 cmd_buffer, image, aspect, aux_usage,
362 level, base_layer, layer_count);
365 void anv_CmdBindPipeline(
366 VkCommandBuffer commandBuffer,
367 VkPipelineBindPoint pipelineBindPoint,
368 VkPipeline _pipeline)
370 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
371 ANV_FROM_HANDLE(anv_pipeline, pipeline, _pipeline);
373 switch (pipelineBindPoint) {
374 case VK_PIPELINE_BIND_POINT_COMPUTE:
375 cmd_buffer->state.compute.base.pipeline = pipeline;
376 cmd_buffer->state.compute.pipeline_dirty = true;
377 cmd_buffer->state.push_constants_dirty |= VK_SHADER_STAGE_COMPUTE_BIT;
378 cmd_buffer->state.descriptors_dirty |= VK_SHADER_STAGE_COMPUTE_BIT;
381 case VK_PIPELINE_BIND_POINT_GRAPHICS:
382 cmd_buffer->state.gfx.base.pipeline = pipeline;
383 cmd_buffer->state.gfx.vb_dirty |= pipeline->vb_used;
384 cmd_buffer->state.gfx.dirty |= ANV_CMD_DIRTY_PIPELINE;
385 cmd_buffer->state.push_constants_dirty |= pipeline->active_stages;
386 cmd_buffer->state.descriptors_dirty |= pipeline->active_stages;
388 /* Apply the dynamic state from the pipeline */
389 cmd_buffer->state.gfx.dirty |= pipeline->dynamic_state_mask;
390 anv_dynamic_state_copy(&cmd_buffer->state.gfx.dynamic,
391 &pipeline->dynamic_state,
392 pipeline->dynamic_state_mask);
396 assert(!"invalid bind point");
401 void anv_CmdSetViewport(
402 VkCommandBuffer commandBuffer,
403 uint32_t firstViewport,
404 uint32_t viewportCount,
405 const VkViewport* pViewports)
407 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
409 const uint32_t total_count = firstViewport + viewportCount;
410 if (cmd_buffer->state.gfx.dynamic.viewport.count < total_count)
411 cmd_buffer->state.gfx.dynamic.viewport.count = total_count;
413 memcpy(cmd_buffer->state.gfx.dynamic.viewport.viewports + firstViewport,
414 pViewports, viewportCount * sizeof(*pViewports));
416 cmd_buffer->state.gfx.dirty |= ANV_CMD_DIRTY_DYNAMIC_VIEWPORT;
419 void anv_CmdSetScissor(
420 VkCommandBuffer commandBuffer,
421 uint32_t firstScissor,
422 uint32_t scissorCount,
423 const VkRect2D* pScissors)
425 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
427 const uint32_t total_count = firstScissor + scissorCount;
428 if (cmd_buffer->state.gfx.dynamic.scissor.count < total_count)
429 cmd_buffer->state.gfx.dynamic.scissor.count = total_count;
431 memcpy(cmd_buffer->state.gfx.dynamic.scissor.scissors + firstScissor,
432 pScissors, scissorCount * sizeof(*pScissors));
434 cmd_buffer->state.gfx.dirty |= ANV_CMD_DIRTY_DYNAMIC_SCISSOR;
437 void anv_CmdSetLineWidth(
438 VkCommandBuffer commandBuffer,
441 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
443 cmd_buffer->state.gfx.dynamic.line_width = lineWidth;
444 cmd_buffer->state.gfx.dirty |= ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH;
447 void anv_CmdSetDepthBias(
448 VkCommandBuffer commandBuffer,
449 float depthBiasConstantFactor,
450 float depthBiasClamp,
451 float depthBiasSlopeFactor)
453 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
455 cmd_buffer->state.gfx.dynamic.depth_bias.bias = depthBiasConstantFactor;
456 cmd_buffer->state.gfx.dynamic.depth_bias.clamp = depthBiasClamp;
457 cmd_buffer->state.gfx.dynamic.depth_bias.slope = depthBiasSlopeFactor;
459 cmd_buffer->state.gfx.dirty |= ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
462 void anv_CmdSetBlendConstants(
463 VkCommandBuffer commandBuffer,
464 const float blendConstants[4])
466 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
468 memcpy(cmd_buffer->state.gfx.dynamic.blend_constants,
469 blendConstants, sizeof(float) * 4);
471 cmd_buffer->state.gfx.dirty |= ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS;
474 void anv_CmdSetDepthBounds(
475 VkCommandBuffer commandBuffer,
476 float minDepthBounds,
477 float maxDepthBounds)
479 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
481 cmd_buffer->state.gfx.dynamic.depth_bounds.min = minDepthBounds;
482 cmd_buffer->state.gfx.dynamic.depth_bounds.max = maxDepthBounds;
484 cmd_buffer->state.gfx.dirty |= ANV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS;
487 void anv_CmdSetStencilCompareMask(
488 VkCommandBuffer commandBuffer,
489 VkStencilFaceFlags faceMask,
490 uint32_t compareMask)
492 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
494 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
495 cmd_buffer->state.gfx.dynamic.stencil_compare_mask.front = compareMask;
496 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
497 cmd_buffer->state.gfx.dynamic.stencil_compare_mask.back = compareMask;
499 cmd_buffer->state.gfx.dirty |= ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK;
502 void anv_CmdSetStencilWriteMask(
503 VkCommandBuffer commandBuffer,
504 VkStencilFaceFlags faceMask,
507 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
509 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
510 cmd_buffer->state.gfx.dynamic.stencil_write_mask.front = writeMask;
511 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
512 cmd_buffer->state.gfx.dynamic.stencil_write_mask.back = writeMask;
514 cmd_buffer->state.gfx.dirty |= ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK;
517 void anv_CmdSetStencilReference(
518 VkCommandBuffer commandBuffer,
519 VkStencilFaceFlags faceMask,
522 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
524 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
525 cmd_buffer->state.gfx.dynamic.stencil_reference.front = reference;
526 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
527 cmd_buffer->state.gfx.dynamic.stencil_reference.back = reference;
529 cmd_buffer->state.gfx.dirty |= ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE;
533 anv_cmd_buffer_bind_descriptor_set(struct anv_cmd_buffer *cmd_buffer,
534 VkPipelineBindPoint bind_point,
535 struct anv_pipeline_layout *layout,
537 struct anv_descriptor_set *set,
538 uint32_t *dynamic_offset_count,
539 const uint32_t **dynamic_offsets)
541 struct anv_descriptor_set_layout *set_layout =
542 layout->set[set_index].layout;
544 struct anv_cmd_pipeline_state *pipe_state;
545 if (bind_point == VK_PIPELINE_BIND_POINT_COMPUTE) {
546 pipe_state = &cmd_buffer->state.compute.base;
548 assert(bind_point == VK_PIPELINE_BIND_POINT_GRAPHICS);
549 pipe_state = &cmd_buffer->state.gfx.base;
551 pipe_state->descriptors[set_index] = set;
553 if (dynamic_offsets) {
554 if (set_layout->dynamic_offset_count > 0) {
555 uint32_t dynamic_offset_start =
556 layout->set[set_index].dynamic_offset_start;
558 /* Assert that everything is in range */
559 assert(set_layout->dynamic_offset_count <= *dynamic_offset_count);
560 assert(dynamic_offset_start + set_layout->dynamic_offset_count <=
561 ARRAY_SIZE(pipe_state->dynamic_offsets));
563 typed_memcpy(&pipe_state->dynamic_offsets[dynamic_offset_start],
564 *dynamic_offsets, set_layout->dynamic_offset_count);
566 *dynamic_offsets += set_layout->dynamic_offset_count;
567 *dynamic_offset_count -= set_layout->dynamic_offset_count;
571 if (bind_point == VK_PIPELINE_BIND_POINT_COMPUTE) {
572 cmd_buffer->state.descriptors_dirty |= VK_SHADER_STAGE_COMPUTE_BIT;
574 assert(bind_point == VK_PIPELINE_BIND_POINT_GRAPHICS);
575 cmd_buffer->state.descriptors_dirty |=
576 set_layout->shader_stages & VK_SHADER_STAGE_ALL_GRAPHICS;
579 /* Pipeline layout objects are required to live at least while any command
580 * buffers that use them are in recording state. We need to grab a reference
581 * to the pipeline layout being bound here so we can compute correct dynamic
582 * offsets for VK_DESCRIPTOR_TYPE_*_DYNAMIC in dynamic_offset_for_binding()
583 * when we record draw commands that come after this.
585 pipe_state->layout = layout;
588 void anv_CmdBindDescriptorSets(
589 VkCommandBuffer commandBuffer,
590 VkPipelineBindPoint pipelineBindPoint,
591 VkPipelineLayout _layout,
593 uint32_t descriptorSetCount,
594 const VkDescriptorSet* pDescriptorSets,
595 uint32_t dynamicOffsetCount,
596 const uint32_t* pDynamicOffsets)
598 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
599 ANV_FROM_HANDLE(anv_pipeline_layout, layout, _layout);
601 assert(firstSet + descriptorSetCount < MAX_SETS);
603 for (uint32_t i = 0; i < descriptorSetCount; i++) {
604 ANV_FROM_HANDLE(anv_descriptor_set, set, pDescriptorSets[i]);
605 anv_cmd_buffer_bind_descriptor_set(cmd_buffer, pipelineBindPoint,
606 layout, firstSet + i, set,
612 void anv_CmdBindVertexBuffers(
613 VkCommandBuffer commandBuffer,
614 uint32_t firstBinding,
615 uint32_t bindingCount,
616 const VkBuffer* pBuffers,
617 const VkDeviceSize* pOffsets)
619 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
620 struct anv_vertex_binding *vb = cmd_buffer->state.vertex_bindings;
622 /* We have to defer setting up vertex buffer since we need the buffer
623 * stride from the pipeline. */
625 assert(firstBinding + bindingCount <= MAX_VBS);
626 for (uint32_t i = 0; i < bindingCount; i++) {
627 vb[firstBinding + i].buffer = anv_buffer_from_handle(pBuffers[i]);
628 vb[firstBinding + i].offset = pOffsets[i];
629 cmd_buffer->state.gfx.vb_dirty |= 1 << (firstBinding + i);
634 anv_isl_format_for_descriptor_type(VkDescriptorType type)
637 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER:
638 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC:
639 return ISL_FORMAT_R32G32B32A32_FLOAT;
641 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER:
642 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC:
643 return ISL_FORMAT_RAW;
646 unreachable("Invalid descriptor type");
651 anv_cmd_buffer_emit_dynamic(struct anv_cmd_buffer *cmd_buffer,
652 const void *data, uint32_t size, uint32_t alignment)
654 struct anv_state state;
656 state = anv_cmd_buffer_alloc_dynamic_state(cmd_buffer, size, alignment);
657 memcpy(state.map, data, size);
659 anv_state_flush(cmd_buffer->device, state);
661 VG(VALGRIND_CHECK_MEM_IS_DEFINED(state.map, size));
667 anv_cmd_buffer_merge_dynamic(struct anv_cmd_buffer *cmd_buffer,
668 uint32_t *a, uint32_t *b,
669 uint32_t dwords, uint32_t alignment)
671 struct anv_state state;
674 state = anv_cmd_buffer_alloc_dynamic_state(cmd_buffer,
675 dwords * 4, alignment);
677 for (uint32_t i = 0; i < dwords; i++)
680 anv_state_flush(cmd_buffer->device, state);
682 VG(VALGRIND_CHECK_MEM_IS_DEFINED(p, dwords * 4));
688 anv_push_constant_value(struct anv_push_constants *data, uint32_t param)
690 if (BRW_PARAM_IS_BUILTIN(param)) {
692 case BRW_PARAM_BUILTIN_ZERO:
694 case BRW_PARAM_BUILTIN_BASE_WORK_GROUP_ID_X:
695 return data->base_work_group_id[0];
696 case BRW_PARAM_BUILTIN_BASE_WORK_GROUP_ID_Y:
697 return data->base_work_group_id[1];
698 case BRW_PARAM_BUILTIN_BASE_WORK_GROUP_ID_Z:
699 return data->base_work_group_id[2];
701 unreachable("Invalid param builtin");
704 uint32_t offset = ANV_PARAM_PUSH_OFFSET(param);
705 assert(offset % sizeof(uint32_t) == 0);
706 if (offset < data->size)
707 return *(uint32_t *)((uint8_t *)data + offset);
714 anv_cmd_buffer_push_constants(struct anv_cmd_buffer *cmd_buffer,
715 gl_shader_stage stage)
717 struct anv_pipeline *pipeline = cmd_buffer->state.gfx.base.pipeline;
719 /* If we don't have this stage, bail. */
720 if (!anv_pipeline_has_stage(pipeline, stage))
721 return (struct anv_state) { .offset = 0 };
723 struct anv_push_constants *data =
724 cmd_buffer->state.push_constants[stage];
725 const struct brw_stage_prog_data *prog_data =
726 pipeline->shaders[stage]->prog_data;
728 /* If we don't actually have any push constants, bail. */
729 if (data == NULL || prog_data == NULL || prog_data->nr_params == 0)
730 return (struct anv_state) { .offset = 0 };
732 struct anv_state state =
733 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer,
734 prog_data->nr_params * sizeof(float),
735 32 /* bottom 5 bits MBZ */);
737 /* Walk through the param array and fill the buffer with data */
738 uint32_t *u32_map = state.map;
739 for (unsigned i = 0; i < prog_data->nr_params; i++)
740 u32_map[i] = anv_push_constant_value(data, prog_data->param[i]);
742 anv_state_flush(cmd_buffer->device, state);
748 anv_cmd_buffer_cs_push_constants(struct anv_cmd_buffer *cmd_buffer)
750 struct anv_push_constants *data =
751 cmd_buffer->state.push_constants[MESA_SHADER_COMPUTE];
752 struct anv_pipeline *pipeline = cmd_buffer->state.compute.base.pipeline;
753 const struct brw_cs_prog_data *cs_prog_data = get_cs_prog_data(pipeline);
754 const struct brw_stage_prog_data *prog_data = &cs_prog_data->base;
756 /* If we don't actually have any push constants, bail. */
757 if (cs_prog_data->push.total.size == 0)
758 return (struct anv_state) { .offset = 0 };
760 const unsigned push_constant_alignment =
761 cmd_buffer->device->info.gen < 8 ? 32 : 64;
762 const unsigned aligned_total_push_constants_size =
763 ALIGN(cs_prog_data->push.total.size, push_constant_alignment);
764 struct anv_state state =
765 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer,
766 aligned_total_push_constants_size,
767 push_constant_alignment);
769 /* Walk through the param array and fill the buffer with data */
770 uint32_t *u32_map = state.map;
772 if (cs_prog_data->push.cross_thread.size > 0) {
774 i < cs_prog_data->push.cross_thread.dwords;
776 assert(prog_data->param[i] != BRW_PARAM_BUILTIN_SUBGROUP_ID);
777 u32_map[i] = anv_push_constant_value(data, prog_data->param[i]);
781 if (cs_prog_data->push.per_thread.size > 0) {
782 for (unsigned t = 0; t < cs_prog_data->threads; t++) {
784 8 * (cs_prog_data->push.per_thread.regs * t +
785 cs_prog_data->push.cross_thread.regs);
786 unsigned src = cs_prog_data->push.cross_thread.dwords;
787 for ( ; src < prog_data->nr_params; src++, dst++) {
788 if (prog_data->param[src] == BRW_PARAM_BUILTIN_SUBGROUP_ID) {
792 anv_push_constant_value(data, prog_data->param[src]);
798 anv_state_flush(cmd_buffer->device, state);
803 void anv_CmdPushConstants(
804 VkCommandBuffer commandBuffer,
805 VkPipelineLayout layout,
806 VkShaderStageFlags stageFlags,
811 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
813 anv_foreach_stage(stage, stageFlags) {
815 anv_cmd_buffer_ensure_push_constant_field(cmd_buffer,
817 if (result != VK_SUCCESS)
820 memcpy(cmd_buffer->state.push_constants[stage]->client_data + offset,
824 cmd_buffer->state.push_constants_dirty |= stageFlags;
827 VkResult anv_CreateCommandPool(
829 const VkCommandPoolCreateInfo* pCreateInfo,
830 const VkAllocationCallbacks* pAllocator,
831 VkCommandPool* pCmdPool)
833 ANV_FROM_HANDLE(anv_device, device, _device);
834 struct anv_cmd_pool *pool;
836 pool = vk_alloc2(&device->alloc, pAllocator, sizeof(*pool), 8,
837 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
839 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
842 pool->alloc = *pAllocator;
844 pool->alloc = device->alloc;
846 list_inithead(&pool->cmd_buffers);
848 *pCmdPool = anv_cmd_pool_to_handle(pool);
853 void anv_DestroyCommandPool(
855 VkCommandPool commandPool,
856 const VkAllocationCallbacks* pAllocator)
858 ANV_FROM_HANDLE(anv_device, device, _device);
859 ANV_FROM_HANDLE(anv_cmd_pool, pool, commandPool);
864 list_for_each_entry_safe(struct anv_cmd_buffer, cmd_buffer,
865 &pool->cmd_buffers, pool_link) {
866 anv_cmd_buffer_destroy(cmd_buffer);
869 vk_free2(&device->alloc, pAllocator, pool);
872 VkResult anv_ResetCommandPool(
874 VkCommandPool commandPool,
875 VkCommandPoolResetFlags flags)
877 ANV_FROM_HANDLE(anv_cmd_pool, pool, commandPool);
879 list_for_each_entry(struct anv_cmd_buffer, cmd_buffer,
880 &pool->cmd_buffers, pool_link) {
881 anv_cmd_buffer_reset(cmd_buffer);
887 void anv_TrimCommandPool(
889 VkCommandPool commandPool,
890 VkCommandPoolTrimFlags flags)
892 /* Nothing for us to do here. Our pools stay pretty tidy. */
896 * Return NULL if the current subpass has no depthstencil attachment.
898 const struct anv_image_view *
899 anv_cmd_buffer_get_depth_stencil_view(const struct anv_cmd_buffer *cmd_buffer)
901 const struct anv_subpass *subpass = cmd_buffer->state.subpass;
902 const struct anv_framebuffer *fb = cmd_buffer->state.framebuffer;
904 if (subpass->depth_stencil_attachment.attachment == VK_ATTACHMENT_UNUSED)
907 const struct anv_image_view *iview =
908 fb->attachments[subpass->depth_stencil_attachment.attachment];
910 assert(iview->aspect_mask & (VK_IMAGE_ASPECT_DEPTH_BIT |
911 VK_IMAGE_ASPECT_STENCIL_BIT));
916 static struct anv_push_descriptor_set *
917 anv_cmd_buffer_get_push_descriptor_set(struct anv_cmd_buffer *cmd_buffer,
918 VkPipelineBindPoint bind_point,
921 struct anv_cmd_pipeline_state *pipe_state;
922 if (bind_point == VK_PIPELINE_BIND_POINT_COMPUTE) {
923 pipe_state = &cmd_buffer->state.compute.base;
925 assert(bind_point == VK_PIPELINE_BIND_POINT_GRAPHICS);
926 pipe_state = &cmd_buffer->state.gfx.base;
929 struct anv_push_descriptor_set **push_set =
930 &pipe_state->push_descriptors[set];
932 if (*push_set == NULL) {
933 *push_set = vk_alloc(&cmd_buffer->pool->alloc,
934 sizeof(struct anv_push_descriptor_set), 8,
935 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
936 if (*push_set == NULL) {
937 anv_batch_set_error(&cmd_buffer->batch, VK_ERROR_OUT_OF_HOST_MEMORY);
945 void anv_CmdPushDescriptorSetKHR(
946 VkCommandBuffer commandBuffer,
947 VkPipelineBindPoint pipelineBindPoint,
948 VkPipelineLayout _layout,
950 uint32_t descriptorWriteCount,
951 const VkWriteDescriptorSet* pDescriptorWrites)
953 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
954 ANV_FROM_HANDLE(anv_pipeline_layout, layout, _layout);
956 assert(_set < MAX_SETS);
958 struct anv_descriptor_set_layout *set_layout = layout->set[_set].layout;
960 struct anv_push_descriptor_set *push_set =
961 anv_cmd_buffer_get_push_descriptor_set(cmd_buffer,
962 pipelineBindPoint, _set);
966 struct anv_descriptor_set *set = &push_set->set;
968 set->layout = set_layout;
969 set->size = anv_descriptor_set_layout_size(set_layout);
970 set->buffer_count = set_layout->buffer_count;
971 set->buffer_views = push_set->buffer_views;
973 /* Go through the user supplied descriptors. */
974 for (uint32_t i = 0; i < descriptorWriteCount; i++) {
975 const VkWriteDescriptorSet *write = &pDescriptorWrites[i];
977 switch (write->descriptorType) {
978 case VK_DESCRIPTOR_TYPE_SAMPLER:
979 case VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER:
980 case VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE:
981 case VK_DESCRIPTOR_TYPE_STORAGE_IMAGE:
982 case VK_DESCRIPTOR_TYPE_INPUT_ATTACHMENT:
983 for (uint32_t j = 0; j < write->descriptorCount; j++) {
984 anv_descriptor_set_write_image_view(set, &cmd_buffer->device->info,
985 write->pImageInfo + j,
986 write->descriptorType,
988 write->dstArrayElement + j);
992 case VK_DESCRIPTOR_TYPE_UNIFORM_TEXEL_BUFFER:
993 case VK_DESCRIPTOR_TYPE_STORAGE_TEXEL_BUFFER:
994 for (uint32_t j = 0; j < write->descriptorCount; j++) {
995 ANV_FROM_HANDLE(anv_buffer_view, bview,
996 write->pTexelBufferView[j]);
998 anv_descriptor_set_write_buffer_view(set,
999 write->descriptorType,
1002 write->dstArrayElement + j);
1006 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER:
1007 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER:
1008 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC:
1009 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC:
1010 for (uint32_t j = 0; j < write->descriptorCount; j++) {
1011 assert(write->pBufferInfo[j].buffer);
1012 ANV_FROM_HANDLE(anv_buffer, buffer, write->pBufferInfo[j].buffer);
1015 anv_descriptor_set_write_buffer(set,
1017 &cmd_buffer->surface_state_stream,
1018 write->descriptorType,
1021 write->dstArrayElement + j,
1022 write->pBufferInfo[j].offset,
1023 write->pBufferInfo[j].range);
1032 anv_cmd_buffer_bind_descriptor_set(cmd_buffer, pipelineBindPoint,
1033 layout, _set, set, NULL, NULL);
1036 void anv_CmdPushDescriptorSetWithTemplateKHR(
1037 VkCommandBuffer commandBuffer,
1038 VkDescriptorUpdateTemplate descriptorUpdateTemplate,
1039 VkPipelineLayout _layout,
1043 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
1044 ANV_FROM_HANDLE(anv_descriptor_update_template, template,
1045 descriptorUpdateTemplate);
1046 ANV_FROM_HANDLE(anv_pipeline_layout, layout, _layout);
1048 assert(_set < MAX_PUSH_DESCRIPTORS);
1050 struct anv_descriptor_set_layout *set_layout = layout->set[_set].layout;
1052 struct anv_push_descriptor_set *push_set =
1053 anv_cmd_buffer_get_push_descriptor_set(cmd_buffer,
1054 template->bind_point, _set);
1058 struct anv_descriptor_set *set = &push_set->set;
1060 set->layout = set_layout;
1061 set->size = anv_descriptor_set_layout_size(set_layout);
1062 set->buffer_count = set_layout->buffer_count;
1063 set->buffer_views = push_set->buffer_views;
1065 anv_descriptor_set_write_template(set,
1067 &cmd_buffer->surface_state_stream,
1071 anv_cmd_buffer_bind_descriptor_set(cmd_buffer, template->bind_point,
1072 layout, _set, set, NULL, NULL);
1075 void anv_CmdSetDeviceMask(
1076 VkCommandBuffer commandBuffer,
1077 uint32_t deviceMask)