2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
30 #include "anv_private.h"
32 #include "vk_format_info.h"
34 /** \file anv_cmd_buffer.c
36 * This file contains all of the stuff for emitting commands into a command
37 * buffer. This includes implementations of most of the vkCmd*
38 * entrypoints. This file is concerned entirely with state emission and
39 * not with the command buffer data structure itself. As far as this file
40 * is concerned, most of anv_cmd_buffer is magic.
43 /* TODO: These are taken from GLES. We should check the Vulkan spec */
44 const struct anv_dynamic_state default_dynamic_state = {
57 .blend_constants = { 0.0f, 0.0f, 0.0f, 0.0f },
62 .stencil_compare_mask = {
66 .stencil_write_mask = {
70 .stencil_reference = {
77 anv_dynamic_state_copy(struct anv_dynamic_state *dest,
78 const struct anv_dynamic_state *src,
81 if (copy_mask & (1 << VK_DYNAMIC_STATE_VIEWPORT)) {
82 dest->viewport.count = src->viewport.count;
83 typed_memcpy(dest->viewport.viewports, src->viewport.viewports,
87 if (copy_mask & (1 << VK_DYNAMIC_STATE_SCISSOR)) {
88 dest->scissor.count = src->scissor.count;
89 typed_memcpy(dest->scissor.scissors, src->scissor.scissors,
93 if (copy_mask & (1 << VK_DYNAMIC_STATE_LINE_WIDTH))
94 dest->line_width = src->line_width;
96 if (copy_mask & (1 << VK_DYNAMIC_STATE_DEPTH_BIAS))
97 dest->depth_bias = src->depth_bias;
99 if (copy_mask & (1 << VK_DYNAMIC_STATE_BLEND_CONSTANTS))
100 typed_memcpy(dest->blend_constants, src->blend_constants, 4);
102 if (copy_mask & (1 << VK_DYNAMIC_STATE_DEPTH_BOUNDS))
103 dest->depth_bounds = src->depth_bounds;
105 if (copy_mask & (1 << VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK))
106 dest->stencil_compare_mask = src->stencil_compare_mask;
108 if (copy_mask & (1 << VK_DYNAMIC_STATE_STENCIL_WRITE_MASK))
109 dest->stencil_write_mask = src->stencil_write_mask;
111 if (copy_mask & (1 << VK_DYNAMIC_STATE_STENCIL_REFERENCE))
112 dest->stencil_reference = src->stencil_reference;
116 anv_cmd_state_init(struct anv_cmd_buffer *cmd_buffer)
118 struct anv_cmd_state *state = &cmd_buffer->state;
120 memset(state, 0, sizeof(*state));
122 state->restart_index = UINT32_MAX;
123 state->dynamic = default_dynamic_state;
127 anv_cmd_state_finish(struct anv_cmd_buffer *cmd_buffer)
129 struct anv_cmd_state *state = &cmd_buffer->state;
131 for (uint32_t i = 0; i < ARRAY_SIZE(state->push_descriptors); i++)
132 vk_free(&cmd_buffer->pool->alloc, state->push_descriptors[i]);
134 for (uint32_t i = 0; i < MESA_SHADER_STAGES; i++)
135 vk_free(&cmd_buffer->pool->alloc, state->push_constants[i]);
137 vk_free(&cmd_buffer->pool->alloc, state->attachments);
141 anv_cmd_state_reset(struct anv_cmd_buffer *cmd_buffer)
143 anv_cmd_state_finish(cmd_buffer);
144 anv_cmd_state_init(cmd_buffer);
148 anv_cmd_buffer_ensure_push_constants_size(struct anv_cmd_buffer *cmd_buffer,
149 gl_shader_stage stage, uint32_t size)
151 struct anv_push_constants **ptr = &cmd_buffer->state.push_constants[stage];
154 *ptr = vk_alloc(&cmd_buffer->pool->alloc, size, 8,
155 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
157 anv_batch_set_error(&cmd_buffer->batch, VK_ERROR_OUT_OF_HOST_MEMORY);
158 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
160 } else if ((*ptr)->size < size) {
161 *ptr = vk_realloc(&cmd_buffer->pool->alloc, *ptr, size, 8,
162 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
164 anv_batch_set_error(&cmd_buffer->batch, VK_ERROR_OUT_OF_HOST_MEMORY);
165 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
173 static VkResult anv_create_cmd_buffer(
174 struct anv_device * device,
175 struct anv_cmd_pool * pool,
176 VkCommandBufferLevel level,
177 VkCommandBuffer* pCommandBuffer)
179 struct anv_cmd_buffer *cmd_buffer;
182 cmd_buffer = vk_alloc(&pool->alloc, sizeof(*cmd_buffer), 8,
183 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
184 if (cmd_buffer == NULL)
185 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
187 cmd_buffer->batch.status = VK_SUCCESS;
189 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
190 cmd_buffer->device = device;
191 cmd_buffer->pool = pool;
192 cmd_buffer->level = level;
194 result = anv_cmd_buffer_init_batch_bo_chain(cmd_buffer);
195 if (result != VK_SUCCESS)
198 anv_state_stream_init(&cmd_buffer->surface_state_stream,
199 &device->surface_state_pool, 4096);
200 anv_state_stream_init(&cmd_buffer->dynamic_state_stream,
201 &device->dynamic_state_pool, 16384);
203 anv_cmd_state_init(cmd_buffer);
206 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
208 /* Init the pool_link so we can safefly call list_del when we destroy
211 list_inithead(&cmd_buffer->pool_link);
214 *pCommandBuffer = anv_cmd_buffer_to_handle(cmd_buffer);
219 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
224 VkResult anv_AllocateCommandBuffers(
226 const VkCommandBufferAllocateInfo* pAllocateInfo,
227 VkCommandBuffer* pCommandBuffers)
229 ANV_FROM_HANDLE(anv_device, device, _device);
230 ANV_FROM_HANDLE(anv_cmd_pool, pool, pAllocateInfo->commandPool);
232 VkResult result = VK_SUCCESS;
235 for (i = 0; i < pAllocateInfo->commandBufferCount; i++) {
236 result = anv_create_cmd_buffer(device, pool, pAllocateInfo->level,
237 &pCommandBuffers[i]);
238 if (result != VK_SUCCESS)
242 if (result != VK_SUCCESS) {
243 anv_FreeCommandBuffers(_device, pAllocateInfo->commandPool,
245 for (i = 0; i < pAllocateInfo->commandBufferCount; i++)
246 pCommandBuffers[i] = VK_NULL_HANDLE;
253 anv_cmd_buffer_destroy(struct anv_cmd_buffer *cmd_buffer)
255 list_del(&cmd_buffer->pool_link);
257 anv_cmd_buffer_fini_batch_bo_chain(cmd_buffer);
259 anv_state_stream_finish(&cmd_buffer->surface_state_stream);
260 anv_state_stream_finish(&cmd_buffer->dynamic_state_stream);
262 anv_cmd_state_finish(cmd_buffer);
264 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
267 void anv_FreeCommandBuffers(
269 VkCommandPool commandPool,
270 uint32_t commandBufferCount,
271 const VkCommandBuffer* pCommandBuffers)
273 for (uint32_t i = 0; i < commandBufferCount; i++) {
274 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, pCommandBuffers[i]);
279 anv_cmd_buffer_destroy(cmd_buffer);
284 anv_cmd_buffer_reset(struct anv_cmd_buffer *cmd_buffer)
286 cmd_buffer->usage_flags = 0;
287 cmd_buffer->state.current_pipeline = UINT32_MAX;
288 anv_cmd_buffer_reset_batch_bo_chain(cmd_buffer);
289 anv_cmd_state_reset(cmd_buffer);
291 anv_state_stream_finish(&cmd_buffer->surface_state_stream);
292 anv_state_stream_init(&cmd_buffer->surface_state_stream,
293 &cmd_buffer->device->surface_state_pool, 4096);
295 anv_state_stream_finish(&cmd_buffer->dynamic_state_stream);
296 anv_state_stream_init(&cmd_buffer->dynamic_state_stream,
297 &cmd_buffer->device->dynamic_state_pool, 16384);
301 VkResult anv_ResetCommandBuffer(
302 VkCommandBuffer commandBuffer,
303 VkCommandBufferResetFlags flags)
305 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
306 return anv_cmd_buffer_reset(cmd_buffer);
310 anv_cmd_buffer_emit_state_base_address(struct anv_cmd_buffer *cmd_buffer)
312 switch (cmd_buffer->device->info.gen) {
314 if (cmd_buffer->device->info.is_haswell)
315 return gen75_cmd_buffer_emit_state_base_address(cmd_buffer);
317 return gen7_cmd_buffer_emit_state_base_address(cmd_buffer);
319 return gen8_cmd_buffer_emit_state_base_address(cmd_buffer);
321 return gen9_cmd_buffer_emit_state_base_address(cmd_buffer);
323 return gen10_cmd_buffer_emit_state_base_address(cmd_buffer);
325 unreachable("unsupported gen\n");
329 void anv_CmdBindPipeline(
330 VkCommandBuffer commandBuffer,
331 VkPipelineBindPoint pipelineBindPoint,
332 VkPipeline _pipeline)
334 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
335 ANV_FROM_HANDLE(anv_pipeline, pipeline, _pipeline);
337 switch (pipelineBindPoint) {
338 case VK_PIPELINE_BIND_POINT_COMPUTE:
339 cmd_buffer->state.compute_pipeline = pipeline;
340 cmd_buffer->state.compute_dirty |= ANV_CMD_DIRTY_PIPELINE;
341 cmd_buffer->state.push_constants_dirty |= VK_SHADER_STAGE_COMPUTE_BIT;
342 cmd_buffer->state.descriptors_dirty |= VK_SHADER_STAGE_COMPUTE_BIT;
345 case VK_PIPELINE_BIND_POINT_GRAPHICS:
346 cmd_buffer->state.pipeline = pipeline;
347 cmd_buffer->state.vb_dirty |= pipeline->vb_used;
348 cmd_buffer->state.dirty |= ANV_CMD_DIRTY_PIPELINE;
349 cmd_buffer->state.push_constants_dirty |= pipeline->active_stages;
350 cmd_buffer->state.descriptors_dirty |= pipeline->active_stages;
352 /* Apply the dynamic state from the pipeline */
353 cmd_buffer->state.dirty |= pipeline->dynamic_state_mask;
354 anv_dynamic_state_copy(&cmd_buffer->state.dynamic,
355 &pipeline->dynamic_state,
356 pipeline->dynamic_state_mask);
360 assert(!"invalid bind point");
365 void anv_CmdSetViewport(
366 VkCommandBuffer commandBuffer,
367 uint32_t firstViewport,
368 uint32_t viewportCount,
369 const VkViewport* pViewports)
371 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
373 const uint32_t total_count = firstViewport + viewportCount;
374 if (cmd_buffer->state.dynamic.viewport.count < total_count)
375 cmd_buffer->state.dynamic.viewport.count = total_count;
377 memcpy(cmd_buffer->state.dynamic.viewport.viewports + firstViewport,
378 pViewports, viewportCount * sizeof(*pViewports));
380 cmd_buffer->state.dirty |= ANV_CMD_DIRTY_DYNAMIC_VIEWPORT;
383 void anv_CmdSetScissor(
384 VkCommandBuffer commandBuffer,
385 uint32_t firstScissor,
386 uint32_t scissorCount,
387 const VkRect2D* pScissors)
389 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
391 const uint32_t total_count = firstScissor + scissorCount;
392 if (cmd_buffer->state.dynamic.scissor.count < total_count)
393 cmd_buffer->state.dynamic.scissor.count = total_count;
395 memcpy(cmd_buffer->state.dynamic.scissor.scissors + firstScissor,
396 pScissors, scissorCount * sizeof(*pScissors));
398 cmd_buffer->state.dirty |= ANV_CMD_DIRTY_DYNAMIC_SCISSOR;
401 void anv_CmdSetLineWidth(
402 VkCommandBuffer commandBuffer,
405 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
407 cmd_buffer->state.dynamic.line_width = lineWidth;
408 cmd_buffer->state.dirty |= ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH;
411 void anv_CmdSetDepthBias(
412 VkCommandBuffer commandBuffer,
413 float depthBiasConstantFactor,
414 float depthBiasClamp,
415 float depthBiasSlopeFactor)
417 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
419 cmd_buffer->state.dynamic.depth_bias.bias = depthBiasConstantFactor;
420 cmd_buffer->state.dynamic.depth_bias.clamp = depthBiasClamp;
421 cmd_buffer->state.dynamic.depth_bias.slope = depthBiasSlopeFactor;
423 cmd_buffer->state.dirty |= ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
426 void anv_CmdSetBlendConstants(
427 VkCommandBuffer commandBuffer,
428 const float blendConstants[4])
430 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
432 memcpy(cmd_buffer->state.dynamic.blend_constants,
433 blendConstants, sizeof(float) * 4);
435 cmd_buffer->state.dirty |= ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS;
438 void anv_CmdSetDepthBounds(
439 VkCommandBuffer commandBuffer,
440 float minDepthBounds,
441 float maxDepthBounds)
443 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
445 cmd_buffer->state.dynamic.depth_bounds.min = minDepthBounds;
446 cmd_buffer->state.dynamic.depth_bounds.max = maxDepthBounds;
448 cmd_buffer->state.dirty |= ANV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS;
451 void anv_CmdSetStencilCompareMask(
452 VkCommandBuffer commandBuffer,
453 VkStencilFaceFlags faceMask,
454 uint32_t compareMask)
456 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
458 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
459 cmd_buffer->state.dynamic.stencil_compare_mask.front = compareMask;
460 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
461 cmd_buffer->state.dynamic.stencil_compare_mask.back = compareMask;
463 cmd_buffer->state.dirty |= ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK;
466 void anv_CmdSetStencilWriteMask(
467 VkCommandBuffer commandBuffer,
468 VkStencilFaceFlags faceMask,
471 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
473 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
474 cmd_buffer->state.dynamic.stencil_write_mask.front = writeMask;
475 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
476 cmd_buffer->state.dynamic.stencil_write_mask.back = writeMask;
478 cmd_buffer->state.dirty |= ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK;
481 void anv_CmdSetStencilReference(
482 VkCommandBuffer commandBuffer,
483 VkStencilFaceFlags faceMask,
486 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
488 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
489 cmd_buffer->state.dynamic.stencil_reference.front = reference;
490 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
491 cmd_buffer->state.dynamic.stencil_reference.back = reference;
493 cmd_buffer->state.dirty |= ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE;
496 void anv_CmdBindDescriptorSets(
497 VkCommandBuffer commandBuffer,
498 VkPipelineBindPoint pipelineBindPoint,
499 VkPipelineLayout _layout,
501 uint32_t descriptorSetCount,
502 const VkDescriptorSet* pDescriptorSets,
503 uint32_t dynamicOffsetCount,
504 const uint32_t* pDynamicOffsets)
506 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
507 ANV_FROM_HANDLE(anv_pipeline_layout, layout, _layout);
508 struct anv_descriptor_set_layout *set_layout;
510 assert(firstSet + descriptorSetCount < MAX_SETS);
512 uint32_t dynamic_slot = 0;
513 for (uint32_t i = 0; i < descriptorSetCount; i++) {
514 ANV_FROM_HANDLE(anv_descriptor_set, set, pDescriptorSets[i]);
515 set_layout = layout->set[firstSet + i].layout;
517 cmd_buffer->state.descriptors[firstSet + i] = set;
519 if (set_layout->dynamic_offset_count > 0) {
520 uint32_t dynamic_offset_start =
521 layout->set[firstSet + i].dynamic_offset_start;
523 /* Assert that everything is in range */
524 assert(dynamic_offset_start + set_layout->dynamic_offset_count <=
525 ARRAY_SIZE(cmd_buffer->state.dynamic_offsets));
526 assert(dynamic_slot + set_layout->dynamic_offset_count <=
529 typed_memcpy(&cmd_buffer->state.dynamic_offsets[dynamic_offset_start],
530 &pDynamicOffsets[dynamic_slot],
531 set_layout->dynamic_offset_count);
533 dynamic_slot += set_layout->dynamic_offset_count;
536 cmd_buffer->state.descriptors_dirty |= set_layout->shader_stages;
540 void anv_CmdBindVertexBuffers(
541 VkCommandBuffer commandBuffer,
542 uint32_t firstBinding,
543 uint32_t bindingCount,
544 const VkBuffer* pBuffers,
545 const VkDeviceSize* pOffsets)
547 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
548 struct anv_vertex_binding *vb = cmd_buffer->state.vertex_bindings;
550 /* We have to defer setting up vertex buffer since we need the buffer
551 * stride from the pipeline. */
553 assert(firstBinding + bindingCount <= MAX_VBS);
554 for (uint32_t i = 0; i < bindingCount; i++) {
555 vb[firstBinding + i].buffer = anv_buffer_from_handle(pBuffers[i]);
556 vb[firstBinding + i].offset = pOffsets[i];
557 cmd_buffer->state.vb_dirty |= 1 << (firstBinding + i);
562 anv_isl_format_for_descriptor_type(VkDescriptorType type)
565 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER:
566 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC:
567 return ISL_FORMAT_R32G32B32A32_FLOAT;
569 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER:
570 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC:
571 return ISL_FORMAT_RAW;
574 unreachable("Invalid descriptor type");
579 anv_cmd_buffer_emit_dynamic(struct anv_cmd_buffer *cmd_buffer,
580 const void *data, uint32_t size, uint32_t alignment)
582 struct anv_state state;
584 state = anv_cmd_buffer_alloc_dynamic_state(cmd_buffer, size, alignment);
585 memcpy(state.map, data, size);
587 anv_state_flush(cmd_buffer->device, state);
589 VG(VALGRIND_CHECK_MEM_IS_DEFINED(state.map, size));
595 anv_cmd_buffer_merge_dynamic(struct anv_cmd_buffer *cmd_buffer,
596 uint32_t *a, uint32_t *b,
597 uint32_t dwords, uint32_t alignment)
599 struct anv_state state;
602 state = anv_cmd_buffer_alloc_dynamic_state(cmd_buffer,
603 dwords * 4, alignment);
605 for (uint32_t i = 0; i < dwords; i++)
608 anv_state_flush(cmd_buffer->device, state);
610 VG(VALGRIND_CHECK_MEM_IS_DEFINED(p, dwords * 4));
616 anv_push_constant_value(struct anv_push_constants *data, uint32_t param)
618 if (BRW_PARAM_IS_BUILTIN(param)) {
620 case BRW_PARAM_BUILTIN_ZERO:
623 unreachable("Invalid param builtin");
626 uint32_t offset = ANV_PARAM_PUSH_OFFSET(param);
627 assert(offset % sizeof(uint32_t) == 0);
628 if (offset < data->size)
629 return *(uint32_t *)((uint8_t *)data + offset);
636 anv_cmd_buffer_push_constants(struct anv_cmd_buffer *cmd_buffer,
637 gl_shader_stage stage)
639 /* If we don't have this stage, bail. */
640 if (!anv_pipeline_has_stage(cmd_buffer->state.pipeline, stage))
641 return (struct anv_state) { .offset = 0 };
643 struct anv_push_constants *data =
644 cmd_buffer->state.push_constants[stage];
645 const struct brw_stage_prog_data *prog_data =
646 cmd_buffer->state.pipeline->shaders[stage]->prog_data;
648 /* If we don't actually have any push constants, bail. */
649 if (data == NULL || prog_data == NULL || prog_data->nr_params == 0)
650 return (struct anv_state) { .offset = 0 };
652 struct anv_state state =
653 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer,
654 prog_data->nr_params * sizeof(float),
655 32 /* bottom 5 bits MBZ */);
657 /* Walk through the param array and fill the buffer with data */
658 uint32_t *u32_map = state.map;
659 for (unsigned i = 0; i < prog_data->nr_params; i++)
660 u32_map[i] = anv_push_constant_value(data, prog_data->param[i]);
662 anv_state_flush(cmd_buffer->device, state);
668 anv_cmd_buffer_cs_push_constants(struct anv_cmd_buffer *cmd_buffer)
670 struct anv_push_constants *data =
671 cmd_buffer->state.push_constants[MESA_SHADER_COMPUTE];
672 struct anv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
673 const struct brw_cs_prog_data *cs_prog_data = get_cs_prog_data(pipeline);
674 const struct brw_stage_prog_data *prog_data = &cs_prog_data->base;
676 /* If we don't actually have any push constants, bail. */
677 if (cs_prog_data->push.total.size == 0)
678 return (struct anv_state) { .offset = 0 };
680 const unsigned push_constant_alignment =
681 cmd_buffer->device->info.gen < 8 ? 32 : 64;
682 const unsigned aligned_total_push_constants_size =
683 ALIGN(cs_prog_data->push.total.size, push_constant_alignment);
684 struct anv_state state =
685 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer,
686 aligned_total_push_constants_size,
687 push_constant_alignment);
689 /* Walk through the param array and fill the buffer with data */
690 uint32_t *u32_map = state.map;
692 if (cs_prog_data->push.cross_thread.size > 0) {
694 i < cs_prog_data->push.cross_thread.dwords;
696 assert(prog_data->param[i] != BRW_PARAM_BUILTIN_SUBGROUP_ID);
697 u32_map[i] = anv_push_constant_value(data, prog_data->param[i]);
701 if (cs_prog_data->push.per_thread.size > 0) {
702 for (unsigned t = 0; t < cs_prog_data->threads; t++) {
704 8 * (cs_prog_data->push.per_thread.regs * t +
705 cs_prog_data->push.cross_thread.regs);
706 unsigned src = cs_prog_data->push.cross_thread.dwords;
707 for ( ; src < prog_data->nr_params; src++, dst++) {
708 if (prog_data->param[src] == BRW_PARAM_BUILTIN_SUBGROUP_ID) {
712 anv_push_constant_value(data, prog_data->param[src]);
718 anv_state_flush(cmd_buffer->device, state);
723 void anv_CmdPushConstants(
724 VkCommandBuffer commandBuffer,
725 VkPipelineLayout layout,
726 VkShaderStageFlags stageFlags,
731 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
733 anv_foreach_stage(stage, stageFlags) {
735 anv_cmd_buffer_ensure_push_constant_field(cmd_buffer,
737 if (result != VK_SUCCESS)
740 memcpy(cmd_buffer->state.push_constants[stage]->client_data + offset,
744 cmd_buffer->state.push_constants_dirty |= stageFlags;
747 VkResult anv_CreateCommandPool(
749 const VkCommandPoolCreateInfo* pCreateInfo,
750 const VkAllocationCallbacks* pAllocator,
751 VkCommandPool* pCmdPool)
753 ANV_FROM_HANDLE(anv_device, device, _device);
754 struct anv_cmd_pool *pool;
756 pool = vk_alloc2(&device->alloc, pAllocator, sizeof(*pool), 8,
757 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
759 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
762 pool->alloc = *pAllocator;
764 pool->alloc = device->alloc;
766 list_inithead(&pool->cmd_buffers);
768 *pCmdPool = anv_cmd_pool_to_handle(pool);
773 void anv_DestroyCommandPool(
775 VkCommandPool commandPool,
776 const VkAllocationCallbacks* pAllocator)
778 ANV_FROM_HANDLE(anv_device, device, _device);
779 ANV_FROM_HANDLE(anv_cmd_pool, pool, commandPool);
784 list_for_each_entry_safe(struct anv_cmd_buffer, cmd_buffer,
785 &pool->cmd_buffers, pool_link) {
786 anv_cmd_buffer_destroy(cmd_buffer);
789 vk_free2(&device->alloc, pAllocator, pool);
792 VkResult anv_ResetCommandPool(
794 VkCommandPool commandPool,
795 VkCommandPoolResetFlags flags)
797 ANV_FROM_HANDLE(anv_cmd_pool, pool, commandPool);
799 list_for_each_entry(struct anv_cmd_buffer, cmd_buffer,
800 &pool->cmd_buffers, pool_link) {
801 anv_cmd_buffer_reset(cmd_buffer);
807 void anv_TrimCommandPoolKHR(
809 VkCommandPool commandPool,
810 VkCommandPoolTrimFlagsKHR flags)
812 /* Nothing for us to do here. Our pools stay pretty tidy. */
816 * Return NULL if the current subpass has no depthstencil attachment.
818 const struct anv_image_view *
819 anv_cmd_buffer_get_depth_stencil_view(const struct anv_cmd_buffer *cmd_buffer)
821 const struct anv_subpass *subpass = cmd_buffer->state.subpass;
822 const struct anv_framebuffer *fb = cmd_buffer->state.framebuffer;
824 if (subpass->depth_stencil_attachment.attachment == VK_ATTACHMENT_UNUSED)
827 const struct anv_image_view *iview =
828 fb->attachments[subpass->depth_stencil_attachment.attachment];
830 assert(iview->aspect_mask & (VK_IMAGE_ASPECT_DEPTH_BIT |
831 VK_IMAGE_ASPECT_STENCIL_BIT));
837 anv_cmd_buffer_ensure_push_descriptor_set(struct anv_cmd_buffer *cmd_buffer,
840 struct anv_push_descriptor_set **push_set =
841 &cmd_buffer->state.push_descriptors[set];
843 if (*push_set == NULL) {
844 *push_set = vk_alloc(&cmd_buffer->pool->alloc,
845 sizeof(struct anv_push_descriptor_set), 8,
846 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
847 if (*push_set == NULL) {
848 anv_batch_set_error(&cmd_buffer->batch, VK_ERROR_OUT_OF_HOST_MEMORY);
849 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
856 void anv_CmdPushDescriptorSetKHR(
857 VkCommandBuffer commandBuffer,
858 VkPipelineBindPoint pipelineBindPoint,
859 VkPipelineLayout _layout,
861 uint32_t descriptorWriteCount,
862 const VkWriteDescriptorSet* pDescriptorWrites)
864 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
865 ANV_FROM_HANDLE(anv_pipeline_layout, layout, _layout);
867 assert(pipelineBindPoint == VK_PIPELINE_BIND_POINT_GRAPHICS ||
868 pipelineBindPoint == VK_PIPELINE_BIND_POINT_COMPUTE);
869 assert(_set < MAX_SETS);
871 const struct anv_descriptor_set_layout *set_layout =
872 layout->set[_set].layout;
874 if (anv_cmd_buffer_ensure_push_descriptor_set(cmd_buffer, _set) != VK_SUCCESS)
876 struct anv_push_descriptor_set *push_set =
877 cmd_buffer->state.push_descriptors[_set];
878 struct anv_descriptor_set *set = &push_set->set;
880 set->layout = set_layout;
881 set->size = anv_descriptor_set_layout_size(set_layout);
882 set->buffer_count = set_layout->buffer_count;
883 set->buffer_views = push_set->buffer_views;
885 /* Go through the user supplied descriptors. */
886 for (uint32_t i = 0; i < descriptorWriteCount; i++) {
887 const VkWriteDescriptorSet *write = &pDescriptorWrites[i];
889 switch (write->descriptorType) {
890 case VK_DESCRIPTOR_TYPE_SAMPLER:
891 case VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER:
892 case VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE:
893 case VK_DESCRIPTOR_TYPE_STORAGE_IMAGE:
894 case VK_DESCRIPTOR_TYPE_INPUT_ATTACHMENT:
895 for (uint32_t j = 0; j < write->descriptorCount; j++) {
896 anv_descriptor_set_write_image_view(set, &cmd_buffer->device->info,
897 write->pImageInfo + j,
898 write->descriptorType,
900 write->dstArrayElement + j);
904 case VK_DESCRIPTOR_TYPE_UNIFORM_TEXEL_BUFFER:
905 case VK_DESCRIPTOR_TYPE_STORAGE_TEXEL_BUFFER:
906 for (uint32_t j = 0; j < write->descriptorCount; j++) {
907 ANV_FROM_HANDLE(anv_buffer_view, bview,
908 write->pTexelBufferView[j]);
910 anv_descriptor_set_write_buffer_view(set,
911 write->descriptorType,
914 write->dstArrayElement + j);
918 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER:
919 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER:
920 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC:
921 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC:
922 for (uint32_t j = 0; j < write->descriptorCount; j++) {
923 assert(write->pBufferInfo[j].buffer);
924 ANV_FROM_HANDLE(anv_buffer, buffer, write->pBufferInfo[j].buffer);
927 anv_descriptor_set_write_buffer(set,
929 &cmd_buffer->surface_state_stream,
930 write->descriptorType,
933 write->dstArrayElement + j,
934 write->pBufferInfo[j].offset,
935 write->pBufferInfo[j].range);
944 cmd_buffer->state.descriptors[_set] = set;
945 cmd_buffer->state.descriptors_dirty |= set_layout->shader_stages;
948 void anv_CmdPushDescriptorSetWithTemplateKHR(
949 VkCommandBuffer commandBuffer,
950 VkDescriptorUpdateTemplateKHR descriptorUpdateTemplate,
951 VkPipelineLayout _layout,
955 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
956 ANV_FROM_HANDLE(anv_descriptor_update_template, template,
957 descriptorUpdateTemplate);
958 ANV_FROM_HANDLE(anv_pipeline_layout, layout, _layout);
960 assert(_set < MAX_PUSH_DESCRIPTORS);
962 const struct anv_descriptor_set_layout *set_layout =
963 layout->set[_set].layout;
965 if (anv_cmd_buffer_ensure_push_descriptor_set(cmd_buffer, _set) != VK_SUCCESS)
967 struct anv_push_descriptor_set *push_set =
968 cmd_buffer->state.push_descriptors[_set];
969 struct anv_descriptor_set *set = &push_set->set;
971 set->layout = set_layout;
972 set->size = anv_descriptor_set_layout_size(set_layout);
973 set->buffer_count = set_layout->buffer_count;
974 set->buffer_views = push_set->buffer_views;
976 anv_descriptor_set_write_template(set,
978 &cmd_buffer->surface_state_stream,
982 cmd_buffer->state.descriptors[_set] = set;
983 cmd_buffer->state.descriptors_dirty |= set_layout->shader_stages;