2 * Copyright © 2016 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 #include "nir/nir_builder.h"
27 enum blit2d_src_type {
28 /* We can make a "normal" image view of this source and just texture
29 * from it like you would in any other shader.
31 BLIT2D_SRC_TYPE_NORMAL,
33 /* The source is W-tiled and we need to detile manually in the shader.
34 * This will work on any platform but is needed for all W-tiled sources
37 BLIT2D_SRC_TYPE_W_DETILE,
42 enum blit2d_dst_type {
43 /* We can bind this destination as a "normal" render target and render
44 * to it just like you would anywhere else.
46 BLIT2D_DST_TYPE_NORMAL,
48 /* The destination is W-tiled and we need to do the tiling manually in
49 * the shader. This is required for all W-tiled destinations.
51 * Sky Lake adds a feature for providing explicit stencil values in the
52 * shader but mesa doesn't support that yet so neither do we.
54 BLIT2D_DST_TYPE_W_TILE,
56 /* The destination has a 3-channel RGB format. Since we can't render to
57 * non-power-of-two textures, we have to bind it as a red texture and
58 * select the correct component for the given red pixel in the shader.
66 vk_format_for_size(int bs)
68 /* The choice of UNORM and UINT formats is very intentional here. Most of
69 * the time, we want to use a UINT format to avoid any rounding error in
70 * the blit. For stencil blits, R8_UINT is required by the hardware.
71 * (It's the only format allowed in conjunction with W-tiling.) Also we
72 * intentionally use the 4-channel formats whenever we can. This is so
73 * that, when we do a RGB <-> RGBX copy, the two formats will line up even
74 * though one of them is 3/4 the size of the other. The choice of UNORM
75 * vs. UINT is also very intentional because Haswell doesn't handle 8 or
76 * 16-bit RGB UINT formats at all so we have to use UNORM there.
77 * Fortunately, the only time we should ever use two different formats in
78 * the table below is for RGB -> RGBA blits and so we will never have any
79 * UNORM/UINT mismatch.
82 case 1: return VK_FORMAT_R8_UINT;
83 case 2: return VK_FORMAT_R8G8_UINT;
84 case 3: return VK_FORMAT_R8G8B8_UNORM;
85 case 4: return VK_FORMAT_R8G8B8A8_UNORM;
86 case 6: return VK_FORMAT_R16G16B16_UNORM;
87 case 8: return VK_FORMAT_R16G16B16A16_UNORM;
88 case 12: return VK_FORMAT_R32G32B32_UINT;
89 case 16: return VK_FORMAT_R32G32B32A32_UINT;
91 unreachable("Invalid format block size");
96 create_iview(struct anv_cmd_buffer *cmd_buffer,
97 struct anv_meta_blit2d_surf *surf,
99 VkImageUsageFlags usage,
103 struct anv_image_view *iview)
105 const VkImageCreateInfo image_info = {
106 .sType = VK_STRUCTURE_TYPE_IMAGE_CREATE_INFO,
107 .imageType = VK_IMAGE_TYPE_2D,
108 .format = vk_format_for_size(surf->bs),
117 .tiling = surf->tiling == ISL_TILING_LINEAR ?
118 VK_IMAGE_TILING_LINEAR : VK_IMAGE_TILING_OPTIMAL,
122 /* Create the VkImage that is bound to the surface's memory. */
123 anv_image_create(anv_device_to_handle(cmd_buffer->device),
124 &(struct anv_image_create_info) {
125 .vk_info = &image_info,
126 .isl_tiling_flags = 1 << surf->tiling,
127 .stride = surf->pitch,
128 }, &cmd_buffer->pool->alloc, img);
130 /* We could use a vk call to bind memory, but that would require
131 * creating a dummy memory object etc. so there's really no point.
133 anv_image_from_handle(*img)->bo = surf->bo;
134 anv_image_from_handle(*img)->offset = surf->base_offset + offset;
136 anv_image_view_init(iview, cmd_buffer->device,
137 &(VkImageViewCreateInfo) {
138 .sType = VK_STRUCTURE_TYPE_IMAGE_VIEW_CREATE_INFO,
140 .viewType = VK_IMAGE_VIEW_TYPE_2D,
141 .format = image_info.format,
142 .subresourceRange = {
143 .aspectMask = VK_IMAGE_ASPECT_COLOR_BIT,
149 }, cmd_buffer, usage);
152 struct blit2d_src_temps {
154 struct anv_image_view iview;
156 struct anv_buffer buffer;
157 struct anv_buffer_view bview;
159 VkDescriptorPool desc_pool;
164 blit2d_bind_src(struct anv_cmd_buffer *cmd_buffer,
165 struct anv_meta_blit2d_surf *src,
166 enum blit2d_src_type src_type,
167 struct anv_meta_blit2d_rect *rect,
168 struct blit2d_src_temps *tmp)
170 struct anv_device *device = cmd_buffer->device;
171 VkDevice vk_device = anv_device_to_handle(cmd_buffer->device);
173 if (src_type == BLIT2D_SRC_TYPE_NORMAL) {
175 isl_tiling_get_intratile_offset_el(&cmd_buffer->device->isl_dev,
176 src->tiling, src->bs, src->pitch,
177 rect->src_x, rect->src_y,
178 &offset, &rect->src_x, &rect->src_y);
180 create_iview(cmd_buffer, src, offset, VK_IMAGE_USAGE_SAMPLED_BIT,
181 rect->src_x + rect->width, rect->src_y + rect->height,
182 &tmp->image, &tmp->iview);
184 anv_CreateDescriptorPool(vk_device,
185 &(const VkDescriptorPoolCreateInfo) {
186 .sType = VK_STRUCTURE_TYPE_DESCRIPTOR_POOL_CREATE_INFO,
191 .pPoolSizes = (VkDescriptorPoolSize[]) {
193 .type = VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE,
197 }, &cmd_buffer->pool->alloc, &tmp->desc_pool);
199 anv_AllocateDescriptorSets(vk_device,
200 &(VkDescriptorSetAllocateInfo) {
201 .sType = VK_STRUCTURE_TYPE_DESCRIPTOR_SET_ALLOCATE_INFO,
202 .descriptorPool = tmp->desc_pool,
203 .descriptorSetCount = 1,
204 .pSetLayouts = &device->meta_state.blit2d.img_ds_layout
207 anv_UpdateDescriptorSets(vk_device,
209 (VkWriteDescriptorSet[]) {
211 .sType = VK_STRUCTURE_TYPE_WRITE_DESCRIPTOR_SET,
214 .dstArrayElement = 0,
215 .descriptorCount = 1,
216 .descriptorType = VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE,
217 .pImageInfo = (VkDescriptorImageInfo[]) {
220 .imageView = anv_image_view_to_handle(&tmp->iview),
221 .imageLayout = VK_IMAGE_LAYOUT_GENERAL,
227 anv_CmdBindDescriptorSets(anv_cmd_buffer_to_handle(cmd_buffer),
228 VK_PIPELINE_BIND_POINT_GRAPHICS,
229 device->meta_state.blit2d.img_p_layout, 0, 1,
232 assert(src_type == BLIT2D_SRC_TYPE_W_DETILE);
233 assert(src->tiling == ISL_TILING_W);
234 assert(src->bs == 1);
236 uint32_t tile_offset = 0;
237 isl_tiling_get_intratile_offset_el(&cmd_buffer->device->isl_dev,
238 ISL_TILING_W, 1, src->pitch,
239 rect->src_x, rect->src_y,
241 &rect->src_x, &rect->src_y);
243 tmp->buffer = (struct anv_buffer) {
245 .size = align_u32(rect->src_y + rect->height, 64) * src->pitch,
246 .usage = VK_BUFFER_USAGE_UNIFORM_TEXEL_BUFFER_BIT,
248 .offset = src->base_offset + tile_offset,
251 anv_buffer_view_init(&tmp->bview, device,
252 &(VkBufferViewCreateInfo) {
253 .sType = VK_STRUCTURE_TYPE_BUFFER_VIEW_CREATE_INFO,
254 .buffer = anv_buffer_to_handle(&tmp->buffer),
255 .format = VK_FORMAT_R8_UINT,
257 .range = VK_WHOLE_SIZE,
260 anv_CreateDescriptorPool(vk_device,
261 &(const VkDescriptorPoolCreateInfo) {
262 .sType = VK_STRUCTURE_TYPE_DESCRIPTOR_POOL_CREATE_INFO,
267 .pPoolSizes = (VkDescriptorPoolSize[]) {
269 .type = VK_DESCRIPTOR_TYPE_UNIFORM_TEXEL_BUFFER,
273 }, &cmd_buffer->pool->alloc, &tmp->desc_pool);
275 anv_AllocateDescriptorSets(vk_device,
276 &(VkDescriptorSetAllocateInfo) {
277 .sType = VK_STRUCTURE_TYPE_DESCRIPTOR_SET_ALLOCATE_INFO,
278 .descriptorPool = tmp->desc_pool,
279 .descriptorSetCount = 1,
280 .pSetLayouts = &device->meta_state.blit2d.buf_ds_layout
283 anv_UpdateDescriptorSets(vk_device,
285 (VkWriteDescriptorSet[]) {
287 .sType = VK_STRUCTURE_TYPE_WRITE_DESCRIPTOR_SET,
290 .dstArrayElement = 0,
291 .descriptorCount = 1,
292 .descriptorType = VK_DESCRIPTOR_TYPE_UNIFORM_TEXEL_BUFFER,
293 .pTexelBufferView = (VkBufferView[]) {
294 anv_buffer_view_to_handle(&tmp->bview),
299 anv_CmdBindDescriptorSets(anv_cmd_buffer_to_handle(cmd_buffer),
300 VK_PIPELINE_BIND_POINT_GRAPHICS,
301 device->meta_state.blit2d.buf_p_layout, 0, 1,
307 blit2d_unbind_src(struct anv_cmd_buffer *cmd_buffer,
308 enum blit2d_src_type src_type,
309 struct blit2d_src_temps *tmp)
311 anv_DestroyDescriptorPool(anv_device_to_handle(cmd_buffer->device),
312 tmp->desc_pool, &cmd_buffer->pool->alloc);
313 if (src_type == BLIT2D_SRC_TYPE_NORMAL) {
314 anv_DestroyImage(anv_device_to_handle(cmd_buffer->device),
315 tmp->image, &cmd_buffer->pool->alloc);
319 struct blit2d_dst_temps {
321 struct anv_image_view iview;
326 blit2d_bind_dst(struct anv_cmd_buffer *cmd_buffer,
327 struct anv_meta_blit2d_surf *dst,
331 struct blit2d_dst_temps *tmp)
333 create_iview(cmd_buffer, dst, offset, VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT,
334 width, height, &tmp->image, &tmp->iview);
336 anv_CreateFramebuffer(anv_device_to_handle(cmd_buffer->device),
337 &(VkFramebufferCreateInfo) {
338 .sType = VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO,
339 .attachmentCount = 1,
340 .pAttachments = (VkImageView[]) {
341 anv_image_view_to_handle(&tmp->iview),
346 }, &cmd_buffer->pool->alloc, &tmp->fb);
350 blit2d_unbind_dst(struct anv_cmd_buffer *cmd_buffer,
351 struct blit2d_dst_temps *tmp)
353 VkDevice vk_device = anv_device_to_handle(cmd_buffer->device);
354 anv_DestroyFramebuffer(vk_device, tmp->fb, &cmd_buffer->pool->alloc);
355 anv_DestroyImage(vk_device, tmp->image, &cmd_buffer->pool->alloc);
359 anv_meta_end_blit2d(struct anv_cmd_buffer *cmd_buffer,
360 struct anv_meta_saved_state *save)
362 anv_meta_restore(save, cmd_buffer);
366 anv_meta_begin_blit2d(struct anv_cmd_buffer *cmd_buffer,
367 struct anv_meta_saved_state *save)
369 anv_meta_save(save, cmd_buffer, 0);
373 bind_pipeline(struct anv_cmd_buffer *cmd_buffer,
374 enum blit2d_src_type src_type,
375 enum blit2d_dst_type dst_type)
377 VkPipeline pipeline =
378 cmd_buffer->device->meta_state.blit2d.pipelines[src_type][dst_type];
380 if (cmd_buffer->state.pipeline != anv_pipeline_from_handle(pipeline)) {
381 anv_CmdBindPipeline(anv_cmd_buffer_to_handle(cmd_buffer),
382 VK_PIPELINE_BIND_POINT_GRAPHICS, pipeline);
387 anv_meta_blit2d_normal_dst(struct anv_cmd_buffer *cmd_buffer,
388 struct anv_meta_blit2d_surf *src,
389 enum blit2d_src_type src_type,
390 struct anv_meta_blit2d_surf *dst,
392 struct anv_meta_blit2d_rect *rects)
394 struct anv_device *device = cmd_buffer->device;
396 for (unsigned r = 0; r < num_rects; ++r) {
397 struct blit2d_src_temps src_temps;
398 blit2d_bind_src(cmd_buffer, src, src_type, &rects[r], &src_temps);
401 isl_tiling_get_intratile_offset_el(&cmd_buffer->device->isl_dev,
402 dst->tiling, dst->bs, dst->pitch,
403 rects[r].dst_x, rects[r].dst_y,
405 &rects[r].dst_x, &rects[r].dst_y);
407 struct blit2d_dst_temps dst_temps;
408 blit2d_bind_dst(cmd_buffer, dst, offset, rects[r].dst_x + rects[r].width,
409 rects[r].dst_y + rects[r].height, &dst_temps);
411 struct blit_vb_data {
416 unsigned vb_size = sizeof(struct anv_vue_header) + 3 * sizeof(*vb_data);
418 struct anv_state vb_state =
419 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer, vb_size, 16);
420 memset(vb_state.map, 0, sizeof(struct anv_vue_header));
421 vb_data = vb_state.map + sizeof(struct anv_vue_header);
423 vb_data[0] = (struct blit_vb_data) {
425 rects[r].dst_x + rects[r].width,
426 rects[r].dst_y + rects[r].height,
429 rects[r].src_x + rects[r].width,
430 rects[r].src_y + rects[r].height,
435 vb_data[1] = (struct blit_vb_data) {
438 rects[r].dst_y + rects[r].height,
442 rects[r].src_y + rects[r].height,
447 vb_data[2] = (struct blit_vb_data) {
459 if (!device->info.has_llc)
460 anv_state_clflush(vb_state);
462 struct anv_buffer vertex_buffer = {
465 .bo = &device->dynamic_state_block_pool.bo,
466 .offset = vb_state.offset,
469 anv_CmdBindVertexBuffers(anv_cmd_buffer_to_handle(cmd_buffer), 0, 2,
471 anv_buffer_to_handle(&vertex_buffer),
472 anv_buffer_to_handle(&vertex_buffer)
476 sizeof(struct anv_vue_header),
479 ANV_CALL(CmdBeginRenderPass)(anv_cmd_buffer_to_handle(cmd_buffer),
480 &(VkRenderPassBeginInfo) {
481 .sType = VK_STRUCTURE_TYPE_RENDER_PASS_BEGIN_INFO,
482 .renderPass = device->meta_state.blit2d.render_pass,
483 .framebuffer = dst_temps.fb,
485 .offset = { rects[r].dst_x, rects[r].dst_y, },
486 .extent = { rects[r].width, rects[r].height },
488 .clearValueCount = 0,
489 .pClearValues = NULL,
490 }, VK_SUBPASS_CONTENTS_INLINE);
492 bind_pipeline(cmd_buffer, src_type, BLIT2D_DST_TYPE_NORMAL);
494 ANV_CALL(CmdDraw)(anv_cmd_buffer_to_handle(cmd_buffer), 3, 1, 0, 0);
496 ANV_CALL(CmdEndRenderPass)(anv_cmd_buffer_to_handle(cmd_buffer));
498 /* At the point where we emit the draw call, all data from the
499 * descriptor sets, etc. has been used. We are free to delete it.
501 blit2d_unbind_src(cmd_buffer, src_type, &src_temps);
502 blit2d_unbind_dst(cmd_buffer, &dst_temps);
507 anv_meta_blit2d_w_tiled_dst(struct anv_cmd_buffer *cmd_buffer,
508 struct anv_meta_blit2d_surf *src,
509 enum blit2d_src_type src_type,
510 struct anv_meta_blit2d_surf *dst,
512 struct anv_meta_blit2d_rect *rects)
514 struct anv_device *device = cmd_buffer->device;
516 for (unsigned r = 0; r < num_rects; ++r) {
517 struct blit2d_src_temps src_temps;
518 blit2d_bind_src(cmd_buffer, src, src_type, &rects[r], &src_temps);
520 assert(dst->bs == 1);
522 isl_tiling_get_intratile_offset_el(&cmd_buffer->device->isl_dev,
523 ISL_TILING_W, 1, dst->pitch,
524 rects[r].dst_x, rects[r].dst_y,
526 &rects[r].dst_x, &rects[r].dst_y);
528 /* The original coordinates were in terms of an actual W-tiled offset
529 * but we are binding this image as Y-tiled. We need to adjust our
530 * rectangle accordingly.
532 uint32_t xmin_Y, xmax_Y, ymin_Y, ymax_Y;
533 xmin_Y = (rects[r].dst_x / 8) * 16;
534 xmax_Y = DIV_ROUND_UP(rects[r].dst_x + rects[r].width, 8) * 16;
535 ymin_Y = (rects[r].dst_y / 4) * 2;
536 ymax_Y = DIV_ROUND_UP(rects[r].dst_y + rects[r].height, 4) * 2;
538 struct anv_meta_blit2d_surf dst_Y = {
540 .tiling = ISL_TILING_Y0,
541 .base_offset = dst->base_offset,
543 .pitch = dst->pitch * 2,
546 struct blit2d_dst_temps dst_temps;
547 blit2d_bind_dst(cmd_buffer, &dst_Y, offset, xmax_Y, ymax_Y, &dst_temps);
549 struct blit_vb_header {
550 struct anv_vue_header vue;
551 int32_t tex_offset[2];
556 struct blit_vb_data {
560 unsigned vb_size = sizeof(*vb_header) + 3 * sizeof(*vb_data);
562 struct anv_state vb_state =
563 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer, vb_size, 16);
564 vb_header = vb_state.map;
566 *vb_header = (struct blit_vb_header) {
568 rects[r].src_x - rects[r].dst_x,
569 rects[r].src_y - rects[r].dst_y,
571 .tex_pitch = src->pitch,
575 rects[r].dst_x + rects[r].width,
576 rects[r].dst_y + rects[r].height,
580 vb_data = (void *)(vb_header + 1);
582 vb_data[0] = (struct blit_vb_data) {
589 vb_data[1] = (struct blit_vb_data) {
596 vb_data[2] = (struct blit_vb_data) {
603 if (!device->info.has_llc)
604 anv_state_clflush(vb_state);
606 struct anv_buffer vertex_buffer = {
609 .bo = &device->dynamic_state_block_pool.bo,
610 .offset = vb_state.offset,
613 anv_CmdBindVertexBuffers(anv_cmd_buffer_to_handle(cmd_buffer), 0, 2,
615 anv_buffer_to_handle(&vertex_buffer),
616 anv_buffer_to_handle(&vertex_buffer)
620 (void *)vb_data - vb_state.map,
623 ANV_CALL(CmdBeginRenderPass)(anv_cmd_buffer_to_handle(cmd_buffer),
624 &(VkRenderPassBeginInfo) {
625 .sType = VK_STRUCTURE_TYPE_RENDER_PASS_BEGIN_INFO,
626 .renderPass = device->meta_state.blit2d.render_pass,
627 .framebuffer = dst_temps.fb,
629 .offset = { xmin_Y, ymin_Y, },
630 .extent = { xmax_Y - xmin_Y, ymax_Y - ymin_Y },
632 .clearValueCount = 0,
633 .pClearValues = NULL,
634 }, VK_SUBPASS_CONTENTS_INLINE);
636 bind_pipeline(cmd_buffer, src_type, BLIT2D_DST_TYPE_W_TILE);
638 ANV_CALL(CmdDraw)(anv_cmd_buffer_to_handle(cmd_buffer), 3, 1, 0, 0);
640 ANV_CALL(CmdEndRenderPass)(anv_cmd_buffer_to_handle(cmd_buffer));
642 /* At the point where we emit the draw call, all data from the
643 * descriptor sets, etc. has been used. We are free to delete it.
645 blit2d_unbind_src(cmd_buffer, src_type, &src_temps);
646 blit2d_unbind_dst(cmd_buffer, &dst_temps);
651 anv_meta_blit2d(struct anv_cmd_buffer *cmd_buffer,
652 struct anv_meta_blit2d_surf *src,
653 struct anv_meta_blit2d_surf *dst,
655 struct anv_meta_blit2d_rect *rects)
657 enum blit2d_src_type src_type;
658 if (src->tiling == ISL_TILING_W && cmd_buffer->device->info.gen < 8) {
659 src_type = BLIT2D_SRC_TYPE_W_DETILE;
661 src_type = BLIT2D_SRC_TYPE_NORMAL;
664 if (dst->tiling == ISL_TILING_W) {
665 anv_meta_blit2d_w_tiled_dst(cmd_buffer, src, src_type, dst,
668 } else if (dst->bs % 3 == 0) {
669 anv_finishme("Blitting to RGB destinations not yet supported");
672 assert(util_is_power_of_two(dst->bs));
673 anv_meta_blit2d_normal_dst(cmd_buffer, src, src_type, dst,
679 build_nir_vertex_shader(void)
681 const struct glsl_type *vec4 = glsl_vec4_type();
684 nir_builder_init_simple_shader(&b, NULL, MESA_SHADER_VERTEX, NULL);
685 b.shader->info.name = ralloc_strdup(b.shader, "meta_blit_vs");
687 nir_variable *pos_in = nir_variable_create(b.shader, nir_var_shader_in,
689 pos_in->data.location = VERT_ATTRIB_GENERIC0;
690 nir_variable *pos_out = nir_variable_create(b.shader, nir_var_shader_out,
691 vec4, "gl_Position");
692 pos_out->data.location = VARYING_SLOT_POS;
693 nir_copy_var(&b, pos_out, pos_in);
695 nir_variable *tex_pos_in = nir_variable_create(b.shader, nir_var_shader_in,
697 tex_pos_in->data.location = VERT_ATTRIB_GENERIC1;
698 nir_variable *tex_pos_out = nir_variable_create(b.shader, nir_var_shader_out,
700 tex_pos_out->data.location = VARYING_SLOT_VAR0;
701 tex_pos_out->data.interpolation = INTERP_QUALIFIER_SMOOTH;
702 nir_copy_var(&b, tex_pos_out, tex_pos_in);
704 nir_variable *other_in = nir_variable_create(b.shader, nir_var_shader_in,
706 other_in->data.location = VERT_ATTRIB_GENERIC2;
707 nir_variable *other_out = nir_variable_create(b.shader, nir_var_shader_out,
709 other_out->data.location = VARYING_SLOT_VAR1;
710 other_out->data.interpolation = INTERP_QUALIFIER_FLAT;
711 nir_copy_var(&b, other_out, other_in);
716 typedef nir_ssa_def* (*texel_fetch_build_func)(struct nir_builder *,
718 nir_ssa_def *, nir_ssa_def *);
721 nir_copy_bits(struct nir_builder *b, nir_ssa_def *dst, unsigned dst_offset,
722 nir_ssa_def *src, unsigned src_offset, unsigned num_bits)
724 unsigned src_mask = (~1u >> (32 - num_bits)) << src_offset;
725 nir_ssa_def *masked = nir_iand(b, src, nir_imm_int(b, src_mask));
727 nir_ssa_def *shifted;
728 if (dst_offset > src_offset) {
729 shifted = nir_ishl(b, masked, nir_imm_int(b, dst_offset - src_offset));
730 } else if (dst_offset < src_offset) {
731 shifted = nir_ushr(b, masked, nir_imm_int(b, src_offset - dst_offset));
733 assert(dst_offset == src_offset);
737 return nir_ior(b, dst, shifted);
741 build_nir_w_tiled_fetch(struct nir_builder *b, struct anv_device *device,
742 nir_ssa_def *tex_pos, nir_ssa_def *tex_pitch)
744 nir_ssa_def *x = nir_channel(b, tex_pos, 0);
745 nir_ssa_def *y = nir_channel(b, tex_pos, 1);
747 /* First, compute the block-aligned offset */
748 nir_ssa_def *x_major = nir_ushr(b, x, nir_imm_int(b, 6));
749 nir_ssa_def *y_major = nir_ushr(b, y, nir_imm_int(b, 6));
750 nir_ssa_def *offset =
751 nir_iadd(b, nir_imul(b, y_major,
752 nir_imul(b, tex_pitch, nir_imm_int(b, 64))),
753 nir_imul(b, x_major, nir_imm_int(b, 4096)));
755 /* Compute the bottom 12 bits of the offset */
756 offset = nir_copy_bits(b, offset, 0, x, 0, 1);
757 offset = nir_copy_bits(b, offset, 1, y, 0, 1);
758 offset = nir_copy_bits(b, offset, 2, x, 1, 1);
759 offset = nir_copy_bits(b, offset, 3, y, 1, 1);
760 offset = nir_copy_bits(b, offset, 4, x, 2, 1);
761 offset = nir_copy_bits(b, offset, 5, y, 2, 4);
762 offset = nir_copy_bits(b, offset, 9, x, 3, 3);
764 if (device->isl_dev.has_bit6_swizzling) {
765 offset = nir_ixor(b, offset,
766 nir_ushr(b, nir_iand(b, offset, nir_imm_int(b, 0x0200)),
770 const struct glsl_type *sampler_type =
771 glsl_sampler_type(GLSL_SAMPLER_DIM_BUF, false, false, GLSL_TYPE_FLOAT);
772 nir_variable *sampler = nir_variable_create(b->shader, nir_var_uniform,
773 sampler_type, "s_tex");
774 sampler->data.descriptor_set = 0;
775 sampler->data.binding = 0;
777 nir_tex_instr *tex = nir_tex_instr_create(b->shader, 1);
778 tex->sampler_dim = GLSL_SAMPLER_DIM_BUF;
779 tex->op = nir_texop_txf;
780 tex->src[0].src_type = nir_tex_src_coord;
781 tex->src[0].src = nir_src_for_ssa(offset);
782 tex->dest_type = nir_type_float; /* TODO */
783 tex->is_array = false;
784 tex->coord_components = 1;
785 tex->texture = nir_deref_var_create(tex, sampler);
788 nir_ssa_dest_init(&tex->instr, &tex->dest, 4, 32, "tex");
789 nir_builder_instr_insert(b, &tex->instr);
791 return &tex->dest.ssa;
795 build_nir_texel_fetch(struct nir_builder *b, struct anv_device *device,
796 nir_ssa_def *tex_pos, nir_ssa_def *tex_pitch)
798 const struct glsl_type *sampler_type =
799 glsl_sampler_type(GLSL_SAMPLER_DIM_2D, false, false, GLSL_TYPE_FLOAT);
800 nir_variable *sampler = nir_variable_create(b->shader, nir_var_uniform,
801 sampler_type, "s_tex");
802 sampler->data.descriptor_set = 0;
803 sampler->data.binding = 0;
805 nir_tex_instr *tex = nir_tex_instr_create(b->shader, 2);
806 tex->sampler_dim = GLSL_SAMPLER_DIM_2D;
807 tex->op = nir_texop_txf;
808 tex->src[0].src_type = nir_tex_src_coord;
809 tex->src[0].src = nir_src_for_ssa(tex_pos);
810 tex->src[1].src_type = nir_tex_src_lod;
811 tex->src[1].src = nir_src_for_ssa(nir_imm_int(b, 0));
812 tex->dest_type = nir_type_float; /* TODO */
813 tex->is_array = false;
814 tex->coord_components = 2;
815 tex->texture = nir_deref_var_create(tex, sampler);
818 nir_ssa_dest_init(&tex->instr, &tex->dest, 4, 32, "tex");
819 nir_builder_instr_insert(b, &tex->instr);
821 return &tex->dest.ssa;
824 static const VkPipelineVertexInputStateCreateInfo normal_vi_create_info = {
825 .sType = VK_STRUCTURE_TYPE_PIPELINE_VERTEX_INPUT_STATE_CREATE_INFO,
826 .vertexBindingDescriptionCount = 2,
827 .pVertexBindingDescriptions = (VkVertexInputBindingDescription[]) {
831 .inputRate = VK_VERTEX_INPUT_RATE_INSTANCE
835 .stride = 5 * sizeof(float),
836 .inputRate = VK_VERTEX_INPUT_RATE_VERTEX
839 .vertexAttributeDescriptionCount = 3,
840 .pVertexAttributeDescriptions = (VkVertexInputAttributeDescription[]) {
845 .format = VK_FORMAT_R32G32B32A32_UINT,
852 .format = VK_FORMAT_R32G32_SFLOAT,
856 /* Texture Coordinate */
859 .format = VK_FORMAT_R32G32B32_SFLOAT,
866 build_nir_copy_fragment_shader(struct anv_device *device,
867 texel_fetch_build_func txf_func)
869 const struct glsl_type *vec4 = glsl_vec4_type();
870 const struct glsl_type *vec3 = glsl_vector_type(GLSL_TYPE_FLOAT, 3);
873 nir_builder_init_simple_shader(&b, NULL, MESA_SHADER_FRAGMENT, NULL);
874 b.shader->info.name = ralloc_strdup(b.shader, "meta_blit2d_fs");
876 nir_variable *tex_pos_in = nir_variable_create(b.shader, nir_var_shader_in,
878 tex_pos_in->data.location = VARYING_SLOT_VAR0;
880 nir_variable *color_out = nir_variable_create(b.shader, nir_var_shader_out,
882 color_out->data.location = FRAG_RESULT_DATA0;
884 nir_ssa_def *pos_int = nir_f2i(&b, nir_load_var(&b, tex_pos_in));
885 unsigned swiz[4] = { 0, 1 };
886 nir_ssa_def *tex_pos = nir_swizzle(&b, pos_int, swiz, 2, false);
887 nir_ssa_def *tex_pitch = nir_channel(&b, pos_int, 2);
889 nir_ssa_def *color = txf_func(&b, device, tex_pos, tex_pitch);
890 nir_store_var(&b, color_out, color, 0xf);
895 static const VkPipelineVertexInputStateCreateInfo w_tiled_vi_create_info = {
896 .sType = VK_STRUCTURE_TYPE_PIPELINE_VERTEX_INPUT_STATE_CREATE_INFO,
897 .vertexBindingDescriptionCount = 2,
898 .pVertexBindingDescriptions = (VkVertexInputBindingDescription[]) {
902 .inputRate = VK_VERTEX_INPUT_RATE_INSTANCE
906 .stride = 2 * sizeof(float),
907 .inputRate = VK_VERTEX_INPUT_RATE_VERTEX
910 .vertexAttributeDescriptionCount = 4,
911 .pVertexAttributeDescriptions = (VkVertexInputAttributeDescription[]) {
916 .format = VK_FORMAT_R32G32B32A32_UINT,
923 .format = VK_FORMAT_R32G32_SFLOAT,
930 .format = VK_FORMAT_R32G32B32_UINT,
934 /* Destination bounds */
937 .format = VK_FORMAT_R32G32B32A32_UINT,
944 build_nir_w_tiled_fragment_shader(struct anv_device *device,
945 texel_fetch_build_func txf_func)
947 const struct glsl_type *vec4 = glsl_vec4_type();
948 const struct glsl_type *ivec3 = glsl_vector_type(GLSL_TYPE_INT, 3);
949 const struct glsl_type *uvec4 = glsl_vector_type(GLSL_TYPE_UINT, 4);
952 nir_builder_init_simple_shader(&b, NULL, MESA_SHADER_FRAGMENT, NULL);
953 b.shader->info.name = ralloc_strdup(b.shader, "meta_blit2d_fs");
955 /* We need gl_FragCoord so we know our Y-tiled position */
956 nir_variable *frag_coord_in = nir_variable_create(b.shader,
958 vec4, "gl_FragCoord");
959 frag_coord_in->data.location = VARYING_SLOT_POS;
960 frag_coord_in->data.origin_upper_left = true;
962 /* In location 0 we have an ivec3 that has the offset from dest to
963 * source in the first two components and the stride in the third.
965 nir_variable *tex_off_in = nir_variable_create(b.shader, nir_var_shader_in,
967 tex_off_in->data.location = VARYING_SLOT_VAR0;
968 tex_off_in->data.interpolation = INTERP_QUALIFIER_FLAT;
970 /* In location 1 we have a uvec4 that gives us the bounds of the
971 * destination. We need to discard if we get outside this boundary.
973 nir_variable *bounds_in = nir_variable_create(b.shader, nir_var_shader_in,
975 bounds_in->data.location = VARYING_SLOT_VAR1;
976 bounds_in->data.interpolation = INTERP_QUALIFIER_FLAT;
978 nir_variable *color_out = nir_variable_create(b.shader, nir_var_shader_out,
980 color_out->data.location = FRAG_RESULT_DATA0;
982 nir_ssa_def *frag_coord_int = nir_f2i(&b, nir_load_var(&b, frag_coord_in));
983 nir_ssa_def *x_Y = nir_channel(&b, frag_coord_int, 0);
984 nir_ssa_def *y_Y = nir_channel(&b, frag_coord_int, 1);
986 /* Compute the W-tiled position from the Y-tiled position */
987 nir_ssa_def *x_W = nir_iand(&b, x_Y, nir_imm_int(&b, 0xffffff80));
988 x_W = nir_ushr(&b, x_W, nir_imm_int(&b, 1));
989 x_W = nir_copy_bits(&b, x_W, 0, x_Y, 0, 1);
990 x_W = nir_copy_bits(&b, x_W, 1, x_Y, 2, 1);
991 x_W = nir_copy_bits(&b, x_W, 2, y_Y, 0, 1);
992 x_W = nir_copy_bits(&b, x_W, 3, x_Y, 4, 3);
994 nir_ssa_def *y_W = nir_iand(&b, y_Y, nir_imm_int(&b, 0xffffffe0));
995 y_W = nir_ishl(&b, y_W, nir_imm_int(&b, 1));
996 y_W = nir_copy_bits(&b, y_W, 0, x_Y, 1, 1);
997 y_W = nir_copy_bits(&b, y_W, 1, x_Y, 3, 1);
998 y_W = nir_copy_bits(&b, y_W, 2, y_Y, 1, 4);
1000 /* Figure out if we are out-of-bounds and discard */
1001 nir_ssa_def *bounds = nir_load_var(&b, bounds_in);
1003 nir_ior(&b, nir_ult(&b, x_W, nir_channel(&b, bounds, 0)),
1004 nir_ior(&b, nir_ult(&b, y_W, nir_channel(&b, bounds, 1)),
1005 nir_ior(&b, nir_uge(&b, x_W, nir_channel(&b, bounds, 2)),
1006 nir_uge(&b, y_W, nir_channel(&b, bounds, 3)))));
1008 nir_intrinsic_instr *discard =
1009 nir_intrinsic_instr_create(b.shader, nir_intrinsic_discard_if);
1010 discard->src[0] = nir_src_for_ssa(oob);
1011 nir_builder_instr_insert(&b, &discard->instr);
1013 unsigned swiz[4] = { 0, 1, 0, 0 };
1014 nir_ssa_def *tex_off =
1015 nir_swizzle(&b, nir_load_var(&b, tex_off_in), swiz, 2, false);
1016 nir_ssa_def *tex_pos = nir_iadd(&b, nir_vec2(&b, x_W, y_W), tex_off);
1017 nir_ssa_def *tex_pitch = nir_channel(&b, nir_load_var(&b, tex_off_in), 2);
1019 nir_ssa_def *color = txf_func(&b, device, tex_pos, tex_pitch);
1020 nir_store_var(&b, color_out, color, 0xf);
1026 anv_device_finish_meta_blit2d_state(struct anv_device *device)
1028 if (device->meta_state.blit2d.render_pass) {
1029 anv_DestroyRenderPass(anv_device_to_handle(device),
1030 device->meta_state.blit2d.render_pass,
1031 &device->meta_state.alloc);
1034 if (device->meta_state.blit2d.img_p_layout) {
1035 anv_DestroyPipelineLayout(anv_device_to_handle(device),
1036 device->meta_state.blit2d.img_p_layout,
1037 &device->meta_state.alloc);
1040 if (device->meta_state.blit2d.img_ds_layout) {
1041 anv_DestroyDescriptorSetLayout(anv_device_to_handle(device),
1042 device->meta_state.blit2d.img_ds_layout,
1043 &device->meta_state.alloc);
1046 if (device->meta_state.blit2d.buf_p_layout) {
1047 anv_DestroyPipelineLayout(anv_device_to_handle(device),
1048 device->meta_state.blit2d.buf_p_layout,
1049 &device->meta_state.alloc);
1052 if (device->meta_state.blit2d.buf_ds_layout) {
1053 anv_DestroyDescriptorSetLayout(anv_device_to_handle(device),
1054 device->meta_state.blit2d.buf_ds_layout,
1055 &device->meta_state.alloc);
1058 for (unsigned src = 0; src < BLIT2D_NUM_SRC_TYPES; src++) {
1059 for (unsigned dst = 0; dst < BLIT2D_NUM_DST_TYPES; dst++) {
1060 if (device->meta_state.blit2d.pipelines[src][dst]) {
1061 anv_DestroyPipeline(anv_device_to_handle(device),
1062 device->meta_state.blit2d.pipelines[src][dst],
1063 &device->meta_state.alloc);
1070 blit2d_init_pipeline(struct anv_device *device,
1071 enum blit2d_src_type src_type,
1072 enum blit2d_dst_type dst_type)
1076 texel_fetch_build_func src_func;
1078 case BLIT2D_SRC_TYPE_NORMAL:
1079 src_func = build_nir_texel_fetch;
1081 case BLIT2D_SRC_TYPE_W_DETILE:
1082 src_func = build_nir_w_tiled_fetch;
1085 unreachable("Invalid blit2d source type");
1088 const VkPipelineVertexInputStateCreateInfo *vi_create_info;
1089 struct anv_shader_module fs = { .nir = NULL };
1091 case BLIT2D_DST_TYPE_NORMAL:
1092 fs.nir = build_nir_copy_fragment_shader(device, src_func);
1093 vi_create_info = &normal_vi_create_info;
1095 case BLIT2D_DST_TYPE_W_TILE:
1096 fs.nir = build_nir_w_tiled_fragment_shader(device, src_func);
1097 vi_create_info = &w_tiled_vi_create_info;
1099 case BLIT2D_DST_TYPE_RGB:
1100 /* Not yet supported */
1105 /* We don't use a vertex shader for blitting, but instead build and pass
1106 * the VUEs directly to the rasterization backend. However, we do need
1107 * to provide GLSL source for the vertex shader so that the compiler
1108 * does not dead-code our inputs.
1110 struct anv_shader_module vs = {
1111 .nir = build_nir_vertex_shader(),
1114 VkPipelineShaderStageCreateInfo pipeline_shader_stages[] = {
1116 .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
1117 .stage = VK_SHADER_STAGE_VERTEX_BIT,
1118 .module = anv_shader_module_to_handle(&vs),
1120 .pSpecializationInfo = NULL
1122 .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
1123 .stage = VK_SHADER_STAGE_FRAGMENT_BIT,
1124 .module = anv_shader_module_to_handle(&fs),
1126 .pSpecializationInfo = NULL
1130 const VkGraphicsPipelineCreateInfo vk_pipeline_info = {
1131 .sType = VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO,
1132 .stageCount = ARRAY_SIZE(pipeline_shader_stages),
1133 .pStages = pipeline_shader_stages,
1134 .pVertexInputState = vi_create_info,
1135 .pInputAssemblyState = &(VkPipelineInputAssemblyStateCreateInfo) {
1136 .sType = VK_STRUCTURE_TYPE_PIPELINE_INPUT_ASSEMBLY_STATE_CREATE_INFO,
1137 .topology = VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP,
1138 .primitiveRestartEnable = false,
1140 .pViewportState = &(VkPipelineViewportStateCreateInfo) {
1141 .sType = VK_STRUCTURE_TYPE_PIPELINE_VIEWPORT_STATE_CREATE_INFO,
1145 .pRasterizationState = &(VkPipelineRasterizationStateCreateInfo) {
1146 .sType = VK_STRUCTURE_TYPE_PIPELINE_RASTERIZATION_STATE_CREATE_INFO,
1147 .rasterizerDiscardEnable = false,
1148 .polygonMode = VK_POLYGON_MODE_FILL,
1149 .cullMode = VK_CULL_MODE_NONE,
1150 .frontFace = VK_FRONT_FACE_COUNTER_CLOCKWISE
1152 .pMultisampleState = &(VkPipelineMultisampleStateCreateInfo) {
1153 .sType = VK_STRUCTURE_TYPE_PIPELINE_MULTISAMPLE_STATE_CREATE_INFO,
1154 .rasterizationSamples = 1,
1155 .sampleShadingEnable = false,
1156 .pSampleMask = (VkSampleMask[]) { UINT32_MAX },
1158 .pColorBlendState = &(VkPipelineColorBlendStateCreateInfo) {
1159 .sType = VK_STRUCTURE_TYPE_PIPELINE_COLOR_BLEND_STATE_CREATE_INFO,
1160 .attachmentCount = 1,
1161 .pAttachments = (VkPipelineColorBlendAttachmentState []) {
1163 VK_COLOR_COMPONENT_A_BIT |
1164 VK_COLOR_COMPONENT_R_BIT |
1165 VK_COLOR_COMPONENT_G_BIT |
1166 VK_COLOR_COMPONENT_B_BIT },
1169 .pDynamicState = &(VkPipelineDynamicStateCreateInfo) {
1170 .sType = VK_STRUCTURE_TYPE_PIPELINE_DYNAMIC_STATE_CREATE_INFO,
1171 .dynamicStateCount = 9,
1172 .pDynamicStates = (VkDynamicState[]) {
1173 VK_DYNAMIC_STATE_VIEWPORT,
1174 VK_DYNAMIC_STATE_SCISSOR,
1175 VK_DYNAMIC_STATE_LINE_WIDTH,
1176 VK_DYNAMIC_STATE_DEPTH_BIAS,
1177 VK_DYNAMIC_STATE_BLEND_CONSTANTS,
1178 VK_DYNAMIC_STATE_DEPTH_BOUNDS,
1179 VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK,
1180 VK_DYNAMIC_STATE_STENCIL_WRITE_MASK,
1181 VK_DYNAMIC_STATE_STENCIL_REFERENCE,
1185 .layout = device->meta_state.blit2d.img_p_layout,
1186 .renderPass = device->meta_state.blit2d.render_pass,
1190 const struct anv_graphics_pipeline_create_info anv_pipeline_info = {
1191 .color_attachment_count = -1,
1192 .use_repclear = false,
1193 .disable_viewport = true,
1194 .disable_scissor = true,
1196 .use_rectlist = true
1199 result = anv_graphics_pipeline_create(anv_device_to_handle(device),
1201 &vk_pipeline_info, &anv_pipeline_info,
1202 &device->meta_state.alloc,
1203 &device->meta_state.blit2d.pipelines[src_type][dst_type]);
1205 ralloc_free(vs.nir);
1206 ralloc_free(fs.nir);
1212 anv_device_init_meta_blit2d_state(struct anv_device *device)
1216 zero(device->meta_state.blit2d);
1218 result = anv_CreateRenderPass(anv_device_to_handle(device),
1219 &(VkRenderPassCreateInfo) {
1220 .sType = VK_STRUCTURE_TYPE_RENDER_PASS_CREATE_INFO,
1221 .attachmentCount = 1,
1222 .pAttachments = &(VkAttachmentDescription) {
1223 .format = VK_FORMAT_UNDEFINED, /* Our shaders don't care */
1224 .loadOp = VK_ATTACHMENT_LOAD_OP_LOAD,
1225 .storeOp = VK_ATTACHMENT_STORE_OP_STORE,
1226 .initialLayout = VK_IMAGE_LAYOUT_GENERAL,
1227 .finalLayout = VK_IMAGE_LAYOUT_GENERAL,
1230 .pSubpasses = &(VkSubpassDescription) {
1231 .pipelineBindPoint = VK_PIPELINE_BIND_POINT_GRAPHICS,
1232 .inputAttachmentCount = 0,
1233 .colorAttachmentCount = 1,
1234 .pColorAttachments = &(VkAttachmentReference) {
1236 .layout = VK_IMAGE_LAYOUT_GENERAL,
1238 .pResolveAttachments = NULL,
1239 .pDepthStencilAttachment = &(VkAttachmentReference) {
1240 .attachment = VK_ATTACHMENT_UNUSED,
1241 .layout = VK_IMAGE_LAYOUT_GENERAL,
1243 .preserveAttachmentCount = 1,
1244 .pPreserveAttachments = (uint32_t[]) { 0 },
1246 .dependencyCount = 0,
1247 }, &device->meta_state.alloc, &device->meta_state.blit2d.render_pass);
1248 if (result != VK_SUCCESS)
1251 result = anv_CreateDescriptorSetLayout(anv_device_to_handle(device),
1252 &(VkDescriptorSetLayoutCreateInfo) {
1253 .sType = VK_STRUCTURE_TYPE_DESCRIPTOR_SET_LAYOUT_CREATE_INFO,
1255 .pBindings = (VkDescriptorSetLayoutBinding[]) {
1258 .descriptorType = VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE,
1259 .descriptorCount = 1,
1260 .stageFlags = VK_SHADER_STAGE_FRAGMENT_BIT,
1261 .pImmutableSamplers = NULL
1264 }, &device->meta_state.alloc, &device->meta_state.blit2d.img_ds_layout);
1265 if (result != VK_SUCCESS)
1268 result = anv_CreatePipelineLayout(anv_device_to_handle(device),
1269 &(VkPipelineLayoutCreateInfo) {
1270 .sType = VK_STRUCTURE_TYPE_PIPELINE_LAYOUT_CREATE_INFO,
1271 .setLayoutCount = 1,
1272 .pSetLayouts = &device->meta_state.blit2d.img_ds_layout,
1274 &device->meta_state.alloc, &device->meta_state.blit2d.img_p_layout);
1275 if (result != VK_SUCCESS)
1278 result = anv_CreateDescriptorSetLayout(anv_device_to_handle(device),
1279 &(VkDescriptorSetLayoutCreateInfo) {
1280 .sType = VK_STRUCTURE_TYPE_DESCRIPTOR_SET_LAYOUT_CREATE_INFO,
1282 .pBindings = (VkDescriptorSetLayoutBinding[]) {
1285 .descriptorType = VK_DESCRIPTOR_TYPE_UNIFORM_TEXEL_BUFFER,
1286 .descriptorCount = 1,
1287 .stageFlags = VK_SHADER_STAGE_FRAGMENT_BIT,
1288 .pImmutableSamplers = NULL
1291 }, &device->meta_state.alloc, &device->meta_state.blit2d.buf_ds_layout);
1292 if (result != VK_SUCCESS)
1295 result = anv_CreatePipelineLayout(anv_device_to_handle(device),
1296 &(VkPipelineLayoutCreateInfo) {
1297 .sType = VK_STRUCTURE_TYPE_PIPELINE_LAYOUT_CREATE_INFO,
1298 .setLayoutCount = 1,
1299 .pSetLayouts = &device->meta_state.blit2d.buf_ds_layout,
1301 &device->meta_state.alloc, &device->meta_state.blit2d.buf_p_layout);
1302 if (result != VK_SUCCESS)
1305 for (unsigned src = 0; src < BLIT2D_NUM_SRC_TYPES; src++) {
1306 for (unsigned dst = 0; dst < BLIT2D_NUM_DST_TYPES; dst++) {
1307 result = blit2d_init_pipeline(device, src, dst);
1308 if (result != VK_SUCCESS)
1316 anv_device_finish_meta_blit2d_state(device);