src/intel/vulkan/anv_pipeline.c

   1 /*
   2  * Copyright © 2015 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include <assert.h>
  25 #include <stdbool.h>
  26 #include <string.h>
  27 #include <unistd.h>
  28 #include <fcntl.h>
  29
  30 #include "util/mesa-sha1.h"
  31 #include "anv_private.h"
  32 #include "brw_nir.h"
  33 #include "anv_nir.h"
  34 #include "nir/spirv/nir_spirv.h"
  35
  36 /* Needed for SWIZZLE macros */
  37 #include "program/prog_instruction.h"
  38
  39 // Shader functions
  40
  41 VkResult anv_CreateShaderModule(
  42     VkDevice                                    _device,
  43     const VkShaderModuleCreateInfo*             pCreateInfo,
  44     const VkAllocationCallbacks*                pAllocator,
  45     VkShaderModule*                             pShaderModule)
  46 {
  47    ANV_FROM_HANDLE(anv_device, device, _device);
  48    struct anv_shader_module *module;
  49
  50    assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SHADER_MODULE_CREATE_INFO);
  51    assert(pCreateInfo->flags == 0);
  52
  53    module = anv_alloc2(&device->alloc, pAllocator,
  54                        sizeof(*module) + pCreateInfo->codeSize, 8,
  55                        VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
  56    if (module == NULL)
  57       return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
  58
  59    module->nir = NULL;
  60    module->size = pCreateInfo->codeSize;
  61    memcpy(module->data, pCreateInfo->pCode, module->size);
  62
  63    _mesa_sha1_compute(module->data, module->size, module->sha1);
  64
  65    *pShaderModule = anv_shader_module_to_handle(module);
  66
  67    return VK_SUCCESS;
  68 }
  69
  70 void anv_DestroyShaderModule(
  71     VkDevice                                    _device,
  72     VkShaderModule                              _module,
  73     const VkAllocationCallbacks*                pAllocator)
  74 {
  75    ANV_FROM_HANDLE(anv_device, device, _device);
  76    ANV_FROM_HANDLE(anv_shader_module, module, _module);
  77
  78    anv_free2(&device->alloc, pAllocator, module);
  79 }
  80
  81 #define SPIR_V_MAGIC_NUMBER 0x07230203
  82
  83 /* Eventually, this will become part of anv_CreateShader.  Unfortunately,
  84  * we can't do that yet because we don't have the ability to copy nir.
  85  */
  86 static nir_shader *
  87 anv_shader_compile_to_nir(struct anv_device *device,
  88                           struct anv_shader_module *module,
  89                           const char *entrypoint_name,
  90                           gl_shader_stage stage,
  91                           const VkSpecializationInfo *spec_info)
  92 {
  93    if (strcmp(entrypoint_name, "main") != 0) {
  94       anv_finishme("Multiple shaders per module not really supported");
  95    }
  96
  97    const struct brw_compiler *compiler =
  98       device->instance->physicalDevice.compiler;
  99    const nir_shader_compiler_options *nir_options =
 100       compiler->glsl_compiler_options[stage].NirOptions;
 101
 102    nir_shader *nir;
 103    nir_function *entry_point;
 104    if (module->nir) {
 105       /* Some things such as our meta clear/blit code will give us a NIR
 106        * shader directly.  In that case, we just ignore the SPIR-V entirely
 107        * and just use the NIR shader */
 108       nir = module->nir;
 109       nir->options = nir_options;
 110       nir_validate_shader(nir);
 111
 112       assert(exec_list_length(&nir->functions) == 1);
 113       struct exec_node *node = exec_list_get_head(&nir->functions);
 114       entry_point = exec_node_data(nir_function, node, node);
 115    } else {
 116       uint32_t *spirv = (uint32_t *) module->data;
 117       assert(spirv[0] == SPIR_V_MAGIC_NUMBER);
 118       assert(module->size % 4 == 0);
 119
 120       uint32_t num_spec_entries = 0;
 121       struct nir_spirv_specialization *spec_entries = NULL;
 122       if (spec_info && spec_info->mapEntryCount > 0) {
 123          num_spec_entries = spec_info->mapEntryCount;
 124          spec_entries = malloc(num_spec_entries * sizeof(*spec_entries));
 125          for (uint32_t i = 0; i < num_spec_entries; i++) {
 126             const uint32_t *data =
 127                spec_info->pData + spec_info->pMapEntries[i].offset;
 128             assert((const void *)(data + 1) <=
 129                    spec_info->pData + spec_info->dataSize);
 130
 131             spec_entries[i].id = spec_info->pMapEntries[i].constantID;
 132             spec_entries[i].data = *data;
 133          }
 134       }
 135
 136       entry_point = spirv_to_nir(spirv, module->size / 4,
 137                                  spec_entries, num_spec_entries,
 138                                  stage, entrypoint_name, nir_options);
 139       nir = entry_point->shader;
 140       assert(nir->stage == stage);
 141       nir_validate_shader(nir);
 142
 143       free(spec_entries);
 144
 145       nir_lower_returns(nir);
 146       nir_validate_shader(nir);
 147
 148       nir_inline_functions(nir);
 149       nir_validate_shader(nir);
 150
 151       /* Pick off the single entrypoint that we want */
 152       foreach_list_typed_safe(nir_function, func, node, &nir->functions) {
 153          if (func != entry_point)
 154             exec_node_remove(&func->node);
 155       }
 156       assert(exec_list_length(&nir->functions) == 1);
 157       entry_point->name = ralloc_strdup(entry_point, "main");
 158
 159       nir_remove_dead_variables(nir, nir_var_shader_in);
 160       nir_remove_dead_variables(nir, nir_var_shader_out);
 161       nir_remove_dead_variables(nir, nir_var_system_value);
 162       nir_validate_shader(nir);
 163
 164       nir_lower_outputs_to_temporaries(entry_point->shader, entry_point);
 165
 166       nir_lower_system_values(nir);
 167       nir_validate_shader(nir);
 168    }
 169
 170    /* Vulkan uses the separate-shader linking model */
 171    nir->info.separate_shader = true;
 172
 173    nir = brw_preprocess_nir(nir, compiler->scalar_stage[stage]);
 174
 175    nir_shader_gather_info(nir, entry_point->impl);
 176
 177    uint32_t indirect_mask = 0;
 178    if (compiler->glsl_compiler_options[stage].EmitNoIndirectInput)
 179       indirect_mask |= (1 << nir_var_shader_in);
 180    if (compiler->glsl_compiler_options[stage].EmitNoIndirectTemp)
 181       indirect_mask |= 1 << nir_var_local;
 182
 183    nir_lower_indirect_derefs(nir, indirect_mask);
 184
 185    return nir;
 186 }
 187
 188 void anv_DestroyPipeline(
 189     VkDevice                                    _device,
 190     VkPipeline                                  _pipeline,
 191     const VkAllocationCallbacks*                pAllocator)
 192 {
 193    ANV_FROM_HANDLE(anv_device, device, _device);
 194    ANV_FROM_HANDLE(anv_pipeline, pipeline, _pipeline);
 195
 196    for (unsigned s = 0; s < MESA_SHADER_STAGES; s++) {
 197       free(pipeline->bindings[s].surface_to_descriptor);
 198       free(pipeline->bindings[s].sampler_to_descriptor);
 199    }
 200
 201    anv_reloc_list_finish(&pipeline->batch_relocs,
 202                          pAllocator ? pAllocator : &device->alloc);
 203    if (pipeline->blend_state.map)
 204       anv_state_pool_free(&device->dynamic_state_pool, pipeline->blend_state);
 205    anv_free2(&device->alloc, pAllocator, pipeline);
 206 }
 207
 208 static const uint32_t vk_to_gen_primitive_type[] = {
 209    [VK_PRIMITIVE_TOPOLOGY_POINT_LIST]                    = _3DPRIM_POINTLIST,
 210    [VK_PRIMITIVE_TOPOLOGY_LINE_LIST]                     = _3DPRIM_LINELIST,
 211    [VK_PRIMITIVE_TOPOLOGY_LINE_STRIP]                    = _3DPRIM_LINESTRIP,
 212    [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST]                 = _3DPRIM_TRILIST,
 213    [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP]                = _3DPRIM_TRISTRIP,
 214    [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN]                  = _3DPRIM_TRIFAN,
 215    [VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY]      = _3DPRIM_LINELIST_ADJ,
 216    [VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY]     = _3DPRIM_LINESTRIP_ADJ,
 217    [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY]  = _3DPRIM_TRILIST_ADJ,
 218    [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY] = _3DPRIM_TRISTRIP_ADJ,
 219 /*   [VK_PRIMITIVE_TOPOLOGY_PATCH_LIST]                = _3DPRIM_PATCHLIST_1 */
 220 };
 221
 222 static void
 223 populate_sampler_prog_key(const struct brw_device_info *devinfo,
 224                           struct brw_sampler_prog_key_data *key)
 225 {
 226    /* XXX: Handle texture swizzle on HSW- */
 227    for (int i = 0; i < MAX_SAMPLERS; i++) {
 228       /* Assume color sampler, no swizzling. (Works for BDW+) */
 229       key->swizzles[i] = SWIZZLE_XYZW;
 230    }
 231 }
 232
 233 static void
 234 populate_vs_prog_key(const struct brw_device_info *devinfo,
 235                      struct brw_vs_prog_key *key)
 236 {
 237    memset(key, 0, sizeof(*key));
 238
 239    populate_sampler_prog_key(devinfo, &key->tex);
 240
 241    /* XXX: Handle vertex input work-arounds */
 242
 243    /* XXX: Handle sampler_prog_key */
 244 }
 245
 246 static void
 247 populate_gs_prog_key(const struct brw_device_info *devinfo,
 248                      struct brw_gs_prog_key *key)
 249 {
 250    memset(key, 0, sizeof(*key));
 251
 252    populate_sampler_prog_key(devinfo, &key->tex);
 253 }
 254
 255 static void
 256 populate_wm_prog_key(const struct brw_device_info *devinfo,
 257                      const VkGraphicsPipelineCreateInfo *info,
 258                      const struct anv_graphics_pipeline_create_info *extra,
 259                      struct brw_wm_prog_key *key)
 260 {
 261    ANV_FROM_HANDLE(anv_render_pass, render_pass, info->renderPass);
 262
 263    memset(key, 0, sizeof(*key));
 264
 265    populate_sampler_prog_key(devinfo, &key->tex);
 266
 267    /* TODO: Fill out key->input_slots_valid */
 268
 269    /* Vulkan doesn't specify a default */
 270    key->high_quality_derivatives = false;
 271
 272    /* XXX Vulkan doesn't appear to specify */
 273    key->clamp_fragment_color = false;
 274
 275    /* Vulkan always specifies upper-left coordinates */
 276    key->drawable_height = 0;
 277    key->render_to_fbo = false;
 278
 279    if (extra && extra->color_attachment_count >= 0) {
 280       key->nr_color_regions = extra->color_attachment_count;
 281    } else {
 282       key->nr_color_regions =
 283          render_pass->subpasses[info->subpass].color_count;
 284    }
 285
 286    key->replicate_alpha = key->nr_color_regions > 1 &&
 287                           info->pMultisampleState &&
 288                           info->pMultisampleState->alphaToCoverageEnable;
 289
 290    if (info->pMultisampleState && info->pMultisampleState->rasterizationSamples > 1) {
 291       /* We should probably pull this out of the shader, but it's fairly
 292        * harmless to compute it and then let dead-code take care of it.
 293        */
 294       key->persample_shading = info->pMultisampleState->sampleShadingEnable;
 295       if (key->persample_shading)
 296          key->persample_2x = info->pMultisampleState->rasterizationSamples == 2;
 297
 298       key->compute_pos_offset = info->pMultisampleState->sampleShadingEnable;
 299       key->compute_sample_id = info->pMultisampleState->sampleShadingEnable;
 300    }
 301 }
 302
 303 static void
 304 populate_cs_prog_key(const struct brw_device_info *devinfo,
 305                      struct brw_cs_prog_key *key)
 306 {
 307    memset(key, 0, sizeof(*key));
 308
 309    populate_sampler_prog_key(devinfo, &key->tex);
 310 }
 311
 312 static nir_shader *
 313 anv_pipeline_compile(struct anv_pipeline *pipeline,
 314                      struct anv_shader_module *module,
 315                      const char *entrypoint,
 316                      gl_shader_stage stage,
 317                      const VkSpecializationInfo *spec_info,
 318                      struct brw_stage_prog_data *prog_data)
 319 {
 320    const struct brw_compiler *compiler =
 321       pipeline->device->instance->physicalDevice.compiler;
 322
 323    nir_shader *nir = anv_shader_compile_to_nir(pipeline->device,
 324                                                module, entrypoint, stage,
 325                                                spec_info);
 326    if (nir == NULL)
 327       return NULL;
 328
 329    anv_nir_lower_push_constants(nir, compiler->scalar_stage[stage]);
 330
 331    /* Figure out the number of parameters */
 332    prog_data->nr_params = 0;
 333
 334    if (nir->num_uniforms > 0) {
 335       /* If the shader uses any push constants at all, we'll just give
 336        * them the maximum possible number
 337        */
 338       prog_data->nr_params += MAX_PUSH_CONSTANTS_SIZE / sizeof(float);
 339    }
 340
 341    if (pipeline->layout && pipeline->layout->stage[stage].has_dynamic_offsets)
 342       prog_data->nr_params += MAX_DYNAMIC_BUFFERS * 2;
 343
 344    if (nir->info.num_images > 0)
 345       prog_data->nr_params += nir->info.num_images * BRW_IMAGE_PARAM_SIZE;
 346
 347    if (prog_data->nr_params > 0) {
 348       /* XXX: I think we're leaking this */
 349       prog_data->param = (const union gl_constant_value **)
 350          malloc(prog_data->nr_params * sizeof(union gl_constant_value *));
 351
 352       /* We now set the param values to be offsets into a
 353        * anv_push_constant_data structure.  Since the compiler doesn't
 354        * actually dereference any of the gl_constant_value pointers in the
 355        * params array, it doesn't really matter what we put here.
 356        */
 357       struct anv_push_constants *null_data = NULL;
 358       if (nir->num_uniforms > 0) {
 359          /* Fill out the push constants section of the param array */
 360          for (unsigned i = 0; i < MAX_PUSH_CONSTANTS_SIZE / sizeof(float); i++)
 361             prog_data->param[i] = (const union gl_constant_value *)
 362                &null_data->client_data[i * sizeof(float)];
 363       }
 364    }
 365
 366    /* Set up dynamic offsets */
 367    anv_nir_apply_dynamic_offsets(pipeline, nir, prog_data);
 368
 369    char surface_usage_mask[256], sampler_usage_mask[256];
 370    zero(surface_usage_mask);
 371    zero(sampler_usage_mask);
 372
 373    /* Apply the actual pipeline layout to UBOs, SSBOs, and textures */
 374    if (pipeline->layout)
 375       anv_nir_apply_pipeline_layout(pipeline, nir, prog_data);
 376
 377    /* All binding table offsets provided by apply_pipeline_layout() are
 378     * relative to the start of the bindint table (plus MAX_RTS for VS).
 379     */
 380    unsigned bias;
 381    switch (stage) {
 382    case MESA_SHADER_FRAGMENT:
 383       bias = MAX_RTS;
 384       break;
 385    case MESA_SHADER_COMPUTE:
 386       bias = 1;
 387       break;
 388    default:
 389       bias = 0;
 390       break;
 391    }
 392    prog_data->binding_table.size_bytes = 0;
 393    prog_data->binding_table.texture_start = bias;
 394    prog_data->binding_table.ubo_start = bias;
 395    prog_data->binding_table.ssbo_start = bias;
 396    prog_data->binding_table.image_start = bias;
 397
 398    /* Finish the optimization and compilation process */
 399    if (nir->stage == MESA_SHADER_COMPUTE)
 400       brw_nir_lower_shared(nir);
 401
 402    /* nir_lower_io will only handle the push constants; we need to set this
 403     * to the full number of possible uniforms.
 404     */
 405    nir->num_uniforms = prog_data->nr_params * 4;
 406
 407    return nir;
 408 }
 409
 410 static void
 411 anv_pipeline_add_compiled_stage(struct anv_pipeline *pipeline,
 412                                 gl_shader_stage stage,
 413                                 struct brw_stage_prog_data *prog_data)
 414 {
 415    struct brw_device_info *devinfo = &pipeline->device->info;
 416    uint32_t max_threads[] = {
 417       [MESA_SHADER_VERTEX]                  = devinfo->max_vs_threads,
 418       [MESA_SHADER_TESS_CTRL]               = devinfo->max_hs_threads,
 419       [MESA_SHADER_TESS_EVAL]               = devinfo->max_ds_threads,
 420       [MESA_SHADER_GEOMETRY]                = devinfo->max_gs_threads,
 421       [MESA_SHADER_FRAGMENT]                = devinfo->max_wm_threads,
 422       [MESA_SHADER_COMPUTE]                 = devinfo->max_cs_threads,
 423    };
 424
 425    pipeline->prog_data[stage] = prog_data;
 426    pipeline->active_stages |= mesa_to_vk_shader_stage(stage);
 427    pipeline->scratch_start[stage] = pipeline->total_scratch;
 428    pipeline->total_scratch =
 429       align_u32(pipeline->total_scratch, 1024) +
 430       prog_data->total_scratch * max_threads[stage];
 431 }
 432
 433 static VkResult
 434 anv_pipeline_compile_vs(struct anv_pipeline *pipeline,
 435                         struct anv_pipeline_cache *cache,
 436                         const VkGraphicsPipelineCreateInfo *info,
 437                         struct anv_shader_module *module,
 438                         const char *entrypoint,
 439                         const VkSpecializationInfo *spec_info)
 440 {
 441    const struct brw_compiler *compiler =
 442       pipeline->device->instance->physicalDevice.compiler;
 443    struct brw_vs_prog_data *prog_data = &pipeline->vs_prog_data;
 444    struct brw_vs_prog_key key;
 445    uint32_t kernel;
 446    unsigned char sha1[20], *hash;
 447
 448    populate_vs_prog_key(&pipeline->device->info, &key);
 449
 450    if (module->size > 0) {
 451       hash = sha1;
 452       anv_hash_shader(hash, &key, sizeof(key), module, entrypoint, spec_info);
 453       kernel = anv_pipeline_cache_search(cache, hash, prog_data);
 454    } else {
 455       hash = NULL;
 456    }
 457
 458    if (module->size == 0 || kernel == NO_KERNEL) {
 459       memset(prog_data, 0, sizeof(*prog_data));
 460
 461       nir_shader *nir = anv_pipeline_compile(pipeline, module, entrypoint,
 462                                              MESA_SHADER_VERTEX, spec_info,
 463                                              &prog_data->base.base);
 464       if (nir == NULL)
 465          return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
 466
 467       void *mem_ctx = ralloc_context(NULL);
 468
 469       if (module->nir == NULL)
 470          ralloc_steal(mem_ctx, nir);
 471
 472       prog_data->inputs_read = nir->info.inputs_read;
 473       if (nir->info.outputs_written & (1ull << VARYING_SLOT_PSIZ))
 474          pipeline->writes_point_size = true;
 475
 476       brw_compute_vue_map(&pipeline->device->info,
 477                           &prog_data->base.vue_map,
 478                           nir->info.outputs_written,
 479                           nir->info.separate_shader);
 480
 481       unsigned code_size;
 482       const unsigned *shader_code =
 483          brw_compile_vs(compiler, NULL, mem_ctx, &key, prog_data, nir,
 484                         NULL, false, -1, &code_size, NULL);
 485       if (shader_code == NULL) {
 486          ralloc_free(mem_ctx);
 487          return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
 488       }
 489
 490       kernel = anv_pipeline_cache_upload_kernel(cache, hash,
 491                                                 shader_code, code_size,
 492                                                 prog_data, sizeof(*prog_data));
 493       ralloc_free(mem_ctx);
 494    }
 495
 496    if (prog_data->base.dispatch_mode == DISPATCH_MODE_SIMD8) {
 497       pipeline->vs_simd8 = kernel;
 498       pipeline->vs_vec4 = NO_KERNEL;
 499    } else {
 500       pipeline->vs_simd8 = NO_KERNEL;
 501       pipeline->vs_vec4 = kernel;
 502    }
 503
 504    anv_pipeline_add_compiled_stage(pipeline, MESA_SHADER_VERTEX,
 505                                    &prog_data->base.base);
 506
 507    return VK_SUCCESS;
 508 }
 509
 510 static VkResult
 511 anv_pipeline_compile_gs(struct anv_pipeline *pipeline,
 512                         struct anv_pipeline_cache *cache,
 513                         const VkGraphicsPipelineCreateInfo *info,
 514                         struct anv_shader_module *module,
 515                         const char *entrypoint,
 516                         const VkSpecializationInfo *spec_info)
 517 {
 518    const struct brw_compiler *compiler =
 519       pipeline->device->instance->physicalDevice.compiler;
 520    struct brw_gs_prog_data *prog_data = &pipeline->gs_prog_data;
 521    struct brw_gs_prog_key key;
 522    uint32_t kernel;
 523    unsigned char sha1[20], *hash;
 524
 525    populate_gs_prog_key(&pipeline->device->info, &key);
 526
 527    if (module->size > 0) {
 528       hash = sha1;
 529       anv_hash_shader(hash, &key, sizeof(key), module, entrypoint, spec_info);
 530       kernel = anv_pipeline_cache_search(cache, hash, prog_data);
 531    } else {
 532       hash = NULL;
 533    }
 534
 535    if (module->size == 0 || kernel == NO_KERNEL) {
 536       memset(prog_data, 0, sizeof(*prog_data));
 537
 538       nir_shader *nir = anv_pipeline_compile(pipeline, module, entrypoint,
 539                                              MESA_SHADER_GEOMETRY, spec_info,
 540                                              &prog_data->base.base);
 541       if (nir == NULL)
 542          return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
 543
 544       void *mem_ctx = ralloc_context(NULL);
 545
 546       if (module->nir == NULL)
 547          ralloc_steal(mem_ctx, nir);
 548
 549       if (nir->info.outputs_written & (1ull << VARYING_SLOT_PSIZ))
 550          pipeline->writes_point_size = true;
 551
 552       brw_compute_vue_map(&pipeline->device->info,
 553                           &prog_data->base.vue_map,
 554                           nir->info.outputs_written,
 555                           nir->info.separate_shader);
 556
 557       unsigned code_size;
 558       const unsigned *shader_code =
 559          brw_compile_gs(compiler, NULL, mem_ctx, &key, prog_data, nir,
 560                         NULL, -1, &code_size, NULL);
 561       if (shader_code == NULL) {
 562          ralloc_free(mem_ctx);
 563          return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
 564       }
 565
 566       /* TODO: SIMD8 GS */
 567       kernel = anv_pipeline_cache_upload_kernel(cache, hash,
 568                                                 shader_code, code_size,
 569                                                 prog_data, sizeof(*prog_data));
 570
 571       ralloc_free(mem_ctx);
 572    }
 573
 574    pipeline->gs_kernel = kernel;
 575
 576    anv_pipeline_add_compiled_stage(pipeline, MESA_SHADER_GEOMETRY,
 577                                    &prog_data->base.base);
 578
 579    return VK_SUCCESS;
 580 }
 581
 582 static VkResult
 583 anv_pipeline_compile_fs(struct anv_pipeline *pipeline,
 584                         struct anv_pipeline_cache *cache,
 585                         const VkGraphicsPipelineCreateInfo *info,
 586                         const struct anv_graphics_pipeline_create_info *extra,
 587                         struct anv_shader_module *module,
 588                         const char *entrypoint,
 589                         const VkSpecializationInfo *spec_info)
 590 {
 591    const struct brw_compiler *compiler =
 592       pipeline->device->instance->physicalDevice.compiler;
 593    struct brw_wm_prog_data *prog_data = &pipeline->wm_prog_data;
 594    struct brw_wm_prog_key key;
 595    uint32_t kernel;
 596    unsigned char sha1[20], *hash;
 597
 598    populate_wm_prog_key(&pipeline->device->info, info, extra, &key);
 599
 600    if (pipeline->use_repclear)
 601       key.nr_color_regions = 1;
 602
 603    if (module->size > 0) {
 604       hash = sha1;
 605       anv_hash_shader(hash, &key, sizeof(key), module, entrypoint, spec_info);
 606       kernel = anv_pipeline_cache_search(cache, hash, prog_data);
 607    } else {
 608       hash = NULL;
 609    }
 610
 611    if (module->size == 0 || kernel == NO_KERNEL) {
 612       memset(prog_data, 0, sizeof(*prog_data));
 613
 614       prog_data->binding_table.render_target_start = 0;
 615
 616       nir_shader *nir = anv_pipeline_compile(pipeline, module, entrypoint,
 617                                              MESA_SHADER_FRAGMENT, spec_info,
 618                                              &prog_data->base);
 619       if (nir == NULL)
 620          return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
 621
 622       nir_function_impl *impl = nir_shader_get_entrypoint(nir)->impl;
 623       nir_foreach_variable_safe(var, &nir->outputs) {
 624          if (var->data.location < FRAG_RESULT_DATA0)
 625             continue;
 626
 627          unsigned rt = var->data.location - FRAG_RESULT_DATA0;
 628          if (rt >= key.nr_color_regions) {
 629             var->data.mode = nir_var_local;
 630             exec_node_remove(&var->node);
 631             exec_list_push_tail(&impl->locals, &var->node);
 632          }
 633       }
 634
 635       void *mem_ctx = ralloc_context(NULL);
 636
 637       if (module->nir == NULL)
 638          ralloc_steal(mem_ctx, nir);
 639
 640       unsigned code_size;
 641       const unsigned *shader_code =
 642          brw_compile_fs(compiler, NULL, mem_ctx, &key, prog_data, nir,
 643                         NULL, -1, -1, pipeline->use_repclear, &code_size, NULL);
 644       if (shader_code == NULL) {
 645          ralloc_free(mem_ctx);
 646          return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
 647       }
 648
 649       kernel = anv_pipeline_cache_upload_kernel(cache, hash,
 650                                                 shader_code, code_size,
 651                                                 prog_data, sizeof(*prog_data));
 652
 653       ralloc_free(mem_ctx);
 654    }
 655
 656    if (prog_data->no_8)
 657       pipeline->ps_simd8 = NO_KERNEL;
 658    else
 659       pipeline->ps_simd8 = kernel;
 660
 661    if (prog_data->no_8 || prog_data->prog_offset_16) {
 662       pipeline->ps_simd16 = kernel + prog_data->prog_offset_16;
 663    } else {
 664       pipeline->ps_simd16 = NO_KERNEL;
 665    }
 666
 667    pipeline->ps_ksp2 = 0;
 668    pipeline->ps_grf_start2 = 0;
 669    if (pipeline->ps_simd8 != NO_KERNEL) {
 670       pipeline->ps_ksp0 = pipeline->ps_simd8;
 671       pipeline->ps_grf_start0 = prog_data->base.dispatch_grf_start_reg;
 672       if (pipeline->ps_simd16 != NO_KERNEL) {
 673          pipeline->ps_ksp2 = pipeline->ps_simd16;
 674          pipeline->ps_grf_start2 = prog_data->dispatch_grf_start_reg_16;
 675       }
 676    } else if (pipeline->ps_simd16 != NO_KERNEL) {
 677       pipeline->ps_ksp0 = pipeline->ps_simd16;
 678       pipeline->ps_grf_start0 = prog_data->dispatch_grf_start_reg_16;
 679    }
 680
 681    anv_pipeline_add_compiled_stage(pipeline, MESA_SHADER_FRAGMENT,
 682                                    &prog_data->base);
 683
 684    return VK_SUCCESS;
 685 }
 686
 687 VkResult
 688 anv_pipeline_compile_cs(struct anv_pipeline *pipeline,
 689                         struct anv_pipeline_cache *cache,
 690                         const VkComputePipelineCreateInfo *info,
 691                         struct anv_shader_module *module,
 692                         const char *entrypoint,
 693                         const VkSpecializationInfo *spec_info)
 694 {
 695    const struct brw_compiler *compiler =
 696       pipeline->device->instance->physicalDevice.compiler;
 697    struct brw_cs_prog_data *prog_data = &pipeline->cs_prog_data;
 698    struct brw_cs_prog_key key;
 699    uint32_t kernel;
 700    unsigned char sha1[20], *hash;
 701
 702    populate_cs_prog_key(&pipeline->device->info, &key);
 703
 704    if (module->size > 0) {
 705       hash = sha1;
 706       anv_hash_shader(hash, &key, sizeof(key), module, entrypoint, spec_info);
 707       kernel = anv_pipeline_cache_search(cache, hash, prog_data);
 708    } else {
 709       hash = NULL;
 710    }
 711
 712    if (module->size == 0 || kernel == NO_KERNEL) {
 713       memset(prog_data, 0, sizeof(*prog_data));
 714
 715       prog_data->binding_table.work_groups_start = 0;
 716
 717       nir_shader *nir = anv_pipeline_compile(pipeline, module, entrypoint,
 718                                              MESA_SHADER_COMPUTE, spec_info,
 719                                              &prog_data->base);
 720       if (nir == NULL)
 721          return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
 722
 723       prog_data->base.total_shared = nir->num_shared;
 724
 725       void *mem_ctx = ralloc_context(NULL);
 726
 727       if (module->nir == NULL)
 728          ralloc_steal(mem_ctx, nir);
 729
 730       unsigned code_size;
 731       const unsigned *shader_code =
 732          brw_compile_cs(compiler, NULL, mem_ctx, &key, prog_data, nir,
 733                         -1, &code_size, NULL);
 734       if (shader_code == NULL) {
 735          ralloc_free(mem_ctx);
 736          return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
 737       }
 738
 739       kernel = anv_pipeline_cache_upload_kernel(cache, hash,
 740                                                 shader_code, code_size,
 741                                                 prog_data, sizeof(*prog_data));
 742       ralloc_free(mem_ctx);
 743    }
 744
 745    pipeline->cs_simd = kernel;
 746
 747    anv_pipeline_add_compiled_stage(pipeline, MESA_SHADER_COMPUTE,
 748                                    &prog_data->base);
 749
 750    return VK_SUCCESS;
 751 }
 752
 753 static void
 754 gen7_compute_urb_partition(struct anv_pipeline *pipeline)
 755 {
 756    const struct brw_device_info *devinfo = &pipeline->device->info;
 757    bool vs_present = pipeline->active_stages & VK_SHADER_STAGE_VERTEX_BIT;
 758    unsigned vs_size = vs_present ? pipeline->vs_prog_data.base.urb_entry_size : 1;
 759    unsigned vs_entry_size_bytes = vs_size * 64;
 760    bool gs_present = pipeline->active_stages & VK_SHADER_STAGE_GEOMETRY_BIT;
 761    unsigned gs_size = gs_present ? pipeline->gs_prog_data.base.urb_entry_size : 1;
 762    unsigned gs_entry_size_bytes = gs_size * 64;
 763
 764    /* From p35 of the Ivy Bridge PRM (section 1.7.1: 3DSTATE_URB_GS):
 765     *
 766     *     VS Number of URB Entries must be divisible by 8 if the VS URB Entry
 767     *     Allocation Size is less than 9 512-bit URB entries.
 768     *
 769     * Similar text exists for GS.
 770     */
 771    unsigned vs_granularity = (vs_size < 9) ? 8 : 1;
 772    unsigned gs_granularity = (gs_size < 9) ? 8 : 1;
 773
 774    /* URB allocations must be done in 8k chunks. */
 775    unsigned chunk_size_bytes = 8192;
 776
 777    /* Determine the size of the URB in chunks. */
 778    unsigned urb_chunks = devinfo->urb.size * 1024 / chunk_size_bytes;
 779
 780    /* Reserve space for push constants */
 781    unsigned push_constant_kb;
 782    if (pipeline->device->info.gen >= 8)
 783       push_constant_kb = 32;
 784    else if (pipeline->device->info.is_haswell)
 785       push_constant_kb = pipeline->device->info.gt == 3 ? 32 : 16;
 786    else
 787       push_constant_kb = 16;
 788
 789    unsigned push_constant_bytes = push_constant_kb * 1024;
 790    unsigned push_constant_chunks =
 791       push_constant_bytes / chunk_size_bytes;
 792
 793    /* Initially, assign each stage the minimum amount of URB space it needs,
 794     * and make a note of how much additional space it "wants" (the amount of
 795     * additional space it could actually make use of).
 796     */
 797
 798    /* VS has a lower limit on the number of URB entries */
 799    unsigned vs_chunks =
 800       ALIGN(devinfo->urb.min_vs_entries * vs_entry_size_bytes,
 801             chunk_size_bytes) / chunk_size_bytes;
 802    unsigned vs_wants =
 803       ALIGN(devinfo->urb.max_vs_entries * vs_entry_size_bytes,
 804             chunk_size_bytes) / chunk_size_bytes - vs_chunks;
 805
 806    unsigned gs_chunks = 0;
 807    unsigned gs_wants = 0;
 808    if (gs_present) {
 809       /* There are two constraints on the minimum amount of URB space we can
 810        * allocate:
 811        *
 812        * (1) We need room for at least 2 URB entries, since we always operate
 813        * the GS in DUAL_OBJECT mode.
 814        *
 815        * (2) We can't allocate less than nr_gs_entries_granularity.
 816        */
 817       gs_chunks = ALIGN(MAX2(gs_granularity, 2) * gs_entry_size_bytes,
 818                         chunk_size_bytes) / chunk_size_bytes;
 819       gs_wants =
 820          ALIGN(devinfo->urb.max_gs_entries * gs_entry_size_bytes,
 821                chunk_size_bytes) / chunk_size_bytes - gs_chunks;
 822    }
 823
 824    /* There should always be enough URB space to satisfy the minimum
 825     * requirements of each stage.
 826     */
 827    unsigned total_needs = push_constant_chunks + vs_chunks + gs_chunks;
 828    assert(total_needs <= urb_chunks);
 829
 830    /* Mete out remaining space (if any) in proportion to "wants". */
 831    unsigned total_wants = vs_wants + gs_wants;
 832    unsigned remaining_space = urb_chunks - total_needs;
 833    if (remaining_space > total_wants)
 834       remaining_space = total_wants;
 835    if (remaining_space > 0) {
 836       unsigned vs_additional = (unsigned)
 837          round(vs_wants * (((double) remaining_space) / total_wants));
 838       vs_chunks += vs_additional;
 839       remaining_space -= vs_additional;
 840       gs_chunks += remaining_space;
 841    }
 842
 843    /* Sanity check that we haven't over-allocated. */
 844    assert(push_constant_chunks + vs_chunks + gs_chunks <= urb_chunks);
 845
 846    /* Finally, compute the number of entries that can fit in the space
 847     * allocated to each stage.
 848     */
 849    unsigned nr_vs_entries = vs_chunks * chunk_size_bytes / vs_entry_size_bytes;
 850    unsigned nr_gs_entries = gs_chunks * chunk_size_bytes / gs_entry_size_bytes;
 851
 852    /* Since we rounded up when computing *_wants, this may be slightly more
 853     * than the maximum allowed amount, so correct for that.
 854     */
 855    nr_vs_entries = MIN2(nr_vs_entries, devinfo->urb.max_vs_entries);
 856    nr_gs_entries = MIN2(nr_gs_entries, devinfo->urb.max_gs_entries);
 857
 858    /* Ensure that we program a multiple of the granularity. */
 859    nr_vs_entries = ROUND_DOWN_TO(nr_vs_entries, vs_granularity);
 860    nr_gs_entries = ROUND_DOWN_TO(nr_gs_entries, gs_granularity);
 861
 862    /* Finally, sanity check to make sure we have at least the minimum number
 863     * of entries needed for each stage.
 864     */
 865    assert(nr_vs_entries >= devinfo->urb.min_vs_entries);
 866    if (gs_present)
 867       assert(nr_gs_entries >= 2);
 868
 869    /* Lay out the URB in the following order:
 870     * - push constants
 871     * - VS
 872     * - GS
 873     */
 874    pipeline->urb.start[MESA_SHADER_VERTEX] = push_constant_chunks;
 875    pipeline->urb.size[MESA_SHADER_VERTEX] = vs_size;
 876    pipeline->urb.entries[MESA_SHADER_VERTEX] = nr_vs_entries;
 877
 878    pipeline->urb.start[MESA_SHADER_GEOMETRY] = push_constant_chunks + vs_chunks;
 879    pipeline->urb.size[MESA_SHADER_GEOMETRY] = gs_size;
 880    pipeline->urb.entries[MESA_SHADER_GEOMETRY] = nr_gs_entries;
 881
 882    pipeline->urb.start[MESA_SHADER_TESS_CTRL] = push_constant_chunks;
 883    pipeline->urb.size[MESA_SHADER_TESS_CTRL] = 1;
 884    pipeline->urb.entries[MESA_SHADER_TESS_CTRL] = 0;
 885
 886    pipeline->urb.start[MESA_SHADER_TESS_EVAL] = push_constant_chunks;
 887    pipeline->urb.size[MESA_SHADER_TESS_EVAL] = 1;
 888    pipeline->urb.entries[MESA_SHADER_TESS_EVAL] = 0;
 889
 890    const unsigned stages =
 891       _mesa_bitcount(pipeline->active_stages & VK_SHADER_STAGE_ALL_GRAPHICS);
 892    unsigned size_per_stage = stages ? (push_constant_kb / stages) : 0;
 893    unsigned used_kb = 0;
 894
 895    /* Broadwell+ and Haswell gt3 require that the push constant sizes be in
 896     * units of 2KB.  Incidentally, these are the same platforms that have
 897     * 32KB worth of push constant space.
 898     */
 899    if (push_constant_kb == 32)
 900       size_per_stage &= ~1u;
 901
 902    for (int i = MESA_SHADER_VERTEX; i < MESA_SHADER_FRAGMENT; i++) {
 903       pipeline->urb.push_size[i] =
 904          (pipeline->active_stages & (1 << i)) ? size_per_stage : 0;
 905       used_kb += pipeline->urb.push_size[i];
 906       assert(used_kb <= push_constant_kb);
 907    }
 908
 909    pipeline->urb.push_size[MESA_SHADER_FRAGMENT] =
 910       push_constant_kb - used_kb;
 911 }
 912
 913 static void
 914 anv_pipeline_init_dynamic_state(struct anv_pipeline *pipeline,
 915                                 const VkGraphicsPipelineCreateInfo *pCreateInfo)
 916 {
 917    anv_cmd_dirty_mask_t states = ANV_CMD_DIRTY_DYNAMIC_ALL;
 918    ANV_FROM_HANDLE(anv_render_pass, pass, pCreateInfo->renderPass);
 919    struct anv_subpass *subpass = &pass->subpasses[pCreateInfo->subpass];
 920
 921    pipeline->dynamic_state = default_dynamic_state;
 922
 923    if (pCreateInfo->pDynamicState) {
 924       /* Remove all of the states that are marked as dynamic */
 925       uint32_t count = pCreateInfo->pDynamicState->dynamicStateCount;
 926       for (uint32_t s = 0; s < count; s++)
 927          states &= ~(1 << pCreateInfo->pDynamicState->pDynamicStates[s]);
 928    }
 929
 930    struct anv_dynamic_state *dynamic = &pipeline->dynamic_state;
 931
 932    dynamic->viewport.count = pCreateInfo->pViewportState->viewportCount;
 933    if (states & (1 << VK_DYNAMIC_STATE_VIEWPORT)) {
 934       typed_memcpy(dynamic->viewport.viewports,
 935                    pCreateInfo->pViewportState->pViewports,
 936                    pCreateInfo->pViewportState->viewportCount);
 937    }
 938
 939    dynamic->scissor.count = pCreateInfo->pViewportState->scissorCount;
 940    if (states & (1 << VK_DYNAMIC_STATE_SCISSOR)) {
 941       typed_memcpy(dynamic->scissor.scissors,
 942                    pCreateInfo->pViewportState->pScissors,
 943                    pCreateInfo->pViewportState->scissorCount);
 944    }
 945
 946    if (states & (1 << VK_DYNAMIC_STATE_LINE_WIDTH)) {
 947       assert(pCreateInfo->pRasterizationState);
 948       dynamic->line_width = pCreateInfo->pRasterizationState->lineWidth;
 949    }
 950
 951    if (states & (1 << VK_DYNAMIC_STATE_DEPTH_BIAS)) {
 952       assert(pCreateInfo->pRasterizationState);
 953       dynamic->depth_bias.bias =
 954          pCreateInfo->pRasterizationState->depthBiasConstantFactor;
 955       dynamic->depth_bias.clamp =
 956          pCreateInfo->pRasterizationState->depthBiasClamp;
 957       dynamic->depth_bias.slope =
 958          pCreateInfo->pRasterizationState->depthBiasSlopeFactor;
 959    }
 960
 961    if (states & (1 << VK_DYNAMIC_STATE_BLEND_CONSTANTS)) {
 962       assert(pCreateInfo->pColorBlendState);
 963       typed_memcpy(dynamic->blend_constants,
 964                    pCreateInfo->pColorBlendState->blendConstants, 4);
 965    }
 966
 967    /* If there is no depthstencil attachment, then don't read
 968     * pDepthStencilState. The Vulkan spec states that pDepthStencilState may
 969     * be NULL in this case. Even if pDepthStencilState is non-NULL, there is
 970     * no need to override the depthstencil defaults in
 971     * anv_pipeline::dynamic_state when there is no depthstencil attachment.
 972     *
 973     * From the Vulkan spec (20 Oct 2015, git-aa308cb):
 974     *
 975     *    pDepthStencilState [...] may only be NULL if renderPass and subpass
 976     *    specify a subpass that has no depth/stencil attachment.
 977     */
 978    if (subpass->depth_stencil_attachment != VK_ATTACHMENT_UNUSED) {
 979       if (states & (1 << VK_DYNAMIC_STATE_DEPTH_BOUNDS)) {
 980          assert(pCreateInfo->pDepthStencilState);
 981          dynamic->depth_bounds.min =
 982             pCreateInfo->pDepthStencilState->minDepthBounds;
 983          dynamic->depth_bounds.max =
 984             pCreateInfo->pDepthStencilState->maxDepthBounds;
 985       }
 986
 987       if (states & (1 << VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK)) {
 988          assert(pCreateInfo->pDepthStencilState);
 989          dynamic->stencil_compare_mask.front =
 990             pCreateInfo->pDepthStencilState->front.compareMask;
 991          dynamic->stencil_compare_mask.back =
 992             pCreateInfo->pDepthStencilState->back.compareMask;
 993       }
 994
 995       if (states & (1 << VK_DYNAMIC_STATE_STENCIL_WRITE_MASK)) {
 996          assert(pCreateInfo->pDepthStencilState);
 997          dynamic->stencil_write_mask.front =
 998             pCreateInfo->pDepthStencilState->front.writeMask;
 999          dynamic->stencil_write_mask.back =
1000             pCreateInfo->pDepthStencilState->back.writeMask;
1001       }
1002
1003       if (states & (1 << VK_DYNAMIC_STATE_STENCIL_REFERENCE)) {
1004          assert(pCreateInfo->pDepthStencilState);
1005          dynamic->stencil_reference.front =
1006             pCreateInfo->pDepthStencilState->front.reference;
1007          dynamic->stencil_reference.back =
1008             pCreateInfo->pDepthStencilState->back.reference;
1009       }
1010    }
1011
1012    pipeline->dynamic_state_mask = states;
1013 }
1014
1015 static void
1016 anv_pipeline_validate_create_info(const VkGraphicsPipelineCreateInfo *info)
1017 {
1018    struct anv_render_pass *renderpass = NULL;
1019    struct anv_subpass *subpass = NULL;
1020
1021    /* Assert that all required members of VkGraphicsPipelineCreateInfo are
1022     * present, as explained by the Vulkan (20 Oct 2015, git-aa308cb), Section
1023     * 4.2 Graphics Pipeline.
1024     */
1025    assert(info->sType == VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO);
1026
1027    renderpass = anv_render_pass_from_handle(info->renderPass);
1028    assert(renderpass);
1029
1030    if (renderpass != &anv_meta_dummy_renderpass) {
1031       assert(info->subpass < renderpass->subpass_count);
1032       subpass = &renderpass->subpasses[info->subpass];
1033    }
1034
1035    assert(info->stageCount >= 1);
1036    assert(info->pVertexInputState);
1037    assert(info->pInputAssemblyState);
1038    assert(info->pViewportState);
1039    assert(info->pRasterizationState);
1040
1041    if (subpass && subpass->depth_stencil_attachment != VK_ATTACHMENT_UNUSED)
1042       assert(info->pDepthStencilState);
1043
1044    if (subpass && subpass->color_count > 0)
1045       assert(info->pColorBlendState);
1046
1047    for (uint32_t i = 0; i < info->stageCount; ++i) {
1048       switch (info->pStages[i].stage) {
1049       case VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT:
1050       case VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT:
1051          assert(info->pTessellationState);
1052          break;
1053       default:
1054          break;
1055       }
1056    }
1057 }
1058
1059 VkResult
1060 anv_pipeline_init(struct anv_pipeline *pipeline,
1061                   struct anv_device *device,
1062                   struct anv_pipeline_cache *cache,
1063                   const VkGraphicsPipelineCreateInfo *pCreateInfo,
1064                   const struct anv_graphics_pipeline_create_info *extra,
1065                   const VkAllocationCallbacks *alloc)
1066 {
1067    VkResult result;
1068
1069    anv_validate {
1070       anv_pipeline_validate_create_info(pCreateInfo);
1071    }
1072
1073    if (alloc == NULL)
1074       alloc = &device->alloc;
1075
1076    pipeline->device = device;
1077    pipeline->layout = anv_pipeline_layout_from_handle(pCreateInfo->layout);
1078
1079    result = anv_reloc_list_init(&pipeline->batch_relocs, alloc);
1080    if (result != VK_SUCCESS)
1081       return result;
1082
1083    pipeline->batch.alloc = alloc;
1084    pipeline->batch.next = pipeline->batch.start = pipeline->batch_data;
1085    pipeline->batch.end = pipeline->batch.start + sizeof(pipeline->batch_data);
1086    pipeline->batch.relocs = &pipeline->batch_relocs;
1087
1088    anv_pipeline_init_dynamic_state(pipeline, pCreateInfo);
1089
1090    if (pCreateInfo->pTessellationState)
1091       anv_finishme("VK_STRUCTURE_TYPE_PIPELINE_TESSELLATION_STATE_CREATE_INFO");
1092
1093    pipeline->use_repclear = extra && extra->use_repclear;
1094    pipeline->writes_point_size = false;
1095
1096    /* When we free the pipeline, we detect stages based on the NULL status
1097     * of various prog_data pointers.  Make them NULL by default.
1098     */
1099    memset(pipeline->prog_data, 0, sizeof(pipeline->prog_data));
1100    memset(pipeline->scratch_start, 0, sizeof(pipeline->scratch_start));
1101    memset(pipeline->bindings, 0, sizeof(pipeline->bindings));
1102
1103    pipeline->vs_simd8 = NO_KERNEL;
1104    pipeline->vs_vec4 = NO_KERNEL;
1105    pipeline->gs_kernel = NO_KERNEL;
1106    pipeline->ps_ksp0 = NO_KERNEL;
1107
1108    pipeline->active_stages = 0;
1109    pipeline->total_scratch = 0;
1110
1111    for (uint32_t i = 0; i < pCreateInfo->stageCount; i++) {
1112       ANV_FROM_HANDLE(anv_shader_module, module,
1113                       pCreateInfo->pStages[i].module);
1114
1115       switch (pCreateInfo->pStages[i].stage) {
1116       case VK_SHADER_STAGE_VERTEX_BIT:
1117          anv_pipeline_compile_vs(pipeline, cache, pCreateInfo, module,
1118                                  pCreateInfo->pStages[i].pName,
1119                                  pCreateInfo->pStages[i].pSpecializationInfo);
1120          break;
1121       case VK_SHADER_STAGE_GEOMETRY_BIT:
1122          anv_pipeline_compile_gs(pipeline, cache, pCreateInfo, module,
1123                                  pCreateInfo->pStages[i].pName,
1124                                  pCreateInfo->pStages[i].pSpecializationInfo);
1125          break;
1126       case VK_SHADER_STAGE_FRAGMENT_BIT:
1127          anv_pipeline_compile_fs(pipeline, cache, pCreateInfo, extra, module,
1128                                  pCreateInfo->pStages[i].pName,
1129                                  pCreateInfo->pStages[i].pSpecializationInfo);
1130          break;
1131       default:
1132          anv_finishme("Unsupported shader stage");
1133       }
1134    }
1135
1136    if (!(pipeline->active_stages & VK_SHADER_STAGE_VERTEX_BIT)) {
1137       /* Vertex is only optional if disable_vs is set */
1138       assert(extra->disable_vs);
1139       memset(&pipeline->vs_prog_data, 0, sizeof(pipeline->vs_prog_data));
1140    }
1141
1142    gen7_compute_urb_partition(pipeline);
1143
1144    const VkPipelineVertexInputStateCreateInfo *vi_info =
1145       pCreateInfo->pVertexInputState;
1146
1147    uint64_t inputs_read;
1148    if (extra && extra->disable_vs) {
1149       /* If the VS is disabled, just assume the user knows what they're
1150        * doing and apply the layout blindly.  This can only come from
1151        * meta, so this *should* be safe.
1152        */
1153       inputs_read = ~0ull;
1154    } else {
1155       inputs_read = pipeline->vs_prog_data.inputs_read;
1156    }
1157
1158    pipeline->vb_used = 0;
1159    for (uint32_t i = 0; i < vi_info->vertexAttributeDescriptionCount; i++) {
1160       const VkVertexInputAttributeDescription *desc =
1161          &vi_info->pVertexAttributeDescriptions[i];
1162
1163       if (inputs_read & (1 << (VERT_ATTRIB_GENERIC0 + desc->location)))
1164          pipeline->vb_used |= 1 << desc->binding;
1165    }
1166
1167    for (uint32_t i = 0; i < vi_info->vertexBindingDescriptionCount; i++) {
1168       const VkVertexInputBindingDescription *desc =
1169          &vi_info->pVertexBindingDescriptions[i];
1170
1171       pipeline->binding_stride[desc->binding] = desc->stride;
1172
1173       /* Step rate is programmed per vertex element (attribute), not
1174        * binding. Set up a map of which bindings step per instance, for
1175        * reference by vertex element setup. */
1176       switch (desc->inputRate) {
1177       default:
1178       case VK_VERTEX_INPUT_RATE_VERTEX:
1179          pipeline->instancing_enable[desc->binding] = false;
1180          break;
1181       case VK_VERTEX_INPUT_RATE_INSTANCE:
1182          pipeline->instancing_enable[desc->binding] = true;
1183          break;
1184       }
1185    }
1186
1187    const VkPipelineInputAssemblyStateCreateInfo *ia_info =
1188       pCreateInfo->pInputAssemblyState;
1189    pipeline->primitive_restart = ia_info->primitiveRestartEnable;
1190    pipeline->topology = vk_to_gen_primitive_type[ia_info->topology];
1191
1192    if (extra && extra->use_rectlist)
1193       pipeline->topology = _3DPRIM_RECTLIST;
1194
1195    while (anv_block_pool_size(&device->scratch_block_pool) <
1196           pipeline->total_scratch)
1197       anv_block_pool_alloc(&device->scratch_block_pool);
1198
1199    return VK_SUCCESS;
1200 }
1201
1202 VkResult
1203 anv_graphics_pipeline_create(
1204    VkDevice _device,
1205    VkPipelineCache _cache,
1206    const VkGraphicsPipelineCreateInfo *pCreateInfo,
1207    const struct anv_graphics_pipeline_create_info *extra,
1208    const VkAllocationCallbacks *pAllocator,
1209    VkPipeline *pPipeline)
1210 {
1211    ANV_FROM_HANDLE(anv_device, device, _device);
1212    ANV_FROM_HANDLE(anv_pipeline_cache, cache, _cache);
1213
1214    if (cache == NULL)
1215       cache = &device->default_pipeline_cache;
1216
1217    switch (device->info.gen) {
1218    case 7:
1219       if (device->info.is_haswell)
1220          return gen75_graphics_pipeline_create(_device, cache, pCreateInfo, extra, pAllocator, pPipeline);
1221       else
1222          return gen7_graphics_pipeline_create(_device, cache, pCreateInfo, extra, pAllocator, pPipeline);
1223    case 8:
1224       return gen8_graphics_pipeline_create(_device, cache, pCreateInfo, extra, pAllocator, pPipeline);
1225    case 9:
1226       return gen9_graphics_pipeline_create(_device, cache, pCreateInfo, extra, pAllocator, pPipeline);
1227    default:
1228       unreachable("unsupported gen\n");
1229    }
1230 }
1231
1232 VkResult anv_CreateGraphicsPipelines(
1233     VkDevice                                    _device,
1234     VkPipelineCache                             pipelineCache,
1235     uint32_t                                    count,
1236     const VkGraphicsPipelineCreateInfo*         pCreateInfos,
1237     const VkAllocationCallbacks*                pAllocator,
1238     VkPipeline*                                 pPipelines)
1239 {
1240    VkResult result = VK_SUCCESS;
1241
1242    unsigned i = 0;
1243    for (; i < count; i++) {
1244       result = anv_graphics_pipeline_create(_device,
1245                                             pipelineCache,
1246                                             &pCreateInfos[i],
1247                                             NULL, pAllocator, &pPipelines[i]);
1248       if (result != VK_SUCCESS) {
1249          for (unsigned j = 0; j < i; j++) {
1250             anv_DestroyPipeline(_device, pPipelines[j], pAllocator);
1251          }
1252
1253          return result;
1254       }
1255    }
1256
1257    return VK_SUCCESS;
1258 }
1259
1260 static VkResult anv_compute_pipeline_create(
1261     VkDevice                                    _device,
1262     VkPipelineCache                             _cache,
1263     const VkComputePipelineCreateInfo*          pCreateInfo,
1264     const VkAllocationCallbacks*                pAllocator,
1265     VkPipeline*                                 pPipeline)
1266 {
1267    ANV_FROM_HANDLE(anv_device, device, _device);
1268    ANV_FROM_HANDLE(anv_pipeline_cache, cache, _cache);
1269
1270    if (cache == NULL)
1271       cache = &device->default_pipeline_cache;
1272
1273    switch (device->info.gen) {
1274    case 7:
1275       if (device->info.is_haswell)
1276          return gen75_compute_pipeline_create(_device, cache, pCreateInfo, pAllocator, pPipeline);
1277       else
1278          return gen7_compute_pipeline_create(_device, cache, pCreateInfo, pAllocator, pPipeline);
1279    case 8:
1280       return gen8_compute_pipeline_create(_device, cache, pCreateInfo, pAllocator, pPipeline);
1281    case 9:
1282       return gen9_compute_pipeline_create(_device, cache, pCreateInfo, pAllocator, pPipeline);
1283    default:
1284       unreachable("unsupported gen\n");
1285    }
1286 }
1287
1288 VkResult anv_CreateComputePipelines(
1289     VkDevice                                    _device,
1290     VkPipelineCache                             pipelineCache,
1291     uint32_t                                    count,
1292     const VkComputePipelineCreateInfo*          pCreateInfos,
1293     const VkAllocationCallbacks*                pAllocator,
1294     VkPipeline*                                 pPipelines)
1295 {
1296    VkResult result = VK_SUCCESS;
1297
1298    unsigned i = 0;
1299    for (; i < count; i++) {
1300       result = anv_compute_pipeline_create(_device, pipelineCache,
1301                                            &pCreateInfos[i],
1302                                            pAllocator, &pPipelines[i]);
1303       if (result != VK_SUCCESS) {
1304          for (unsigned j = 0; j < i; j++) {
1305             anv_DestroyPipeline(_device, pPipelines[j], pAllocator);
1306          }
1307
1308          return result;
1309       }
1310    }
1311
1312    return VK_SUCCESS;
1313 }