2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
40 #define __gen_validate_value(x) VALGRIND_CHECK_MEM_IS_DEFINED(&(x), sizeof(x))
46 #include "common/gen_clflush.h"
47 #include "common/gen_gem.h"
48 #include "dev/gen_device_info.h"
49 #include "blorp/blorp.h"
50 #include "compiler/brw_compiler.h"
51 #include "util/macros.h"
52 #include "util/hash_table.h"
53 #include "util/list.h"
55 #include "util/u_atomic.h"
56 #include "util/u_vector.h"
57 #include "util/u_math.h"
60 #include "vk_debug_report.h"
62 /* Pre-declarations needed for WSI entrypoints */
65 typedef struct xcb_connection_t xcb_connection_t;
66 typedef uint32_t xcb_visualid_t;
67 typedef uint32_t xcb_window_t;
70 struct anv_buffer_view;
71 struct anv_image_view;
76 #include <vulkan/vulkan.h>
77 #include <vulkan/vulkan_intel.h>
78 #include <vulkan/vk_icd.h>
79 #include <vulkan/vk_android_native_buffer.h>
81 #include "anv_entrypoints.h"
82 #include "anv_extensions.h"
85 #include "common/gen_debug.h"
86 #include "common/intel_log.h"
87 #include "wsi_common.h"
89 /* anv Virtual Memory Layout
90 * =========================
92 * When the anv driver is determining the virtual graphics addresses of memory
93 * objects itself using the softpin mechanism, the following memory ranges
96 * Three special considerations to notice:
98 * (1) the dynamic state pool is located within the same 4 GiB as the low
99 * heap. This is to work around a VF cache issue described in a comment in
100 * anv_physical_device_init_heaps.
102 * (2) the binding table pool is located at lower addresses than the surface
103 * state pool, within a 4 GiB range. This allows surface state base addresses
104 * to cover both binding tables (16 bit offsets) and surface states (32 bit
107 * (3) the last 4 GiB of the address space is withheld from the high
108 * heap. Various hardware units will read past the end of an object for
109 * various reasons. This healthy margin prevents reads from wrapping around
112 #define LOW_HEAP_MIN_ADDRESS 0x000000001000ULL /* 4 KiB */
113 #define LOW_HEAP_MAX_ADDRESS 0x0000bfffffffULL
114 #define DYNAMIC_STATE_POOL_MIN_ADDRESS 0x0000c0000000ULL /* 3 GiB */
115 #define DYNAMIC_STATE_POOL_MAX_ADDRESS 0x0000ffffffffULL
116 #define BINDING_TABLE_POOL_MIN_ADDRESS 0x000100000000ULL /* 4 GiB */
117 #define BINDING_TABLE_POOL_MAX_ADDRESS 0x00013fffffffULL
118 #define SURFACE_STATE_POOL_MIN_ADDRESS 0x000140000000ULL /* 5 GiB */
119 #define SURFACE_STATE_POOL_MAX_ADDRESS 0x00017fffffffULL
120 #define INSTRUCTION_STATE_POOL_MIN_ADDRESS 0x000180000000ULL /* 6 GiB */
121 #define INSTRUCTION_STATE_POOL_MAX_ADDRESS 0x0001bfffffffULL
122 #define HIGH_HEAP_MIN_ADDRESS 0x0001c0000000ULL /* 7 GiB */
123 #define HIGH_HEAP_MAX_ADDRESS 0xfffeffffffffULL
125 #define LOW_HEAP_SIZE \
126 (LOW_HEAP_MAX_ADDRESS - LOW_HEAP_MIN_ADDRESS + 1)
127 #define HIGH_HEAP_SIZE \
128 (HIGH_HEAP_MAX_ADDRESS - HIGH_HEAP_MIN_ADDRESS + 1)
129 #define DYNAMIC_STATE_POOL_SIZE \
130 (DYNAMIC_STATE_POOL_MAX_ADDRESS - DYNAMIC_STATE_POOL_MIN_ADDRESS + 1)
131 #define BINDING_TABLE_POOL_SIZE \
132 (BINDING_TABLE_POOL_MAX_ADDRESS - BINDING_TABLE_POOL_MIN_ADDRESS + 1)
133 #define SURFACE_STATE_POOL_SIZE \
134 (SURFACE_STATE_POOL_MAX_ADDRESS - SURFACE_STATE_POOL_MIN_ADDRESS + 1)
135 #define INSTRUCTION_STATE_POOL_SIZE \
136 (INSTRUCTION_STATE_POOL_MAX_ADDRESS - INSTRUCTION_STATE_POOL_MIN_ADDRESS + 1)
138 /* Allowing different clear colors requires us to perform a depth resolve at
139 * the end of certain render passes. This is because while slow clears store
140 * the clear color in the HiZ buffer, fast clears (without a resolve) don't.
141 * See the PRMs for examples describing when additional resolves would be
142 * necessary. To enable fast clears without requiring extra resolves, we set
143 * the clear value to a globally-defined one. We could allow different values
144 * if the user doesn't expect coherent data during or after a render passes
145 * (VK_ATTACHMENT_STORE_OP_DONT_CARE), but such users (aside from the CTS)
146 * don't seem to exist yet. In almost all Vulkan applications tested thus far,
147 * 1.0f seems to be the only value used. The only application that doesn't set
148 * this value does so through the usage of an seemingly uninitialized clear
151 #define ANV_HZ_FC_VAL 1.0f
156 #define MAX_VIEWPORTS 16
157 #define MAX_SCISSORS 16
158 #define MAX_PUSH_CONSTANTS_SIZE 128
159 #define MAX_DYNAMIC_BUFFERS 16
160 #define MAX_IMAGES 64
161 #define MAX_GEN8_IMAGES 8
162 #define MAX_PUSH_DESCRIPTORS 32 /* Minimum requirement */
164 /* The kernel relocation API has a limitation of a 32-bit delta value
165 * applied to the address before it is written which, in spite of it being
166 * unsigned, is treated as signed . Because of the way that this maps to
167 * the Vulkan API, we cannot handle an offset into a buffer that does not
168 * fit into a signed 32 bits. The only mechanism we have for dealing with
169 * this at the moment is to limit all VkDeviceMemory objects to a maximum
170 * of 2GB each. The Vulkan spec allows us to do this:
172 * "Some platforms may have a limit on the maximum size of a single
173 * allocation. For example, certain systems may fail to create
174 * allocations with a size greater than or equal to 4GB. Such a limit is
175 * implementation-dependent, and if such a failure occurs then the error
176 * VK_ERROR_OUT_OF_DEVICE_MEMORY should be returned."
178 * We don't use vk_error here because it's not an error so much as an
179 * indication to the application that the allocation is too large.
181 #define MAX_MEMORY_ALLOCATION_SIZE (1ull << 31)
183 #define ANV_SVGS_VB_INDEX MAX_VBS
184 #define ANV_DRAWID_VB_INDEX (MAX_VBS + 1)
186 #define anv_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
188 static inline uint32_t
189 align_down_npot_u32(uint32_t v, uint32_t a)
194 static inline uint32_t
195 align_u32(uint32_t v, uint32_t a)
197 assert(a != 0 && a == (a & -a));
198 return (v + a - 1) & ~(a - 1);
201 static inline uint64_t
202 align_u64(uint64_t v, uint64_t a)
204 assert(a != 0 && a == (a & -a));
205 return (v + a - 1) & ~(a - 1);
208 static inline int32_t
209 align_i32(int32_t v, int32_t a)
211 assert(a != 0 && a == (a & -a));
212 return (v + a - 1) & ~(a - 1);
215 /** Alignment must be a power of 2. */
217 anv_is_aligned(uintmax_t n, uintmax_t a)
219 assert(a == (a & -a));
220 return (n & (a - 1)) == 0;
223 static inline uint32_t
224 anv_minify(uint32_t n, uint32_t levels)
226 if (unlikely(n == 0))
229 return MAX2(n >> levels, 1);
233 anv_clamp_f(float f, float min, float max)
246 anv_clear_mask(uint32_t *inout_mask, uint32_t clear_mask)
248 if (*inout_mask & clear_mask) {
249 *inout_mask &= ~clear_mask;
256 static inline union isl_color_value
257 vk_to_isl_color(VkClearColorValue color)
259 return (union isl_color_value) {
269 #define for_each_bit(b, dword) \
270 for (uint32_t __dword = (dword); \
271 (b) = __builtin_ffs(__dword) - 1, __dword; \
272 __dword &= ~(1 << (b)))
274 #define typed_memcpy(dest, src, count) ({ \
275 STATIC_ASSERT(sizeof(*src) == sizeof(*dest)); \
276 memcpy((dest), (src), (count) * sizeof(*(src))); \
279 /* Mapping from anv object to VkDebugReportObjectTypeEXT. New types need
280 * to be added here in order to utilize mapping in debug/error/perf macros.
282 #define REPORT_OBJECT_TYPE(o) \
283 __builtin_choose_expr ( \
284 __builtin_types_compatible_p (__typeof (o), struct anv_instance*), \
285 VK_DEBUG_REPORT_OBJECT_TYPE_INSTANCE_EXT, \
286 __builtin_choose_expr ( \
287 __builtin_types_compatible_p (__typeof (o), struct anv_physical_device*), \
288 VK_DEBUG_REPORT_OBJECT_TYPE_PHYSICAL_DEVICE_EXT, \
289 __builtin_choose_expr ( \
290 __builtin_types_compatible_p (__typeof (o), struct anv_device*), \
291 VK_DEBUG_REPORT_OBJECT_TYPE_DEVICE_EXT, \
292 __builtin_choose_expr ( \
293 __builtin_types_compatible_p (__typeof (o), const struct anv_device*), \
294 VK_DEBUG_REPORT_OBJECT_TYPE_DEVICE_EXT, \
295 __builtin_choose_expr ( \
296 __builtin_types_compatible_p (__typeof (o), struct anv_queue*), \
297 VK_DEBUG_REPORT_OBJECT_TYPE_QUEUE_EXT, \
298 __builtin_choose_expr ( \
299 __builtin_types_compatible_p (__typeof (o), struct anv_semaphore*), \
300 VK_DEBUG_REPORT_OBJECT_TYPE_SEMAPHORE_EXT, \
301 __builtin_choose_expr ( \
302 __builtin_types_compatible_p (__typeof (o), struct anv_cmd_buffer*), \
303 VK_DEBUG_REPORT_OBJECT_TYPE_COMMAND_BUFFER_EXT, \
304 __builtin_choose_expr ( \
305 __builtin_types_compatible_p (__typeof (o), struct anv_fence*), \
306 VK_DEBUG_REPORT_OBJECT_TYPE_FENCE_EXT, \
307 __builtin_choose_expr ( \
308 __builtin_types_compatible_p (__typeof (o), struct anv_device_memory*), \
309 VK_DEBUG_REPORT_OBJECT_TYPE_DEVICE_MEMORY_EXT, \
310 __builtin_choose_expr ( \
311 __builtin_types_compatible_p (__typeof (o), struct anv_buffer*), \
312 VK_DEBUG_REPORT_OBJECT_TYPE_BUFFER_EXT, \
313 __builtin_choose_expr ( \
314 __builtin_types_compatible_p (__typeof (o), struct anv_image*), \
315 VK_DEBUG_REPORT_OBJECT_TYPE_IMAGE_EXT, \
316 __builtin_choose_expr ( \
317 __builtin_types_compatible_p (__typeof (o), const struct anv_image*), \
318 VK_DEBUG_REPORT_OBJECT_TYPE_IMAGE_EXT, \
319 __builtin_choose_expr ( \
320 __builtin_types_compatible_p (__typeof (o), struct anv_event*), \
321 VK_DEBUG_REPORT_OBJECT_TYPE_EVENT_EXT, \
322 __builtin_choose_expr ( \
323 __builtin_types_compatible_p (__typeof (o), struct anv_query_pool*), \
324 VK_DEBUG_REPORT_OBJECT_TYPE_QUERY_POOL_EXT, \
325 __builtin_choose_expr ( \
326 __builtin_types_compatible_p (__typeof (o), struct anv_buffer_view*), \
327 VK_DEBUG_REPORT_OBJECT_TYPE_BUFFER_VIEW_EXT, \
328 __builtin_choose_expr ( \
329 __builtin_types_compatible_p (__typeof (o), struct anv_image_view*), \
330 VK_DEBUG_REPORT_OBJECT_TYPE_IMAGE_VIEW_EXT, \
331 __builtin_choose_expr ( \
332 __builtin_types_compatible_p (__typeof (o), struct anv_shader_module*), \
333 VK_DEBUG_REPORT_OBJECT_TYPE_SHADER_MODULE_EXT, \
334 __builtin_choose_expr ( \
335 __builtin_types_compatible_p (__typeof (o), struct anv_pipeline_cache*), \
336 VK_DEBUG_REPORT_OBJECT_TYPE_PIPELINE_CACHE_EXT, \
337 __builtin_choose_expr ( \
338 __builtin_types_compatible_p (__typeof (o), struct anv_pipeline_layout*), \
339 VK_DEBUG_REPORT_OBJECT_TYPE_PIPELINE_LAYOUT_EXT, \
340 __builtin_choose_expr ( \
341 __builtin_types_compatible_p (__typeof (o), struct anv_render_pass*), \
342 VK_DEBUG_REPORT_OBJECT_TYPE_RENDER_PASS_EXT, \
343 __builtin_choose_expr ( \
344 __builtin_types_compatible_p (__typeof (o), struct anv_pipeline*), \
345 VK_DEBUG_REPORT_OBJECT_TYPE_PIPELINE_EXT, \
346 __builtin_choose_expr ( \
347 __builtin_types_compatible_p (__typeof (o), struct anv_descriptor_set_layout*), \
348 VK_DEBUG_REPORT_OBJECT_TYPE_DESCRIPTOR_SET_LAYOUT_EXT, \
349 __builtin_choose_expr ( \
350 __builtin_types_compatible_p (__typeof (o), struct anv_sampler*), \
351 VK_DEBUG_REPORT_OBJECT_TYPE_SAMPLER_EXT, \
352 __builtin_choose_expr ( \
353 __builtin_types_compatible_p (__typeof (o), struct anv_descriptor_pool*), \
354 VK_DEBUG_REPORT_OBJECT_TYPE_DESCRIPTOR_POOL_EXT, \
355 __builtin_choose_expr ( \
356 __builtin_types_compatible_p (__typeof (o), struct anv_descriptor_set*), \
357 VK_DEBUG_REPORT_OBJECT_TYPE_DESCRIPTOR_SET_EXT, \
358 __builtin_choose_expr ( \
359 __builtin_types_compatible_p (__typeof (o), struct anv_framebuffer*), \
360 VK_DEBUG_REPORT_OBJECT_TYPE_FRAMEBUFFER_EXT, \
361 __builtin_choose_expr ( \
362 __builtin_types_compatible_p (__typeof (o), struct anv_cmd_pool*), \
363 VK_DEBUG_REPORT_OBJECT_TYPE_COMMAND_POOL_EXT, \
364 __builtin_choose_expr ( \
365 __builtin_types_compatible_p (__typeof (o), struct anv_surface*), \
366 VK_DEBUG_REPORT_OBJECT_TYPE_SURFACE_KHR_EXT, \
367 __builtin_choose_expr ( \
368 __builtin_types_compatible_p (__typeof (o), struct wsi_swapchain*), \
369 VK_DEBUG_REPORT_OBJECT_TYPE_SWAPCHAIN_KHR_EXT, \
370 __builtin_choose_expr ( \
371 __builtin_types_compatible_p (__typeof (o), struct vk_debug_callback*), \
372 VK_DEBUG_REPORT_OBJECT_TYPE_DEBUG_REPORT_CALLBACK_EXT_EXT, \
373 __builtin_choose_expr ( \
374 __builtin_types_compatible_p (__typeof (o), void*), \
375 VK_DEBUG_REPORT_OBJECT_TYPE_UNKNOWN_EXT, \
376 /* The void expression results in a compile-time error \
377 when assigning the result to something. */ \
378 (void)0)))))))))))))))))))))))))))))))
380 /* Whenever we generate an error, pass it through this function. Useful for
381 * debugging, where we can break on it. Only call at error site, not when
382 * propagating errors. Might be useful to plug in a stack trace here.
385 VkResult __vk_errorv(struct anv_instance *instance, const void *object,
386 VkDebugReportObjectTypeEXT type, VkResult error,
387 const char *file, int line, const char *format,
390 VkResult __vk_errorf(struct anv_instance *instance, const void *object,
391 VkDebugReportObjectTypeEXT type, VkResult error,
392 const char *file, int line, const char *format, ...);
395 #define vk_error(error) __vk_errorf(NULL, NULL,\
396 VK_DEBUG_REPORT_OBJECT_TYPE_UNKNOWN_EXT,\
397 error, __FILE__, __LINE__, NULL)
398 #define vk_errorv(instance, obj, error, format, args)\
399 __vk_errorv(instance, obj, REPORT_OBJECT_TYPE(obj), error,\
400 __FILE__, __LINE__, format, args)
401 #define vk_errorf(instance, obj, error, format, ...)\
402 __vk_errorf(instance, obj, REPORT_OBJECT_TYPE(obj), error,\
403 __FILE__, __LINE__, format, ## __VA_ARGS__)
405 #define vk_error(error) error
406 #define vk_errorf(instance, obj, error, format, ...) error
410 * Warn on ignored extension structs.
412 * The Vulkan spec requires us to ignore unsupported or unknown structs in
413 * a pNext chain. In debug mode, emitting warnings for ignored structs may
414 * help us discover structs that we should not have ignored.
417 * From the Vulkan 1.0.38 spec:
419 * Any component of the implementation (the loader, any enabled layers,
420 * and drivers) must skip over, without processing (other than reading the
421 * sType and pNext members) any chained structures with sType values not
422 * defined by extensions supported by that component.
424 #define anv_debug_ignored_stype(sType) \
425 intel_logd("%s: ignored VkStructureType %u\n", __func__, (sType))
427 void __anv_perf_warn(struct anv_instance *instance, const void *object,
428 VkDebugReportObjectTypeEXT type, const char *file,
429 int line, const char *format, ...)
430 anv_printflike(6, 7);
431 void anv_loge(const char *format, ...) anv_printflike(1, 2);
432 void anv_loge_v(const char *format, va_list va);
435 * Print a FINISHME message, including its source location.
437 #define anv_finishme(format, ...) \
439 static bool reported = false; \
441 intel_logw("%s:%d: FINISHME: " format, __FILE__, __LINE__, \
448 * Print a perf warning message. Set INTEL_DEBUG=perf to see these.
450 #define anv_perf_warn(instance, obj, format, ...) \
452 static bool reported = false; \
453 if (!reported && unlikely(INTEL_DEBUG & DEBUG_PERF)) { \
454 __anv_perf_warn(instance, obj, REPORT_OBJECT_TYPE(obj), __FILE__, __LINE__,\
455 format, ##__VA_ARGS__); \
460 /* A non-fatal assert. Useful for debugging. */
462 #define anv_assert(x) ({ \
463 if (unlikely(!(x))) \
464 intel_loge("%s:%d ASSERT: %s", __FILE__, __LINE__, #x); \
467 #define anv_assert(x)
470 /* A multi-pointer allocator
472 * When copying data structures from the user (such as a render pass), it's
473 * common to need to allocate data for a bunch of different things. Instead
474 * of doing several allocations and having to handle all of the error checking
475 * that entails, it can be easier to do a single allocation. This struct
476 * helps facilitate that. The intended usage looks like this:
479 * anv_multialloc_add(&ma, &main_ptr, 1);
480 * anv_multialloc_add(&ma, &substruct1, substruct1Count);
481 * anv_multialloc_add(&ma, &substruct2, substruct2Count);
483 * if (!anv_multialloc_alloc(&ma, pAllocator, VK_ALLOCATION_SCOPE_FOO))
484 * return vk_error(VK_ERROR_OUT_OF_HOST_MEORY);
486 struct anv_multialloc {
494 #define ANV_MULTIALLOC_INIT \
495 ((struct anv_multialloc) { 0, })
497 #define ANV_MULTIALLOC(_name) \
498 struct anv_multialloc _name = ANV_MULTIALLOC_INIT
500 __attribute__((always_inline))
502 _anv_multialloc_add(struct anv_multialloc *ma,
503 void **ptr, size_t size, size_t align)
505 size_t offset = align_u64(ma->size, align);
506 ma->size = offset + size;
507 ma->align = MAX2(ma->align, align);
509 /* Store the offset in the pointer. */
510 *ptr = (void *)(uintptr_t)offset;
512 assert(ma->ptr_count < ARRAY_SIZE(ma->ptrs));
513 ma->ptrs[ma->ptr_count++] = ptr;
516 #define anv_multialloc_add_size(_ma, _ptr, _size) \
517 _anv_multialloc_add((_ma), (void **)(_ptr), (_size), __alignof__(**(_ptr)))
519 #define anv_multialloc_add(_ma, _ptr, _count) \
520 anv_multialloc_add_size(_ma, _ptr, (_count) * sizeof(**(_ptr)));
522 __attribute__((always_inline))
524 anv_multialloc_alloc(struct anv_multialloc *ma,
525 const VkAllocationCallbacks *alloc,
526 VkSystemAllocationScope scope)
528 void *ptr = vk_alloc(alloc, ma->size, ma->align, scope);
532 /* Fill out each of the pointers with their final value.
534 * for (uint32_t i = 0; i < ma->ptr_count; i++)
535 * *ma->ptrs[i] = ptr + (uintptr_t)*ma->ptrs[i];
537 * Unfortunately, even though ma->ptr_count is basically guaranteed to be a
538 * constant, GCC is incapable of figuring this out and unrolling the loop
539 * so we have to give it a little help.
541 STATIC_ASSERT(ARRAY_SIZE(ma->ptrs) == 8);
542 #define _ANV_MULTIALLOC_UPDATE_POINTER(_i) \
543 if ((_i) < ma->ptr_count) \
544 *ma->ptrs[_i] = ptr + (uintptr_t)*ma->ptrs[_i]
545 _ANV_MULTIALLOC_UPDATE_POINTER(0);
546 _ANV_MULTIALLOC_UPDATE_POINTER(1);
547 _ANV_MULTIALLOC_UPDATE_POINTER(2);
548 _ANV_MULTIALLOC_UPDATE_POINTER(3);
549 _ANV_MULTIALLOC_UPDATE_POINTER(4);
550 _ANV_MULTIALLOC_UPDATE_POINTER(5);
551 _ANV_MULTIALLOC_UPDATE_POINTER(6);
552 _ANV_MULTIALLOC_UPDATE_POINTER(7);
553 #undef _ANV_MULTIALLOC_UPDATE_POINTER
558 __attribute__((always_inline))
560 anv_multialloc_alloc2(struct anv_multialloc *ma,
561 const VkAllocationCallbacks *parent_alloc,
562 const VkAllocationCallbacks *alloc,
563 VkSystemAllocationScope scope)
565 return anv_multialloc_alloc(ma, alloc ? alloc : parent_alloc, scope);
568 /* Extra ANV-defined BO flags which won't be passed to the kernel */
569 #define ANV_BO_EXTERNAL (1ull << 31)
570 #define ANV_BO_FLAG_MASK (1ull << 31)
575 /* Index into the current validation list. This is used by the
576 * validation list building alrogithm to track which buffers are already
577 * in the validation list so that we can ensure uniqueness.
581 /* Last known offset. This value is provided by the kernel when we
582 * execbuf and is used as the presumed offset for the next bunch of
590 /** Flags to pass to the kernel through drm_i915_exec_object2::flags */
595 anv_bo_init(struct anv_bo *bo, uint32_t gem_handle, uint64_t size)
597 bo->gem_handle = gem_handle;
605 /* Represents a lock-free linked list of "free" things. This is used by
606 * both the block pool and the state pools. Unfortunately, in order to
607 * solve the ABA problem, we can't use a single uint32_t head.
609 union anv_free_list {
613 /* A simple count that is incremented every time the head changes. */
619 #define ANV_FREE_LIST_EMPTY ((union anv_free_list) { { 1, 0 } })
621 struct anv_block_state {
631 struct anv_block_pool {
632 struct anv_device *device;
638 /* The address where the start of the pool is pinned. The various bos that
639 * are created as the pool grows will have addresses in the range
640 * [start_address, start_address + BLOCK_POOL_MEMFD_SIZE).
642 uint64_t start_address;
644 /* The offset from the start of the bo to the "center" of the block
645 * pool. Pointers to allocated blocks are given by
646 * bo.map + center_bo_offset + offsets.
648 uint32_t center_bo_offset;
650 /* Current memory map of the block pool. This pointer may or may not
651 * point to the actual beginning of the block pool memory. If
652 * anv_block_pool_alloc_back has ever been called, then this pointer
653 * will point to the "center" position of the buffer and all offsets
654 * (negative or positive) given out by the block pool alloc functions
655 * will be valid relative to this pointer.
657 * In particular, map == bo.map + center_offset
663 * Array of mmaps and gem handles owned by the block pool, reclaimed when
664 * the block pool is destroyed.
666 struct u_vector mmap_cleanups;
668 struct anv_block_state state;
670 struct anv_block_state back_state;
673 /* Block pools are backed by a fixed-size 1GB memfd */
674 #define BLOCK_POOL_MEMFD_SIZE (1ul << 30)
676 /* The center of the block pool is also the middle of the memfd. This may
677 * change in the future if we decide differently for some reason.
679 #define BLOCK_POOL_MEMFD_CENTER (BLOCK_POOL_MEMFD_SIZE / 2)
681 static inline uint32_t
682 anv_block_pool_size(struct anv_block_pool *pool)
684 return pool->state.end + pool->back_state.end;
693 #define ANV_STATE_NULL ((struct anv_state) { .alloc_size = 0 })
695 struct anv_fixed_size_state_pool {
696 union anv_free_list free_list;
697 struct anv_block_state block;
700 #define ANV_MIN_STATE_SIZE_LOG2 6
701 #define ANV_MAX_STATE_SIZE_LOG2 20
703 #define ANV_STATE_BUCKETS (ANV_MAX_STATE_SIZE_LOG2 - ANV_MIN_STATE_SIZE_LOG2 + 1)
705 struct anv_state_pool {
706 struct anv_block_pool block_pool;
708 /* The size of blocks which will be allocated from the block pool */
711 /** Free list for "back" allocations */
712 union anv_free_list back_alloc_free_list;
714 struct anv_fixed_size_state_pool buckets[ANV_STATE_BUCKETS];
717 struct anv_state_stream_block;
719 struct anv_state_stream {
720 struct anv_state_pool *state_pool;
722 /* The size of blocks to allocate from the state pool */
725 /* Current block we're allocating from */
726 struct anv_state block;
728 /* Offset into the current block at which to allocate the next state */
731 /* List of all blocks allocated from this pool */
732 struct anv_state_stream_block *block_list;
735 /* The block_pool functions exported for testing only. The block pool should
736 * only be used via a state pool (see below).
738 VkResult anv_block_pool_init(struct anv_block_pool *pool,
739 struct anv_device *device,
740 uint64_t start_address,
741 uint32_t initial_size,
743 void anv_block_pool_finish(struct anv_block_pool *pool);
744 int32_t anv_block_pool_alloc(struct anv_block_pool *pool,
745 uint32_t block_size);
746 int32_t anv_block_pool_alloc_back(struct anv_block_pool *pool,
747 uint32_t block_size);
749 VkResult anv_state_pool_init(struct anv_state_pool *pool,
750 struct anv_device *device,
751 uint64_t start_address,
754 void anv_state_pool_finish(struct anv_state_pool *pool);
755 struct anv_state anv_state_pool_alloc(struct anv_state_pool *pool,
756 uint32_t state_size, uint32_t alignment);
757 struct anv_state anv_state_pool_alloc_back(struct anv_state_pool *pool);
758 void anv_state_pool_free(struct anv_state_pool *pool, struct anv_state state);
759 void anv_state_stream_init(struct anv_state_stream *stream,
760 struct anv_state_pool *state_pool,
761 uint32_t block_size);
762 void anv_state_stream_finish(struct anv_state_stream *stream);
763 struct anv_state anv_state_stream_alloc(struct anv_state_stream *stream,
764 uint32_t size, uint32_t alignment);
767 * Implements a pool of re-usable BOs. The interface is identical to that
768 * of block_pool except that each block is its own BO.
771 struct anv_device *device;
778 void anv_bo_pool_init(struct anv_bo_pool *pool, struct anv_device *device,
780 void anv_bo_pool_finish(struct anv_bo_pool *pool);
781 VkResult anv_bo_pool_alloc(struct anv_bo_pool *pool, struct anv_bo *bo,
783 void anv_bo_pool_free(struct anv_bo_pool *pool, const struct anv_bo *bo);
785 struct anv_scratch_bo {
790 struct anv_scratch_pool {
791 /* Indexed by Per-Thread Scratch Space number (the hardware value) and stage */
792 struct anv_scratch_bo bos[16][MESA_SHADER_STAGES];
795 void anv_scratch_pool_init(struct anv_device *device,
796 struct anv_scratch_pool *pool);
797 void anv_scratch_pool_finish(struct anv_device *device,
798 struct anv_scratch_pool *pool);
799 struct anv_bo *anv_scratch_pool_alloc(struct anv_device *device,
800 struct anv_scratch_pool *pool,
801 gl_shader_stage stage,
802 unsigned per_thread_scratch);
804 /** Implements a BO cache that ensures a 1-1 mapping of GEM BOs to anv_bos */
805 struct anv_bo_cache {
806 struct hash_table *bo_map;
807 pthread_mutex_t mutex;
810 VkResult anv_bo_cache_init(struct anv_bo_cache *cache);
811 void anv_bo_cache_finish(struct anv_bo_cache *cache);
812 VkResult anv_bo_cache_alloc(struct anv_device *device,
813 struct anv_bo_cache *cache,
814 uint64_t size, uint64_t bo_flags,
816 VkResult anv_bo_cache_import(struct anv_device *device,
817 struct anv_bo_cache *cache,
818 int fd, uint64_t bo_flags,
820 VkResult anv_bo_cache_export(struct anv_device *device,
821 struct anv_bo_cache *cache,
822 struct anv_bo *bo_in, int *fd_out);
823 void anv_bo_cache_release(struct anv_device *device,
824 struct anv_bo_cache *cache,
827 struct anv_memory_type {
828 /* Standard bits passed on to the client */
829 VkMemoryPropertyFlags propertyFlags;
832 /* Driver-internal book-keeping */
833 VkBufferUsageFlags valid_buffer_usage;
836 struct anv_memory_heap {
837 /* Standard bits passed on to the client */
839 VkMemoryHeapFlags flags;
841 /* Driver-internal book-keeping */
842 bool supports_48bit_addresses;
845 struct anv_physical_device {
846 VK_LOADER_DATA _loader_data;
848 struct anv_instance * instance;
859 struct gen_device_info info;
860 /** Amount of "GPU memory" we want to advertise
862 * Clearly, this value is bogus since Intel is a UMA architecture. On
863 * gen7 platforms, we are limited by GTT size unless we want to implement
864 * fine-grained tracking and GTT splitting. On Broadwell and above we are
865 * practically unlimited. However, we will never report more than 3/4 of
866 * the total system ram to try and avoid running out of RAM.
868 bool supports_48bit_addresses;
869 struct brw_compiler * compiler;
870 struct isl_device isl_dev;
871 int cmd_parser_version;
873 bool has_exec_capture;
876 bool has_syncobj_wait;
877 bool has_context_priority;
879 bool has_context_isolation;
881 struct anv_device_extension_table supported_extensions;
884 uint32_t subslice_total;
888 struct anv_memory_type types[VK_MAX_MEMORY_TYPES];
890 struct anv_memory_heap heaps[VK_MAX_MEMORY_HEAPS];
893 uint8_t driver_build_sha1[20];
894 uint8_t pipeline_cache_uuid[VK_UUID_SIZE];
895 uint8_t driver_uuid[VK_UUID_SIZE];
896 uint8_t device_uuid[VK_UUID_SIZE];
898 struct disk_cache * disk_cache;
900 struct wsi_device wsi_device;
905 struct anv_app_info {
906 const char* app_name;
907 uint32_t app_version;
908 const char* engine_name;
909 uint32_t engine_version;
910 uint32_t api_version;
913 struct anv_instance {
914 VK_LOADER_DATA _loader_data;
916 VkAllocationCallbacks alloc;
918 struct anv_app_info app_info;
920 struct anv_instance_extension_table enabled_extensions;
921 struct anv_instance_dispatch_table dispatch;
922 struct anv_device_dispatch_table device_dispatch;
924 int physicalDeviceCount;
925 struct anv_physical_device physicalDevice;
927 bool pipeline_cache_enabled;
929 struct vk_debug_report_instance debug_report_callbacks;
932 VkResult anv_init_wsi(struct anv_physical_device *physical_device);
933 void anv_finish_wsi(struct anv_physical_device *physical_device);
935 uint32_t anv_physical_device_api_version(struct anv_physical_device *dev);
936 bool anv_physical_device_extension_supported(struct anv_physical_device *dev,
940 VK_LOADER_DATA _loader_data;
942 struct anv_device * device;
944 VkDeviceQueueCreateFlags flags;
947 struct anv_pipeline_cache {
948 struct anv_device * device;
949 pthread_mutex_t mutex;
951 struct hash_table * cache;
954 struct anv_pipeline_bind_map;
956 void anv_pipeline_cache_init(struct anv_pipeline_cache *cache,
957 struct anv_device *device,
959 void anv_pipeline_cache_finish(struct anv_pipeline_cache *cache);
961 struct anv_shader_bin *
962 anv_pipeline_cache_search(struct anv_pipeline_cache *cache,
963 const void *key, uint32_t key_size);
964 struct anv_shader_bin *
965 anv_pipeline_cache_upload_kernel(struct anv_pipeline_cache *cache,
966 const void *key_data, uint32_t key_size,
967 const void *kernel_data, uint32_t kernel_size,
968 const void *constant_data,
969 uint32_t constant_data_size,
970 const struct brw_stage_prog_data *prog_data,
971 uint32_t prog_data_size,
972 const struct anv_pipeline_bind_map *bind_map);
974 struct anv_shader_bin *
975 anv_device_search_for_kernel(struct anv_device *device,
976 struct anv_pipeline_cache *cache,
977 const void *key_data, uint32_t key_size);
979 struct anv_shader_bin *
980 anv_device_upload_kernel(struct anv_device *device,
981 struct anv_pipeline_cache *cache,
982 const void *key_data, uint32_t key_size,
983 const void *kernel_data, uint32_t kernel_size,
984 const void *constant_data,
985 uint32_t constant_data_size,
986 const struct brw_stage_prog_data *prog_data,
987 uint32_t prog_data_size,
988 const struct anv_pipeline_bind_map *bind_map);
991 VK_LOADER_DATA _loader_data;
993 VkAllocationCallbacks alloc;
995 struct anv_instance * instance;
998 struct gen_device_info info;
999 struct isl_device isl_dev;
1002 bool can_chain_batches;
1003 bool robust_buffer_access;
1004 struct anv_device_extension_table enabled_extensions;
1005 struct anv_device_dispatch_table dispatch;
1007 pthread_mutex_t vma_mutex;
1008 struct util_vma_heap vma_lo;
1009 struct util_vma_heap vma_hi;
1010 uint64_t vma_lo_available;
1011 uint64_t vma_hi_available;
1013 struct anv_bo_pool batch_bo_pool;
1015 struct anv_bo_cache bo_cache;
1017 struct anv_state_pool dynamic_state_pool;
1018 struct anv_state_pool instruction_state_pool;
1019 struct anv_state_pool binding_table_pool;
1020 struct anv_state_pool surface_state_pool;
1022 struct anv_bo workaround_bo;
1023 struct anv_bo trivial_batch_bo;
1024 struct anv_bo hiz_clear_bo;
1026 struct anv_pipeline_cache default_pipeline_cache;
1027 struct blorp_context blorp;
1029 struct anv_state border_colors;
1031 struct anv_queue queue;
1033 struct anv_scratch_pool scratch_pool;
1035 uint32_t default_mocs;
1036 uint32_t external_mocs;
1038 pthread_mutex_t mutex;
1039 pthread_cond_t queue_submit;
1043 static inline struct anv_state_pool *
1044 anv_binding_table_pool(struct anv_device *device)
1046 if (device->instance->physicalDevice.use_softpin)
1047 return &device->binding_table_pool;
1049 return &device->surface_state_pool;
1052 static inline struct anv_state
1053 anv_binding_table_pool_alloc(struct anv_device *device) {
1054 if (device->instance->physicalDevice.use_softpin)
1055 return anv_state_pool_alloc(&device->binding_table_pool,
1056 device->binding_table_pool.block_size, 0);
1058 return anv_state_pool_alloc_back(&device->surface_state_pool);
1062 anv_binding_table_pool_free(struct anv_device *device, struct anv_state state) {
1063 anv_state_pool_free(anv_binding_table_pool(device), state);
1066 static inline uint32_t
1067 anv_mocs_for_bo(const struct anv_device *device, const struct anv_bo *bo)
1069 if (bo->flags & ANV_BO_EXTERNAL)
1070 return device->external_mocs;
1072 return device->default_mocs;
1076 anv_state_flush(struct anv_device *device, struct anv_state state)
1078 if (device->info.has_llc)
1081 gen_flush_range(state.map, state.alloc_size);
1084 void anv_device_init_blorp(struct anv_device *device);
1085 void anv_device_finish_blorp(struct anv_device *device);
1087 VkResult _anv_device_set_lost(struct anv_device *device,
1088 const char *file, int line,
1089 const char *msg, ...);
1090 #define anv_device_set_lost(dev, ...) \
1091 _anv_device_set_lost(dev, __FILE__, __LINE__, __VA_ARGS__)
1094 anv_device_is_lost(struct anv_device *device)
1096 return unlikely(device->_lost);
1099 VkResult anv_device_execbuf(struct anv_device *device,
1100 struct drm_i915_gem_execbuffer2 *execbuf,
1101 struct anv_bo **execbuf_bos);
1102 VkResult anv_device_query_status(struct anv_device *device);
1103 VkResult anv_device_bo_busy(struct anv_device *device, struct anv_bo *bo);
1104 VkResult anv_device_wait(struct anv_device *device, struct anv_bo *bo,
1107 void* anv_gem_mmap(struct anv_device *device,
1108 uint32_t gem_handle, uint64_t offset, uint64_t size, uint32_t flags);
1109 void anv_gem_munmap(void *p, uint64_t size);
1110 uint32_t anv_gem_create(struct anv_device *device, uint64_t size);
1111 void anv_gem_close(struct anv_device *device, uint32_t gem_handle);
1112 uint32_t anv_gem_userptr(struct anv_device *device, void *mem, size_t size);
1113 int anv_gem_busy(struct anv_device *device, uint32_t gem_handle);
1114 int anv_gem_wait(struct anv_device *device, uint32_t gem_handle, int64_t *timeout_ns);
1115 int anv_gem_execbuffer(struct anv_device *device,
1116 struct drm_i915_gem_execbuffer2 *execbuf);
1117 int anv_gem_set_tiling(struct anv_device *device, uint32_t gem_handle,
1118 uint32_t stride, uint32_t tiling);
1119 int anv_gem_create_context(struct anv_device *device);
1120 bool anv_gem_has_context_priority(int fd);
1121 int anv_gem_destroy_context(struct anv_device *device, int context);
1122 int anv_gem_set_context_param(int fd, int context, uint32_t param,
1124 int anv_gem_get_context_param(int fd, int context, uint32_t param,
1126 int anv_gem_get_param(int fd, uint32_t param);
1127 int anv_gem_get_tiling(struct anv_device *device, uint32_t gem_handle);
1128 bool anv_gem_get_bit6_swizzle(int fd, uint32_t tiling);
1129 int anv_gem_get_aperture(int fd, uint64_t *size);
1130 int anv_gem_gpu_get_reset_stats(struct anv_device *device,
1131 uint32_t *active, uint32_t *pending);
1132 int anv_gem_handle_to_fd(struct anv_device *device, uint32_t gem_handle);
1133 int anv_gem_reg_read(struct anv_device *device,
1134 uint32_t offset, uint64_t *result);
1135 uint32_t anv_gem_fd_to_handle(struct anv_device *device, int fd);
1136 int anv_gem_set_caching(struct anv_device *device, uint32_t gem_handle, uint32_t caching);
1137 int anv_gem_set_domain(struct anv_device *device, uint32_t gem_handle,
1138 uint32_t read_domains, uint32_t write_domain);
1139 int anv_gem_sync_file_merge(struct anv_device *device, int fd1, int fd2);
1140 uint32_t anv_gem_syncobj_create(struct anv_device *device, uint32_t flags);
1141 void anv_gem_syncobj_destroy(struct anv_device *device, uint32_t handle);
1142 int anv_gem_syncobj_handle_to_fd(struct anv_device *device, uint32_t handle);
1143 uint32_t anv_gem_syncobj_fd_to_handle(struct anv_device *device, int fd);
1144 int anv_gem_syncobj_export_sync_file(struct anv_device *device,
1146 int anv_gem_syncobj_import_sync_file(struct anv_device *device,
1147 uint32_t handle, int fd);
1148 void anv_gem_syncobj_reset(struct anv_device *device, uint32_t handle);
1149 bool anv_gem_supports_syncobj_wait(int fd);
1150 int anv_gem_syncobj_wait(struct anv_device *device,
1151 uint32_t *handles, uint32_t num_handles,
1152 int64_t abs_timeout_ns, bool wait_all);
1154 bool anv_vma_alloc(struct anv_device *device, struct anv_bo *bo);
1155 void anv_vma_free(struct anv_device *device, struct anv_bo *bo);
1157 VkResult anv_bo_init_new(struct anv_bo *bo, struct anv_device *device, uint64_t size);
1159 struct anv_reloc_list {
1160 uint32_t num_relocs;
1161 uint32_t array_length;
1162 struct drm_i915_gem_relocation_entry * relocs;
1163 struct anv_bo ** reloc_bos;
1167 VkResult anv_reloc_list_init(struct anv_reloc_list *list,
1168 const VkAllocationCallbacks *alloc);
1169 void anv_reloc_list_finish(struct anv_reloc_list *list,
1170 const VkAllocationCallbacks *alloc);
1172 VkResult anv_reloc_list_add(struct anv_reloc_list *list,
1173 const VkAllocationCallbacks *alloc,
1174 uint32_t offset, struct anv_bo *target_bo,
1177 struct anv_batch_bo {
1178 /* Link in the anv_cmd_buffer.owned_batch_bos list */
1179 struct list_head link;
1183 /* Bytes actually consumed in this batch BO */
1186 struct anv_reloc_list relocs;
1190 const VkAllocationCallbacks * alloc;
1196 struct anv_reloc_list * relocs;
1198 /* This callback is called (with the associated user data) in the event
1199 * that the batch runs out of space.
1201 VkResult (*extend_cb)(struct anv_batch *, void *);
1205 * Current error status of the command buffer. Used to track inconsistent
1206 * or incomplete command buffer states that are the consequence of run-time
1207 * errors such as out of memory scenarios. We want to track this in the
1208 * batch because the command buffer object is not visible to some parts
1214 void *anv_batch_emit_dwords(struct anv_batch *batch, int num_dwords);
1215 void anv_batch_emit_batch(struct anv_batch *batch, struct anv_batch *other);
1216 uint64_t anv_batch_emit_reloc(struct anv_batch *batch,
1217 void *location, struct anv_bo *bo, uint32_t offset);
1218 VkResult anv_device_submit_simple_batch(struct anv_device *device,
1219 struct anv_batch *batch);
1221 static inline VkResult
1222 anv_batch_set_error(struct anv_batch *batch, VkResult error)
1224 assert(error != VK_SUCCESS);
1225 if (batch->status == VK_SUCCESS)
1226 batch->status = error;
1227 return batch->status;
1231 anv_batch_has_error(struct anv_batch *batch)
1233 return batch->status != VK_SUCCESS;
1236 struct anv_address {
1241 #define ANV_NULL_ADDRESS ((struct anv_address) { NULL, 0 })
1244 anv_address_is_null(struct anv_address addr)
1246 return addr.bo == NULL && addr.offset == 0;
1249 static inline uint64_t
1250 anv_address_physical(struct anv_address addr)
1252 if (addr.bo && (addr.bo->flags & EXEC_OBJECT_PINNED))
1253 return gen_canonical_address(addr.bo->offset + addr.offset);
1255 return gen_canonical_address(addr.offset);
1258 static inline struct anv_address
1259 anv_address_add(struct anv_address addr, uint64_t offset)
1261 addr.offset += offset;
1266 write_reloc(const struct anv_device *device, void *p, uint64_t v, bool flush)
1268 unsigned reloc_size = 0;
1269 if (device->info.gen >= 8) {
1270 reloc_size = sizeof(uint64_t);
1271 *(uint64_t *)p = gen_canonical_address(v);
1273 reloc_size = sizeof(uint32_t);
1277 if (flush && !device->info.has_llc)
1278 gen_flush_range(p, reloc_size);
1281 static inline uint64_t
1282 _anv_combine_address(struct anv_batch *batch, void *location,
1283 const struct anv_address address, uint32_t delta)
1285 if (address.bo == NULL) {
1286 return address.offset + delta;
1288 assert(batch->start <= location && location < batch->end);
1290 return anv_batch_emit_reloc(batch, location, address.bo, address.offset + delta);
1294 #define __gen_address_type struct anv_address
1295 #define __gen_user_data struct anv_batch
1296 #define __gen_combine_address _anv_combine_address
1298 /* Wrapper macros needed to work around preprocessor argument issues. In
1299 * particular, arguments don't get pre-evaluated if they are concatenated.
1300 * This means that, if you pass GENX(3DSTATE_PS) into the emit macro, the
1301 * GENX macro won't get evaluated if the emit macro contains "cmd ## foo".
1302 * We can work around this easily enough with these helpers.
1304 #define __anv_cmd_length(cmd) cmd ## _length
1305 #define __anv_cmd_length_bias(cmd) cmd ## _length_bias
1306 #define __anv_cmd_header(cmd) cmd ## _header
1307 #define __anv_cmd_pack(cmd) cmd ## _pack
1308 #define __anv_reg_num(reg) reg ## _num
1310 #define anv_pack_struct(dst, struc, ...) do { \
1311 struct struc __template = { \
1314 __anv_cmd_pack(struc)(NULL, dst, &__template); \
1315 VG(VALGRIND_CHECK_MEM_IS_DEFINED(dst, __anv_cmd_length(struc) * 4)); \
1318 #define anv_batch_emitn(batch, n, cmd, ...) ({ \
1319 void *__dst = anv_batch_emit_dwords(batch, n); \
1321 struct cmd __template = { \
1322 __anv_cmd_header(cmd), \
1323 .DWordLength = n - __anv_cmd_length_bias(cmd), \
1326 __anv_cmd_pack(cmd)(batch, __dst, &__template); \
1331 #define anv_batch_emit_merge(batch, dwords0, dwords1) \
1335 STATIC_ASSERT(ARRAY_SIZE(dwords0) == ARRAY_SIZE(dwords1)); \
1336 dw = anv_batch_emit_dwords((batch), ARRAY_SIZE(dwords0)); \
1339 for (uint32_t i = 0; i < ARRAY_SIZE(dwords0); i++) \
1340 dw[i] = (dwords0)[i] | (dwords1)[i]; \
1341 VG(VALGRIND_CHECK_MEM_IS_DEFINED(dw, ARRAY_SIZE(dwords0) * 4));\
1344 #define anv_batch_emit(batch, cmd, name) \
1345 for (struct cmd name = { __anv_cmd_header(cmd) }, \
1346 *_dst = anv_batch_emit_dwords(batch, __anv_cmd_length(cmd)); \
1347 __builtin_expect(_dst != NULL, 1); \
1348 ({ __anv_cmd_pack(cmd)(batch, _dst, &name); \
1349 VG(VALGRIND_CHECK_MEM_IS_DEFINED(_dst, __anv_cmd_length(cmd) * 4)); \
1353 #define GEN7_MOCS (struct GEN7_MEMORY_OBJECT_CONTROL_STATE) { \
1354 .GraphicsDataTypeGFDT = 0, \
1355 .LLCCacheabilityControlLLCCC = 0, \
1356 .L3CacheabilityControlL3CC = 1, \
1359 #define GEN75_MOCS (struct GEN75_MEMORY_OBJECT_CONTROL_STATE) { \
1360 .LLCeLLCCacheabilityControlLLCCC = 0, \
1361 .L3CacheabilityControlL3CC = 1, \
1364 #define GEN8_MOCS (struct GEN8_MEMORY_OBJECT_CONTROL_STATE) { \
1365 .MemoryTypeLLCeLLCCacheabilityControl = WB, \
1366 .TargetCache = L3DefertoPATforLLCeLLCselection, \
1367 .AgeforQUADLRU = 0 \
1370 #define GEN8_EXTERNAL_MOCS (struct GEN8_MEMORY_OBJECT_CONTROL_STATE) { \
1371 .MemoryTypeLLCeLLCCacheabilityControl = UCwithFenceifcoherentcycle, \
1372 .TargetCache = L3DefertoPATforLLCeLLCselection, \
1373 .AgeforQUADLRU = 0 \
1376 /* Skylake: MOCS is now an index into an array of 62 different caching
1377 * configurations programmed by the kernel.
1380 #define GEN9_MOCS (struct GEN9_MEMORY_OBJECT_CONTROL_STATE) { \
1381 /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */ \
1382 .IndextoMOCSTables = 2 \
1385 #define GEN9_EXTERNAL_MOCS (struct GEN9_MEMORY_OBJECT_CONTROL_STATE) { \
1386 /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */ \
1387 .IndextoMOCSTables = 1 \
1390 /* Cannonlake MOCS defines are duplicates of Skylake MOCS defines. */
1391 #define GEN10_MOCS (struct GEN10_MEMORY_OBJECT_CONTROL_STATE) { \
1392 /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */ \
1393 .IndextoMOCSTables = 2 \
1396 #define GEN10_EXTERNAL_MOCS (struct GEN10_MEMORY_OBJECT_CONTROL_STATE) { \
1397 /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */ \
1398 .IndextoMOCSTables = 1 \
1401 /* Ice Lake MOCS defines are duplicates of Skylake MOCS defines. */
1402 #define GEN11_MOCS (struct GEN11_MEMORY_OBJECT_CONTROL_STATE) { \
1403 /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */ \
1404 .IndextoMOCSTables = 2 \
1407 #define GEN11_EXTERNAL_MOCS (struct GEN11_MEMORY_OBJECT_CONTROL_STATE) { \
1408 /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */ \
1409 .IndextoMOCSTables = 1 \
1412 struct anv_device_memory {
1414 struct anv_memory_type * type;
1415 VkDeviceSize map_size;
1420 * Header for Vertex URB Entry (VUE)
1422 struct anv_vue_header {
1424 uint32_t RTAIndex; /* RenderTargetArrayIndex */
1425 uint32_t ViewportIndex;
1429 struct anv_descriptor_set_binding_layout {
1431 /* The type of the descriptors in this binding */
1432 VkDescriptorType type;
1435 /* Number of array elements in this binding */
1436 uint16_t array_size;
1438 /* Index into the flattend descriptor set */
1439 uint16_t descriptor_index;
1441 /* Index into the dynamic state array for a dynamic buffer */
1442 int16_t dynamic_offset_index;
1444 /* Index into the descriptor set buffer views */
1445 int16_t buffer_index;
1448 /* Index into the binding table for the associated surface */
1449 int16_t surface_index;
1451 /* Index into the sampler table for the associated sampler */
1452 int16_t sampler_index;
1454 /* Index into the image table for the associated image */
1455 int16_t image_index;
1456 } stage[MESA_SHADER_STAGES];
1458 /* Immutable samplers (or NULL if no immutable samplers) */
1459 struct anv_sampler **immutable_samplers;
1462 struct anv_descriptor_set_layout {
1463 /* Descriptor set layouts can be destroyed at almost any time */
1466 /* Number of bindings in this descriptor set */
1467 uint16_t binding_count;
1469 /* Total size of the descriptor set with room for all array entries */
1472 /* Shader stages affected by this descriptor set */
1473 uint16_t shader_stages;
1475 /* Number of buffers in this descriptor set */
1476 uint16_t buffer_count;
1478 /* Number of dynamic offsets used by this descriptor set */
1479 uint16_t dynamic_offset_count;
1481 /* Bindings in this descriptor set */
1482 struct anv_descriptor_set_binding_layout binding[0];
1486 anv_descriptor_set_layout_ref(struct anv_descriptor_set_layout *layout)
1488 assert(layout && layout->ref_cnt >= 1);
1489 p_atomic_inc(&layout->ref_cnt);
1493 anv_descriptor_set_layout_unref(struct anv_device *device,
1494 struct anv_descriptor_set_layout *layout)
1496 assert(layout && layout->ref_cnt >= 1);
1497 if (p_atomic_dec_zero(&layout->ref_cnt))
1498 vk_free(&device->alloc, layout);
1501 struct anv_descriptor {
1502 VkDescriptorType type;
1506 VkImageLayout layout;
1507 struct anv_image_view *image_view;
1508 struct anv_sampler *sampler;
1512 struct anv_buffer *buffer;
1517 struct anv_buffer_view *buffer_view;
1521 struct anv_descriptor_set {
1522 struct anv_descriptor_set_layout *layout;
1524 uint32_t buffer_count;
1525 struct anv_buffer_view *buffer_views;
1527 /* Link to descriptor pool's desc_sets list . */
1528 struct list_head pool_link;
1530 struct anv_descriptor descriptors[0];
1533 struct anv_buffer_view {
1534 enum isl_format format; /**< VkBufferViewCreateInfo::format */
1535 uint64_t range; /**< VkBufferViewCreateInfo::range */
1537 struct anv_address address;
1539 struct anv_state surface_state;
1540 struct anv_state storage_surface_state;
1541 struct anv_state writeonly_storage_surface_state;
1543 struct brw_image_param storage_image_param;
1546 struct anv_push_descriptor_set {
1547 struct anv_descriptor_set set;
1549 /* Put this field right behind anv_descriptor_set so it fills up the
1550 * descriptors[0] field. */
1551 struct anv_descriptor descriptors[MAX_PUSH_DESCRIPTORS];
1552 struct anv_buffer_view buffer_views[MAX_PUSH_DESCRIPTORS];
1555 struct anv_descriptor_pool {
1560 struct anv_state_stream surface_state_stream;
1561 void *surface_state_free_list;
1563 struct list_head desc_sets;
1568 enum anv_descriptor_template_entry_type {
1569 ANV_DESCRIPTOR_TEMPLATE_ENTRY_TYPE_IMAGE,
1570 ANV_DESCRIPTOR_TEMPLATE_ENTRY_TYPE_BUFFER,
1571 ANV_DESCRIPTOR_TEMPLATE_ENTRY_TYPE_BUFFER_VIEW
1574 struct anv_descriptor_template_entry {
1575 /* The type of descriptor in this entry */
1576 VkDescriptorType type;
1578 /* Binding in the descriptor set */
1581 /* Offset at which to write into the descriptor set binding */
1582 uint32_t array_element;
1584 /* Number of elements to write into the descriptor set binding */
1585 uint32_t array_count;
1587 /* Offset into the user provided data */
1590 /* Stride between elements into the user provided data */
1594 struct anv_descriptor_update_template {
1595 VkPipelineBindPoint bind_point;
1597 /* The descriptor set this template corresponds to. This value is only
1598 * valid if the template was created with the templateType
1599 * VK_DESCRIPTOR_UPDATE_TEMPLATE_TYPE_DESCRIPTOR_SET_KHR.
1603 /* Number of entries in this template */
1604 uint32_t entry_count;
1606 /* Entries of the template */
1607 struct anv_descriptor_template_entry entries[0];
1611 anv_descriptor_set_layout_size(const struct anv_descriptor_set_layout *layout);
1614 anv_descriptor_set_write_image_view(struct anv_descriptor_set *set,
1615 const struct gen_device_info * const devinfo,
1616 const VkDescriptorImageInfo * const info,
1617 VkDescriptorType type,
1622 anv_descriptor_set_write_buffer_view(struct anv_descriptor_set *set,
1623 VkDescriptorType type,
1624 struct anv_buffer_view *buffer_view,
1629 anv_descriptor_set_write_buffer(struct anv_descriptor_set *set,
1630 struct anv_device *device,
1631 struct anv_state_stream *alloc_stream,
1632 VkDescriptorType type,
1633 struct anv_buffer *buffer,
1636 VkDeviceSize offset,
1637 VkDeviceSize range);
1640 anv_descriptor_set_write_template(struct anv_descriptor_set *set,
1641 struct anv_device *device,
1642 struct anv_state_stream *alloc_stream,
1643 const struct anv_descriptor_update_template *template,
1647 anv_descriptor_set_create(struct anv_device *device,
1648 struct anv_descriptor_pool *pool,
1649 struct anv_descriptor_set_layout *layout,
1650 struct anv_descriptor_set **out_set);
1653 anv_descriptor_set_destroy(struct anv_device *device,
1654 struct anv_descriptor_pool *pool,
1655 struct anv_descriptor_set *set);
1657 #define ANV_DESCRIPTOR_SET_SHADER_CONSTANTS (UINT8_MAX - 1)
1658 #define ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS UINT8_MAX
1660 struct anv_pipeline_binding {
1661 /* The descriptor set this surface corresponds to. The special value of
1662 * ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS indicates that the offset refers
1663 * to a color attachment and not a regular descriptor.
1667 /* Binding in the descriptor set */
1670 /* Index in the binding */
1673 /* Plane in the binding index */
1676 /* Input attachment index (relative to the subpass) */
1677 uint8_t input_attachment_index;
1679 /* For a storage image, whether it is write-only */
1683 struct anv_pipeline_layout {
1685 struct anv_descriptor_set_layout *layout;
1686 uint32_t dynamic_offset_start;
1692 bool has_dynamic_offsets;
1693 } stage[MESA_SHADER_STAGES];
1695 unsigned char sha1[20];
1699 struct anv_device * device;
1702 VkBufferUsageFlags usage;
1704 /* Set when bound */
1705 struct anv_address address;
1708 static inline uint64_t
1709 anv_buffer_get_range(struct anv_buffer *buffer, uint64_t offset, uint64_t range)
1711 assert(offset <= buffer->size);
1712 if (range == VK_WHOLE_SIZE) {
1713 return buffer->size - offset;
1715 assert(range + offset >= range);
1716 assert(range + offset <= buffer->size);
1721 enum anv_cmd_dirty_bits {
1722 ANV_CMD_DIRTY_DYNAMIC_VIEWPORT = 1 << 0, /* VK_DYNAMIC_STATE_VIEWPORT */
1723 ANV_CMD_DIRTY_DYNAMIC_SCISSOR = 1 << 1, /* VK_DYNAMIC_STATE_SCISSOR */
1724 ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH = 1 << 2, /* VK_DYNAMIC_STATE_LINE_WIDTH */
1725 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS = 1 << 3, /* VK_DYNAMIC_STATE_DEPTH_BIAS */
1726 ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS = 1 << 4, /* VK_DYNAMIC_STATE_BLEND_CONSTANTS */
1727 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS = 1 << 5, /* VK_DYNAMIC_STATE_DEPTH_BOUNDS */
1728 ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK = 1 << 6, /* VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK */
1729 ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK = 1 << 7, /* VK_DYNAMIC_STATE_STENCIL_WRITE_MASK */
1730 ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE = 1 << 8, /* VK_DYNAMIC_STATE_STENCIL_REFERENCE */
1731 ANV_CMD_DIRTY_DYNAMIC_ALL = (1 << 9) - 1,
1732 ANV_CMD_DIRTY_PIPELINE = 1 << 9,
1733 ANV_CMD_DIRTY_INDEX_BUFFER = 1 << 10,
1734 ANV_CMD_DIRTY_RENDER_TARGETS = 1 << 11,
1736 typedef uint32_t anv_cmd_dirty_mask_t;
1738 enum anv_pipe_bits {
1739 ANV_PIPE_DEPTH_CACHE_FLUSH_BIT = (1 << 0),
1740 ANV_PIPE_STALL_AT_SCOREBOARD_BIT = (1 << 1),
1741 ANV_PIPE_STATE_CACHE_INVALIDATE_BIT = (1 << 2),
1742 ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT = (1 << 3),
1743 ANV_PIPE_VF_CACHE_INVALIDATE_BIT = (1 << 4),
1744 ANV_PIPE_DATA_CACHE_FLUSH_BIT = (1 << 5),
1745 ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT = (1 << 10),
1746 ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT = (1 << 11),
1747 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT = (1 << 12),
1748 ANV_PIPE_DEPTH_STALL_BIT = (1 << 13),
1749 ANV_PIPE_CS_STALL_BIT = (1 << 20),
1751 /* This bit does not exist directly in PIPE_CONTROL. Instead it means that
1752 * a flush has happened but not a CS stall. The next time we do any sort
1753 * of invalidation we need to insert a CS stall at that time. Otherwise,
1754 * we would have to CS stall on every flush which could be bad.
1756 ANV_PIPE_NEEDS_CS_STALL_BIT = (1 << 21),
1758 /* This bit does not exist directly in PIPE_CONTROL. It means that render
1759 * target operations are ongoing. Some operations like copies on the
1760 * command streamer might need to be aware of this to trigger the
1761 * appropriate stall before they can proceed with the copy.
1763 ANV_PIPE_RENDER_TARGET_WRITES = (1 << 22),
1766 #define ANV_PIPE_FLUSH_BITS ( \
1767 ANV_PIPE_DEPTH_CACHE_FLUSH_BIT | \
1768 ANV_PIPE_DATA_CACHE_FLUSH_BIT | \
1769 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT)
1771 #define ANV_PIPE_STALL_BITS ( \
1772 ANV_PIPE_STALL_AT_SCOREBOARD_BIT | \
1773 ANV_PIPE_DEPTH_STALL_BIT | \
1774 ANV_PIPE_CS_STALL_BIT)
1776 #define ANV_PIPE_INVALIDATE_BITS ( \
1777 ANV_PIPE_STATE_CACHE_INVALIDATE_BIT | \
1778 ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT | \
1779 ANV_PIPE_VF_CACHE_INVALIDATE_BIT | \
1780 ANV_PIPE_DATA_CACHE_FLUSH_BIT | \
1781 ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT | \
1782 ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT)
1784 static inline enum anv_pipe_bits
1785 anv_pipe_flush_bits_for_access_flags(VkAccessFlags flags)
1787 enum anv_pipe_bits pipe_bits = 0;
1790 for_each_bit(b, flags) {
1791 switch ((VkAccessFlagBits)(1 << b)) {
1792 case VK_ACCESS_SHADER_WRITE_BIT:
1793 pipe_bits |= ANV_PIPE_DATA_CACHE_FLUSH_BIT;
1795 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT:
1796 pipe_bits |= ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT;
1798 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT:
1799 pipe_bits |= ANV_PIPE_DEPTH_CACHE_FLUSH_BIT;
1801 case VK_ACCESS_TRANSFER_WRITE_BIT:
1802 pipe_bits |= ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT;
1803 pipe_bits |= ANV_PIPE_DEPTH_CACHE_FLUSH_BIT;
1805 case VK_ACCESS_MEMORY_WRITE_BIT:
1806 pipe_bits |= ANV_PIPE_FLUSH_BITS;
1809 break; /* Nothing to do */
1816 static inline enum anv_pipe_bits
1817 anv_pipe_invalidate_bits_for_access_flags(VkAccessFlags flags)
1819 enum anv_pipe_bits pipe_bits = 0;
1822 for_each_bit(b, flags) {
1823 switch ((VkAccessFlagBits)(1 << b)) {
1824 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT:
1825 case VK_ACCESS_INDEX_READ_BIT:
1826 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT:
1827 pipe_bits |= ANV_PIPE_VF_CACHE_INVALIDATE_BIT;
1829 case VK_ACCESS_UNIFORM_READ_BIT:
1830 pipe_bits |= ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT;
1831 pipe_bits |= ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT;
1833 case VK_ACCESS_SHADER_READ_BIT:
1834 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT:
1835 case VK_ACCESS_TRANSFER_READ_BIT:
1836 pipe_bits |= ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT;
1838 case VK_ACCESS_MEMORY_READ_BIT:
1839 pipe_bits |= ANV_PIPE_INVALIDATE_BITS;
1841 case VK_ACCESS_MEMORY_WRITE_BIT:
1842 pipe_bits |= ANV_PIPE_FLUSH_BITS;
1845 break; /* Nothing to do */
1852 #define VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV ( \
1853 VK_IMAGE_ASPECT_COLOR_BIT | \
1854 VK_IMAGE_ASPECT_PLANE_0_BIT | \
1855 VK_IMAGE_ASPECT_PLANE_1_BIT | \
1856 VK_IMAGE_ASPECT_PLANE_2_BIT)
1857 #define VK_IMAGE_ASPECT_PLANES_BITS_ANV ( \
1858 VK_IMAGE_ASPECT_PLANE_0_BIT | \
1859 VK_IMAGE_ASPECT_PLANE_1_BIT | \
1860 VK_IMAGE_ASPECT_PLANE_2_BIT)
1862 struct anv_vertex_binding {
1863 struct anv_buffer * buffer;
1864 VkDeviceSize offset;
1867 #define ANV_PARAM_PUSH(offset) ((1 << 16) | (uint32_t)(offset))
1868 #define ANV_PARAM_PUSH_OFFSET(param) ((param) & 0xffff)
1870 struct anv_push_constants {
1871 /* Current allocated size of this push constants data structure.
1872 * Because a decent chunk of it may not be used (images on SKL, for
1873 * instance), we won't actually allocate the entire structure up-front.
1877 /* Push constant data provided by the client through vkPushConstants */
1878 uint8_t client_data[MAX_PUSH_CONSTANTS_SIZE];
1880 /* Used for vkCmdDispatchBase */
1881 uint32_t base_work_group_id[3];
1883 /* Image data for image_load_store on pre-SKL */
1884 struct brw_image_param images[MAX_GEN8_IMAGES];
1887 struct anv_dynamic_state {
1890 VkViewport viewports[MAX_VIEWPORTS];
1895 VkRect2D scissors[MAX_SCISSORS];
1906 float blend_constants[4];
1916 } stencil_compare_mask;
1921 } stencil_write_mask;
1926 } stencil_reference;
1929 extern const struct anv_dynamic_state default_dynamic_state;
1931 void anv_dynamic_state_copy(struct anv_dynamic_state *dest,
1932 const struct anv_dynamic_state *src,
1933 uint32_t copy_mask);
1935 struct anv_surface_state {
1936 struct anv_state state;
1937 /** Address of the surface referred to by this state
1939 * This address is relative to the start of the BO.
1941 struct anv_address address;
1942 /* Address of the aux surface, if any
1944 * This field is ANV_NULL_ADDRESS if and only if no aux surface exists.
1946 * With the exception of gen8, the bottom 12 bits of this address' offset
1947 * include extra aux information.
1949 struct anv_address aux_address;
1950 /* Address of the clear color, if any
1952 * This address is relative to the start of the BO.
1954 struct anv_address clear_address;
1958 * Attachment state when recording a renderpass instance.
1960 * The clear value is valid only if there exists a pending clear.
1962 struct anv_attachment_state {
1963 enum isl_aux_usage aux_usage;
1964 enum isl_aux_usage input_aux_usage;
1965 struct anv_surface_state color;
1966 struct anv_surface_state input;
1968 VkImageLayout current_layout;
1969 VkImageAspectFlags pending_clear_aspects;
1970 VkImageAspectFlags pending_load_aspects;
1972 VkClearValue clear_value;
1973 bool clear_color_is_zero_one;
1974 bool clear_color_is_zero;
1976 /* When multiview is active, attachments with a renderpass clear
1977 * operation have their respective layers cleared on the first
1978 * subpass that uses them, and only in that subpass. We keep track
1979 * of this using a bitfield to indicate which layers of an attachment
1980 * have not been cleared yet when multiview is active.
1982 uint32_t pending_clear_views;
1985 /** State tracking for particular pipeline bind point
1987 * This struct is the base struct for anv_cmd_graphics_state and
1988 * anv_cmd_compute_state. These are used to track state which is bound to a
1989 * particular type of pipeline. Generic state that applies per-stage such as
1990 * binding table offsets and push constants is tracked generically with a
1991 * per-stage array in anv_cmd_state.
1993 struct anv_cmd_pipeline_state {
1994 struct anv_pipeline *pipeline;
1995 struct anv_pipeline_layout *layout;
1997 struct anv_descriptor_set *descriptors[MAX_SETS];
1998 uint32_t dynamic_offsets[MAX_DYNAMIC_BUFFERS];
2000 struct anv_push_descriptor_set *push_descriptors[MAX_SETS];
2003 /** State tracking for graphics pipeline
2005 * This has anv_cmd_pipeline_state as a base struct to track things which get
2006 * bound to a graphics pipeline. Along with general pipeline bind point state
2007 * which is in the anv_cmd_pipeline_state base struct, it also contains other
2008 * state which is graphics-specific.
2010 struct anv_cmd_graphics_state {
2011 struct anv_cmd_pipeline_state base;
2013 anv_cmd_dirty_mask_t dirty;
2016 struct anv_dynamic_state dynamic;
2019 struct anv_buffer *index_buffer;
2020 uint32_t index_type; /**< 3DSTATE_INDEX_BUFFER.IndexFormat */
2021 uint32_t index_offset;
2025 /** State tracking for compute pipeline
2027 * This has anv_cmd_pipeline_state as a base struct to track things which get
2028 * bound to a compute pipeline. Along with general pipeline bind point state
2029 * which is in the anv_cmd_pipeline_state base struct, it also contains other
2030 * state which is compute-specific.
2032 struct anv_cmd_compute_state {
2033 struct anv_cmd_pipeline_state base;
2035 bool pipeline_dirty;
2037 struct anv_address num_workgroups;
2040 /** State required while building cmd buffer */
2041 struct anv_cmd_state {
2042 /* PIPELINE_SELECT.PipelineSelection */
2043 uint32_t current_pipeline;
2044 const struct gen_l3_config * current_l3_config;
2046 struct anv_cmd_graphics_state gfx;
2047 struct anv_cmd_compute_state compute;
2049 enum anv_pipe_bits pending_pipe_bits;
2050 VkShaderStageFlags descriptors_dirty;
2051 VkShaderStageFlags push_constants_dirty;
2053 struct anv_framebuffer * framebuffer;
2054 struct anv_render_pass * pass;
2055 struct anv_subpass * subpass;
2056 VkRect2D render_area;
2057 uint32_t restart_index;
2058 struct anv_vertex_binding vertex_bindings[MAX_VBS];
2059 VkShaderStageFlags push_constant_stages;
2060 struct anv_push_constants * push_constants[MESA_SHADER_STAGES];
2061 struct anv_state binding_tables[MESA_SHADER_STAGES];
2062 struct anv_state samplers[MESA_SHADER_STAGES];
2065 * Whether or not the gen8 PMA fix is enabled. We ensure that, at the top
2066 * of any command buffer it is disabled by disabling it in EndCommandBuffer
2067 * and before invoking the secondary in ExecuteCommands.
2069 bool pma_fix_enabled;
2072 * Whether or not we know for certain that HiZ is enabled for the current
2073 * subpass. If, for whatever reason, we are unsure as to whether HiZ is
2074 * enabled or not, this will be false.
2079 * Array length is anv_cmd_state::pass::attachment_count. Array content is
2080 * valid only when recording a render pass instance.
2082 struct anv_attachment_state * attachments;
2085 * Surface states for color render targets. These are stored in a single
2086 * flat array. For depth-stencil attachments, the surface state is simply
2089 struct anv_state render_pass_states;
2092 * A null surface state of the right size to match the framebuffer. This
2093 * is one of the states in render_pass_states.
2095 struct anv_state null_surface_state;
2098 struct anv_cmd_pool {
2099 VkAllocationCallbacks alloc;
2100 struct list_head cmd_buffers;
2103 #define ANV_CMD_BUFFER_BATCH_SIZE 8192
2105 enum anv_cmd_buffer_exec_mode {
2106 ANV_CMD_BUFFER_EXEC_MODE_PRIMARY,
2107 ANV_CMD_BUFFER_EXEC_MODE_EMIT,
2108 ANV_CMD_BUFFER_EXEC_MODE_GROW_AND_EMIT,
2109 ANV_CMD_BUFFER_EXEC_MODE_CHAIN,
2110 ANV_CMD_BUFFER_EXEC_MODE_COPY_AND_CHAIN,
2113 struct anv_cmd_buffer {
2114 VK_LOADER_DATA _loader_data;
2116 struct anv_device * device;
2118 struct anv_cmd_pool * pool;
2119 struct list_head pool_link;
2121 struct anv_batch batch;
2123 /* Fields required for the actual chain of anv_batch_bo's.
2125 * These fields are initialized by anv_cmd_buffer_init_batch_bo_chain().
2127 struct list_head batch_bos;
2128 enum anv_cmd_buffer_exec_mode exec_mode;
2130 /* A vector of anv_batch_bo pointers for every batch or surface buffer
2131 * referenced by this command buffer
2133 * initialized by anv_cmd_buffer_init_batch_bo_chain()
2135 struct u_vector seen_bbos;
2137 /* A vector of int32_t's for every block of binding tables.
2139 * initialized by anv_cmd_buffer_init_batch_bo_chain()
2141 struct u_vector bt_block_states;
2144 struct anv_reloc_list surface_relocs;
2145 /** Last seen surface state block pool center bo offset */
2146 uint32_t last_ss_pool_center;
2148 /* Serial for tracking buffer completion */
2151 /* Stream objects for storing temporary data */
2152 struct anv_state_stream surface_state_stream;
2153 struct anv_state_stream dynamic_state_stream;
2155 VkCommandBufferUsageFlags usage_flags;
2156 VkCommandBufferLevel level;
2158 struct anv_cmd_state state;
2161 VkResult anv_cmd_buffer_init_batch_bo_chain(struct anv_cmd_buffer *cmd_buffer);
2162 void anv_cmd_buffer_fini_batch_bo_chain(struct anv_cmd_buffer *cmd_buffer);
2163 void anv_cmd_buffer_reset_batch_bo_chain(struct anv_cmd_buffer *cmd_buffer);
2164 void anv_cmd_buffer_end_batch_buffer(struct anv_cmd_buffer *cmd_buffer);
2165 void anv_cmd_buffer_add_secondary(struct anv_cmd_buffer *primary,
2166 struct anv_cmd_buffer *secondary);
2167 void anv_cmd_buffer_prepare_execbuf(struct anv_cmd_buffer *cmd_buffer);
2168 VkResult anv_cmd_buffer_execbuf(struct anv_device *device,
2169 struct anv_cmd_buffer *cmd_buffer,
2170 const VkSemaphore *in_semaphores,
2171 uint32_t num_in_semaphores,
2172 const VkSemaphore *out_semaphores,
2173 uint32_t num_out_semaphores,
2176 VkResult anv_cmd_buffer_reset(struct anv_cmd_buffer *cmd_buffer);
2179 anv_cmd_buffer_ensure_push_constants_size(struct anv_cmd_buffer *cmd_buffer,
2180 gl_shader_stage stage, uint32_t size);
2181 #define anv_cmd_buffer_ensure_push_constant_field(cmd_buffer, stage, field) \
2182 anv_cmd_buffer_ensure_push_constants_size(cmd_buffer, stage, \
2183 (offsetof(struct anv_push_constants, field) + \
2184 sizeof(cmd_buffer->state.push_constants[0]->field)))
2186 struct anv_state anv_cmd_buffer_emit_dynamic(struct anv_cmd_buffer *cmd_buffer,
2187 const void *data, uint32_t size, uint32_t alignment);
2188 struct anv_state anv_cmd_buffer_merge_dynamic(struct anv_cmd_buffer *cmd_buffer,
2189 uint32_t *a, uint32_t *b,
2190 uint32_t dwords, uint32_t alignment);
2193 anv_cmd_buffer_surface_base_address(struct anv_cmd_buffer *cmd_buffer);
2195 anv_cmd_buffer_alloc_binding_table(struct anv_cmd_buffer *cmd_buffer,
2196 uint32_t entries, uint32_t *state_offset);
2198 anv_cmd_buffer_alloc_surface_state(struct anv_cmd_buffer *cmd_buffer);
2200 anv_cmd_buffer_alloc_dynamic_state(struct anv_cmd_buffer *cmd_buffer,
2201 uint32_t size, uint32_t alignment);
2204 anv_cmd_buffer_new_binding_table_block(struct anv_cmd_buffer *cmd_buffer);
2206 void gen8_cmd_buffer_emit_viewport(struct anv_cmd_buffer *cmd_buffer);
2207 void gen8_cmd_buffer_emit_depth_viewport(struct anv_cmd_buffer *cmd_buffer,
2208 bool depth_clamp_enable);
2209 void gen7_cmd_buffer_emit_scissor(struct anv_cmd_buffer *cmd_buffer);
2211 void anv_cmd_buffer_setup_attachments(struct anv_cmd_buffer *cmd_buffer,
2212 struct anv_render_pass *pass,
2213 struct anv_framebuffer *framebuffer,
2214 const VkClearValue *clear_values);
2216 void anv_cmd_buffer_emit_state_base_address(struct anv_cmd_buffer *cmd_buffer);
2219 anv_cmd_buffer_push_constants(struct anv_cmd_buffer *cmd_buffer,
2220 gl_shader_stage stage);
2222 anv_cmd_buffer_cs_push_constants(struct anv_cmd_buffer *cmd_buffer);
2224 void anv_cmd_buffer_resolve_subpass(struct anv_cmd_buffer *cmd_buffer);
2226 const struct anv_image_view *
2227 anv_cmd_buffer_get_depth_stencil_view(const struct anv_cmd_buffer *cmd_buffer);
2230 anv_cmd_buffer_alloc_blorp_binding_table(struct anv_cmd_buffer *cmd_buffer,
2231 uint32_t num_entries,
2232 uint32_t *state_offset,
2233 struct anv_state *bt_state);
2235 void anv_cmd_buffer_dump(struct anv_cmd_buffer *cmd_buffer);
2237 enum anv_fence_type {
2238 ANV_FENCE_TYPE_NONE = 0,
2240 ANV_FENCE_TYPE_SYNCOBJ,
2244 enum anv_bo_fence_state {
2245 /** Indicates that this is a new (or newly reset fence) */
2246 ANV_BO_FENCE_STATE_RESET,
2248 /** Indicates that this fence has been submitted to the GPU but is still
2249 * (as far as we know) in use by the GPU.
2251 ANV_BO_FENCE_STATE_SUBMITTED,
2253 ANV_BO_FENCE_STATE_SIGNALED,
2256 struct anv_fence_impl {
2257 enum anv_fence_type type;
2260 /** Fence implementation for BO fences
2262 * These fences use a BO and a set of CPU-tracked state flags. The BO
2263 * is added to the object list of the last execbuf call in a QueueSubmit
2264 * and is marked EXEC_WRITE. The state flags track when the BO has been
2265 * submitted to the kernel. We need to do this because Vulkan lets you
2266 * wait on a fence that has not yet been submitted and I915_GEM_BUSY
2267 * will say it's idle in this case.
2271 enum anv_bo_fence_state state;
2274 /** DRM syncobj handle for syncobj-based fences */
2278 struct wsi_fence *fence_wsi;
2283 /* Permanent fence state. Every fence has some form of permanent state
2284 * (type != ANV_SEMAPHORE_TYPE_NONE). This may be a BO to fence on (for
2285 * cross-process fences) or it could just be a dummy for use internally.
2287 struct anv_fence_impl permanent;
2289 /* Temporary fence state. A fence *may* have temporary state. That state
2290 * is added to the fence by an import operation and is reset back to
2291 * ANV_SEMAPHORE_TYPE_NONE when the fence is reset. A fence with temporary
2292 * state cannot be signaled because the fence must already be signaled
2293 * before the temporary state can be exported from the fence in the other
2294 * process and imported here.
2296 struct anv_fence_impl temporary;
2301 struct anv_state state;
2304 enum anv_semaphore_type {
2305 ANV_SEMAPHORE_TYPE_NONE = 0,
2306 ANV_SEMAPHORE_TYPE_DUMMY,
2307 ANV_SEMAPHORE_TYPE_BO,
2308 ANV_SEMAPHORE_TYPE_SYNC_FILE,
2309 ANV_SEMAPHORE_TYPE_DRM_SYNCOBJ,
2312 struct anv_semaphore_impl {
2313 enum anv_semaphore_type type;
2316 /* A BO representing this semaphore when type == ANV_SEMAPHORE_TYPE_BO.
2317 * This BO will be added to the object list on any execbuf2 calls for
2318 * which this semaphore is used as a wait or signal fence. When used as
2319 * a signal fence, the EXEC_OBJECT_WRITE flag will be set.
2323 /* The sync file descriptor when type == ANV_SEMAPHORE_TYPE_SYNC_FILE.
2324 * If the semaphore is in the unsignaled state due to either just being
2325 * created or because it has been used for a wait, fd will be -1.
2329 /* Sync object handle when type == ANV_SEMAPHORE_TYPE_DRM_SYNCOBJ.
2330 * Unlike GEM BOs, DRM sync objects aren't deduplicated by the kernel on
2331 * import so we don't need to bother with a userspace cache.
2337 struct anv_semaphore {
2338 /* Permanent semaphore state. Every semaphore has some form of permanent
2339 * state (type != ANV_SEMAPHORE_TYPE_NONE). This may be a BO to fence on
2340 * (for cross-process semaphores0 or it could just be a dummy for use
2343 struct anv_semaphore_impl permanent;
2345 /* Temporary semaphore state. A semaphore *may* have temporary state.
2346 * That state is added to the semaphore by an import operation and is reset
2347 * back to ANV_SEMAPHORE_TYPE_NONE when the semaphore is waited on. A
2348 * semaphore with temporary state cannot be signaled because the semaphore
2349 * must already be signaled before the temporary state can be exported from
2350 * the semaphore in the other process and imported here.
2352 struct anv_semaphore_impl temporary;
2355 void anv_semaphore_reset_temporary(struct anv_device *device,
2356 struct anv_semaphore *semaphore);
2358 struct anv_shader_module {
2359 unsigned char sha1[20];
2364 static inline gl_shader_stage
2365 vk_to_mesa_shader_stage(VkShaderStageFlagBits vk_stage)
2367 assert(__builtin_popcount(vk_stage) == 1);
2368 return ffs(vk_stage) - 1;
2371 static inline VkShaderStageFlagBits
2372 mesa_to_vk_shader_stage(gl_shader_stage mesa_stage)
2374 return (1 << mesa_stage);
2377 #define ANV_STAGE_MASK ((1 << MESA_SHADER_STAGES) - 1)
2379 #define anv_foreach_stage(stage, stage_bits) \
2380 for (gl_shader_stage stage, \
2381 __tmp = (gl_shader_stage)((stage_bits) & ANV_STAGE_MASK); \
2382 stage = __builtin_ffs(__tmp) - 1, __tmp; \
2383 __tmp &= ~(1 << (stage)))
2385 struct anv_pipeline_bind_map {
2386 uint32_t surface_count;
2387 uint32_t sampler_count;
2388 uint32_t image_count;
2390 struct anv_pipeline_binding * surface_to_descriptor;
2391 struct anv_pipeline_binding * sampler_to_descriptor;
2394 struct anv_shader_bin_key {
2399 struct anv_shader_bin {
2402 const struct anv_shader_bin_key *key;
2404 struct anv_state kernel;
2405 uint32_t kernel_size;
2407 struct anv_state constant_data;
2408 uint32_t constant_data_size;
2410 const struct brw_stage_prog_data *prog_data;
2411 uint32_t prog_data_size;
2413 struct anv_pipeline_bind_map bind_map;
2416 struct anv_shader_bin *
2417 anv_shader_bin_create(struct anv_device *device,
2418 const void *key, uint32_t key_size,
2419 const void *kernel, uint32_t kernel_size,
2420 const void *constant_data, uint32_t constant_data_size,
2421 const struct brw_stage_prog_data *prog_data,
2422 uint32_t prog_data_size, const void *prog_data_param,
2423 const struct anv_pipeline_bind_map *bind_map);
2426 anv_shader_bin_destroy(struct anv_device *device, struct anv_shader_bin *shader);
2429 anv_shader_bin_ref(struct anv_shader_bin *shader)
2431 assert(shader && shader->ref_cnt >= 1);
2432 p_atomic_inc(&shader->ref_cnt);
2436 anv_shader_bin_unref(struct anv_device *device, struct anv_shader_bin *shader)
2438 assert(shader && shader->ref_cnt >= 1);
2439 if (p_atomic_dec_zero(&shader->ref_cnt))
2440 anv_shader_bin_destroy(device, shader);
2443 struct anv_pipeline {
2444 struct anv_device * device;
2445 struct anv_batch batch;
2446 uint32_t batch_data[512];
2447 struct anv_reloc_list batch_relocs;
2448 uint32_t dynamic_state_mask;
2449 struct anv_dynamic_state dynamic_state;
2451 struct anv_subpass * subpass;
2453 bool needs_data_cache;
2455 struct anv_shader_bin * shaders[MESA_SHADER_STAGES];
2458 const struct gen_l3_config * l3_config;
2459 uint32_t total_size;
2462 VkShaderStageFlags active_stages;
2463 struct anv_state blend_state;
2466 struct anv_pipeline_vertex_binding {
2469 uint32_t instance_divisor;
2472 bool primitive_restart;
2475 uint32_t cs_right_mask;
2478 bool depth_test_enable;
2479 bool writes_stencil;
2480 bool stencil_test_enable;
2481 bool depth_clamp_enable;
2482 bool sample_shading_enable;
2487 uint32_t depth_stencil_state[3];
2493 uint32_t wm_depth_stencil[3];
2497 uint32_t wm_depth_stencil[4];
2500 uint32_t interface_descriptor_data[8];
2504 anv_pipeline_has_stage(const struct anv_pipeline *pipeline,
2505 gl_shader_stage stage)
2507 return (pipeline->active_stages & mesa_to_vk_shader_stage(stage)) != 0;
2510 #define ANV_DECL_GET_PROG_DATA_FUNC(prefix, stage) \
2511 static inline const struct brw_##prefix##_prog_data * \
2512 get_##prefix##_prog_data(const struct anv_pipeline *pipeline) \
2514 if (anv_pipeline_has_stage(pipeline, stage)) { \
2515 return (const struct brw_##prefix##_prog_data *) \
2516 pipeline->shaders[stage]->prog_data; \
2522 ANV_DECL_GET_PROG_DATA_FUNC(vs, MESA_SHADER_VERTEX)
2523 ANV_DECL_GET_PROG_DATA_FUNC(tcs, MESA_SHADER_TESS_CTRL)
2524 ANV_DECL_GET_PROG_DATA_FUNC(tes, MESA_SHADER_TESS_EVAL)
2525 ANV_DECL_GET_PROG_DATA_FUNC(gs, MESA_SHADER_GEOMETRY)
2526 ANV_DECL_GET_PROG_DATA_FUNC(wm, MESA_SHADER_FRAGMENT)
2527 ANV_DECL_GET_PROG_DATA_FUNC(cs, MESA_SHADER_COMPUTE)
2529 static inline const struct brw_vue_prog_data *
2530 anv_pipeline_get_last_vue_prog_data(const struct anv_pipeline *pipeline)
2532 if (anv_pipeline_has_stage(pipeline, MESA_SHADER_GEOMETRY))
2533 return &get_gs_prog_data(pipeline)->base;
2534 else if (anv_pipeline_has_stage(pipeline, MESA_SHADER_TESS_EVAL))
2535 return &get_tes_prog_data(pipeline)->base;
2537 return &get_vs_prog_data(pipeline)->base;
2541 anv_pipeline_init(struct anv_pipeline *pipeline, struct anv_device *device,
2542 struct anv_pipeline_cache *cache,
2543 const VkGraphicsPipelineCreateInfo *pCreateInfo,
2544 const VkAllocationCallbacks *alloc);
2547 anv_pipeline_compile_cs(struct anv_pipeline *pipeline,
2548 struct anv_pipeline_cache *cache,
2549 const VkComputePipelineCreateInfo *info,
2550 const struct anv_shader_module *module,
2551 const char *entrypoint,
2552 const VkSpecializationInfo *spec_info);
2554 struct anv_format_plane {
2555 enum isl_format isl_format:16;
2556 struct isl_swizzle swizzle;
2558 /* Whether this plane contains chroma channels */
2561 /* For downscaling of YUV planes */
2562 uint8_t denominator_scales[2];
2564 /* How to map sampled ycbcr planes to a single 4 component element. */
2565 struct isl_swizzle ycbcr_swizzle;
2570 struct anv_format_plane planes[3];
2575 static inline uint32_t
2576 anv_image_aspect_to_plane(VkImageAspectFlags image_aspects,
2577 VkImageAspectFlags aspect_mask)
2579 switch (aspect_mask) {
2580 case VK_IMAGE_ASPECT_COLOR_BIT:
2581 case VK_IMAGE_ASPECT_DEPTH_BIT:
2582 case VK_IMAGE_ASPECT_PLANE_0_BIT:
2584 case VK_IMAGE_ASPECT_STENCIL_BIT:
2585 if ((image_aspects & VK_IMAGE_ASPECT_DEPTH_BIT) == 0)
2588 case VK_IMAGE_ASPECT_PLANE_1_BIT:
2590 case VK_IMAGE_ASPECT_PLANE_2_BIT:
2593 /* Purposefully assert with depth/stencil aspects. */
2594 unreachable("invalid image aspect");
2598 static inline uint32_t
2599 anv_image_aspect_get_planes(VkImageAspectFlags aspect_mask)
2601 uint32_t planes = 0;
2603 if (aspect_mask & (VK_IMAGE_ASPECT_COLOR_BIT |
2604 VK_IMAGE_ASPECT_DEPTH_BIT |
2605 VK_IMAGE_ASPECT_STENCIL_BIT |
2606 VK_IMAGE_ASPECT_PLANE_0_BIT))
2608 if (aspect_mask & VK_IMAGE_ASPECT_PLANE_1_BIT)
2610 if (aspect_mask & VK_IMAGE_ASPECT_PLANE_2_BIT)
2613 if ((aspect_mask & VK_IMAGE_ASPECT_DEPTH_BIT) != 0 &&
2614 (aspect_mask & VK_IMAGE_ASPECT_STENCIL_BIT) != 0)
2620 static inline VkImageAspectFlags
2621 anv_plane_to_aspect(VkImageAspectFlags image_aspects,
2624 if (image_aspects & VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV) {
2625 if (util_bitcount(image_aspects) > 1)
2626 return VK_IMAGE_ASPECT_PLANE_0_BIT << plane;
2627 return VK_IMAGE_ASPECT_COLOR_BIT;
2629 if (image_aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
2630 return VK_IMAGE_ASPECT_DEPTH_BIT << plane;
2631 assert(image_aspects == VK_IMAGE_ASPECT_STENCIL_BIT);
2632 return VK_IMAGE_ASPECT_STENCIL_BIT;
2635 #define anv_foreach_image_aspect_bit(b, image, aspects) \
2636 for_each_bit(b, anv_image_expand_aspects(image, aspects))
2638 const struct anv_format *
2639 anv_get_format(VkFormat format);
2641 static inline uint32_t
2642 anv_get_format_planes(VkFormat vk_format)
2644 const struct anv_format *format = anv_get_format(vk_format);
2646 return format != NULL ? format->n_planes : 0;
2649 struct anv_format_plane
2650 anv_get_format_plane(const struct gen_device_info *devinfo, VkFormat vk_format,
2651 VkImageAspectFlagBits aspect, VkImageTiling tiling);
2653 static inline enum isl_format
2654 anv_get_isl_format(const struct gen_device_info *devinfo, VkFormat vk_format,
2655 VkImageAspectFlags aspect, VkImageTiling tiling)
2657 return anv_get_format_plane(devinfo, vk_format, aspect, tiling).isl_format;
2660 static inline struct isl_swizzle
2661 anv_swizzle_for_render(struct isl_swizzle swizzle)
2663 /* Sometimes the swizzle will have alpha map to one. We do this to fake
2664 * RGB as RGBA for texturing
2666 assert(swizzle.a == ISL_CHANNEL_SELECT_ONE ||
2667 swizzle.a == ISL_CHANNEL_SELECT_ALPHA);
2669 /* But it doesn't matter what we render to that channel */
2670 swizzle.a = ISL_CHANNEL_SELECT_ALPHA;
2676 anv_pipeline_setup_l3_config(struct anv_pipeline *pipeline, bool needs_slm);
2679 * Subsurface of an anv_image.
2681 struct anv_surface {
2682 /** Valid only if isl_surf::size_B > 0. */
2683 struct isl_surf isl;
2686 * Offset from VkImage's base address, as bound by vkBindImageMemory().
2693 /* The original VkFormat provided by the client. This may not match any
2694 * of the actual surface formats.
2697 const struct anv_format *format;
2699 VkImageAspectFlags aspects;
2702 uint32_t array_size;
2703 uint32_t samples; /**< VkImageCreateInfo::samples */
2705 VkImageUsageFlags usage; /**< Superset of VkImageCreateInfo::usage. */
2706 VkImageTiling tiling; /** VkImageCreateInfo::tiling */
2708 /** True if this is needs to be bound to an appropriately tiled BO.
2710 * When not using modifiers, consumers such as X11, Wayland, and KMS need
2711 * the tiling passed via I915_GEM_SET_TILING. When exporting these buffers
2712 * we require a dedicated allocation so that we can know to allocate a
2715 bool needs_set_tiling;
2718 * Must be DRM_FORMAT_MOD_INVALID unless tiling is
2719 * VK_IMAGE_TILING_DRM_FORMAT_MODIFIER_EXT.
2721 uint64_t drm_format_mod;
2726 /* Whether the image is made of several underlying buffer objects rather a
2727 * single one with different offsets.
2734 * For each foo, anv_image::planes[x].surface is valid if and only if
2735 * anv_image::aspects has a x aspect. Refer to anv_image_aspect_to_plane()
2736 * to figure the number associated with a given aspect.
2738 * The hardware requires that the depth buffer and stencil buffer be
2739 * separate surfaces. From Vulkan's perspective, though, depth and stencil
2740 * reside in the same VkImage. To satisfy both the hardware and Vulkan, we
2741 * allocate the depth and stencil buffers as separate surfaces in the same
2746 * -----------------------
2748 * ----------------------- |
2749 * | shadow surface0 | |
2750 * ----------------------- | Plane 0
2751 * | aux surface0 | |
2752 * ----------------------- |
2753 * | fast clear colors0 | \|/
2754 * -----------------------
2756 * ----------------------- |
2757 * | shadow surface1 | |
2758 * ----------------------- | Plane 1
2759 * | aux surface1 | |
2760 * ----------------------- |
2761 * | fast clear colors1 | \|/
2762 * -----------------------
2765 * -----------------------
2769 * Offset of the entire plane (whenever the image is disjoint this is
2777 struct anv_surface surface;
2780 * A surface which shadows the main surface and may have different
2781 * tiling. This is used for sampling using a tiling that isn't supported
2782 * for other operations.
2784 struct anv_surface shadow_surface;
2787 * For color images, this is the aux usage for this image when not used
2788 * as a color attachment.
2790 * For depth/stencil images, this is set to ISL_AUX_USAGE_HIZ if the
2791 * image has a HiZ buffer.
2793 enum isl_aux_usage aux_usage;
2795 struct anv_surface aux_surface;
2798 * Offset of the fast clear state (used to compute the
2799 * fast_clear_state_offset of the following planes).
2801 uint32_t fast_clear_state_offset;
2804 * BO associated with this plane, set when bound.
2806 struct anv_address address;
2809 * When destroying the image, also free the bo.
2815 /* The ordering of this enum is important */
2816 enum anv_fast_clear_type {
2817 /** Image does not have/support any fast-clear blocks */
2818 ANV_FAST_CLEAR_NONE = 0,
2819 /** Image has/supports fast-clear but only to the default value */
2820 ANV_FAST_CLEAR_DEFAULT_VALUE = 1,
2821 /** Image has/supports fast-clear with an arbitrary fast-clear value */
2822 ANV_FAST_CLEAR_ANY = 2,
2825 /* Returns the number of auxiliary buffer levels attached to an image. */
2826 static inline uint8_t
2827 anv_image_aux_levels(const struct anv_image * const image,
2828 VkImageAspectFlagBits aspect)
2830 uint32_t plane = anv_image_aspect_to_plane(image->aspects, aspect);
2831 return image->planes[plane].aux_surface.isl.size_B > 0 ?
2832 image->planes[plane].aux_surface.isl.levels : 0;
2835 /* Returns the number of auxiliary buffer layers attached to an image. */
2836 static inline uint32_t
2837 anv_image_aux_layers(const struct anv_image * const image,
2838 VkImageAspectFlagBits aspect,
2839 const uint8_t miplevel)
2843 /* The miplevel must exist in the main buffer. */
2844 assert(miplevel < image->levels);
2846 if (miplevel >= anv_image_aux_levels(image, aspect)) {
2847 /* There are no layers with auxiliary data because the miplevel has no
2852 uint32_t plane = anv_image_aspect_to_plane(image->aspects, aspect);
2853 return MAX2(image->planes[plane].aux_surface.isl.logical_level0_px.array_len,
2854 image->planes[plane].aux_surface.isl.logical_level0_px.depth >> miplevel);
2858 static inline struct anv_address
2859 anv_image_get_clear_color_addr(const struct anv_device *device,
2860 const struct anv_image *image,
2861 VkImageAspectFlagBits aspect)
2863 assert(image->aspects & VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV);
2865 uint32_t plane = anv_image_aspect_to_plane(image->aspects, aspect);
2866 return anv_address_add(image->planes[plane].address,
2867 image->planes[plane].fast_clear_state_offset);
2870 static inline struct anv_address
2871 anv_image_get_fast_clear_type_addr(const struct anv_device *device,
2872 const struct anv_image *image,
2873 VkImageAspectFlagBits aspect)
2875 struct anv_address addr =
2876 anv_image_get_clear_color_addr(device, image, aspect);
2878 const unsigned clear_color_state_size = device->info.gen >= 10 ?
2879 device->isl_dev.ss.clear_color_state_size :
2880 device->isl_dev.ss.clear_value_size;
2881 addr.offset += clear_color_state_size;
2885 static inline struct anv_address
2886 anv_image_get_compression_state_addr(const struct anv_device *device,
2887 const struct anv_image *image,
2888 VkImageAspectFlagBits aspect,
2889 uint32_t level, uint32_t array_layer)
2891 assert(level < anv_image_aux_levels(image, aspect));
2892 assert(array_layer < anv_image_aux_layers(image, aspect, level));
2893 UNUSED uint32_t plane = anv_image_aspect_to_plane(image->aspects, aspect);
2894 assert(image->planes[plane].aux_usage == ISL_AUX_USAGE_CCS_E);
2896 struct anv_address addr =
2897 anv_image_get_fast_clear_type_addr(device, image, aspect);
2898 addr.offset += 4; /* Go past the fast clear type */
2900 if (image->type == VK_IMAGE_TYPE_3D) {
2901 for (uint32_t l = 0; l < level; l++)
2902 addr.offset += anv_minify(image->extent.depth, l) * 4;
2904 addr.offset += level * image->array_size * 4;
2906 addr.offset += array_layer * 4;
2911 /* Returns true if a HiZ-enabled depth buffer can be sampled from. */
2913 anv_can_sample_with_hiz(const struct gen_device_info * const devinfo,
2914 const struct anv_image *image)
2916 if (!(image->aspects & VK_IMAGE_ASPECT_DEPTH_BIT))
2919 if (devinfo->gen < 8)
2922 return image->samples == 1;
2926 anv_cmd_buffer_mark_image_written(struct anv_cmd_buffer *cmd_buffer,
2927 const struct anv_image *image,
2928 VkImageAspectFlagBits aspect,
2929 enum isl_aux_usage aux_usage,
2931 uint32_t base_layer,
2932 uint32_t layer_count);
2935 anv_image_clear_color(struct anv_cmd_buffer *cmd_buffer,
2936 const struct anv_image *image,
2937 VkImageAspectFlagBits aspect,
2938 enum isl_aux_usage aux_usage,
2939 enum isl_format format, struct isl_swizzle swizzle,
2940 uint32_t level, uint32_t base_layer, uint32_t layer_count,
2941 VkRect2D area, union isl_color_value clear_color);
2943 anv_image_clear_depth_stencil(struct anv_cmd_buffer *cmd_buffer,
2944 const struct anv_image *image,
2945 VkImageAspectFlags aspects,
2946 enum isl_aux_usage depth_aux_usage,
2948 uint32_t base_layer, uint32_t layer_count,
2950 float depth_value, uint8_t stencil_value);
2952 anv_image_hiz_op(struct anv_cmd_buffer *cmd_buffer,
2953 const struct anv_image *image,
2954 VkImageAspectFlagBits aspect, uint32_t level,
2955 uint32_t base_layer, uint32_t layer_count,
2956 enum isl_aux_op hiz_op);
2958 anv_image_hiz_clear(struct anv_cmd_buffer *cmd_buffer,
2959 const struct anv_image *image,
2960 VkImageAspectFlags aspects,
2962 uint32_t base_layer, uint32_t layer_count,
2963 VkRect2D area, uint8_t stencil_value);
2965 anv_image_mcs_op(struct anv_cmd_buffer *cmd_buffer,
2966 const struct anv_image *image,
2967 enum isl_format format,
2968 VkImageAspectFlagBits aspect,
2969 uint32_t base_layer, uint32_t layer_count,
2970 enum isl_aux_op mcs_op, union isl_color_value *clear_value,
2973 anv_image_ccs_op(struct anv_cmd_buffer *cmd_buffer,
2974 const struct anv_image *image,
2975 enum isl_format format,
2976 VkImageAspectFlagBits aspect, uint32_t level,
2977 uint32_t base_layer, uint32_t layer_count,
2978 enum isl_aux_op ccs_op, union isl_color_value *clear_value,
2982 anv_image_copy_to_shadow(struct anv_cmd_buffer *cmd_buffer,
2983 const struct anv_image *image,
2984 uint32_t base_level, uint32_t level_count,
2985 uint32_t base_layer, uint32_t layer_count);
2988 anv_layout_to_aux_usage(const struct gen_device_info * const devinfo,
2989 const struct anv_image *image,
2990 const VkImageAspectFlagBits aspect,
2991 const VkImageLayout layout);
2993 enum anv_fast_clear_type
2994 anv_layout_to_fast_clear_type(const struct gen_device_info * const devinfo,
2995 const struct anv_image * const image,
2996 const VkImageAspectFlagBits aspect,
2997 const VkImageLayout layout);
2999 /* This is defined as a macro so that it works for both
3000 * VkImageSubresourceRange and VkImageSubresourceLayers
3002 #define anv_get_layerCount(_image, _range) \
3003 ((_range)->layerCount == VK_REMAINING_ARRAY_LAYERS ? \
3004 (_image)->array_size - (_range)->baseArrayLayer : (_range)->layerCount)
3006 static inline uint32_t
3007 anv_get_levelCount(const struct anv_image *image,
3008 const VkImageSubresourceRange *range)
3010 return range->levelCount == VK_REMAINING_MIP_LEVELS ?
3011 image->levels - range->baseMipLevel : range->levelCount;
3014 static inline VkImageAspectFlags
3015 anv_image_expand_aspects(const struct anv_image *image,
3016 VkImageAspectFlags aspects)
3018 /* If the underlying image has color plane aspects and
3019 * VK_IMAGE_ASPECT_COLOR_BIT has been requested, then return the aspects of
3020 * the underlying image. */
3021 if ((image->aspects & VK_IMAGE_ASPECT_PLANES_BITS_ANV) != 0 &&
3022 aspects == VK_IMAGE_ASPECT_COLOR_BIT)
3023 return image->aspects;
3029 anv_image_aspects_compatible(VkImageAspectFlags aspects1,
3030 VkImageAspectFlags aspects2)
3032 if (aspects1 == aspects2)
3035 /* Only 1 color aspects are compatibles. */
3036 if ((aspects1 & VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV) != 0 &&
3037 (aspects2 & VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV) != 0 &&
3038 util_bitcount(aspects1) == util_bitcount(aspects2))
3044 struct anv_image_view {
3045 const struct anv_image *image; /**< VkImageViewCreateInfo::image */
3047 VkImageAspectFlags aspect_mask;
3049 VkExtent3D extent; /**< Extent of VkImageViewCreateInfo::baseMipLevel. */
3053 uint32_t image_plane;
3055 struct isl_view isl;
3058 * RENDER_SURFACE_STATE when using image as a sampler surface with an
3059 * image layout of SHADER_READ_ONLY_OPTIMAL or
3060 * DEPTH_STENCIL_READ_ONLY_OPTIMAL.
3062 struct anv_surface_state optimal_sampler_surface_state;
3065 * RENDER_SURFACE_STATE when using image as a sampler surface with an
3066 * image layout of GENERAL.
3068 struct anv_surface_state general_sampler_surface_state;
3071 * RENDER_SURFACE_STATE when using image as a storage image. Separate
3072 * states for write-only and readable, using the real format for
3073 * write-only and the lowered format for readable.
3075 struct anv_surface_state storage_surface_state;
3076 struct anv_surface_state writeonly_storage_surface_state;
3078 struct brw_image_param storage_image_param;
3082 enum anv_image_view_state_flags {
3083 ANV_IMAGE_VIEW_STATE_STORAGE_WRITE_ONLY = (1 << 0),
3084 ANV_IMAGE_VIEW_STATE_TEXTURE_OPTIMAL = (1 << 1),
3087 void anv_image_fill_surface_state(struct anv_device *device,
3088 const struct anv_image *image,
3089 VkImageAspectFlagBits aspect,
3090 const struct isl_view *view,
3091 isl_surf_usage_flags_t view_usage,
3092 enum isl_aux_usage aux_usage,
3093 const union isl_color_value *clear_color,
3094 enum anv_image_view_state_flags flags,
3095 struct anv_surface_state *state_inout,
3096 struct brw_image_param *image_param_out);
3098 struct anv_image_create_info {
3099 const VkImageCreateInfo *vk_info;
3101 /** An opt-in bitmask which filters an ISL-mapping of the Vulkan tiling. */
3102 isl_tiling_flags_t isl_tiling_flags;
3104 /** These flags will be added to any derived from VkImageCreateInfo. */
3105 isl_surf_usage_flags_t isl_extra_usage_flags;
3110 VkResult anv_image_create(VkDevice _device,
3111 const struct anv_image_create_info *info,
3112 const VkAllocationCallbacks* alloc,
3116 VkResult anv_image_from_gralloc(VkDevice device_h,
3117 const VkImageCreateInfo *base_info,
3118 const VkNativeBufferANDROID *gralloc_info,
3119 const VkAllocationCallbacks *alloc,
3123 const struct anv_surface *
3124 anv_image_get_surface_for_aspect_mask(const struct anv_image *image,
3125 VkImageAspectFlags aspect_mask);
3128 anv_isl_format_for_descriptor_type(VkDescriptorType type);
3130 static inline struct VkExtent3D
3131 anv_sanitize_image_extent(const VkImageType imageType,
3132 const struct VkExtent3D imageExtent)
3134 switch (imageType) {
3135 case VK_IMAGE_TYPE_1D:
3136 return (VkExtent3D) { imageExtent.width, 1, 1 };
3137 case VK_IMAGE_TYPE_2D:
3138 return (VkExtent3D) { imageExtent.width, imageExtent.height, 1 };
3139 case VK_IMAGE_TYPE_3D:
3142 unreachable("invalid image type");
3146 static inline struct VkOffset3D
3147 anv_sanitize_image_offset(const VkImageType imageType,
3148 const struct VkOffset3D imageOffset)
3150 switch (imageType) {
3151 case VK_IMAGE_TYPE_1D:
3152 return (VkOffset3D) { imageOffset.x, 0, 0 };
3153 case VK_IMAGE_TYPE_2D:
3154 return (VkOffset3D) { imageOffset.x, imageOffset.y, 0 };
3155 case VK_IMAGE_TYPE_3D:
3158 unreachable("invalid image type");
3163 void anv_fill_buffer_surface_state(struct anv_device *device,
3164 struct anv_state state,
3165 enum isl_format format,
3166 struct anv_address address,
3167 uint32_t range, uint32_t stride);
3170 anv_clear_color_from_att_state(union isl_color_value *clear_color,
3171 const struct anv_attachment_state *att_state,
3172 const struct anv_image_view *iview)
3174 const struct isl_format_layout *view_fmtl =
3175 isl_format_get_layout(iview->planes[0].isl.format);
3177 #define COPY_CLEAR_COLOR_CHANNEL(c, i) \
3178 if (view_fmtl->channels.c.bits) \
3179 clear_color->u32[i] = att_state->clear_value.color.uint32[i]
3181 COPY_CLEAR_COLOR_CHANNEL(r, 0);
3182 COPY_CLEAR_COLOR_CHANNEL(g, 1);
3183 COPY_CLEAR_COLOR_CHANNEL(b, 2);
3184 COPY_CLEAR_COLOR_CHANNEL(a, 3);
3186 #undef COPY_CLEAR_COLOR_CHANNEL
3190 struct anv_ycbcr_conversion {
3191 const struct anv_format * format;
3192 VkSamplerYcbcrModelConversion ycbcr_model;
3193 VkSamplerYcbcrRange ycbcr_range;
3194 VkComponentSwizzle mapping[4];
3195 VkChromaLocation chroma_offsets[2];
3196 VkFilter chroma_filter;
3197 bool chroma_reconstruction;
3200 struct anv_sampler {
3201 uint32_t state[3][4];
3203 struct anv_ycbcr_conversion *conversion;
3206 struct anv_framebuffer {
3211 uint32_t attachment_count;
3212 struct anv_image_view * attachments[0];
3215 struct anv_subpass_attachment {
3216 VkImageUsageFlagBits usage;
3217 uint32_t attachment;
3218 VkImageLayout layout;
3221 struct anv_subpass {
3222 uint32_t attachment_count;
3225 * A pointer to all attachment references used in this subpass.
3226 * Only valid if ::attachment_count > 0.
3228 struct anv_subpass_attachment * attachments;
3229 uint32_t input_count;
3230 struct anv_subpass_attachment * input_attachments;
3231 uint32_t color_count;
3232 struct anv_subpass_attachment * color_attachments;
3233 struct anv_subpass_attachment * resolve_attachments;
3235 struct anv_subpass_attachment * depth_stencil_attachment;
3239 /** Subpass has a depth/stencil self-dependency */
3240 bool has_ds_self_dep;
3242 /** Subpass has at least one resolve attachment */
3246 static inline unsigned
3247 anv_subpass_view_count(const struct anv_subpass *subpass)
3249 return MAX2(1, util_bitcount(subpass->view_mask));
3252 struct anv_render_pass_attachment {
3253 /* TODO: Consider using VkAttachmentDescription instead of storing each of
3254 * its members individually.
3258 VkImageUsageFlags usage;
3259 VkAttachmentLoadOp load_op;
3260 VkAttachmentStoreOp store_op;
3261 VkAttachmentLoadOp stencil_load_op;
3262 VkImageLayout initial_layout;
3263 VkImageLayout final_layout;
3264 VkImageLayout first_subpass_layout;
3266 /* The subpass id in which the attachment will be used last. */
3267 uint32_t last_subpass_idx;
3270 struct anv_render_pass {
3271 uint32_t attachment_count;
3272 uint32_t subpass_count;
3273 /* An array of subpass_count+1 flushes, one per subpass boundary */
3274 enum anv_pipe_bits * subpass_flushes;
3275 struct anv_render_pass_attachment * attachments;
3276 struct anv_subpass subpasses[0];
3279 #define ANV_PIPELINE_STATISTICS_MASK 0x000007ff
3281 struct anv_query_pool {
3283 VkQueryPipelineStatisticFlags pipeline_statistics;
3284 /** Stride between slots, in bytes */
3286 /** Number of slots in this query pool */
3291 int anv_get_instance_entrypoint_index(const char *name);
3292 int anv_get_device_entrypoint_index(const char *name);
3295 anv_instance_entrypoint_is_enabled(int index, uint32_t core_version,
3296 const struct anv_instance_extension_table *instance);
3299 anv_device_entrypoint_is_enabled(int index, uint32_t core_version,
3300 const struct anv_instance_extension_table *instance,
3301 const struct anv_device_extension_table *device);
3303 void *anv_lookup_entrypoint(const struct gen_device_info *devinfo,
3306 void anv_dump_image_to_ppm(struct anv_device *device,
3307 struct anv_image *image, unsigned miplevel,
3308 unsigned array_layer, VkImageAspectFlagBits aspect,
3309 const char *filename);
3311 enum anv_dump_action {
3312 ANV_DUMP_FRAMEBUFFERS_BIT = 0x1,
3315 void anv_dump_start(struct anv_device *device, enum anv_dump_action actions);
3316 void anv_dump_finish(void);
3318 void anv_dump_add_framebuffer(struct anv_cmd_buffer *cmd_buffer,
3319 struct anv_framebuffer *fb);
3321 static inline uint32_t
3322 anv_get_subpass_id(const struct anv_cmd_state * const cmd_state)
3324 /* This function must be called from within a subpass. */
3325 assert(cmd_state->pass && cmd_state->subpass);
3327 const uint32_t subpass_id = cmd_state->subpass - cmd_state->pass->subpasses;
3329 /* The id of this subpass shouldn't exceed the number of subpasses in this
3330 * render pass minus 1.
3332 assert(subpass_id < cmd_state->pass->subpass_count);
3336 #define ANV_DEFINE_HANDLE_CASTS(__anv_type, __VkType) \
3338 static inline struct __anv_type * \
3339 __anv_type ## _from_handle(__VkType _handle) \
3341 return (struct __anv_type *) _handle; \
3344 static inline __VkType \
3345 __anv_type ## _to_handle(struct __anv_type *_obj) \
3347 return (__VkType) _obj; \
3350 #define ANV_DEFINE_NONDISP_HANDLE_CASTS(__anv_type, __VkType) \
3352 static inline struct __anv_type * \
3353 __anv_type ## _from_handle(__VkType _handle) \
3355 return (struct __anv_type *)(uintptr_t) _handle; \
3358 static inline __VkType \
3359 __anv_type ## _to_handle(struct __anv_type *_obj) \
3361 return (__VkType)(uintptr_t) _obj; \
3364 #define ANV_FROM_HANDLE(__anv_type, __name, __handle) \
3365 struct __anv_type *__name = __anv_type ## _from_handle(__handle)
3367 ANV_DEFINE_HANDLE_CASTS(anv_cmd_buffer, VkCommandBuffer)
3368 ANV_DEFINE_HANDLE_CASTS(anv_device, VkDevice)
3369 ANV_DEFINE_HANDLE_CASTS(anv_instance, VkInstance)
3370 ANV_DEFINE_HANDLE_CASTS(anv_physical_device, VkPhysicalDevice)
3371 ANV_DEFINE_HANDLE_CASTS(anv_queue, VkQueue)
3373 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_cmd_pool, VkCommandPool)
3374 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_buffer, VkBuffer)
3375 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_buffer_view, VkBufferView)
3376 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_pool, VkDescriptorPool)
3377 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_set, VkDescriptorSet)
3378 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_set_layout, VkDescriptorSetLayout)
3379 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_update_template, VkDescriptorUpdateTemplateKHR)
3380 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_device_memory, VkDeviceMemory)
3381 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_fence, VkFence)
3382 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_event, VkEvent)
3383 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_framebuffer, VkFramebuffer)
3384 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_image, VkImage)
3385 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_image_view, VkImageView);
3386 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_pipeline_cache, VkPipelineCache)
3387 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_pipeline, VkPipeline)
3388 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_pipeline_layout, VkPipelineLayout)
3389 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_query_pool, VkQueryPool)
3390 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_render_pass, VkRenderPass)
3391 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_sampler, VkSampler)
3392 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_semaphore, VkSemaphore)
3393 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_shader_module, VkShaderModule)
3394 ANV_DEFINE_NONDISP_HANDLE_CASTS(vk_debug_report_callback, VkDebugReportCallbackEXT)
3395 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_ycbcr_conversion, VkSamplerYcbcrConversion)
3397 /* Gen-specific function declarations */
3399 # include "anv_genX.h"
3401 # define genX(x) gen7_##x
3402 # include "anv_genX.h"
3404 # define genX(x) gen75_##x
3405 # include "anv_genX.h"
3407 # define genX(x) gen8_##x
3408 # include "anv_genX.h"
3410 # define genX(x) gen9_##x
3411 # include "anv_genX.h"
3413 # define genX(x) gen10_##x
3414 # include "anv_genX.h"
3416 # define genX(x) gen11_##x
3417 # include "anv_genX.h"
3421 #endif /* ANV_PRIVATE_H */