2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
39 #define __gen_validate_value(x) VALGRIND_CHECK_MEM_IS_DEFINED(&(x), sizeof(x))
44 #include "common/gen_device_info.h"
45 #include "blorp/blorp.h"
46 #include "compiler/brw_compiler.h"
47 #include "util/macros.h"
48 #include "util/list.h"
49 #include "util/u_vector.h"
50 #include "util/vk_alloc.h"
52 /* Pre-declarations needed for WSI entrypoints */
55 typedef struct xcb_connection_t xcb_connection_t;
56 typedef uint32_t xcb_visualid_t;
57 typedef uint32_t xcb_window_t;
60 struct anv_buffer_view;
61 struct anv_image_view;
65 #include <vulkan/vulkan.h>
66 #include <vulkan/vulkan_intel.h>
67 #include <vulkan/vk_icd.h>
69 #include "anv_entrypoints.h"
72 #include "common/gen_debug.h"
73 #include "wsi_common.h"
75 /* Allowing different clear colors requires us to perform a depth resolve at
76 * the end of certain render passes. This is because while slow clears store
77 * the clear color in the HiZ buffer, fast clears (without a resolve) don't.
78 * See the PRMs for examples describing when additional resolves would be
79 * necessary. To enable fast clears without requiring extra resolves, we set
80 * the clear value to a globally-defined one. We could allow different values
81 * if the user doesn't expect coherent data during or after a render passes
82 * (VK_ATTACHMENT_STORE_OP_DONT_CARE), but such users (aside from the CTS)
83 * don't seem to exist yet. In almost all Vulkan applications tested thus far,
84 * 1.0f seems to be the only value used. The only application that doesn't set
85 * this value does so through the usage of an seemingly uninitialized clear
88 #define ANV_HZ_FC_VAL 1.0f
93 #define MAX_VIEWPORTS 16
94 #define MAX_SCISSORS 16
95 #define MAX_PUSH_CONSTANTS_SIZE 128
96 #define MAX_DYNAMIC_BUFFERS 16
98 #define MAX_PUSH_DESCRIPTORS 32 /* Minimum requirement */
100 #define ANV_SVGS_VB_INDEX MAX_VBS
101 #define ANV_DRAWID_VB_INDEX (MAX_VBS + 1)
103 #define anv_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
105 static inline uint32_t
106 align_down_npot_u32(uint32_t v, uint32_t a)
111 static inline uint32_t
112 align_u32(uint32_t v, uint32_t a)
114 assert(a != 0 && a == (a & -a));
115 return (v + a - 1) & ~(a - 1);
118 static inline uint64_t
119 align_u64(uint64_t v, uint64_t a)
121 assert(a != 0 && a == (a & -a));
122 return (v + a - 1) & ~(a - 1);
125 static inline int32_t
126 align_i32(int32_t v, int32_t a)
128 assert(a != 0 && a == (a & -a));
129 return (v + a - 1) & ~(a - 1);
132 /** Alignment must be a power of 2. */
134 anv_is_aligned(uintmax_t n, uintmax_t a)
136 assert(a == (a & -a));
137 return (n & (a - 1)) == 0;
140 static inline uint32_t
141 anv_minify(uint32_t n, uint32_t levels)
143 if (unlikely(n == 0))
146 return MAX2(n >> levels, 1);
150 anv_clamp_f(float f, float min, float max)
163 anv_clear_mask(uint32_t *inout_mask, uint32_t clear_mask)
165 if (*inout_mask & clear_mask) {
166 *inout_mask &= ~clear_mask;
173 static inline union isl_color_value
174 vk_to_isl_color(VkClearColorValue color)
176 return (union isl_color_value) {
186 #define for_each_bit(b, dword) \
187 for (uint32_t __dword = (dword); \
188 (b) = __builtin_ffs(__dword) - 1, __dword; \
189 __dword &= ~(1 << (b)))
191 #define typed_memcpy(dest, src, count) ({ \
192 STATIC_ASSERT(sizeof(*src) == sizeof(*dest)); \
193 memcpy((dest), (src), (count) * sizeof(*(src))); \
196 /* Whenever we generate an error, pass it through this function. Useful for
197 * debugging, where we can break on it. Only call at error site, not when
198 * propagating errors. Might be useful to plug in a stack trace here.
201 VkResult __vk_errorf(VkResult error, const char *file, int line, const char *format, ...);
204 #define vk_error(error) __vk_errorf(error, __FILE__, __LINE__, NULL);
205 #define vk_errorf(error, format, ...) __vk_errorf(error, __FILE__, __LINE__, format, ## __VA_ARGS__);
206 #define anv_debug(format, ...) fprintf(stderr, "debug: " format, ##__VA_ARGS__)
208 #define vk_error(error) error
209 #define vk_errorf(error, format, ...) error
210 #define anv_debug(format, ...)
214 * Warn on ignored extension structs.
216 * The Vulkan spec requires us to ignore unsupported or unknown structs in
217 * a pNext chain. In debug mode, emitting warnings for ignored structs may
218 * help us discover structs that we should not have ignored.
221 * From the Vulkan 1.0.38 spec:
223 * Any component of the implementation (the loader, any enabled layers,
224 * and drivers) must skip over, without processing (other than reading the
225 * sType and pNext members) any chained structures with sType values not
226 * defined by extensions supported by that component.
228 #define anv_debug_ignored_stype(sType) \
229 anv_debug("debug: %s: ignored VkStructureType %u\n", __func__, (sType))
231 void __anv_finishme(const char *file, int line, const char *format, ...)
232 anv_printflike(3, 4);
233 void __anv_perf_warn(const char *file, int line, const char *format, ...)
234 anv_printflike(3, 4);
235 void anv_loge(const char *format, ...) anv_printflike(1, 2);
236 void anv_loge_v(const char *format, va_list va);
239 * Print a FINISHME message, including its source location.
241 #define anv_finishme(format, ...) \
243 static bool reported = false; \
245 __anv_finishme(__FILE__, __LINE__, format, ##__VA_ARGS__); \
251 * Print a perf warning message. Set INTEL_DEBUG=perf to see these.
253 #define anv_perf_warn(format, ...) \
255 static bool reported = false; \
256 if (!reported && unlikely(INTEL_DEBUG & DEBUG_PERF)) { \
257 __anv_perf_warn(__FILE__, __LINE__, format, ##__VA_ARGS__); \
262 /* A non-fatal assert. Useful for debugging. */
264 #define anv_assert(x) ({ \
265 if (unlikely(!(x))) \
266 fprintf(stderr, "%s:%d ASSERT: %s\n", __FILE__, __LINE__, #x); \
269 #define anv_assert(x)
272 /* A multi-pointer allocator
274 * When copying data structures from the user (such as a render pass), it's
275 * common to need to allocate data for a bunch of different things. Instead
276 * of doing several allocations and having to handle all of the error checking
277 * that entails, it can be easier to do a single allocation. This struct
278 * helps facilitate that. The intended usage looks like this:
281 * anv_multialloc_add(&ma, &main_ptr, 1);
282 * anv_multialloc_add(&ma, &substruct1, substruct1Count);
283 * anv_multialloc_add(&ma, &substruct2, substruct2Count);
285 * if (!anv_multialloc_alloc(&ma, pAllocator, VK_ALLOCATION_SCOPE_FOO))
286 * return vk_error(VK_ERROR_OUT_OF_HOST_MEORY);
288 struct anv_multialloc {
296 #define ANV_MULTIALLOC_INIT \
297 ((struct anv_multialloc) { 0, })
299 #define ANV_MULTIALLOC(_name) \
300 struct anv_multialloc _name = ANV_MULTIALLOC_INIT
302 __attribute__((always_inline))
304 _anv_multialloc_add(struct anv_multialloc *ma,
305 void **ptr, size_t size, size_t align)
307 size_t offset = align_u64(ma->size, align);
308 ma->size = offset + size;
309 ma->align = MAX2(ma->align, align);
311 /* Store the offset in the pointer. */
312 *ptr = (void *)(uintptr_t)offset;
314 assert(ma->ptr_count < ARRAY_SIZE(ma->ptrs));
315 ma->ptrs[ma->ptr_count++] = ptr;
318 #define anv_multialloc_add(_ma, _ptr, _count) \
319 _anv_multialloc_add((_ma), (void **)(_ptr), \
320 (_count) * sizeof(**(_ptr)), __alignof__(**(_ptr)))
322 __attribute__((always_inline))
324 anv_multialloc_alloc(struct anv_multialloc *ma,
325 const VkAllocationCallbacks *alloc,
326 VkSystemAllocationScope scope)
328 void *ptr = vk_alloc(alloc, ma->size, ma->align, scope);
332 /* Fill out each of the pointers with their final value.
334 * for (uint32_t i = 0; i < ma->ptr_count; i++)
335 * *ma->ptrs[i] = ptr + (uintptr_t)*ma->ptrs[i];
337 * Unfortunately, even though ma->ptr_count is basically guaranteed to be a
338 * constant, GCC is incapable of figuring this out and unrolling the loop
339 * so we have to give it a little help.
341 STATIC_ASSERT(ARRAY_SIZE(ma->ptrs) == 8);
342 #define _ANV_MULTIALLOC_UPDATE_POINTER(_i) \
343 if ((_i) < ma->ptr_count) \
344 *ma->ptrs[_i] = ptr + (uintptr_t)*ma->ptrs[_i]
345 _ANV_MULTIALLOC_UPDATE_POINTER(0);
346 _ANV_MULTIALLOC_UPDATE_POINTER(1);
347 _ANV_MULTIALLOC_UPDATE_POINTER(2);
348 _ANV_MULTIALLOC_UPDATE_POINTER(3);
349 _ANV_MULTIALLOC_UPDATE_POINTER(4);
350 _ANV_MULTIALLOC_UPDATE_POINTER(5);
351 _ANV_MULTIALLOC_UPDATE_POINTER(6);
352 _ANV_MULTIALLOC_UPDATE_POINTER(7);
353 #undef _ANV_MULTIALLOC_UPDATE_POINTER
358 __attribute__((always_inline))
360 anv_multialloc_alloc2(struct anv_multialloc *ma,
361 const VkAllocationCallbacks *parent_alloc,
362 const VkAllocationCallbacks *alloc,
363 VkSystemAllocationScope scope)
365 return anv_multialloc_alloc(ma, alloc ? alloc : parent_alloc, scope);
369 * A dynamically growable, circular buffer. Elements are added at head and
370 * removed from tail. head and tail are free-running uint32_t indices and we
371 * only compute the modulo with size when accessing the array. This way,
372 * number of bytes in the queue is always head - tail, even in case of
379 /* Index into the current validation list. This is used by the
380 * validation list building alrogithm to track which buffers are already
381 * in the validation list so that we can ensure uniqueness.
385 /* Last known offset. This value is provided by the kernel when we
386 * execbuf and is used as the presumed offset for the next bunch of
394 /** Flags to pass to the kernel through drm_i915_exec_object2::flags */
399 anv_bo_init(struct anv_bo *bo, uint32_t gem_handle, uint64_t size)
401 bo->gem_handle = gem_handle;
409 /* Represents a lock-free linked list of "free" things. This is used by
410 * both the block pool and the state pools. Unfortunately, in order to
411 * solve the ABA problem, we can't use a single uint32_t head.
413 union anv_free_list {
417 /* A simple count that is incremented every time the head changes. */
423 #define ANV_FREE_LIST_EMPTY ((union anv_free_list) { { 1, 0 } })
425 struct anv_block_state {
435 struct anv_block_pool {
436 struct anv_device *device;
440 /* The offset from the start of the bo to the "center" of the block
441 * pool. Pointers to allocated blocks are given by
442 * bo.map + center_bo_offset + offsets.
444 uint32_t center_bo_offset;
446 /* Current memory map of the block pool. This pointer may or may not
447 * point to the actual beginning of the block pool memory. If
448 * anv_block_pool_alloc_back has ever been called, then this pointer
449 * will point to the "center" position of the buffer and all offsets
450 * (negative or positive) given out by the block pool alloc functions
451 * will be valid relative to this pointer.
453 * In particular, map == bo.map + center_offset
459 * Array of mmaps and gem handles owned by the block pool, reclaimed when
460 * the block pool is destroyed.
462 struct u_vector mmap_cleanups;
464 struct anv_block_state state;
466 struct anv_block_state back_state;
469 /* Block pools are backed by a fixed-size 1GB memfd */
470 #define BLOCK_POOL_MEMFD_SIZE (1ul << 30)
472 /* The center of the block pool is also the middle of the memfd. This may
473 * change in the future if we decide differently for some reason.
475 #define BLOCK_POOL_MEMFD_CENTER (BLOCK_POOL_MEMFD_SIZE / 2)
477 static inline uint32_t
478 anv_block_pool_size(struct anv_block_pool *pool)
480 return pool->state.end + pool->back_state.end;
489 #define ANV_STATE_NULL ((struct anv_state) { .alloc_size = 0 })
491 struct anv_fixed_size_state_pool {
492 union anv_free_list free_list;
493 struct anv_block_state block;
496 #define ANV_MIN_STATE_SIZE_LOG2 6
497 #define ANV_MAX_STATE_SIZE_LOG2 20
499 #define ANV_STATE_BUCKETS (ANV_MAX_STATE_SIZE_LOG2 - ANV_MIN_STATE_SIZE_LOG2 + 1)
501 struct anv_state_pool {
502 struct anv_block_pool block_pool;
504 /* The size of blocks which will be allocated from the block pool */
507 /** Free list for "back" allocations */
508 union anv_free_list back_alloc_free_list;
510 struct anv_fixed_size_state_pool buckets[ANV_STATE_BUCKETS];
513 struct anv_state_stream_block;
515 struct anv_state_stream {
516 struct anv_state_pool *state_pool;
518 /* The size of blocks to allocate from the state pool */
521 /* Current block we're allocating from */
522 struct anv_state block;
524 /* Offset into the current block at which to allocate the next state */
527 /* List of all blocks allocated from this pool */
528 struct anv_state_stream_block *block_list;
531 #define CACHELINE_SIZE 64
532 #define CACHELINE_MASK 63
535 anv_clflush_range(void *start, size_t size)
537 void *p = (void *) (((uintptr_t) start) & ~CACHELINE_MASK);
538 void *end = start + size;
541 __builtin_ia32_clflush(p);
547 anv_flush_range(void *start, size_t size)
549 __builtin_ia32_mfence();
550 anv_clflush_range(start, size);
554 anv_invalidate_range(void *start, size_t size)
556 anv_clflush_range(start, size);
557 __builtin_ia32_mfence();
560 /* The block_pool functions exported for testing only. The block pool should
561 * only be used via a state pool (see below).
563 VkResult anv_block_pool_init(struct anv_block_pool *pool,
564 struct anv_device *device,
565 uint32_t initial_size);
566 void anv_block_pool_finish(struct anv_block_pool *pool);
567 int32_t anv_block_pool_alloc(struct anv_block_pool *pool,
568 uint32_t block_size);
569 int32_t anv_block_pool_alloc_back(struct anv_block_pool *pool,
570 uint32_t block_size);
572 VkResult anv_state_pool_init(struct anv_state_pool *pool,
573 struct anv_device *device,
574 uint32_t block_size);
575 void anv_state_pool_finish(struct anv_state_pool *pool);
576 struct anv_state anv_state_pool_alloc(struct anv_state_pool *pool,
577 uint32_t state_size, uint32_t alignment);
578 struct anv_state anv_state_pool_alloc_back(struct anv_state_pool *pool);
579 void anv_state_pool_free(struct anv_state_pool *pool, struct anv_state state);
580 void anv_state_stream_init(struct anv_state_stream *stream,
581 struct anv_state_pool *state_pool,
582 uint32_t block_size);
583 void anv_state_stream_finish(struct anv_state_stream *stream);
584 struct anv_state anv_state_stream_alloc(struct anv_state_stream *stream,
585 uint32_t size, uint32_t alignment);
588 * Implements a pool of re-usable BOs. The interface is identical to that
589 * of block_pool except that each block is its own BO.
592 struct anv_device *device;
597 void anv_bo_pool_init(struct anv_bo_pool *pool, struct anv_device *device);
598 void anv_bo_pool_finish(struct anv_bo_pool *pool);
599 VkResult anv_bo_pool_alloc(struct anv_bo_pool *pool, struct anv_bo *bo,
601 void anv_bo_pool_free(struct anv_bo_pool *pool, const struct anv_bo *bo);
603 struct anv_scratch_bo {
608 struct anv_scratch_pool {
609 /* Indexed by Per-Thread Scratch Space number (the hardware value) and stage */
610 struct anv_scratch_bo bos[16][MESA_SHADER_STAGES];
613 void anv_scratch_pool_init(struct anv_device *device,
614 struct anv_scratch_pool *pool);
615 void anv_scratch_pool_finish(struct anv_device *device,
616 struct anv_scratch_pool *pool);
617 struct anv_bo *anv_scratch_pool_alloc(struct anv_device *device,
618 struct anv_scratch_pool *pool,
619 gl_shader_stage stage,
620 unsigned per_thread_scratch);
622 /** Implements a BO cache that ensures a 1-1 mapping of GEM BOs to anv_bos */
623 struct anv_bo_cache {
624 struct hash_table *bo_map;
625 pthread_mutex_t mutex;
628 VkResult anv_bo_cache_init(struct anv_bo_cache *cache);
629 void anv_bo_cache_finish(struct anv_bo_cache *cache);
630 VkResult anv_bo_cache_alloc(struct anv_device *device,
631 struct anv_bo_cache *cache,
632 uint64_t size, struct anv_bo **bo);
633 VkResult anv_bo_cache_import(struct anv_device *device,
634 struct anv_bo_cache *cache,
635 int fd, uint64_t size, struct anv_bo **bo);
636 VkResult anv_bo_cache_export(struct anv_device *device,
637 struct anv_bo_cache *cache,
638 struct anv_bo *bo_in, int *fd_out);
639 void anv_bo_cache_release(struct anv_device *device,
640 struct anv_bo_cache *cache,
643 struct anv_memory_type {
644 /* Standard bits passed on to the client */
645 VkMemoryPropertyFlags propertyFlags;
648 /* Driver-internal book-keeping */
649 VkBufferUsageFlags valid_buffer_usage;
652 struct anv_memory_heap {
653 /* Standard bits passed on to the client */
655 VkMemoryHeapFlags flags;
657 /* Driver-internal book-keeping */
658 bool supports_48bit_addresses;
661 struct anv_physical_device {
662 VK_LOADER_DATA _loader_data;
664 struct anv_instance * instance;
668 struct gen_device_info info;
669 /** Amount of "GPU memory" we want to advertise
671 * Clearly, this value is bogus since Intel is a UMA architecture. On
672 * gen7 platforms, we are limited by GTT size unless we want to implement
673 * fine-grained tracking and GTT splitting. On Broadwell and above we are
674 * practically unlimited. However, we will never report more than 3/4 of
675 * the total system ram to try and avoid running out of RAM.
677 bool supports_48bit_addresses;
678 struct brw_compiler * compiler;
679 struct isl_device isl_dev;
680 int cmd_parser_version;
684 uint32_t subslice_total;
688 struct anv_memory_type types[VK_MAX_MEMORY_TYPES];
690 struct anv_memory_heap heaps[VK_MAX_MEMORY_HEAPS];
693 uint8_t pipeline_cache_uuid[VK_UUID_SIZE];
694 uint8_t driver_uuid[VK_UUID_SIZE];
695 uint8_t device_uuid[VK_UUID_SIZE];
697 struct wsi_device wsi_device;
701 struct anv_instance {
702 VK_LOADER_DATA _loader_data;
704 VkAllocationCallbacks alloc;
707 int physicalDeviceCount;
708 struct anv_physical_device physicalDevice;
711 VkResult anv_init_wsi(struct anv_physical_device *physical_device);
712 void anv_finish_wsi(struct anv_physical_device *physical_device);
715 VK_LOADER_DATA _loader_data;
717 struct anv_device * device;
719 struct anv_state_pool * pool;
722 struct anv_pipeline_cache {
723 struct anv_device * device;
724 pthread_mutex_t mutex;
726 struct hash_table * cache;
729 struct anv_pipeline_bind_map;
731 void anv_pipeline_cache_init(struct anv_pipeline_cache *cache,
732 struct anv_device *device,
734 void anv_pipeline_cache_finish(struct anv_pipeline_cache *cache);
736 struct anv_shader_bin *
737 anv_pipeline_cache_search(struct anv_pipeline_cache *cache,
738 const void *key, uint32_t key_size);
739 struct anv_shader_bin *
740 anv_pipeline_cache_upload_kernel(struct anv_pipeline_cache *cache,
741 const void *key_data, uint32_t key_size,
742 const void *kernel_data, uint32_t kernel_size,
743 const struct brw_stage_prog_data *prog_data,
744 uint32_t prog_data_size,
745 const struct anv_pipeline_bind_map *bind_map);
748 VK_LOADER_DATA _loader_data;
750 VkAllocationCallbacks alloc;
752 struct anv_instance * instance;
754 struct gen_device_info info;
755 struct isl_device isl_dev;
758 bool can_chain_batches;
759 bool robust_buffer_access;
761 struct anv_bo_pool batch_bo_pool;
763 struct anv_bo_cache bo_cache;
765 struct anv_state_pool dynamic_state_pool;
766 struct anv_state_pool instruction_state_pool;
767 struct anv_state_pool surface_state_pool;
769 struct anv_bo workaround_bo;
771 struct anv_pipeline_cache blorp_shader_cache;
772 struct blorp_context blorp;
774 struct anv_state border_colors;
776 struct anv_queue queue;
778 struct anv_scratch_pool scratch_pool;
780 uint32_t default_mocs;
782 pthread_mutex_t mutex;
783 pthread_cond_t queue_submit;
788 anv_state_flush(struct anv_device *device, struct anv_state state)
790 if (device->info.has_llc)
793 anv_flush_range(state.map, state.alloc_size);
796 void anv_device_init_blorp(struct anv_device *device);
797 void anv_device_finish_blorp(struct anv_device *device);
799 VkResult anv_device_execbuf(struct anv_device *device,
800 struct drm_i915_gem_execbuffer2 *execbuf,
801 struct anv_bo **execbuf_bos);
802 VkResult anv_device_query_status(struct anv_device *device);
803 VkResult anv_device_bo_busy(struct anv_device *device, struct anv_bo *bo);
804 VkResult anv_device_wait(struct anv_device *device, struct anv_bo *bo,
807 void* anv_gem_mmap(struct anv_device *device,
808 uint32_t gem_handle, uint64_t offset, uint64_t size, uint32_t flags);
809 void anv_gem_munmap(void *p, uint64_t size);
810 uint32_t anv_gem_create(struct anv_device *device, uint64_t size);
811 void anv_gem_close(struct anv_device *device, uint32_t gem_handle);
812 uint32_t anv_gem_userptr(struct anv_device *device, void *mem, size_t size);
813 int anv_gem_busy(struct anv_device *device, uint32_t gem_handle);
814 int anv_gem_wait(struct anv_device *device, uint32_t gem_handle, int64_t *timeout_ns);
815 int anv_gem_execbuffer(struct anv_device *device,
816 struct drm_i915_gem_execbuffer2 *execbuf);
817 int anv_gem_set_tiling(struct anv_device *device, uint32_t gem_handle,
818 uint32_t stride, uint32_t tiling);
819 int anv_gem_create_context(struct anv_device *device);
820 int anv_gem_destroy_context(struct anv_device *device, int context);
821 int anv_gem_get_context_param(int fd, int context, uint32_t param,
823 int anv_gem_get_param(int fd, uint32_t param);
824 bool anv_gem_get_bit6_swizzle(int fd, uint32_t tiling);
825 int anv_gem_get_aperture(int fd, uint64_t *size);
826 bool anv_gem_supports_48b_addresses(int fd);
827 int anv_gem_gpu_get_reset_stats(struct anv_device *device,
828 uint32_t *active, uint32_t *pending);
829 int anv_gem_handle_to_fd(struct anv_device *device, uint32_t gem_handle);
830 uint32_t anv_gem_fd_to_handle(struct anv_device *device, int fd);
831 int anv_gem_set_caching(struct anv_device *device, uint32_t gem_handle, uint32_t caching);
832 int anv_gem_set_domain(struct anv_device *device, uint32_t gem_handle,
833 uint32_t read_domains, uint32_t write_domain);
835 VkResult anv_bo_init_new(struct anv_bo *bo, struct anv_device *device, uint64_t size);
837 struct anv_reloc_list {
839 uint32_t array_length;
840 struct drm_i915_gem_relocation_entry * relocs;
841 struct anv_bo ** reloc_bos;
844 VkResult anv_reloc_list_init(struct anv_reloc_list *list,
845 const VkAllocationCallbacks *alloc);
846 void anv_reloc_list_finish(struct anv_reloc_list *list,
847 const VkAllocationCallbacks *alloc);
849 VkResult anv_reloc_list_add(struct anv_reloc_list *list,
850 const VkAllocationCallbacks *alloc,
851 uint32_t offset, struct anv_bo *target_bo,
854 struct anv_batch_bo {
855 /* Link in the anv_cmd_buffer.owned_batch_bos list */
856 struct list_head link;
860 /* Bytes actually consumed in this batch BO */
863 struct anv_reloc_list relocs;
867 const VkAllocationCallbacks * alloc;
873 struct anv_reloc_list * relocs;
875 /* This callback is called (with the associated user data) in the event
876 * that the batch runs out of space.
878 VkResult (*extend_cb)(struct anv_batch *, void *);
882 * Current error status of the command buffer. Used to track inconsistent
883 * or incomplete command buffer states that are the consequence of run-time
884 * errors such as out of memory scenarios. We want to track this in the
885 * batch because the command buffer object is not visible to some parts
891 void *anv_batch_emit_dwords(struct anv_batch *batch, int num_dwords);
892 void anv_batch_emit_batch(struct anv_batch *batch, struct anv_batch *other);
893 uint64_t anv_batch_emit_reloc(struct anv_batch *batch,
894 void *location, struct anv_bo *bo, uint32_t offset);
895 VkResult anv_device_submit_simple_batch(struct anv_device *device,
896 struct anv_batch *batch);
898 static inline VkResult
899 anv_batch_set_error(struct anv_batch *batch, VkResult error)
901 assert(error != VK_SUCCESS);
902 if (batch->status == VK_SUCCESS)
903 batch->status = error;
904 return batch->status;
908 anv_batch_has_error(struct anv_batch *batch)
910 return batch->status != VK_SUCCESS;
918 static inline uint64_t
919 _anv_combine_address(struct anv_batch *batch, void *location,
920 const struct anv_address address, uint32_t delta)
922 if (address.bo == NULL) {
923 return address.offset + delta;
925 assert(batch->start <= location && location < batch->end);
927 return anv_batch_emit_reloc(batch, location, address.bo, address.offset + delta);
931 #define __gen_address_type struct anv_address
932 #define __gen_user_data struct anv_batch
933 #define __gen_combine_address _anv_combine_address
935 /* Wrapper macros needed to work around preprocessor argument issues. In
936 * particular, arguments don't get pre-evaluated if they are concatenated.
937 * This means that, if you pass GENX(3DSTATE_PS) into the emit macro, the
938 * GENX macro won't get evaluated if the emit macro contains "cmd ## foo".
939 * We can work around this easily enough with these helpers.
941 #define __anv_cmd_length(cmd) cmd ## _length
942 #define __anv_cmd_length_bias(cmd) cmd ## _length_bias
943 #define __anv_cmd_header(cmd) cmd ## _header
944 #define __anv_cmd_pack(cmd) cmd ## _pack
945 #define __anv_reg_num(reg) reg ## _num
947 #define anv_pack_struct(dst, struc, ...) do { \
948 struct struc __template = { \
951 __anv_cmd_pack(struc)(NULL, dst, &__template); \
952 VG(VALGRIND_CHECK_MEM_IS_DEFINED(dst, __anv_cmd_length(struc) * 4)); \
955 #define anv_batch_emitn(batch, n, cmd, ...) ({ \
956 void *__dst = anv_batch_emit_dwords(batch, n); \
958 struct cmd __template = { \
959 __anv_cmd_header(cmd), \
960 .DWordLength = n - __anv_cmd_length_bias(cmd), \
963 __anv_cmd_pack(cmd)(batch, __dst, &__template); \
968 #define anv_batch_emit_merge(batch, dwords0, dwords1) \
972 STATIC_ASSERT(ARRAY_SIZE(dwords0) == ARRAY_SIZE(dwords1)); \
973 dw = anv_batch_emit_dwords((batch), ARRAY_SIZE(dwords0)); \
976 for (uint32_t i = 0; i < ARRAY_SIZE(dwords0); i++) \
977 dw[i] = (dwords0)[i] | (dwords1)[i]; \
978 VG(VALGRIND_CHECK_MEM_IS_DEFINED(dw, ARRAY_SIZE(dwords0) * 4));\
981 #define anv_batch_emit(batch, cmd, name) \
982 for (struct cmd name = { __anv_cmd_header(cmd) }, \
983 *_dst = anv_batch_emit_dwords(batch, __anv_cmd_length(cmd)); \
984 __builtin_expect(_dst != NULL, 1); \
985 ({ __anv_cmd_pack(cmd)(batch, _dst, &name); \
986 VG(VALGRIND_CHECK_MEM_IS_DEFINED(_dst, __anv_cmd_length(cmd) * 4)); \
990 #define GEN7_MOCS (struct GEN7_MEMORY_OBJECT_CONTROL_STATE) { \
991 .GraphicsDataTypeGFDT = 0, \
992 .LLCCacheabilityControlLLCCC = 0, \
993 .L3CacheabilityControlL3CC = 1, \
996 #define GEN75_MOCS (struct GEN75_MEMORY_OBJECT_CONTROL_STATE) { \
997 .LLCeLLCCacheabilityControlLLCCC = 0, \
998 .L3CacheabilityControlL3CC = 1, \
1001 #define GEN8_MOCS (struct GEN8_MEMORY_OBJECT_CONTROL_STATE) { \
1002 .MemoryTypeLLCeLLCCacheabilityControl = WB, \
1003 .TargetCache = L3DefertoPATforLLCeLLCselection, \
1004 .AgeforQUADLRU = 0 \
1007 /* Skylake: MOCS is now an index into an array of 62 different caching
1008 * configurations programmed by the kernel.
1011 #define GEN9_MOCS (struct GEN9_MEMORY_OBJECT_CONTROL_STATE) { \
1012 /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */ \
1013 .IndextoMOCSTables = 2 \
1016 #define GEN9_MOCS_PTE { \
1017 /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */ \
1018 .IndextoMOCSTables = 1 \
1021 struct anv_device_memory {
1023 struct anv_memory_type * type;
1024 VkDeviceSize map_size;
1029 * Header for Vertex URB Entry (VUE)
1031 struct anv_vue_header {
1033 uint32_t RTAIndex; /* RenderTargetArrayIndex */
1034 uint32_t ViewportIndex;
1038 struct anv_descriptor_set_binding_layout {
1040 /* The type of the descriptors in this binding */
1041 VkDescriptorType type;
1044 /* Number of array elements in this binding */
1045 uint16_t array_size;
1047 /* Index into the flattend descriptor set */
1048 uint16_t descriptor_index;
1050 /* Index into the dynamic state array for a dynamic buffer */
1051 int16_t dynamic_offset_index;
1053 /* Index into the descriptor set buffer views */
1054 int16_t buffer_index;
1057 /* Index into the binding table for the associated surface */
1058 int16_t surface_index;
1060 /* Index into the sampler table for the associated sampler */
1061 int16_t sampler_index;
1063 /* Index into the image table for the associated image */
1064 int16_t image_index;
1065 } stage[MESA_SHADER_STAGES];
1067 /* Immutable samplers (or NULL if no immutable samplers) */
1068 struct anv_sampler **immutable_samplers;
1071 struct anv_descriptor_set_layout {
1072 /* Number of bindings in this descriptor set */
1073 uint16_t binding_count;
1075 /* Total size of the descriptor set with room for all array entries */
1078 /* Shader stages affected by this descriptor set */
1079 uint16_t shader_stages;
1081 /* Number of buffers in this descriptor set */
1082 uint16_t buffer_count;
1084 /* Number of dynamic offsets used by this descriptor set */
1085 uint16_t dynamic_offset_count;
1087 /* Bindings in this descriptor set */
1088 struct anv_descriptor_set_binding_layout binding[0];
1091 struct anv_descriptor {
1092 VkDescriptorType type;
1096 struct anv_image_view *image_view;
1097 struct anv_sampler *sampler;
1099 /* Used to determine whether or not we need the surface state to have
1100 * the auxiliary buffer enabled.
1102 enum isl_aux_usage aux_usage;
1106 struct anv_buffer *buffer;
1111 struct anv_buffer_view *buffer_view;
1115 struct anv_descriptor_set {
1116 const struct anv_descriptor_set_layout *layout;
1118 uint32_t buffer_count;
1119 struct anv_buffer_view *buffer_views;
1120 struct anv_descriptor descriptors[0];
1123 struct anv_buffer_view {
1124 enum isl_format format; /**< VkBufferViewCreateInfo::format */
1126 uint32_t offset; /**< Offset into bo. */
1127 uint64_t range; /**< VkBufferViewCreateInfo::range */
1129 struct anv_state surface_state;
1130 struct anv_state storage_surface_state;
1131 struct anv_state writeonly_storage_surface_state;
1133 struct brw_image_param storage_image_param;
1136 struct anv_push_descriptor_set {
1137 struct anv_descriptor_set set;
1139 /* Put this field right behind anv_descriptor_set so it fills up the
1140 * descriptors[0] field. */
1141 struct anv_descriptor descriptors[MAX_PUSH_DESCRIPTORS];
1143 struct anv_buffer_view buffer_views[MAX_PUSH_DESCRIPTORS];
1146 struct anv_descriptor_pool {
1151 struct anv_state_stream surface_state_stream;
1152 void *surface_state_free_list;
1157 enum anv_descriptor_template_entry_type {
1158 ANV_DESCRIPTOR_TEMPLATE_ENTRY_TYPE_IMAGE,
1159 ANV_DESCRIPTOR_TEMPLATE_ENTRY_TYPE_BUFFER,
1160 ANV_DESCRIPTOR_TEMPLATE_ENTRY_TYPE_BUFFER_VIEW
1163 struct anv_descriptor_template_entry {
1164 /* The type of descriptor in this entry */
1165 VkDescriptorType type;
1167 /* Binding in the descriptor set */
1170 /* Offset at which to write into the descriptor set binding */
1171 uint32_t array_element;
1173 /* Number of elements to write into the descriptor set binding */
1174 uint32_t array_count;
1176 /* Offset into the user provided data */
1179 /* Stride between elements into the user provided data */
1183 struct anv_descriptor_update_template {
1184 /* The descriptor set this template corresponds to. This value is only
1185 * valid if the template was created with the templateType
1186 * VK_DESCRIPTOR_UPDATE_TEMPLATE_TYPE_DESCRIPTOR_SET_KHR.
1190 /* Number of entries in this template */
1191 uint32_t entry_count;
1193 /* Entries of the template */
1194 struct anv_descriptor_template_entry entries[0];
1198 anv_descriptor_set_layout_size(const struct anv_descriptor_set_layout *layout);
1201 anv_descriptor_set_write_image_view(struct anv_descriptor_set *set,
1202 const struct gen_device_info * const devinfo,
1203 const VkDescriptorImageInfo * const info,
1204 VkDescriptorType type,
1209 anv_descriptor_set_write_buffer_view(struct anv_descriptor_set *set,
1210 VkDescriptorType type,
1211 struct anv_buffer_view *buffer_view,
1216 anv_descriptor_set_write_buffer(struct anv_descriptor_set *set,
1217 struct anv_device *device,
1218 struct anv_state_stream *alloc_stream,
1219 VkDescriptorType type,
1220 struct anv_buffer *buffer,
1223 VkDeviceSize offset,
1224 VkDeviceSize range);
1227 anv_descriptor_set_write_template(struct anv_descriptor_set *set,
1228 struct anv_device *device,
1229 struct anv_state_stream *alloc_stream,
1230 const struct anv_descriptor_update_template *template,
1234 anv_descriptor_set_create(struct anv_device *device,
1235 struct anv_descriptor_pool *pool,
1236 const struct anv_descriptor_set_layout *layout,
1237 struct anv_descriptor_set **out_set);
1240 anv_descriptor_set_destroy(struct anv_device *device,
1241 struct anv_descriptor_pool *pool,
1242 struct anv_descriptor_set *set);
1244 #define ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS UINT8_MAX
1246 struct anv_pipeline_binding {
1247 /* The descriptor set this surface corresponds to. The special value of
1248 * ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS indicates that the offset refers
1249 * to a color attachment and not a regular descriptor.
1253 /* Binding in the descriptor set */
1256 /* Index in the binding */
1259 /* Input attachment index (relative to the subpass) */
1260 uint8_t input_attachment_index;
1262 /* For a storage image, whether it is write-only */
1266 struct anv_pipeline_layout {
1268 struct anv_descriptor_set_layout *layout;
1269 uint32_t dynamic_offset_start;
1275 bool has_dynamic_offsets;
1276 } stage[MESA_SHADER_STAGES];
1278 unsigned char sha1[20];
1282 struct anv_device * device;
1285 VkBufferUsageFlags usage;
1287 /* Set when bound */
1289 VkDeviceSize offset;
1292 static inline uint64_t
1293 anv_buffer_get_range(struct anv_buffer *buffer, uint64_t offset, uint64_t range)
1295 assert(offset <= buffer->size);
1296 if (range == VK_WHOLE_SIZE) {
1297 return buffer->size - offset;
1299 assert(range <= buffer->size);
1304 enum anv_cmd_dirty_bits {
1305 ANV_CMD_DIRTY_DYNAMIC_VIEWPORT = 1 << 0, /* VK_DYNAMIC_STATE_VIEWPORT */
1306 ANV_CMD_DIRTY_DYNAMIC_SCISSOR = 1 << 1, /* VK_DYNAMIC_STATE_SCISSOR */
1307 ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH = 1 << 2, /* VK_DYNAMIC_STATE_LINE_WIDTH */
1308 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS = 1 << 3, /* VK_DYNAMIC_STATE_DEPTH_BIAS */
1309 ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS = 1 << 4, /* VK_DYNAMIC_STATE_BLEND_CONSTANTS */
1310 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS = 1 << 5, /* VK_DYNAMIC_STATE_DEPTH_BOUNDS */
1311 ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK = 1 << 6, /* VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK */
1312 ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK = 1 << 7, /* VK_DYNAMIC_STATE_STENCIL_WRITE_MASK */
1313 ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE = 1 << 8, /* VK_DYNAMIC_STATE_STENCIL_REFERENCE */
1314 ANV_CMD_DIRTY_DYNAMIC_ALL = (1 << 9) - 1,
1315 ANV_CMD_DIRTY_PIPELINE = 1 << 9,
1316 ANV_CMD_DIRTY_INDEX_BUFFER = 1 << 10,
1317 ANV_CMD_DIRTY_RENDER_TARGETS = 1 << 11,
1319 typedef uint32_t anv_cmd_dirty_mask_t;
1321 enum anv_pipe_bits {
1322 ANV_PIPE_DEPTH_CACHE_FLUSH_BIT = (1 << 0),
1323 ANV_PIPE_STALL_AT_SCOREBOARD_BIT = (1 << 1),
1324 ANV_PIPE_STATE_CACHE_INVALIDATE_BIT = (1 << 2),
1325 ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT = (1 << 3),
1326 ANV_PIPE_VF_CACHE_INVALIDATE_BIT = (1 << 4),
1327 ANV_PIPE_DATA_CACHE_FLUSH_BIT = (1 << 5),
1328 ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT = (1 << 10),
1329 ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT = (1 << 11),
1330 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT = (1 << 12),
1331 ANV_PIPE_DEPTH_STALL_BIT = (1 << 13),
1332 ANV_PIPE_CS_STALL_BIT = (1 << 20),
1334 /* This bit does not exist directly in PIPE_CONTROL. Instead it means that
1335 * a flush has happened but not a CS stall. The next time we do any sort
1336 * of invalidation we need to insert a CS stall at that time. Otherwise,
1337 * we would have to CS stall on every flush which could be bad.
1339 ANV_PIPE_NEEDS_CS_STALL_BIT = (1 << 21),
1342 #define ANV_PIPE_FLUSH_BITS ( \
1343 ANV_PIPE_DEPTH_CACHE_FLUSH_BIT | \
1344 ANV_PIPE_DATA_CACHE_FLUSH_BIT | \
1345 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT)
1347 #define ANV_PIPE_STALL_BITS ( \
1348 ANV_PIPE_STALL_AT_SCOREBOARD_BIT | \
1349 ANV_PIPE_DEPTH_STALL_BIT | \
1350 ANV_PIPE_CS_STALL_BIT)
1352 #define ANV_PIPE_INVALIDATE_BITS ( \
1353 ANV_PIPE_STATE_CACHE_INVALIDATE_BIT | \
1354 ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT | \
1355 ANV_PIPE_VF_CACHE_INVALIDATE_BIT | \
1356 ANV_PIPE_DATA_CACHE_FLUSH_BIT | \
1357 ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT | \
1358 ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT)
1360 static inline enum anv_pipe_bits
1361 anv_pipe_flush_bits_for_access_flags(VkAccessFlags flags)
1363 enum anv_pipe_bits pipe_bits = 0;
1366 for_each_bit(b, flags) {
1367 switch ((VkAccessFlagBits)(1 << b)) {
1368 case VK_ACCESS_SHADER_WRITE_BIT:
1369 pipe_bits |= ANV_PIPE_DATA_CACHE_FLUSH_BIT;
1371 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT:
1372 pipe_bits |= ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT;
1374 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT:
1375 pipe_bits |= ANV_PIPE_DEPTH_CACHE_FLUSH_BIT;
1377 case VK_ACCESS_TRANSFER_WRITE_BIT:
1378 pipe_bits |= ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT;
1379 pipe_bits |= ANV_PIPE_DEPTH_CACHE_FLUSH_BIT;
1382 break; /* Nothing to do */
1389 static inline enum anv_pipe_bits
1390 anv_pipe_invalidate_bits_for_access_flags(VkAccessFlags flags)
1392 enum anv_pipe_bits pipe_bits = 0;
1395 for_each_bit(b, flags) {
1396 switch ((VkAccessFlagBits)(1 << b)) {
1397 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT:
1398 case VK_ACCESS_INDEX_READ_BIT:
1399 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT:
1400 pipe_bits |= ANV_PIPE_VF_CACHE_INVALIDATE_BIT;
1402 case VK_ACCESS_UNIFORM_READ_BIT:
1403 pipe_bits |= ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT;
1404 pipe_bits |= ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT;
1406 case VK_ACCESS_SHADER_READ_BIT:
1407 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT:
1408 case VK_ACCESS_TRANSFER_READ_BIT:
1409 pipe_bits |= ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT;
1412 break; /* Nothing to do */
1419 struct anv_vertex_binding {
1420 struct anv_buffer * buffer;
1421 VkDeviceSize offset;
1424 struct anv_push_constants {
1425 /* Current allocated size of this push constants data structure.
1426 * Because a decent chunk of it may not be used (images on SKL, for
1427 * instance), we won't actually allocate the entire structure up-front.
1431 /* Push constant data provided by the client through vkPushConstants */
1432 uint8_t client_data[MAX_PUSH_CONSTANTS_SIZE];
1434 /* Our hardware only provides zero-based vertex and instance id so, in
1435 * order to satisfy the vulkan requirements, we may have to push one or
1436 * both of these into the shader.
1438 uint32_t base_vertex;
1439 uint32_t base_instance;
1441 /* Image data for image_load_store on pre-SKL */
1442 struct brw_image_param images[MAX_IMAGES];
1445 struct anv_dynamic_state {
1448 VkViewport viewports[MAX_VIEWPORTS];
1453 VkRect2D scissors[MAX_SCISSORS];
1464 float blend_constants[4];
1474 } stencil_compare_mask;
1479 } stencil_write_mask;
1484 } stencil_reference;
1487 extern const struct anv_dynamic_state default_dynamic_state;
1489 void anv_dynamic_state_copy(struct anv_dynamic_state *dest,
1490 const struct anv_dynamic_state *src,
1491 uint32_t copy_mask);
1494 * Attachment state when recording a renderpass instance.
1496 * The clear value is valid only if there exists a pending clear.
1498 struct anv_attachment_state {
1499 enum isl_aux_usage aux_usage;
1500 enum isl_aux_usage input_aux_usage;
1501 struct anv_state color_rt_state;
1502 struct anv_state input_att_state;
1504 VkImageLayout current_layout;
1505 VkImageAspectFlags pending_clear_aspects;
1507 VkClearValue clear_value;
1508 bool clear_color_is_zero_one;
1511 /** State required while building cmd buffer */
1512 struct anv_cmd_state {
1513 /* PIPELINE_SELECT.PipelineSelection */
1514 uint32_t current_pipeline;
1515 const struct gen_l3_config * current_l3_config;
1517 anv_cmd_dirty_mask_t dirty;
1518 anv_cmd_dirty_mask_t compute_dirty;
1519 enum anv_pipe_bits pending_pipe_bits;
1520 uint32_t num_workgroups_offset;
1521 struct anv_bo *num_workgroups_bo;
1522 VkShaderStageFlags descriptors_dirty;
1523 VkShaderStageFlags push_constants_dirty;
1524 uint32_t scratch_size;
1525 struct anv_pipeline * pipeline;
1526 struct anv_pipeline * compute_pipeline;
1527 struct anv_framebuffer * framebuffer;
1528 struct anv_render_pass * pass;
1529 struct anv_subpass * subpass;
1530 VkRect2D render_area;
1531 uint32_t restart_index;
1532 struct anv_vertex_binding vertex_bindings[MAX_VBS];
1533 struct anv_descriptor_set * descriptors[MAX_SETS];
1534 uint32_t dynamic_offsets[MAX_DYNAMIC_BUFFERS];
1535 VkShaderStageFlags push_constant_stages;
1536 struct anv_push_constants * push_constants[MESA_SHADER_STAGES];
1537 struct anv_state binding_tables[MESA_SHADER_STAGES];
1538 struct anv_state samplers[MESA_SHADER_STAGES];
1539 struct anv_dynamic_state dynamic;
1542 struct anv_push_descriptor_set push_descriptor;
1545 * Whether or not the gen8 PMA fix is enabled. We ensure that, at the top
1546 * of any command buffer it is disabled by disabling it in EndCommandBuffer
1547 * and before invoking the secondary in ExecuteCommands.
1549 bool pma_fix_enabled;
1552 * Whether or not we know for certain that HiZ is enabled for the current
1553 * subpass. If, for whatever reason, we are unsure as to whether HiZ is
1554 * enabled or not, this will be false.
1559 * Array length is anv_cmd_state::pass::attachment_count. Array content is
1560 * valid only when recording a render pass instance.
1562 struct anv_attachment_state * attachments;
1565 * Surface states for color render targets. These are stored in a single
1566 * flat array. For depth-stencil attachments, the surface state is simply
1569 struct anv_state render_pass_states;
1572 * A null surface state of the right size to match the framebuffer. This
1573 * is one of the states in render_pass_states.
1575 struct anv_state null_surface_state;
1578 struct anv_buffer * index_buffer;
1579 uint32_t index_type; /**< 3DSTATE_INDEX_BUFFER.IndexFormat */
1580 uint32_t index_offset;
1584 struct anv_cmd_pool {
1585 VkAllocationCallbacks alloc;
1586 struct list_head cmd_buffers;
1589 #define ANV_CMD_BUFFER_BATCH_SIZE 8192
1591 enum anv_cmd_buffer_exec_mode {
1592 ANV_CMD_BUFFER_EXEC_MODE_PRIMARY,
1593 ANV_CMD_BUFFER_EXEC_MODE_EMIT,
1594 ANV_CMD_BUFFER_EXEC_MODE_GROW_AND_EMIT,
1595 ANV_CMD_BUFFER_EXEC_MODE_CHAIN,
1596 ANV_CMD_BUFFER_EXEC_MODE_COPY_AND_CHAIN,
1599 struct anv_cmd_buffer {
1600 VK_LOADER_DATA _loader_data;
1602 struct anv_device * device;
1604 struct anv_cmd_pool * pool;
1605 struct list_head pool_link;
1607 struct anv_batch batch;
1609 /* Fields required for the actual chain of anv_batch_bo's.
1611 * These fields are initialized by anv_cmd_buffer_init_batch_bo_chain().
1613 struct list_head batch_bos;
1614 enum anv_cmd_buffer_exec_mode exec_mode;
1616 /* A vector of anv_batch_bo pointers for every batch or surface buffer
1617 * referenced by this command buffer
1619 * initialized by anv_cmd_buffer_init_batch_bo_chain()
1621 struct u_vector seen_bbos;
1623 /* A vector of int32_t's for every block of binding tables.
1625 * initialized by anv_cmd_buffer_init_batch_bo_chain()
1627 struct u_vector bt_block_states;
1630 struct anv_reloc_list surface_relocs;
1631 /** Last seen surface state block pool center bo offset */
1632 uint32_t last_ss_pool_center;
1634 /* Serial for tracking buffer completion */
1637 /* Stream objects for storing temporary data */
1638 struct anv_state_stream surface_state_stream;
1639 struct anv_state_stream dynamic_state_stream;
1641 VkCommandBufferUsageFlags usage_flags;
1642 VkCommandBufferLevel level;
1644 struct anv_cmd_state state;
1647 VkResult anv_cmd_buffer_init_batch_bo_chain(struct anv_cmd_buffer *cmd_buffer);
1648 void anv_cmd_buffer_fini_batch_bo_chain(struct anv_cmd_buffer *cmd_buffer);
1649 void anv_cmd_buffer_reset_batch_bo_chain(struct anv_cmd_buffer *cmd_buffer);
1650 void anv_cmd_buffer_end_batch_buffer(struct anv_cmd_buffer *cmd_buffer);
1651 void anv_cmd_buffer_add_secondary(struct anv_cmd_buffer *primary,
1652 struct anv_cmd_buffer *secondary);
1653 void anv_cmd_buffer_prepare_execbuf(struct anv_cmd_buffer *cmd_buffer);
1654 VkResult anv_cmd_buffer_execbuf(struct anv_device *device,
1655 struct anv_cmd_buffer *cmd_buffer,
1656 const VkSemaphore *in_semaphores,
1657 uint32_t num_in_semaphores,
1658 const VkSemaphore *out_semaphores,
1659 uint32_t num_out_semaphores);
1661 VkResult anv_cmd_buffer_reset(struct anv_cmd_buffer *cmd_buffer);
1664 anv_cmd_buffer_ensure_push_constants_size(struct anv_cmd_buffer *cmd_buffer,
1665 gl_shader_stage stage, uint32_t size);
1666 #define anv_cmd_buffer_ensure_push_constant_field(cmd_buffer, stage, field) \
1667 anv_cmd_buffer_ensure_push_constants_size(cmd_buffer, stage, \
1668 (offsetof(struct anv_push_constants, field) + \
1669 sizeof(cmd_buffer->state.push_constants[0]->field)))
1671 struct anv_state anv_cmd_buffer_emit_dynamic(struct anv_cmd_buffer *cmd_buffer,
1672 const void *data, uint32_t size, uint32_t alignment);
1673 struct anv_state anv_cmd_buffer_merge_dynamic(struct anv_cmd_buffer *cmd_buffer,
1674 uint32_t *a, uint32_t *b,
1675 uint32_t dwords, uint32_t alignment);
1678 anv_cmd_buffer_surface_base_address(struct anv_cmd_buffer *cmd_buffer);
1680 anv_cmd_buffer_alloc_binding_table(struct anv_cmd_buffer *cmd_buffer,
1681 uint32_t entries, uint32_t *state_offset);
1683 anv_cmd_buffer_alloc_surface_state(struct anv_cmd_buffer *cmd_buffer);
1685 anv_cmd_buffer_alloc_dynamic_state(struct anv_cmd_buffer *cmd_buffer,
1686 uint32_t size, uint32_t alignment);
1689 anv_cmd_buffer_new_binding_table_block(struct anv_cmd_buffer *cmd_buffer);
1691 void gen8_cmd_buffer_emit_viewport(struct anv_cmd_buffer *cmd_buffer);
1692 void gen8_cmd_buffer_emit_depth_viewport(struct anv_cmd_buffer *cmd_buffer,
1693 bool depth_clamp_enable);
1694 void gen7_cmd_buffer_emit_scissor(struct anv_cmd_buffer *cmd_buffer);
1696 void anv_cmd_buffer_setup_attachments(struct anv_cmd_buffer *cmd_buffer,
1697 struct anv_render_pass *pass,
1698 struct anv_framebuffer *framebuffer,
1699 const VkClearValue *clear_values);
1701 void anv_cmd_buffer_emit_state_base_address(struct anv_cmd_buffer *cmd_buffer);
1704 anv_cmd_buffer_push_constants(struct anv_cmd_buffer *cmd_buffer,
1705 gl_shader_stage stage);
1707 anv_cmd_buffer_cs_push_constants(struct anv_cmd_buffer *cmd_buffer);
1709 void anv_cmd_buffer_clear_subpass(struct anv_cmd_buffer *cmd_buffer);
1710 void anv_cmd_buffer_resolve_subpass(struct anv_cmd_buffer *cmd_buffer);
1712 const struct anv_image_view *
1713 anv_cmd_buffer_get_depth_stencil_view(const struct anv_cmd_buffer *cmd_buffer);
1716 anv_cmd_buffer_alloc_blorp_binding_table(struct anv_cmd_buffer *cmd_buffer,
1717 uint32_t num_entries,
1718 uint32_t *state_offset,
1719 struct anv_state *bt_state);
1721 void anv_cmd_buffer_dump(struct anv_cmd_buffer *cmd_buffer);
1723 enum anv_fence_state {
1724 /** Indicates that this is a new (or newly reset fence) */
1725 ANV_FENCE_STATE_RESET,
1727 /** Indicates that this fence has been submitted to the GPU but is still
1728 * (as far as we know) in use by the GPU.
1730 ANV_FENCE_STATE_SUBMITTED,
1732 ANV_FENCE_STATE_SIGNALED,
1737 struct drm_i915_gem_execbuffer2 execbuf;
1738 struct drm_i915_gem_exec_object2 exec2_objects[1];
1739 enum anv_fence_state state;
1744 struct anv_state state;
1747 enum anv_semaphore_type {
1748 ANV_SEMAPHORE_TYPE_NONE = 0,
1749 ANV_SEMAPHORE_TYPE_DUMMY,
1750 ANV_SEMAPHORE_TYPE_BO,
1753 struct anv_semaphore_impl {
1754 enum anv_semaphore_type type;
1756 /* A BO representing this semaphore when type == ANV_SEMAPHORE_TYPE_BO.
1757 * This BO will be added to the object list on any execbuf2 calls for
1758 * which this semaphore is used as a wait or signal fence. When used as
1759 * a signal fence, the EXEC_OBJECT_WRITE flag will be set.
1764 struct anv_semaphore {
1765 /* Permanent semaphore state. Every semaphore has some form of permanent
1766 * state (type != ANV_SEMAPHORE_TYPE_NONE). This may be a BO to fence on
1767 * (for cross-process semaphores0 or it could just be a dummy for use
1770 struct anv_semaphore_impl permanent;
1772 /* Temporary semaphore state. A semaphore *may* have temporary state.
1773 * That state is added to the semaphore by an import operation and is reset
1774 * back to ANV_SEMAPHORE_TYPE_NONE when the semaphore is waited on. A
1775 * semaphore with temporary state cannot be signaled because the semaphore
1776 * must already be signaled before the temporary state can be exported from
1777 * the semaphore in the other process and imported here.
1779 struct anv_semaphore_impl temporary;
1782 struct anv_shader_module {
1783 unsigned char sha1[20];
1788 static inline gl_shader_stage
1789 vk_to_mesa_shader_stage(VkShaderStageFlagBits vk_stage)
1791 assert(__builtin_popcount(vk_stage) == 1);
1792 return ffs(vk_stage) - 1;
1795 static inline VkShaderStageFlagBits
1796 mesa_to_vk_shader_stage(gl_shader_stage mesa_stage)
1798 return (1 << mesa_stage);
1801 #define ANV_STAGE_MASK ((1 << MESA_SHADER_STAGES) - 1)
1803 #define anv_foreach_stage(stage, stage_bits) \
1804 for (gl_shader_stage stage, \
1805 __tmp = (gl_shader_stage)((stage_bits) & ANV_STAGE_MASK); \
1806 stage = __builtin_ffs(__tmp) - 1, __tmp; \
1807 __tmp &= ~(1 << (stage)))
1809 struct anv_pipeline_bind_map {
1810 uint32_t surface_count;
1811 uint32_t sampler_count;
1812 uint32_t image_count;
1814 struct anv_pipeline_binding * surface_to_descriptor;
1815 struct anv_pipeline_binding * sampler_to_descriptor;
1818 struct anv_shader_bin_key {
1823 struct anv_shader_bin {
1826 const struct anv_shader_bin_key *key;
1828 struct anv_state kernel;
1829 uint32_t kernel_size;
1831 const struct brw_stage_prog_data *prog_data;
1832 uint32_t prog_data_size;
1834 struct anv_pipeline_bind_map bind_map;
1836 /* Prog data follows, then params, then the key, all aligned to 8-bytes */
1839 struct anv_shader_bin *
1840 anv_shader_bin_create(struct anv_device *device,
1841 const void *key, uint32_t key_size,
1842 const void *kernel, uint32_t kernel_size,
1843 const struct brw_stage_prog_data *prog_data,
1844 uint32_t prog_data_size, const void *prog_data_param,
1845 const struct anv_pipeline_bind_map *bind_map);
1848 anv_shader_bin_destroy(struct anv_device *device, struct anv_shader_bin *shader);
1851 anv_shader_bin_ref(struct anv_shader_bin *shader)
1853 assert(shader && shader->ref_cnt >= 1);
1854 __sync_fetch_and_add(&shader->ref_cnt, 1);
1858 anv_shader_bin_unref(struct anv_device *device, struct anv_shader_bin *shader)
1860 assert(shader && shader->ref_cnt >= 1);
1861 if (__sync_fetch_and_add(&shader->ref_cnt, -1) == 1)
1862 anv_shader_bin_destroy(device, shader);
1865 struct anv_pipeline {
1866 struct anv_device * device;
1867 struct anv_batch batch;
1868 uint32_t batch_data[512];
1869 struct anv_reloc_list batch_relocs;
1870 uint32_t dynamic_state_mask;
1871 struct anv_dynamic_state dynamic_state;
1873 struct anv_subpass * subpass;
1874 struct anv_pipeline_layout * layout;
1876 bool needs_data_cache;
1878 struct anv_shader_bin * shaders[MESA_SHADER_STAGES];
1881 const struct gen_l3_config * l3_config;
1882 uint32_t total_size;
1885 VkShaderStageFlags active_stages;
1886 struct anv_state blend_state;
1889 uint32_t binding_stride[MAX_VBS];
1890 bool instancing_enable[MAX_VBS];
1891 bool primitive_restart;
1894 uint32_t cs_right_mask;
1897 bool depth_test_enable;
1898 bool writes_stencil;
1899 bool stencil_test_enable;
1900 bool depth_clamp_enable;
1901 bool sample_shading_enable;
1906 uint32_t depth_stencil_state[3];
1912 uint32_t wm_depth_stencil[3];
1916 uint32_t wm_depth_stencil[4];
1919 uint32_t interface_descriptor_data[8];
1923 anv_pipeline_has_stage(const struct anv_pipeline *pipeline,
1924 gl_shader_stage stage)
1926 return (pipeline->active_stages & mesa_to_vk_shader_stage(stage)) != 0;
1929 #define ANV_DECL_GET_PROG_DATA_FUNC(prefix, stage) \
1930 static inline const struct brw_##prefix##_prog_data * \
1931 get_##prefix##_prog_data(const struct anv_pipeline *pipeline) \
1933 if (anv_pipeline_has_stage(pipeline, stage)) { \
1934 return (const struct brw_##prefix##_prog_data *) \
1935 pipeline->shaders[stage]->prog_data; \
1941 ANV_DECL_GET_PROG_DATA_FUNC(vs, MESA_SHADER_VERTEX)
1942 ANV_DECL_GET_PROG_DATA_FUNC(tcs, MESA_SHADER_TESS_CTRL)
1943 ANV_DECL_GET_PROG_DATA_FUNC(tes, MESA_SHADER_TESS_EVAL)
1944 ANV_DECL_GET_PROG_DATA_FUNC(gs, MESA_SHADER_GEOMETRY)
1945 ANV_DECL_GET_PROG_DATA_FUNC(wm, MESA_SHADER_FRAGMENT)
1946 ANV_DECL_GET_PROG_DATA_FUNC(cs, MESA_SHADER_COMPUTE)
1948 static inline const struct brw_vue_prog_data *
1949 anv_pipeline_get_last_vue_prog_data(const struct anv_pipeline *pipeline)
1951 if (anv_pipeline_has_stage(pipeline, MESA_SHADER_GEOMETRY))
1952 return &get_gs_prog_data(pipeline)->base;
1953 else if (anv_pipeline_has_stage(pipeline, MESA_SHADER_TESS_EVAL))
1954 return &get_tes_prog_data(pipeline)->base;
1956 return &get_vs_prog_data(pipeline)->base;
1960 anv_pipeline_init(struct anv_pipeline *pipeline, struct anv_device *device,
1961 struct anv_pipeline_cache *cache,
1962 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1963 const VkAllocationCallbacks *alloc);
1966 anv_pipeline_compile_cs(struct anv_pipeline *pipeline,
1967 struct anv_pipeline_cache *cache,
1968 const VkComputePipelineCreateInfo *info,
1969 struct anv_shader_module *module,
1970 const char *entrypoint,
1971 const VkSpecializationInfo *spec_info);
1974 enum isl_format isl_format:16;
1975 struct isl_swizzle swizzle;
1979 anv_get_format(const struct gen_device_info *devinfo, VkFormat format,
1980 VkImageAspectFlags aspect, VkImageTiling tiling);
1982 static inline enum isl_format
1983 anv_get_isl_format(const struct gen_device_info *devinfo, VkFormat vk_format,
1984 VkImageAspectFlags aspect, VkImageTiling tiling)
1986 return anv_get_format(devinfo, vk_format, aspect, tiling).isl_format;
1989 static inline struct isl_swizzle
1990 anv_swizzle_for_render(struct isl_swizzle swizzle)
1992 /* Sometimes the swizzle will have alpha map to one. We do this to fake
1993 * RGB as RGBA for texturing
1995 assert(swizzle.a == ISL_CHANNEL_SELECT_ONE ||
1996 swizzle.a == ISL_CHANNEL_SELECT_ALPHA);
1998 /* But it doesn't matter what we render to that channel */
1999 swizzle.a = ISL_CHANNEL_SELECT_ALPHA;
2005 anv_pipeline_setup_l3_config(struct anv_pipeline *pipeline, bool needs_slm);
2008 * Subsurface of an anv_image.
2010 struct anv_surface {
2011 /** Valid only if isl_surf::size > 0. */
2012 struct isl_surf isl;
2015 * Offset from VkImage's base address, as bound by vkBindImageMemory().
2022 /* The original VkFormat provided by the client. This may not match any
2023 * of the actual surface formats.
2026 VkImageAspectFlags aspects;
2029 uint32_t array_size;
2030 uint32_t samples; /**< VkImageCreateInfo::samples */
2031 VkImageUsageFlags usage; /**< Superset of VkImageCreateInfo::usage. */
2032 VkImageTiling tiling; /** VkImageCreateInfo::tiling */
2037 /* Set when bound */
2039 VkDeviceSize offset;
2044 * For each foo, anv_image::foo_surface is valid if and only if
2045 * anv_image::aspects has a foo aspect.
2047 * The hardware requires that the depth buffer and stencil buffer be
2048 * separate surfaces. From Vulkan's perspective, though, depth and stencil
2049 * reside in the same VkImage. To satisfy both the hardware and Vulkan, we
2050 * allocate the depth and stencil buffers as separate surfaces in the same
2054 struct anv_surface color_surface;
2057 struct anv_surface depth_surface;
2058 struct anv_surface stencil_surface;
2063 * For color images, this is the aux usage for this image when not used as a
2066 * For depth/stencil images, this is set to ISL_AUX_USAGE_HIZ if the image
2069 enum isl_aux_usage aux_usage;
2071 struct anv_surface aux_surface;
2074 /* Returns true if a HiZ-enabled depth buffer can be sampled from. */
2076 anv_can_sample_with_hiz(const struct gen_device_info * const devinfo,
2077 const VkImageAspectFlags aspect_mask,
2078 const uint32_t samples)
2080 /* Validate the inputs. */
2081 assert(devinfo && aspect_mask && samples);
2082 return devinfo->gen >= 8 && (aspect_mask & VK_IMAGE_ASPECT_DEPTH_BIT) &&
2087 anv_gen8_hiz_op_resolve(struct anv_cmd_buffer *cmd_buffer,
2088 const struct anv_image *image,
2089 enum blorp_hiz_op op);
2092 anv_image_ccs_clear(struct anv_cmd_buffer *cmd_buffer,
2093 const struct anv_image *image,
2094 const struct isl_view *view,
2095 const VkImageSubresourceRange *subresourceRange);
2098 anv_layout_to_aux_usage(const struct gen_device_info * const devinfo,
2099 const struct anv_image *image,
2100 const VkImageAspectFlags aspects,
2101 const VkImageLayout layout);
2103 /* This is defined as a macro so that it works for both
2104 * VkImageSubresourceRange and VkImageSubresourceLayers
2106 #define anv_get_layerCount(_image, _range) \
2107 ((_range)->layerCount == VK_REMAINING_ARRAY_LAYERS ? \
2108 (_image)->array_size - (_range)->baseArrayLayer : (_range)->layerCount)
2110 static inline uint32_t
2111 anv_get_levelCount(const struct anv_image *image,
2112 const VkImageSubresourceRange *range)
2114 return range->levelCount == VK_REMAINING_MIP_LEVELS ?
2115 image->levels - range->baseMipLevel : range->levelCount;
2119 struct anv_image_view {
2120 const struct anv_image *image; /**< VkImageViewCreateInfo::image */
2122 uint32_t offset; /**< Offset into bo. */
2124 struct isl_view isl;
2126 VkImageAspectFlags aspect_mask;
2128 VkExtent3D extent; /**< Extent of VkImageViewCreateInfo::baseMipLevel. */
2130 /** RENDER_SURFACE_STATE when using image as a sampler surface. */
2131 struct anv_state sampler_surface_state;
2134 * RENDER_SURFACE_STATE when using image as a sampler surface with the
2135 * auxiliary buffer disabled.
2137 struct anv_state no_aux_sampler_surface_state;
2140 * RENDER_SURFACE_STATE when using image as a storage image. Separate states
2141 * for write-only and readable, using the real format for write-only and the
2142 * lowered format for readable.
2144 struct anv_state storage_surface_state;
2145 struct anv_state writeonly_storage_surface_state;
2147 struct brw_image_param storage_image_param;
2150 struct anv_image_create_info {
2151 const VkImageCreateInfo *vk_info;
2153 /** An opt-in bitmask which filters an ISL-mapping of the Vulkan tiling. */
2154 isl_tiling_flags_t isl_tiling_flags;
2159 VkResult anv_image_create(VkDevice _device,
2160 const struct anv_image_create_info *info,
2161 const VkAllocationCallbacks* alloc,
2164 const struct anv_surface *
2165 anv_image_get_surface_for_aspect_mask(const struct anv_image *image,
2166 VkImageAspectFlags aspect_mask);
2169 anv_isl_format_for_descriptor_type(VkDescriptorType type);
2171 static inline struct VkExtent3D
2172 anv_sanitize_image_extent(const VkImageType imageType,
2173 const struct VkExtent3D imageExtent)
2175 switch (imageType) {
2176 case VK_IMAGE_TYPE_1D:
2177 return (VkExtent3D) { imageExtent.width, 1, 1 };
2178 case VK_IMAGE_TYPE_2D:
2179 return (VkExtent3D) { imageExtent.width, imageExtent.height, 1 };
2180 case VK_IMAGE_TYPE_3D:
2183 unreachable("invalid image type");
2187 static inline struct VkOffset3D
2188 anv_sanitize_image_offset(const VkImageType imageType,
2189 const struct VkOffset3D imageOffset)
2191 switch (imageType) {
2192 case VK_IMAGE_TYPE_1D:
2193 return (VkOffset3D) { imageOffset.x, 0, 0 };
2194 case VK_IMAGE_TYPE_2D:
2195 return (VkOffset3D) { imageOffset.x, imageOffset.y, 0 };
2196 case VK_IMAGE_TYPE_3D:
2199 unreachable("invalid image type");
2204 void anv_fill_buffer_surface_state(struct anv_device *device,
2205 struct anv_state state,
2206 enum isl_format format,
2207 uint32_t offset, uint32_t range,
2210 void anv_image_view_fill_image_param(struct anv_device *device,
2211 struct anv_image_view *view,
2212 struct brw_image_param *param);
2213 void anv_buffer_view_fill_image_param(struct anv_device *device,
2214 struct anv_buffer_view *view,
2215 struct brw_image_param *param);
2217 struct anv_sampler {
2221 struct anv_framebuffer {
2226 uint32_t attachment_count;
2227 struct anv_image_view * attachments[0];
2230 struct anv_subpass {
2231 uint32_t attachment_count;
2234 * A pointer to all attachment references used in this subpass.
2235 * Only valid if ::attachment_count > 0.
2237 VkAttachmentReference * attachments;
2238 uint32_t input_count;
2239 VkAttachmentReference * input_attachments;
2240 uint32_t color_count;
2241 VkAttachmentReference * color_attachments;
2242 VkAttachmentReference * resolve_attachments;
2244 VkAttachmentReference depth_stencil_attachment;
2248 /** Subpass has a depth/stencil self-dependency */
2249 bool has_ds_self_dep;
2251 /** Subpass has at least one resolve attachment */
2255 static inline unsigned
2256 anv_subpass_view_count(const struct anv_subpass *subpass)
2258 return MAX2(1, _mesa_bitcount(subpass->view_mask));
2261 enum anv_subpass_usage {
2262 ANV_SUBPASS_USAGE_DRAW = (1 << 0),
2263 ANV_SUBPASS_USAGE_INPUT = (1 << 1),
2264 ANV_SUBPASS_USAGE_RESOLVE_SRC = (1 << 2),
2265 ANV_SUBPASS_USAGE_RESOLVE_DST = (1 << 3),
2268 struct anv_render_pass_attachment {
2269 /* TODO: Consider using VkAttachmentDescription instead of storing each of
2270 * its members individually.
2274 VkImageUsageFlags usage;
2275 VkAttachmentLoadOp load_op;
2276 VkAttachmentStoreOp store_op;
2277 VkAttachmentLoadOp stencil_load_op;
2278 VkImageLayout initial_layout;
2279 VkImageLayout final_layout;
2281 /* An array, indexed by subpass id, of how the attachment will be used. */
2282 enum anv_subpass_usage * subpass_usage;
2284 /* The subpass id in which the attachment will be used last. */
2285 uint32_t last_subpass_idx;
2288 struct anv_render_pass {
2289 uint32_t attachment_count;
2290 uint32_t subpass_count;
2291 /* An array of subpass_count+1 flushes, one per subpass boundary */
2292 enum anv_pipe_bits * subpass_flushes;
2293 struct anv_render_pass_attachment * attachments;
2294 struct anv_subpass subpasses[0];
2297 #define ANV_PIPELINE_STATISTICS_MASK 0x000007ff
2299 struct anv_query_pool {
2301 VkQueryPipelineStatisticFlags pipeline_statistics;
2302 /** Stride between slots, in bytes */
2304 /** Number of slots in this query pool */
2309 void *anv_lookup_entrypoint(const struct gen_device_info *devinfo,
2312 void anv_dump_image_to_ppm(struct anv_device *device,
2313 struct anv_image *image, unsigned miplevel,
2314 unsigned array_layer, VkImageAspectFlagBits aspect,
2315 const char *filename);
2317 enum anv_dump_action {
2318 ANV_DUMP_FRAMEBUFFERS_BIT = 0x1,
2321 void anv_dump_start(struct anv_device *device, enum anv_dump_action actions);
2322 void anv_dump_finish(void);
2324 void anv_dump_add_framebuffer(struct anv_cmd_buffer *cmd_buffer,
2325 struct anv_framebuffer *fb);
2327 static inline uint32_t
2328 anv_get_subpass_id(const struct anv_cmd_state * const cmd_state)
2330 /* This function must be called from within a subpass. */
2331 assert(cmd_state->pass && cmd_state->subpass);
2333 const uint32_t subpass_id = cmd_state->subpass - cmd_state->pass->subpasses;
2335 /* The id of this subpass shouldn't exceed the number of subpasses in this
2336 * render pass minus 1.
2338 assert(subpass_id < cmd_state->pass->subpass_count);
2342 #define ANV_DEFINE_HANDLE_CASTS(__anv_type, __VkType) \
2344 static inline struct __anv_type * \
2345 __anv_type ## _from_handle(__VkType _handle) \
2347 return (struct __anv_type *) _handle; \
2350 static inline __VkType \
2351 __anv_type ## _to_handle(struct __anv_type *_obj) \
2353 return (__VkType) _obj; \
2356 #define ANV_DEFINE_NONDISP_HANDLE_CASTS(__anv_type, __VkType) \
2358 static inline struct __anv_type * \
2359 __anv_type ## _from_handle(__VkType _handle) \
2361 return (struct __anv_type *)(uintptr_t) _handle; \
2364 static inline __VkType \
2365 __anv_type ## _to_handle(struct __anv_type *_obj) \
2367 return (__VkType)(uintptr_t) _obj; \
2370 #define ANV_FROM_HANDLE(__anv_type, __name, __handle) \
2371 struct __anv_type *__name = __anv_type ## _from_handle(__handle)
2373 ANV_DEFINE_HANDLE_CASTS(anv_cmd_buffer, VkCommandBuffer)
2374 ANV_DEFINE_HANDLE_CASTS(anv_device, VkDevice)
2375 ANV_DEFINE_HANDLE_CASTS(anv_instance, VkInstance)
2376 ANV_DEFINE_HANDLE_CASTS(anv_physical_device, VkPhysicalDevice)
2377 ANV_DEFINE_HANDLE_CASTS(anv_queue, VkQueue)
2379 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_cmd_pool, VkCommandPool)
2380 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_buffer, VkBuffer)
2381 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_buffer_view, VkBufferView)
2382 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_pool, VkDescriptorPool)
2383 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_set, VkDescriptorSet)
2384 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_set_layout, VkDescriptorSetLayout)
2385 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_update_template, VkDescriptorUpdateTemplateKHR)
2386 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_device_memory, VkDeviceMemory)
2387 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_fence, VkFence)
2388 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_event, VkEvent)
2389 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_framebuffer, VkFramebuffer)
2390 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_image, VkImage)
2391 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_image_view, VkImageView);
2392 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_pipeline_cache, VkPipelineCache)
2393 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_pipeline, VkPipeline)
2394 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_pipeline_layout, VkPipelineLayout)
2395 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_query_pool, VkQueryPool)
2396 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_render_pass, VkRenderPass)
2397 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_sampler, VkSampler)
2398 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_semaphore, VkSemaphore)
2399 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_shader_module, VkShaderModule)
2401 /* Gen-specific function declarations */
2403 # include "anv_genX.h"
2405 # define genX(x) gen7_##x
2406 # include "anv_genX.h"
2408 # define genX(x) gen75_##x
2409 # include "anv_genX.h"
2411 # define genX(x) gen8_##x
2412 # include "anv_genX.h"
2414 # define genX(x) gen9_##x
2415 # include "anv_genX.h"
2419 #endif /* ANV_PRIVATE_H */