2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
38 #define __gen_validate_value(x) VALGRIND_CHECK_MEM_IS_DEFINED(&(x), sizeof(x))
43 #include "brw_device_info.h"
44 #include "brw_compiler.h"
45 #include "util/macros.h"
46 #include "util/list.h"
48 /* Pre-declarations needed for WSI entrypoints */
51 typedef struct xcb_connection_t xcb_connection_t;
52 typedef uint32_t xcb_visualid_t;
53 typedef uint32_t xcb_window_t;
57 #include <vulkan/vulkan.h>
58 #include <vulkan/vulkan_intel.h>
59 #include <vulkan/vk_icd.h>
61 #include "anv_entrypoints.h"
62 #include "brw_context.h"
72 #define MAX_VIEWPORTS 16
73 #define MAX_SCISSORS 16
74 #define MAX_PUSH_CONSTANTS_SIZE 128
75 #define MAX_DYNAMIC_BUFFERS 16
77 #define MAX_SAMPLES_LOG2 4 /* SKL supports 16 samples */
79 #define anv_noreturn __attribute__((__noreturn__))
80 #define anv_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
82 #define MIN(a, b) ((a) < (b) ? (a) : (b))
83 #define MAX(a, b) ((a) > (b) ? (a) : (b))
85 static inline uint32_t
86 align_down_npot_u32(uint32_t v, uint32_t a)
91 static inline uint32_t
92 align_u32(uint32_t v, uint32_t a)
94 assert(a != 0 && a == (a & -a));
95 return (v + a - 1) & ~(a - 1);
98 static inline uint64_t
99 align_u64(uint64_t v, uint64_t a)
101 assert(a != 0 && a == (a & -a));
102 return (v + a - 1) & ~(a - 1);
105 static inline int32_t
106 align_i32(int32_t v, int32_t a)
108 assert(a != 0 && a == (a & -a));
109 return (v + a - 1) & ~(a - 1);
112 /** Alignment must be a power of 2. */
114 anv_is_aligned(uintmax_t n, uintmax_t a)
116 assert(a == (a & -a));
117 return (n & (a - 1)) == 0;
120 static inline uint32_t
121 anv_minify(uint32_t n, uint32_t levels)
123 if (unlikely(n == 0))
126 return MAX(n >> levels, 1);
130 anv_clamp_f(float f, float min, float max)
143 anv_clear_mask(uint32_t *inout_mask, uint32_t clear_mask)
145 if (*inout_mask & clear_mask) {
146 *inout_mask &= ~clear_mask;
153 #define for_each_bit(b, dword) \
154 for (uint32_t __dword = (dword); \
155 (b) = __builtin_ffs(__dword) - 1, __dword; \
156 __dword &= ~(1 << (b)))
158 #define typed_memcpy(dest, src, count) ({ \
159 static_assert(sizeof(*src) == sizeof(*dest), ""); \
160 memcpy((dest), (src), (count) * sizeof(*(src))); \
163 #define zero(x) (memset(&(x), 0, sizeof(x)))
165 /* Define no kernel as 1, since that's an illegal offset for a kernel */
169 VkStructureType sType;
173 /* Whenever we generate an error, pass it through this function. Useful for
174 * debugging, where we can break on it. Only call at error site, not when
175 * propagating errors. Might be useful to plug in a stack trace here.
178 VkResult __vk_errorf(VkResult error, const char *file, int line, const char *format, ...);
181 #define vk_error(error) __vk_errorf(error, __FILE__, __LINE__, NULL);
182 #define vk_errorf(error, format, ...) __vk_errorf(error, __FILE__, __LINE__, format, ## __VA_ARGS__);
184 #define vk_error(error) error
185 #define vk_errorf(error, format, ...) error
188 void __anv_finishme(const char *file, int line, const char *format, ...)
189 anv_printflike(3, 4);
190 void anv_loge(const char *format, ...) anv_printflike(1, 2);
191 void anv_loge_v(const char *format, va_list va);
194 * Print a FINISHME message, including its source location.
196 #define anv_finishme(format, ...) \
197 __anv_finishme(__FILE__, __LINE__, format, ##__VA_ARGS__);
199 /* A non-fatal assert. Useful for debugging. */
201 #define anv_assert(x) ({ \
202 if (unlikely(!(x))) \
203 fprintf(stderr, "%s:%d ASSERT: %s\n", __FILE__, __LINE__, #x); \
206 #define anv_assert(x)
210 * If a block of code is annotated with anv_validate, then the block runs only
214 #define anv_validate if (1)
216 #define anv_validate if (0)
219 void anv_abortf(const char *format, ...) anv_noreturn anv_printflike(1, 2);
220 void anv_abortfv(const char *format, va_list va) anv_noreturn;
222 #define stub_return(v) \
224 anv_finishme("stub %s", __func__); \
230 anv_finishme("stub %s", __func__); \
235 * A dynamically growable, circular buffer. Elements are added at head and
236 * removed from tail. head and tail are free-running uint32_t indices and we
237 * only compute the modulo with size when accessing the array. This way,
238 * number of bytes in the queue is always head - tail, even in case of
245 uint32_t element_size;
250 int anv_vector_init(struct anv_vector *queue, uint32_t element_size, uint32_t size);
251 void *anv_vector_add(struct anv_vector *queue);
252 void *anv_vector_remove(struct anv_vector *queue);
255 anv_vector_length(struct anv_vector *queue)
257 return (queue->head - queue->tail) / queue->element_size;
261 anv_vector_head(struct anv_vector *vector)
263 assert(vector->tail < vector->head);
264 return (void *)((char *)vector->data +
265 ((vector->head - vector->element_size) &
266 (vector->size - 1)));
270 anv_vector_tail(struct anv_vector *vector)
272 return (void *)((char *)vector->data + (vector->tail & (vector->size - 1)));
276 anv_vector_finish(struct anv_vector *queue)
281 #define anv_vector_foreach(elem, queue) \
282 static_assert(__builtin_types_compatible_p(__typeof__(queue), struct anv_vector *), ""); \
283 for (uint32_t __anv_vector_offset = (queue)->tail; \
284 elem = (queue)->data + (__anv_vector_offset & ((queue)->size - 1)), __anv_vector_offset < (queue)->head; \
285 __anv_vector_offset += (queue)->element_size)
290 /* Index into the current validation list. This is used by the
291 * validation list building alrogithm to track which buffers are already
292 * in the validation list so that we can ensure uniqueness.
296 /* Last known offset. This value is provided by the kernel when we
297 * execbuf and is used as the presumed offset for the next bunch of
305 /* We need to set the WRITE flag on winsys bos so GEM will know we're
306 * writing to them and synchronize uses on other rings (eg if the display
307 * server uses the blitter ring).
312 /* Represents a lock-free linked list of "free" things. This is used by
313 * both the block pool and the state pools. Unfortunately, in order to
314 * solve the ABA problem, we can't use a single uint32_t head.
316 union anv_free_list {
320 /* A simple count that is incremented every time the head changes. */
326 #define ANV_FREE_LIST_EMPTY ((union anv_free_list) { { 1, 0 } })
328 struct anv_block_state {
338 struct anv_block_pool {
339 struct anv_device *device;
343 /* The offset from the start of the bo to the "center" of the block
344 * pool. Pointers to allocated blocks are given by
345 * bo.map + center_bo_offset + offsets.
347 uint32_t center_bo_offset;
349 /* Current memory map of the block pool. This pointer may or may not
350 * point to the actual beginning of the block pool memory. If
351 * anv_block_pool_alloc_back has ever been called, then this pointer
352 * will point to the "center" position of the buffer and all offsets
353 * (negative or positive) given out by the block pool alloc functions
354 * will be valid relative to this pointer.
356 * In particular, map == bo.map + center_offset
362 * Array of mmaps and gem handles owned by the block pool, reclaimed when
363 * the block pool is destroyed.
365 struct anv_vector mmap_cleanups;
369 union anv_free_list free_list;
370 struct anv_block_state state;
372 union anv_free_list back_free_list;
373 struct anv_block_state back_state;
376 /* Block pools are backed by a fixed-size 2GB memfd */
377 #define BLOCK_POOL_MEMFD_SIZE (1ull << 32)
379 /* The center of the block pool is also the middle of the memfd. This may
380 * change in the future if we decide differently for some reason.
382 #define BLOCK_POOL_MEMFD_CENTER (BLOCK_POOL_MEMFD_SIZE / 2)
384 static inline uint32_t
385 anv_block_pool_size(struct anv_block_pool *pool)
387 return pool->state.end + pool->back_state.end;
396 struct anv_fixed_size_state_pool {
398 union anv_free_list free_list;
399 struct anv_block_state block;
402 #define ANV_MIN_STATE_SIZE_LOG2 6
403 #define ANV_MAX_STATE_SIZE_LOG2 10
405 #define ANV_STATE_BUCKETS (ANV_MAX_STATE_SIZE_LOG2 - ANV_MIN_STATE_SIZE_LOG2)
407 struct anv_state_pool {
408 struct anv_block_pool *block_pool;
409 struct anv_fixed_size_state_pool buckets[ANV_STATE_BUCKETS];
412 struct anv_state_stream_block;
414 struct anv_state_stream {
415 struct anv_block_pool *block_pool;
417 /* The current working block */
418 struct anv_state_stream_block *block;
420 /* Offset at which the current block starts */
422 /* Offset at which to allocate the next state */
424 /* Offset at which the current block ends */
428 #define CACHELINE_SIZE 64
429 #define CACHELINE_MASK 63
432 anv_clflush_range(void *start, size_t size)
434 void *p = (void *) (((uintptr_t) start) & ~CACHELINE_MASK);
435 void *end = start + size;
437 __builtin_ia32_mfence();
439 __builtin_ia32_clflush(p);
445 anv_state_clflush(struct anv_state state)
447 anv_clflush_range(state.map, state.alloc_size);
450 void anv_block_pool_init(struct anv_block_pool *pool,
451 struct anv_device *device, uint32_t block_size);
452 void anv_block_pool_finish(struct anv_block_pool *pool);
453 int32_t anv_block_pool_alloc(struct anv_block_pool *pool);
454 int32_t anv_block_pool_alloc_back(struct anv_block_pool *pool);
455 void anv_block_pool_free(struct anv_block_pool *pool, int32_t offset);
456 void anv_state_pool_init(struct anv_state_pool *pool,
457 struct anv_block_pool *block_pool);
458 void anv_state_pool_finish(struct anv_state_pool *pool);
459 struct anv_state anv_state_pool_alloc(struct anv_state_pool *pool,
460 size_t state_size, size_t alignment);
461 void anv_state_pool_free(struct anv_state_pool *pool, struct anv_state state);
462 void anv_state_stream_init(struct anv_state_stream *stream,
463 struct anv_block_pool *block_pool);
464 void anv_state_stream_finish(struct anv_state_stream *stream);
465 struct anv_state anv_state_stream_alloc(struct anv_state_stream *stream,
466 uint32_t size, uint32_t alignment);
469 * Implements a pool of re-usable BOs. The interface is identical to that
470 * of block_pool except that each block is its own BO.
473 struct anv_device *device;
478 void anv_bo_pool_init(struct anv_bo_pool *pool, struct anv_device *device);
479 void anv_bo_pool_finish(struct anv_bo_pool *pool);
480 VkResult anv_bo_pool_alloc(struct anv_bo_pool *pool, struct anv_bo *bo,
482 void anv_bo_pool_free(struct anv_bo_pool *pool, const struct anv_bo *bo);
484 struct anv_scratch_pool {
485 /* Indexed by Per-Thread Scratch Space number (the hardware value) and stage */
486 struct anv_bo bos[16][MESA_SHADER_STAGES];
489 void anv_scratch_pool_init(struct anv_device *device,
490 struct anv_scratch_pool *pool);
491 void anv_scratch_pool_finish(struct anv_device *device,
492 struct anv_scratch_pool *pool);
493 struct anv_bo *anv_scratch_pool_alloc(struct anv_device *device,
494 struct anv_scratch_pool *pool,
495 gl_shader_stage stage,
496 unsigned per_thread_scratch);
498 void *anv_resolve_entrypoint(uint32_t index);
500 extern struct anv_dispatch_table dtable;
502 #define ANV_CALL(func) ({ \
503 if (dtable.func == NULL) { \
504 size_t idx = offsetof(struct anv_dispatch_table, func) / sizeof(void *); \
505 dtable.entrypoints[idx] = anv_resolve_entrypoint(idx); \
511 anv_alloc(const VkAllocationCallbacks *alloc,
512 size_t size, size_t align,
513 VkSystemAllocationScope scope)
515 return alloc->pfnAllocation(alloc->pUserData, size, align, scope);
519 anv_realloc(const VkAllocationCallbacks *alloc,
520 void *ptr, size_t size, size_t align,
521 VkSystemAllocationScope scope)
523 return alloc->pfnReallocation(alloc->pUserData, ptr, size, align, scope);
527 anv_free(const VkAllocationCallbacks *alloc, void *data)
529 alloc->pfnFree(alloc->pUserData, data);
533 anv_alloc2(const VkAllocationCallbacks *parent_alloc,
534 const VkAllocationCallbacks *alloc,
535 size_t size, size_t align,
536 VkSystemAllocationScope scope)
539 return anv_alloc(alloc, size, align, scope);
541 return anv_alloc(parent_alloc, size, align, scope);
545 anv_free2(const VkAllocationCallbacks *parent_alloc,
546 const VkAllocationCallbacks *alloc,
550 anv_free(alloc, data);
552 anv_free(parent_alloc, data);
555 struct anv_wsi_interaface;
557 #define VK_ICD_WSI_PLATFORM_MAX 5
559 struct anv_physical_device {
560 VK_LOADER_DATA _loader_data;
562 struct anv_instance * instance;
566 const struct brw_device_info * info;
567 uint64_t aperture_size;
568 struct brw_compiler * compiler;
569 struct isl_device isl_dev;
570 int cmd_parser_version;
572 struct anv_wsi_interface * wsi[VK_ICD_WSI_PLATFORM_MAX];
575 struct anv_instance {
576 VK_LOADER_DATA _loader_data;
578 VkAllocationCallbacks alloc;
581 int physicalDeviceCount;
582 struct anv_physical_device physicalDevice;
585 VkResult anv_init_wsi(struct anv_physical_device *physical_device);
586 void anv_finish_wsi(struct anv_physical_device *physical_device);
588 struct anv_meta_state {
589 VkAllocationCallbacks alloc;
592 * Use array element `i` for images with `2^i` samples.
596 * Pipeline N is used to clear color attachment N of the current
599 * HACK: We use one pipeline per color attachment to work around the
600 * compiler's inability to dynamically set the render target index of
601 * the render target write message.
603 struct anv_pipeline *color_pipelines[MAX_RTS];
605 struct anv_pipeline *depth_only_pipeline;
606 struct anv_pipeline *stencil_only_pipeline;
607 struct anv_pipeline *depthstencil_pipeline;
608 } clear[1 + MAX_SAMPLES_LOG2];
611 VkRenderPass render_pass;
613 /** Pipeline that blits from a 1D image. */
614 VkPipeline pipeline_1d_src;
616 /** Pipeline that blits from a 2D image. */
617 VkPipeline pipeline_2d_src;
619 /** Pipeline that blits from a 3D image. */
620 VkPipeline pipeline_3d_src;
622 VkPipelineLayout pipeline_layout;
623 VkDescriptorSetLayout ds_layout;
627 VkRenderPass render_pass;
629 VkPipelineLayout img_p_layout;
630 VkDescriptorSetLayout img_ds_layout;
631 VkPipelineLayout buf_p_layout;
632 VkDescriptorSetLayout buf_ds_layout;
634 /* Pipelines indexed by source and destination type. See the
635 * blit2d_src_type and blit2d_dst_type enums in anv_meta_blit2d.c to
636 * see what these mean.
638 VkPipeline pipelines[2][3];
642 /** Pipeline [i] resolves an image with 2^(i+1) samples. */
643 VkPipeline pipelines[MAX_SAMPLES_LOG2];
646 VkPipelineLayout pipeline_layout;
647 VkDescriptorSetLayout ds_layout;
652 VK_LOADER_DATA _loader_data;
654 struct anv_device * device;
656 struct anv_state_pool * pool;
659 struct anv_pipeline_cache {
660 struct anv_device * device;
661 struct anv_state_stream program_stream;
662 pthread_mutex_t mutex;
666 uint32_t kernel_count;
667 uint32_t * hash_table;
670 struct anv_pipeline_bind_map;
672 void anv_pipeline_cache_init(struct anv_pipeline_cache *cache,
673 struct anv_device *device);
674 void anv_pipeline_cache_finish(struct anv_pipeline_cache *cache);
675 uint32_t anv_pipeline_cache_search(struct anv_pipeline_cache *cache,
676 const unsigned char *sha1,
677 const struct brw_stage_prog_data **prog_data,
678 struct anv_pipeline_bind_map *map);
679 uint32_t anv_pipeline_cache_upload_kernel(struct anv_pipeline_cache *cache,
680 const unsigned char *sha1,
683 const struct brw_stage_prog_data **prog_data,
684 size_t prog_data_size,
685 struct anv_pipeline_bind_map *map);
688 VK_LOADER_DATA _loader_data;
690 VkAllocationCallbacks alloc;
692 struct anv_instance * instance;
694 struct brw_device_info info;
695 struct isl_device isl_dev;
698 bool can_chain_batches;
699 bool robust_buffer_access;
701 struct anv_bo_pool batch_bo_pool;
703 struct anv_block_pool dynamic_state_block_pool;
704 struct anv_state_pool dynamic_state_pool;
706 struct anv_block_pool instruction_block_pool;
707 struct anv_pipeline_cache default_pipeline_cache;
709 struct anv_block_pool surface_state_block_pool;
710 struct anv_state_pool surface_state_pool;
712 struct anv_bo workaround_bo;
714 struct anv_meta_state meta_state;
716 struct anv_state border_colors;
718 struct anv_queue queue;
720 struct anv_scratch_pool scratch_pool;
722 uint32_t default_mocs;
724 pthread_mutex_t mutex;
727 void anv_device_get_cache_uuid(void *uuid);
730 void* anv_gem_mmap(struct anv_device *device,
731 uint32_t gem_handle, uint64_t offset, uint64_t size, uint32_t flags);
732 void anv_gem_munmap(void *p, uint64_t size);
733 uint32_t anv_gem_create(struct anv_device *device, size_t size);
734 void anv_gem_close(struct anv_device *device, uint32_t gem_handle);
735 uint32_t anv_gem_userptr(struct anv_device *device, void *mem, size_t size);
736 int anv_gem_wait(struct anv_device *device, uint32_t gem_handle, int64_t *timeout_ns);
737 int anv_gem_execbuffer(struct anv_device *device,
738 struct drm_i915_gem_execbuffer2 *execbuf);
739 int anv_gem_set_tiling(struct anv_device *device, uint32_t gem_handle,
740 uint32_t stride, uint32_t tiling);
741 int anv_gem_create_context(struct anv_device *device);
742 int anv_gem_destroy_context(struct anv_device *device, int context);
743 int anv_gem_get_param(int fd, uint32_t param);
744 bool anv_gem_get_bit6_swizzle(int fd, uint32_t tiling);
745 int anv_gem_get_aperture(int fd, uint64_t *size);
746 int anv_gem_handle_to_fd(struct anv_device *device, uint32_t gem_handle);
747 uint32_t anv_gem_fd_to_handle(struct anv_device *device, int fd);
748 int anv_gem_set_caching(struct anv_device *device, uint32_t gem_handle, uint32_t caching);
749 int anv_gem_set_domain(struct anv_device *device, uint32_t gem_handle,
750 uint32_t read_domains, uint32_t write_domain);
752 VkResult anv_bo_init_new(struct anv_bo *bo, struct anv_device *device, uint64_t size);
754 struct anv_reloc_list {
757 struct drm_i915_gem_relocation_entry * relocs;
758 struct anv_bo ** reloc_bos;
761 VkResult anv_reloc_list_init(struct anv_reloc_list *list,
762 const VkAllocationCallbacks *alloc);
763 void anv_reloc_list_finish(struct anv_reloc_list *list,
764 const VkAllocationCallbacks *alloc);
766 uint64_t anv_reloc_list_add(struct anv_reloc_list *list,
767 const VkAllocationCallbacks *alloc,
768 uint32_t offset, struct anv_bo *target_bo,
771 struct anv_batch_bo {
772 /* Link in the anv_cmd_buffer.owned_batch_bos list */
773 struct list_head link;
777 /* Bytes actually consumed in this batch BO */
780 /* Last seen surface state block pool bo offset */
781 uint32_t last_ss_pool_bo_offset;
783 struct anv_reloc_list relocs;
787 const VkAllocationCallbacks * alloc;
793 struct anv_reloc_list * relocs;
795 /* This callback is called (with the associated user data) in the event
796 * that the batch runs out of space.
798 VkResult (*extend_cb)(struct anv_batch *, void *);
802 void *anv_batch_emit_dwords(struct anv_batch *batch, int num_dwords);
803 void anv_batch_emit_batch(struct anv_batch *batch, struct anv_batch *other);
804 uint64_t anv_batch_emit_reloc(struct anv_batch *batch,
805 void *location, struct anv_bo *bo, uint32_t offset);
806 VkResult anv_device_submit_simple_batch(struct anv_device *device,
807 struct anv_batch *batch);
814 #define __gen_address_type struct anv_address
815 #define __gen_user_data struct anv_batch
817 static inline uint64_t
818 __gen_combine_address(struct anv_batch *batch, void *location,
819 const struct anv_address address, uint32_t delta)
821 if (address.bo == NULL) {
822 return address.offset + delta;
824 assert(batch->start <= location && location < batch->end);
826 return anv_batch_emit_reloc(batch, location, address.bo, address.offset + delta);
830 /* Wrapper macros needed to work around preprocessor argument issues. In
831 * particular, arguments don't get pre-evaluated if they are concatenated.
832 * This means that, if you pass GENX(3DSTATE_PS) into the emit macro, the
833 * GENX macro won't get evaluated if the emit macro contains "cmd ## foo".
834 * We can work around this easily enough with these helpers.
836 #define __anv_cmd_length(cmd) cmd ## _length
837 #define __anv_cmd_length_bias(cmd) cmd ## _length_bias
838 #define __anv_cmd_header(cmd) cmd ## _header
839 #define __anv_cmd_pack(cmd) cmd ## _pack
840 #define __anv_reg_num(reg) reg ## _num
842 #define anv_pack_struct(dst, struc, ...) do { \
843 struct struc __template = { \
846 __anv_cmd_pack(struc)(NULL, dst, &__template); \
847 VG(VALGRIND_CHECK_MEM_IS_DEFINED(dst, __anv_cmd_length(struc) * 4)); \
850 #define anv_batch_emitn(batch, n, cmd, ...) ({ \
851 void *__dst = anv_batch_emit_dwords(batch, n); \
852 struct cmd __template = { \
853 __anv_cmd_header(cmd), \
854 .DWordLength = n - __anv_cmd_length_bias(cmd), \
857 __anv_cmd_pack(cmd)(batch, __dst, &__template); \
861 #define anv_batch_emit_merge(batch, dwords0, dwords1) \
865 static_assert(ARRAY_SIZE(dwords0) == ARRAY_SIZE(dwords1), "mismatch merge"); \
866 dw = anv_batch_emit_dwords((batch), ARRAY_SIZE(dwords0)); \
867 for (uint32_t i = 0; i < ARRAY_SIZE(dwords0); i++) \
868 dw[i] = (dwords0)[i] | (dwords1)[i]; \
869 VG(VALGRIND_CHECK_MEM_IS_DEFINED(dw, ARRAY_SIZE(dwords0) * 4));\
872 #define anv_batch_emit(batch, cmd, name) \
873 for (struct cmd name = { __anv_cmd_header(cmd) }, \
874 *_dst = anv_batch_emit_dwords(batch, __anv_cmd_length(cmd)); \
875 __builtin_expect(_dst != NULL, 1); \
876 ({ __anv_cmd_pack(cmd)(batch, _dst, &name); \
877 VG(VALGRIND_CHECK_MEM_IS_DEFINED(_dst, __anv_cmd_length(cmd) * 4)); \
881 #define anv_state_pool_emit(pool, cmd, align, ...) ({ \
882 const uint32_t __size = __anv_cmd_length(cmd) * 4; \
883 struct anv_state __state = \
884 anv_state_pool_alloc((pool), __size, align); \
885 struct cmd __template = { \
888 __anv_cmd_pack(cmd)(NULL, __state.map, &__template); \
889 VG(VALGRIND_CHECK_MEM_IS_DEFINED(__state.map, __anv_cmd_length(cmd) * 4)); \
890 if (!(pool)->block_pool->device->info.has_llc) \
891 anv_state_clflush(__state); \
895 #define GEN7_MOCS (struct GEN7_MEMORY_OBJECT_CONTROL_STATE) { \
896 .GraphicsDataTypeGFDT = 0, \
897 .LLCCacheabilityControlLLCCC = 0, \
898 .L3CacheabilityControlL3CC = 1, \
901 #define GEN75_MOCS (struct GEN75_MEMORY_OBJECT_CONTROL_STATE) { \
902 .LLCeLLCCacheabilityControlLLCCC = 0, \
903 .L3CacheabilityControlL3CC = 1, \
906 #define GEN8_MOCS (struct GEN8_MEMORY_OBJECT_CONTROL_STATE) { \
907 .MemoryTypeLLCeLLCCacheabilityControl = WB, \
908 .TargetCache = L3DefertoPATforLLCeLLCselection, \
912 /* Skylake: MOCS is now an index into an array of 62 different caching
913 * configurations programmed by the kernel.
916 #define GEN9_MOCS (struct GEN9_MEMORY_OBJECT_CONTROL_STATE) { \
917 /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */ \
918 .IndextoMOCSTables = 2 \
921 #define GEN9_MOCS_PTE { \
922 /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */ \
923 .IndextoMOCSTables = 1 \
926 struct anv_device_memory {
929 VkDeviceSize map_size;
934 * Header for Vertex URB Entry (VUE)
936 struct anv_vue_header {
938 uint32_t RTAIndex; /* RenderTargetArrayIndex */
939 uint32_t ViewportIndex;
943 struct anv_descriptor_set_binding_layout {
945 /* The type of the descriptors in this binding */
946 VkDescriptorType type;
949 /* Number of array elements in this binding */
952 /* Index into the flattend descriptor set */
953 uint16_t descriptor_index;
955 /* Index into the dynamic state array for a dynamic buffer */
956 int16_t dynamic_offset_index;
958 /* Index into the descriptor set buffer views */
959 int16_t buffer_index;
962 /* Index into the binding table for the associated surface */
963 int16_t surface_index;
965 /* Index into the sampler table for the associated sampler */
966 int16_t sampler_index;
968 /* Index into the image table for the associated image */
970 } stage[MESA_SHADER_STAGES];
972 /* Immutable samplers (or NULL if no immutable samplers) */
973 struct anv_sampler **immutable_samplers;
976 struct anv_descriptor_set_layout {
977 /* Number of bindings in this descriptor set */
978 uint16_t binding_count;
980 /* Total size of the descriptor set with room for all array entries */
983 /* Shader stages affected by this descriptor set */
984 uint16_t shader_stages;
986 /* Number of buffers in this descriptor set */
987 uint16_t buffer_count;
989 /* Number of dynamic offsets used by this descriptor set */
990 uint16_t dynamic_offset_count;
992 /* Bindings in this descriptor set */
993 struct anv_descriptor_set_binding_layout binding[0];
996 struct anv_descriptor {
997 VkDescriptorType type;
1001 struct anv_image_view *image_view;
1002 struct anv_sampler *sampler;
1005 struct anv_buffer_view *buffer_view;
1009 struct anv_descriptor_set {
1010 const struct anv_descriptor_set_layout *layout;
1012 uint32_t buffer_count;
1013 struct anv_buffer_view *buffer_views;
1014 struct anv_descriptor descriptors[0];
1017 struct anv_descriptor_pool {
1022 struct anv_state_stream surface_state_stream;
1023 void *surface_state_free_list;
1029 anv_descriptor_set_create(struct anv_device *device,
1030 struct anv_descriptor_pool *pool,
1031 const struct anv_descriptor_set_layout *layout,
1032 struct anv_descriptor_set **out_set);
1035 anv_descriptor_set_destroy(struct anv_device *device,
1036 struct anv_descriptor_pool *pool,
1037 struct anv_descriptor_set *set);
1039 #define ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS UINT8_MAX
1041 struct anv_pipeline_binding {
1042 /* The descriptor set this surface corresponds to. The special value of
1043 * ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS indicates that the offset refers
1044 * to a color attachment and not a regular descriptor.
1048 /* Binding in the descriptor set */
1051 /* Index in the binding */
1055 struct anv_pipeline_layout {
1057 struct anv_descriptor_set_layout *layout;
1058 uint32_t dynamic_offset_start;
1064 bool has_dynamic_offsets;
1065 } stage[MESA_SHADER_STAGES];
1069 struct anv_device * device;
1072 VkBufferUsageFlags usage;
1074 /* Set when bound */
1076 VkDeviceSize offset;
1079 enum anv_cmd_dirty_bits {
1080 ANV_CMD_DIRTY_DYNAMIC_VIEWPORT = 1 << 0, /* VK_DYNAMIC_STATE_VIEWPORT */
1081 ANV_CMD_DIRTY_DYNAMIC_SCISSOR = 1 << 1, /* VK_DYNAMIC_STATE_SCISSOR */
1082 ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH = 1 << 2, /* VK_DYNAMIC_STATE_LINE_WIDTH */
1083 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS = 1 << 3, /* VK_DYNAMIC_STATE_DEPTH_BIAS */
1084 ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS = 1 << 4, /* VK_DYNAMIC_STATE_BLEND_CONSTANTS */
1085 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS = 1 << 5, /* VK_DYNAMIC_STATE_DEPTH_BOUNDS */
1086 ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK = 1 << 6, /* VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK */
1087 ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK = 1 << 7, /* VK_DYNAMIC_STATE_STENCIL_WRITE_MASK */
1088 ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE = 1 << 8, /* VK_DYNAMIC_STATE_STENCIL_REFERENCE */
1089 ANV_CMD_DIRTY_DYNAMIC_ALL = (1 << 9) - 1,
1090 ANV_CMD_DIRTY_PIPELINE = 1 << 9,
1091 ANV_CMD_DIRTY_INDEX_BUFFER = 1 << 10,
1092 ANV_CMD_DIRTY_RENDER_TARGETS = 1 << 11,
1094 typedef uint32_t anv_cmd_dirty_mask_t;
1096 enum anv_pipe_bits {
1097 ANV_PIPE_DEPTH_CACHE_FLUSH_BIT = (1 << 0),
1098 ANV_PIPE_STALL_AT_SCOREBOARD_BIT = (1 << 1),
1099 ANV_PIPE_STATE_CACHE_INVALIDATE_BIT = (1 << 2),
1100 ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT = (1 << 3),
1101 ANV_PIPE_VF_CACHE_INVALIDATE_BIT = (1 << 4),
1102 ANV_PIPE_DATA_CACHE_FLUSH_BIT = (1 << 5),
1103 ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT = (1 << 10),
1104 ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT = (1 << 11),
1105 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT = (1 << 12),
1106 ANV_PIPE_DEPTH_STALL_BIT = (1 << 13),
1107 ANV_PIPE_CS_STALL_BIT = (1 << 20),
1109 /* This bit does not exist directly in PIPE_CONTROL. Instead it means that
1110 * a flush has happened but not a CS stall. The next time we do any sort
1111 * of invalidation we need to insert a CS stall at that time. Otherwise,
1112 * we would have to CS stall on every flush which could be bad.
1114 ANV_PIPE_NEEDS_CS_STALL_BIT = (1 << 21),
1117 #define ANV_PIPE_FLUSH_BITS ( \
1118 ANV_PIPE_DEPTH_CACHE_FLUSH_BIT | \
1119 ANV_PIPE_DATA_CACHE_FLUSH_BIT | \
1120 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT)
1122 #define ANV_PIPE_STALL_BITS ( \
1123 ANV_PIPE_STALL_AT_SCOREBOARD_BIT | \
1124 ANV_PIPE_DEPTH_STALL_BIT | \
1125 ANV_PIPE_CS_STALL_BIT)
1127 #define ANV_PIPE_INVALIDATE_BITS ( \
1128 ANV_PIPE_STATE_CACHE_INVALIDATE_BIT | \
1129 ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT | \
1130 ANV_PIPE_VF_CACHE_INVALIDATE_BIT | \
1131 ANV_PIPE_DATA_CACHE_FLUSH_BIT | \
1132 ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT | \
1133 ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT)
1135 struct anv_vertex_binding {
1136 struct anv_buffer * buffer;
1137 VkDeviceSize offset;
1140 struct anv_push_constants {
1141 /* Current allocated size of this push constants data structure.
1142 * Because a decent chunk of it may not be used (images on SKL, for
1143 * instance), we won't actually allocate the entire structure up-front.
1147 /* Push constant data provided by the client through vkPushConstants */
1148 uint8_t client_data[MAX_PUSH_CONSTANTS_SIZE];
1150 /* Our hardware only provides zero-based vertex and instance id so, in
1151 * order to satisfy the vulkan requirements, we may have to push one or
1152 * both of these into the shader.
1154 uint32_t base_vertex;
1155 uint32_t base_instance;
1157 /* Offsets and ranges for dynamically bound buffers */
1161 } dynamic[MAX_DYNAMIC_BUFFERS];
1163 /* Image data for image_load_store on pre-SKL */
1164 struct brw_image_param images[MAX_IMAGES];
1167 struct anv_dynamic_state {
1170 VkViewport viewports[MAX_VIEWPORTS];
1175 VkRect2D scissors[MAX_SCISSORS];
1186 float blend_constants[4];
1196 } stencil_compare_mask;
1201 } stencil_write_mask;
1206 } stencil_reference;
1209 extern const struct anv_dynamic_state default_dynamic_state;
1211 void anv_dynamic_state_copy(struct anv_dynamic_state *dest,
1212 const struct anv_dynamic_state *src,
1213 uint32_t copy_mask);
1216 * Attachment state when recording a renderpass instance.
1218 * The clear value is valid only if there exists a pending clear.
1220 struct anv_attachment_state {
1221 VkImageAspectFlags pending_clear_aspects;
1222 VkClearValue clear_value;
1225 /** State required while building cmd buffer */
1226 struct anv_cmd_state {
1227 /* PIPELINE_SELECT.PipelineSelection */
1228 uint32_t current_pipeline;
1229 const struct anv_l3_config * current_l3_config;
1231 anv_cmd_dirty_mask_t dirty;
1232 anv_cmd_dirty_mask_t compute_dirty;
1233 enum anv_pipe_bits pending_pipe_bits;
1234 uint32_t num_workgroups_offset;
1235 struct anv_bo *num_workgroups_bo;
1236 VkShaderStageFlags descriptors_dirty;
1237 VkShaderStageFlags push_constants_dirty;
1238 uint32_t scratch_size;
1239 struct anv_pipeline * pipeline;
1240 struct anv_pipeline * compute_pipeline;
1241 struct anv_framebuffer * framebuffer;
1242 struct anv_render_pass * pass;
1243 struct anv_subpass * subpass;
1244 VkRect2D render_area;
1245 uint32_t restart_index;
1246 struct anv_vertex_binding vertex_bindings[MAX_VBS];
1247 struct anv_descriptor_set * descriptors[MAX_SETS];
1248 VkShaderStageFlags push_constant_stages;
1249 struct anv_push_constants * push_constants[MESA_SHADER_STAGES];
1250 struct anv_state binding_tables[MESA_SHADER_STAGES];
1251 struct anv_state samplers[MESA_SHADER_STAGES];
1252 struct anv_dynamic_state dynamic;
1256 * Array length is anv_cmd_state::pass::attachment_count. Array content is
1257 * valid only when recording a render pass instance.
1259 struct anv_attachment_state * attachments;
1262 struct anv_buffer * index_buffer;
1263 uint32_t index_type; /**< 3DSTATE_INDEX_BUFFER.IndexFormat */
1264 uint32_t index_offset;
1268 struct anv_cmd_pool {
1269 VkAllocationCallbacks alloc;
1270 struct list_head cmd_buffers;
1273 #define ANV_CMD_BUFFER_BATCH_SIZE 8192
1275 enum anv_cmd_buffer_exec_mode {
1276 ANV_CMD_BUFFER_EXEC_MODE_PRIMARY,
1277 ANV_CMD_BUFFER_EXEC_MODE_EMIT,
1278 ANV_CMD_BUFFER_EXEC_MODE_GROW_AND_EMIT,
1279 ANV_CMD_BUFFER_EXEC_MODE_CHAIN,
1280 ANV_CMD_BUFFER_EXEC_MODE_COPY_AND_CHAIN,
1283 struct anv_cmd_buffer {
1284 VK_LOADER_DATA _loader_data;
1286 struct anv_device * device;
1288 struct anv_cmd_pool * pool;
1289 struct list_head pool_link;
1291 struct anv_batch batch;
1293 /* Fields required for the actual chain of anv_batch_bo's.
1295 * These fields are initialized by anv_cmd_buffer_init_batch_bo_chain().
1297 struct list_head batch_bos;
1298 enum anv_cmd_buffer_exec_mode exec_mode;
1300 /* A vector of anv_batch_bo pointers for every batch or surface buffer
1301 * referenced by this command buffer
1303 * initialized by anv_cmd_buffer_init_batch_bo_chain()
1305 struct anv_vector seen_bbos;
1307 /* A vector of int32_t's for every block of binding tables.
1309 * initialized by anv_cmd_buffer_init_batch_bo_chain()
1311 struct anv_vector bt_blocks;
1313 struct anv_reloc_list surface_relocs;
1315 /* Information needed for execbuf
1317 * These fields are generated by anv_cmd_buffer_prepare_execbuf().
1320 struct drm_i915_gem_execbuffer2 execbuf;
1322 struct drm_i915_gem_exec_object2 * objects;
1324 struct anv_bo ** bos;
1326 /* Allocated length of the 'objects' and 'bos' arrays */
1327 uint32_t array_length;
1332 /* Serial for tracking buffer completion */
1335 /* Stream objects for storing temporary data */
1336 struct anv_state_stream surface_state_stream;
1337 struct anv_state_stream dynamic_state_stream;
1339 VkCommandBufferUsageFlags usage_flags;
1340 VkCommandBufferLevel level;
1342 struct anv_cmd_state state;
1345 VkResult anv_cmd_buffer_init_batch_bo_chain(struct anv_cmd_buffer *cmd_buffer);
1346 void anv_cmd_buffer_fini_batch_bo_chain(struct anv_cmd_buffer *cmd_buffer);
1347 void anv_cmd_buffer_reset_batch_bo_chain(struct anv_cmd_buffer *cmd_buffer);
1348 void anv_cmd_buffer_end_batch_buffer(struct anv_cmd_buffer *cmd_buffer);
1349 void anv_cmd_buffer_add_secondary(struct anv_cmd_buffer *primary,
1350 struct anv_cmd_buffer *secondary);
1351 void anv_cmd_buffer_prepare_execbuf(struct anv_cmd_buffer *cmd_buffer);
1353 VkResult anv_cmd_buffer_emit_binding_table(struct anv_cmd_buffer *cmd_buffer,
1354 unsigned stage, struct anv_state *bt_state);
1355 VkResult anv_cmd_buffer_emit_samplers(struct anv_cmd_buffer *cmd_buffer,
1356 unsigned stage, struct anv_state *state);
1357 uint32_t anv_cmd_buffer_flush_descriptor_sets(struct anv_cmd_buffer *cmd_buffer);
1359 struct anv_state anv_cmd_buffer_emit_dynamic(struct anv_cmd_buffer *cmd_buffer,
1360 const void *data, uint32_t size, uint32_t alignment);
1361 struct anv_state anv_cmd_buffer_merge_dynamic(struct anv_cmd_buffer *cmd_buffer,
1362 uint32_t *a, uint32_t *b,
1363 uint32_t dwords, uint32_t alignment);
1366 anv_cmd_buffer_surface_base_address(struct anv_cmd_buffer *cmd_buffer);
1368 anv_cmd_buffer_alloc_binding_table(struct anv_cmd_buffer *cmd_buffer,
1369 uint32_t entries, uint32_t *state_offset);
1371 anv_cmd_buffer_alloc_surface_state(struct anv_cmd_buffer *cmd_buffer);
1373 anv_cmd_buffer_alloc_dynamic_state(struct anv_cmd_buffer *cmd_buffer,
1374 uint32_t size, uint32_t alignment);
1377 anv_cmd_buffer_new_binding_table_block(struct anv_cmd_buffer *cmd_buffer);
1379 void gen8_cmd_buffer_emit_viewport(struct anv_cmd_buffer *cmd_buffer);
1380 void gen8_cmd_buffer_emit_depth_viewport(struct anv_cmd_buffer *cmd_buffer,
1381 bool depth_clamp_enable);
1382 void gen7_cmd_buffer_emit_scissor(struct anv_cmd_buffer *cmd_buffer);
1384 void anv_cmd_buffer_emit_state_base_address(struct anv_cmd_buffer *cmd_buffer);
1386 void anv_cmd_state_setup_attachments(struct anv_cmd_buffer *cmd_buffer,
1387 const VkRenderPassBeginInfo *info);
1389 void anv_cmd_buffer_set_subpass(struct anv_cmd_buffer *cmd_buffer,
1390 struct anv_subpass *subpass);
1393 anv_cmd_buffer_push_constants(struct anv_cmd_buffer *cmd_buffer,
1394 gl_shader_stage stage);
1396 anv_cmd_buffer_cs_push_constants(struct anv_cmd_buffer *cmd_buffer);
1398 void anv_cmd_buffer_clear_subpass(struct anv_cmd_buffer *cmd_buffer);
1399 void anv_cmd_buffer_resolve_subpass(struct anv_cmd_buffer *cmd_buffer);
1401 const struct anv_image_view *
1402 anv_cmd_buffer_get_depth_stencil_view(const struct anv_cmd_buffer *cmd_buffer);
1404 void anv_cmd_buffer_dump(struct anv_cmd_buffer *cmd_buffer);
1408 struct drm_i915_gem_execbuffer2 execbuf;
1409 struct drm_i915_gem_exec_object2 exec2_objects[1];
1415 struct anv_state state;
1420 struct anv_shader_module {
1421 struct nir_shader * nir;
1423 unsigned char sha1[20];
1428 void anv_hash_shader(unsigned char *hash, const void *key, size_t key_size,
1429 struct anv_shader_module *module,
1430 const char *entrypoint,
1431 const VkSpecializationInfo *spec_info);
1433 static inline gl_shader_stage
1434 vk_to_mesa_shader_stage(VkShaderStageFlagBits vk_stage)
1436 assert(__builtin_popcount(vk_stage) == 1);
1437 return ffs(vk_stage) - 1;
1440 static inline VkShaderStageFlagBits
1441 mesa_to_vk_shader_stage(gl_shader_stage mesa_stage)
1443 return (1 << mesa_stage);
1446 #define ANV_STAGE_MASK ((1 << MESA_SHADER_STAGES) - 1)
1448 #define anv_foreach_stage(stage, stage_bits) \
1449 for (gl_shader_stage stage, \
1450 __tmp = (gl_shader_stage)((stage_bits) & ANV_STAGE_MASK); \
1451 stage = __builtin_ffs(__tmp) - 1, __tmp; \
1452 __tmp &= ~(1 << (stage)))
1454 struct anv_pipeline_bind_map {
1455 uint32_t surface_count;
1456 uint32_t sampler_count;
1457 uint32_t image_count;
1458 uint32_t attachment_count;
1460 struct anv_pipeline_binding * surface_to_descriptor;
1461 struct anv_pipeline_binding * sampler_to_descriptor;
1462 uint32_t * surface_to_attachment;
1465 struct anv_pipeline {
1466 struct anv_device * device;
1467 struct anv_batch batch;
1468 uint32_t batch_data[512];
1469 struct anv_reloc_list batch_relocs;
1470 uint32_t dynamic_state_mask;
1471 struct anv_dynamic_state dynamic_state;
1473 struct anv_pipeline_layout * layout;
1474 struct anv_pipeline_bind_map bindings[MESA_SHADER_STAGES];
1477 bool needs_data_cache;
1479 const struct brw_stage_prog_data * prog_data[MESA_SHADER_STAGES];
1481 uint32_t start[MESA_SHADER_GEOMETRY + 1];
1482 uint32_t size[MESA_SHADER_GEOMETRY + 1];
1483 uint32_t entries[MESA_SHADER_GEOMETRY + 1];
1484 const struct anv_l3_config * l3_config;
1485 uint32_t total_size;
1488 VkShaderStageFlags active_stages;
1489 struct anv_state blend_state;
1497 uint32_t binding_stride[MAX_VBS];
1498 bool instancing_enable[MAX_VBS];
1499 bool primitive_restart;
1502 uint32_t cs_right_mask;
1504 bool depth_clamp_enable;
1508 uint32_t depth_stencil_state[3];
1514 uint32_t wm_depth_stencil[3];
1518 uint32_t wm_depth_stencil[4];
1522 static inline const struct brw_vs_prog_data *
1523 get_vs_prog_data(struct anv_pipeline *pipeline)
1525 return (const struct brw_vs_prog_data *) pipeline->prog_data[MESA_SHADER_VERTEX];
1528 static inline const struct brw_gs_prog_data *
1529 get_gs_prog_data(struct anv_pipeline *pipeline)
1531 return (const struct brw_gs_prog_data *) pipeline->prog_data[MESA_SHADER_GEOMETRY];
1534 static inline const struct brw_wm_prog_data *
1535 get_wm_prog_data(struct anv_pipeline *pipeline)
1537 return (const struct brw_wm_prog_data *) pipeline->prog_data[MESA_SHADER_FRAGMENT];
1540 static inline const struct brw_cs_prog_data *
1541 get_cs_prog_data(struct anv_pipeline *pipeline)
1543 return (const struct brw_cs_prog_data *) pipeline->prog_data[MESA_SHADER_COMPUTE];
1546 struct anv_graphics_pipeline_create_info {
1548 * If non-negative, overrides the color attachment count of the pipeline's
1551 int8_t color_attachment_count;
1559 anv_pipeline_init(struct anv_pipeline *pipeline, struct anv_device *device,
1560 struct anv_pipeline_cache *cache,
1561 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1562 const struct anv_graphics_pipeline_create_info *extra,
1563 const VkAllocationCallbacks *alloc);
1566 anv_pipeline_compile_cs(struct anv_pipeline *pipeline,
1567 struct anv_pipeline_cache *cache,
1568 const VkComputePipelineCreateInfo *info,
1569 struct anv_shader_module *module,
1570 const char *entrypoint,
1571 const VkSpecializationInfo *spec_info);
1574 anv_graphics_pipeline_create(VkDevice device,
1575 VkPipelineCache cache,
1576 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1577 const struct anv_graphics_pipeline_create_info *extra,
1578 const VkAllocationCallbacks *alloc,
1579 VkPipeline *pPipeline);
1581 struct anv_format_swizzle {
1582 enum isl_channel_select r:4;
1583 enum isl_channel_select g:4;
1584 enum isl_channel_select b:4;
1585 enum isl_channel_select a:4;
1589 enum isl_format isl_format:16;
1590 struct anv_format_swizzle swizzle;
1594 anv_get_format(const struct brw_device_info *devinfo, VkFormat format,
1595 VkImageAspectFlags aspect, VkImageTiling tiling);
1597 static inline enum isl_format
1598 anv_get_isl_format(const struct brw_device_info *devinfo, VkFormat vk_format,
1599 VkImageAspectFlags aspect, VkImageTiling tiling)
1601 return anv_get_format(devinfo, vk_format, aspect, tiling).isl_format;
1605 anv_compute_urb_partition(struct anv_pipeline *pipeline);
1608 anv_setup_pipeline_l3_config(struct anv_pipeline *pipeline);
1611 * Subsurface of an anv_image.
1613 struct anv_surface {
1614 struct isl_surf isl;
1617 * Offset from VkImage's base address, as bound by vkBindImageMemory().
1624 /* The original VkFormat provided by the client. This may not match any
1625 * of the actual surface formats.
1628 VkImageAspectFlags aspects;
1631 uint32_t array_size;
1632 uint32_t samples; /**< VkImageCreateInfo::samples */
1633 VkImageUsageFlags usage; /**< Superset of VkImageCreateInfo::usage. */
1634 VkImageTiling tiling; /** VkImageCreateInfo::tiling */
1639 /* Set when bound */
1641 VkDeviceSize offset;
1646 * For each foo, anv_image::foo_surface is valid if and only if
1647 * anv_image::aspects has a foo aspect.
1649 * The hardware requires that the depth buffer and stencil buffer be
1650 * separate surfaces. From Vulkan's perspective, though, depth and stencil
1651 * reside in the same VkImage. To satisfy both the hardware and Vulkan, we
1652 * allocate the depth and stencil buffers as separate surfaces in the same
1656 struct anv_surface color_surface;
1659 struct anv_surface depth_surface;
1660 struct anv_surface stencil_surface;
1665 static inline uint32_t
1666 anv_get_layerCount(const struct anv_image *image,
1667 const VkImageSubresourceRange *range)
1669 return range->layerCount == VK_REMAINING_ARRAY_LAYERS ?
1670 image->array_size - range->baseArrayLayer : range->layerCount;
1673 static inline uint32_t
1674 anv_get_levelCount(const struct anv_image *image,
1675 const VkImageSubresourceRange *range)
1677 return range->levelCount == VK_REMAINING_MIP_LEVELS ?
1678 image->levels - range->baseMipLevel : range->levelCount;
1682 struct anv_image_view {
1683 const struct anv_image *image; /**< VkImageViewCreateInfo::image */
1685 uint32_t offset; /**< Offset into bo. */
1687 VkImageAspectFlags aspect_mask;
1689 uint32_t base_layer;
1691 VkExtent3D extent; /**< Extent of VkImageViewCreateInfo::baseMipLevel. */
1693 /** RENDER_SURFACE_STATE when using image as a color render target. */
1694 struct anv_state color_rt_surface_state;
1696 /** RENDER_SURFACE_STATE when using image as a sampler surface. */
1697 struct anv_state sampler_surface_state;
1699 /** RENDER_SURFACE_STATE when using image as a storage image. */
1700 struct anv_state storage_surface_state;
1702 struct brw_image_param storage_image_param;
1705 struct anv_image_create_info {
1706 const VkImageCreateInfo *vk_info;
1707 isl_tiling_flags_t isl_tiling_flags;
1711 VkResult anv_image_create(VkDevice _device,
1712 const struct anv_image_create_info *info,
1713 const VkAllocationCallbacks* alloc,
1716 struct anv_surface *
1717 anv_image_get_surface_for_aspect_mask(struct anv_image *image,
1718 VkImageAspectFlags aspect_mask);
1720 void anv_image_view_init(struct anv_image_view *view,
1721 struct anv_device *device,
1722 const VkImageViewCreateInfo* pCreateInfo,
1723 struct anv_cmd_buffer *cmd_buffer,
1724 VkImageUsageFlags usage_mask);
1726 struct anv_buffer_view {
1727 enum isl_format format; /**< VkBufferViewCreateInfo::format */
1729 uint32_t offset; /**< Offset into bo. */
1730 uint64_t range; /**< VkBufferViewCreateInfo::range */
1732 struct anv_state surface_state;
1733 struct anv_state storage_surface_state;
1735 struct brw_image_param storage_image_param;
1738 void anv_buffer_view_init(struct anv_buffer_view *view,
1739 struct anv_device *device,
1740 const VkBufferViewCreateInfo* pCreateInfo,
1741 struct anv_cmd_buffer *cmd_buffer);
1744 anv_isl_format_for_descriptor_type(VkDescriptorType type);
1746 static inline struct VkExtent3D
1747 anv_sanitize_image_extent(const VkImageType imageType,
1748 const struct VkExtent3D imageExtent)
1750 switch (imageType) {
1751 case VK_IMAGE_TYPE_1D:
1752 return (VkExtent3D) { imageExtent.width, 1, 1 };
1753 case VK_IMAGE_TYPE_2D:
1754 return (VkExtent3D) { imageExtent.width, imageExtent.height, 1 };
1755 case VK_IMAGE_TYPE_3D:
1758 unreachable("invalid image type");
1762 static inline struct VkOffset3D
1763 anv_sanitize_image_offset(const VkImageType imageType,
1764 const struct VkOffset3D imageOffset)
1766 switch (imageType) {
1767 case VK_IMAGE_TYPE_1D:
1768 return (VkOffset3D) { imageOffset.x, 0, 0 };
1769 case VK_IMAGE_TYPE_2D:
1770 return (VkOffset3D) { imageOffset.x, imageOffset.y, 0 };
1771 case VK_IMAGE_TYPE_3D:
1774 unreachable("invalid image type");
1779 void anv_fill_buffer_surface_state(struct anv_device *device,
1780 struct anv_state state,
1781 enum isl_format format,
1782 uint32_t offset, uint32_t range,
1785 void anv_image_view_fill_image_param(struct anv_device *device,
1786 struct anv_image_view *view,
1787 struct brw_image_param *param);
1788 void anv_buffer_view_fill_image_param(struct anv_device *device,
1789 struct anv_buffer_view *view,
1790 struct brw_image_param *param);
1792 struct anv_sampler {
1796 struct anv_framebuffer {
1801 uint32_t attachment_count;
1802 struct anv_image_view * attachments[0];
1805 struct anv_subpass {
1806 uint32_t input_count;
1807 uint32_t * input_attachments;
1808 uint32_t color_count;
1809 uint32_t * color_attachments;
1810 uint32_t * resolve_attachments;
1811 uint32_t depth_stencil_attachment;
1813 /** Subpass has at least one resolve attachment */
1817 struct anv_render_pass_attachment {
1820 VkAttachmentLoadOp load_op;
1821 VkAttachmentLoadOp stencil_load_op;
1824 struct anv_render_pass {
1825 uint32_t attachment_count;
1826 uint32_t subpass_count;
1827 uint32_t * subpass_attachments;
1828 struct anv_render_pass_attachment * attachments;
1829 struct anv_subpass subpasses[0];
1832 extern struct anv_render_pass anv_meta_dummy_renderpass;
1834 struct anv_query_pool_slot {
1840 struct anv_query_pool {
1846 VkResult anv_device_init_meta(struct anv_device *device);
1847 void anv_device_finish_meta(struct anv_device *device);
1849 void *anv_lookup_entrypoint(const char *name);
1851 void anv_dump_image_to_ppm(struct anv_device *device,
1852 struct anv_image *image, unsigned miplevel,
1853 unsigned array_layer, const char *filename);
1855 #define ANV_DEFINE_HANDLE_CASTS(__anv_type, __VkType) \
1857 static inline struct __anv_type * \
1858 __anv_type ## _from_handle(__VkType _handle) \
1860 return (struct __anv_type *) _handle; \
1863 static inline __VkType \
1864 __anv_type ## _to_handle(struct __anv_type *_obj) \
1866 return (__VkType) _obj; \
1869 #define ANV_DEFINE_NONDISP_HANDLE_CASTS(__anv_type, __VkType) \
1871 static inline struct __anv_type * \
1872 __anv_type ## _from_handle(__VkType _handle) \
1874 return (struct __anv_type *)(uintptr_t) _handle; \
1877 static inline __VkType \
1878 __anv_type ## _to_handle(struct __anv_type *_obj) \
1880 return (__VkType)(uintptr_t) _obj; \
1883 #define ANV_FROM_HANDLE(__anv_type, __name, __handle) \
1884 struct __anv_type *__name = __anv_type ## _from_handle(__handle)
1886 ANV_DEFINE_HANDLE_CASTS(anv_cmd_buffer, VkCommandBuffer)
1887 ANV_DEFINE_HANDLE_CASTS(anv_device, VkDevice)
1888 ANV_DEFINE_HANDLE_CASTS(anv_instance, VkInstance)
1889 ANV_DEFINE_HANDLE_CASTS(anv_physical_device, VkPhysicalDevice)
1890 ANV_DEFINE_HANDLE_CASTS(anv_queue, VkQueue)
1892 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_cmd_pool, VkCommandPool)
1893 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_buffer, VkBuffer)
1894 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_buffer_view, VkBufferView)
1895 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_pool, VkDescriptorPool)
1896 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_set, VkDescriptorSet)
1897 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_set_layout, VkDescriptorSetLayout)
1898 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_device_memory, VkDeviceMemory)
1899 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_fence, VkFence)
1900 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_event, VkEvent)
1901 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_framebuffer, VkFramebuffer)
1902 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_image, VkImage)
1903 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_image_view, VkImageView);
1904 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_pipeline_cache, VkPipelineCache)
1905 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_pipeline, VkPipeline)
1906 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_pipeline_layout, VkPipelineLayout)
1907 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_query_pool, VkQueryPool)
1908 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_render_pass, VkRenderPass)
1909 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_sampler, VkSampler)
1910 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_shader_module, VkShaderModule)
1912 #define ANV_DEFINE_STRUCT_CASTS(__anv_type, __VkType) \
1914 static inline const __VkType * \
1915 __anv_type ## _to_ ## __VkType(const struct __anv_type *__anv_obj) \
1917 return (const __VkType *) __anv_obj; \
1920 #define ANV_COMMON_TO_STRUCT(__VkType, __vk_name, __common_name) \
1921 const __VkType *__vk_name = anv_common_to_ ## __VkType(__common_name)
1923 ANV_DEFINE_STRUCT_CASTS(anv_common, VkMemoryBarrier)
1924 ANV_DEFINE_STRUCT_CASTS(anv_common, VkBufferMemoryBarrier)
1925 ANV_DEFINE_STRUCT_CASTS(anv_common, VkImageMemoryBarrier)
1927 /* Gen-specific function declarations */
1929 # include "anv_genX.h"
1931 # define genX(x) gen7_##x
1932 # include "anv_genX.h"
1934 # define genX(x) gen75_##x
1935 # include "anv_genX.h"
1937 # define genX(x) gen8_##x
1938 # include "anv_genX.h"
1940 # define genX(x) gen9_##x
1941 # include "anv_genX.h"