2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
39 #define __gen_validate_value(x) VALGRIND_CHECK_MEM_IS_DEFINED(&(x), sizeof(x))
44 #include "common/gen_device_info.h"
45 #include "blorp/blorp.h"
46 #include "brw_compiler.h"
47 #include "util/macros.h"
48 #include "util/list.h"
50 /* Pre-declarations needed for WSI entrypoints */
53 typedef struct xcb_connection_t xcb_connection_t;
54 typedef uint32_t xcb_visualid_t;
55 typedef uint32_t xcb_window_t;
59 #include <vulkan/vulkan.h>
60 #include <vulkan/vulkan_intel.h>
61 #include <vulkan/vk_icd.h>
63 #include "anv_entrypoints.h"
64 #include "brw_context.h"
74 #define MAX_VIEWPORTS 16
75 #define MAX_SCISSORS 16
76 #define MAX_PUSH_CONSTANTS_SIZE 128
77 #define MAX_DYNAMIC_BUFFERS 16
79 #define MAX_SAMPLES_LOG2 4 /* SKL supports 16 samples */
81 #define anv_noreturn __attribute__((__noreturn__))
82 #define anv_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
84 #define MIN(a, b) ((a) < (b) ? (a) : (b))
85 #define MAX(a, b) ((a) > (b) ? (a) : (b))
87 static inline uint32_t
88 align_down_npot_u32(uint32_t v, uint32_t a)
93 static inline uint32_t
94 align_u32(uint32_t v, uint32_t a)
96 assert(a != 0 && a == (a & -a));
97 return (v + a - 1) & ~(a - 1);
100 static inline uint64_t
101 align_u64(uint64_t v, uint64_t a)
103 assert(a != 0 && a == (a & -a));
104 return (v + a - 1) & ~(a - 1);
107 static inline int32_t
108 align_i32(int32_t v, int32_t a)
110 assert(a != 0 && a == (a & -a));
111 return (v + a - 1) & ~(a - 1);
114 /** Alignment must be a power of 2. */
116 anv_is_aligned(uintmax_t n, uintmax_t a)
118 assert(a == (a & -a));
119 return (n & (a - 1)) == 0;
122 static inline uint32_t
123 anv_minify(uint32_t n, uint32_t levels)
125 if (unlikely(n == 0))
128 return MAX(n >> levels, 1);
132 anv_clamp_f(float f, float min, float max)
145 anv_clear_mask(uint32_t *inout_mask, uint32_t clear_mask)
147 if (*inout_mask & clear_mask) {
148 *inout_mask &= ~clear_mask;
155 #define for_each_bit(b, dword) \
156 for (uint32_t __dword = (dword); \
157 (b) = __builtin_ffs(__dword) - 1, __dword; \
158 __dword &= ~(1 << (b)))
160 #define typed_memcpy(dest, src, count) ({ \
161 static_assert(sizeof(*src) == sizeof(*dest), ""); \
162 memcpy((dest), (src), (count) * sizeof(*(src))); \
165 #define zero(x) (memset(&(x), 0, sizeof(x)))
167 /* Define no kernel as 1, since that's an illegal offset for a kernel */
171 VkStructureType sType;
175 /* Whenever we generate an error, pass it through this function. Useful for
176 * debugging, where we can break on it. Only call at error site, not when
177 * propagating errors. Might be useful to plug in a stack trace here.
180 VkResult __vk_errorf(VkResult error, const char *file, int line, const char *format, ...);
183 #define vk_error(error) __vk_errorf(error, __FILE__, __LINE__, NULL);
184 #define vk_errorf(error, format, ...) __vk_errorf(error, __FILE__, __LINE__, format, ## __VA_ARGS__);
186 #define vk_error(error) error
187 #define vk_errorf(error, format, ...) error
190 void __anv_finishme(const char *file, int line, const char *format, ...)
191 anv_printflike(3, 4);
192 void anv_loge(const char *format, ...) anv_printflike(1, 2);
193 void anv_loge_v(const char *format, va_list va);
196 * Print a FINISHME message, including its source location.
198 #define anv_finishme(format, ...) \
199 __anv_finishme(__FILE__, __LINE__, format, ##__VA_ARGS__);
201 /* A non-fatal assert. Useful for debugging. */
203 #define anv_assert(x) ({ \
204 if (unlikely(!(x))) \
205 fprintf(stderr, "%s:%d ASSERT: %s\n", __FILE__, __LINE__, #x); \
208 #define anv_assert(x)
212 * If a block of code is annotated with anv_validate, then the block runs only
216 #define anv_validate if (1)
218 #define anv_validate if (0)
221 void anv_abortf(const char *format, ...) anv_noreturn anv_printflike(1, 2);
222 void anv_abortfv(const char *format, va_list va) anv_noreturn;
224 #define stub_return(v) \
226 anv_finishme("stub %s", __func__); \
232 anv_finishme("stub %s", __func__); \
237 * A dynamically growable, circular buffer. Elements are added at head and
238 * removed from tail. head and tail are free-running uint32_t indices and we
239 * only compute the modulo with size when accessing the array. This way,
240 * number of bytes in the queue is always head - tail, even in case of
247 uint32_t element_size;
252 int anv_vector_init(struct anv_vector *queue, uint32_t element_size, uint32_t size);
253 void *anv_vector_add(struct anv_vector *queue);
254 void *anv_vector_remove(struct anv_vector *queue);
257 anv_vector_length(struct anv_vector *queue)
259 return (queue->head - queue->tail) / queue->element_size;
263 anv_vector_head(struct anv_vector *vector)
265 assert(vector->tail < vector->head);
266 return (void *)((char *)vector->data +
267 ((vector->head - vector->element_size) &
268 (vector->size - 1)));
272 anv_vector_tail(struct anv_vector *vector)
274 return (void *)((char *)vector->data + (vector->tail & (vector->size - 1)));
278 anv_vector_finish(struct anv_vector *queue)
283 #define anv_vector_foreach(elem, queue) \
284 static_assert(__builtin_types_compatible_p(__typeof__(queue), struct anv_vector *), ""); \
285 for (uint32_t __anv_vector_offset = (queue)->tail; \
286 elem = (queue)->data + (__anv_vector_offset & ((queue)->size - 1)), __anv_vector_offset < (queue)->head; \
287 __anv_vector_offset += (queue)->element_size)
292 /* Index into the current validation list. This is used by the
293 * validation list building alrogithm to track which buffers are already
294 * in the validation list so that we can ensure uniqueness.
298 /* Last known offset. This value is provided by the kernel when we
299 * execbuf and is used as the presumed offset for the next bunch of
307 /* We need to set the WRITE flag on winsys bos so GEM will know we're
308 * writing to them and synchronize uses on other rings (eg if the display
309 * server uses the blitter ring).
314 /* Represents a lock-free linked list of "free" things. This is used by
315 * both the block pool and the state pools. Unfortunately, in order to
316 * solve the ABA problem, we can't use a single uint32_t head.
318 union anv_free_list {
322 /* A simple count that is incremented every time the head changes. */
328 #define ANV_FREE_LIST_EMPTY ((union anv_free_list) { { 1, 0 } })
330 struct anv_block_state {
340 struct anv_block_pool {
341 struct anv_device *device;
345 /* The offset from the start of the bo to the "center" of the block
346 * pool. Pointers to allocated blocks are given by
347 * bo.map + center_bo_offset + offsets.
349 uint32_t center_bo_offset;
351 /* Current memory map of the block pool. This pointer may or may not
352 * point to the actual beginning of the block pool memory. If
353 * anv_block_pool_alloc_back has ever been called, then this pointer
354 * will point to the "center" position of the buffer and all offsets
355 * (negative or positive) given out by the block pool alloc functions
356 * will be valid relative to this pointer.
358 * In particular, map == bo.map + center_offset
364 * Array of mmaps and gem handles owned by the block pool, reclaimed when
365 * the block pool is destroyed.
367 struct anv_vector mmap_cleanups;
371 union anv_free_list free_list;
372 struct anv_block_state state;
374 union anv_free_list back_free_list;
375 struct anv_block_state back_state;
378 /* Block pools are backed by a fixed-size 2GB memfd */
379 #define BLOCK_POOL_MEMFD_SIZE (1ull << 32)
381 /* The center of the block pool is also the middle of the memfd. This may
382 * change in the future if we decide differently for some reason.
384 #define BLOCK_POOL_MEMFD_CENTER (BLOCK_POOL_MEMFD_SIZE / 2)
386 static inline uint32_t
387 anv_block_pool_size(struct anv_block_pool *pool)
389 return pool->state.end + pool->back_state.end;
398 struct anv_fixed_size_state_pool {
400 union anv_free_list free_list;
401 struct anv_block_state block;
404 #define ANV_MIN_STATE_SIZE_LOG2 6
405 #define ANV_MAX_STATE_SIZE_LOG2 17
407 #define ANV_STATE_BUCKETS (ANV_MAX_STATE_SIZE_LOG2 - ANV_MIN_STATE_SIZE_LOG2 + 1)
409 struct anv_state_pool {
410 struct anv_block_pool *block_pool;
411 struct anv_fixed_size_state_pool buckets[ANV_STATE_BUCKETS];
414 struct anv_state_stream_block;
416 struct anv_state_stream {
417 struct anv_block_pool *block_pool;
419 /* The current working block */
420 struct anv_state_stream_block *block;
422 /* Offset at which the current block starts */
424 /* Offset at which to allocate the next state */
426 /* Offset at which the current block ends */
430 #define CACHELINE_SIZE 64
431 #define CACHELINE_MASK 63
434 anv_clflush_range(void *start, size_t size)
436 void *p = (void *) (((uintptr_t) start) & ~CACHELINE_MASK);
437 void *end = start + size;
439 __builtin_ia32_mfence();
441 __builtin_ia32_clflush(p);
447 anv_state_clflush(struct anv_state state)
449 anv_clflush_range(state.map, state.alloc_size);
452 void anv_block_pool_init(struct anv_block_pool *pool,
453 struct anv_device *device, uint32_t block_size);
454 void anv_block_pool_finish(struct anv_block_pool *pool);
455 int32_t anv_block_pool_alloc(struct anv_block_pool *pool);
456 int32_t anv_block_pool_alloc_back(struct anv_block_pool *pool);
457 void anv_block_pool_free(struct anv_block_pool *pool, int32_t offset);
458 void anv_state_pool_init(struct anv_state_pool *pool,
459 struct anv_block_pool *block_pool);
460 void anv_state_pool_finish(struct anv_state_pool *pool);
461 struct anv_state anv_state_pool_alloc(struct anv_state_pool *pool,
462 size_t state_size, size_t alignment);
463 void anv_state_pool_free(struct anv_state_pool *pool, struct anv_state state);
464 void anv_state_stream_init(struct anv_state_stream *stream,
465 struct anv_block_pool *block_pool);
466 void anv_state_stream_finish(struct anv_state_stream *stream);
467 struct anv_state anv_state_stream_alloc(struct anv_state_stream *stream,
468 uint32_t size, uint32_t alignment);
471 * Implements a pool of re-usable BOs. The interface is identical to that
472 * of block_pool except that each block is its own BO.
475 struct anv_device *device;
480 void anv_bo_pool_init(struct anv_bo_pool *pool, struct anv_device *device);
481 void anv_bo_pool_finish(struct anv_bo_pool *pool);
482 VkResult anv_bo_pool_alloc(struct anv_bo_pool *pool, struct anv_bo *bo,
484 void anv_bo_pool_free(struct anv_bo_pool *pool, const struct anv_bo *bo);
486 struct anv_scratch_pool {
487 /* Indexed by Per-Thread Scratch Space number (the hardware value) and stage */
488 struct anv_bo bos[16][MESA_SHADER_STAGES];
491 void anv_scratch_pool_init(struct anv_device *device,
492 struct anv_scratch_pool *pool);
493 void anv_scratch_pool_finish(struct anv_device *device,
494 struct anv_scratch_pool *pool);
495 struct anv_bo *anv_scratch_pool_alloc(struct anv_device *device,
496 struct anv_scratch_pool *pool,
497 gl_shader_stage stage,
498 unsigned per_thread_scratch);
500 void *anv_resolve_entrypoint(uint32_t index);
502 extern struct anv_dispatch_table dtable;
504 #define ANV_CALL(func) ({ \
505 if (dtable.func == NULL) { \
506 size_t idx = offsetof(struct anv_dispatch_table, func) / sizeof(void *); \
507 dtable.entrypoints[idx] = anv_resolve_entrypoint(idx); \
513 anv_alloc(const VkAllocationCallbacks *alloc,
514 size_t size, size_t align,
515 VkSystemAllocationScope scope)
517 return alloc->pfnAllocation(alloc->pUserData, size, align, scope);
521 anv_realloc(const VkAllocationCallbacks *alloc,
522 void *ptr, size_t size, size_t align,
523 VkSystemAllocationScope scope)
525 return alloc->pfnReallocation(alloc->pUserData, ptr, size, align, scope);
529 anv_free(const VkAllocationCallbacks *alloc, void *data)
531 alloc->pfnFree(alloc->pUserData, data);
535 anv_alloc2(const VkAllocationCallbacks *parent_alloc,
536 const VkAllocationCallbacks *alloc,
537 size_t size, size_t align,
538 VkSystemAllocationScope scope)
541 return anv_alloc(alloc, size, align, scope);
543 return anv_alloc(parent_alloc, size, align, scope);
547 anv_free2(const VkAllocationCallbacks *parent_alloc,
548 const VkAllocationCallbacks *alloc,
552 anv_free(alloc, data);
554 anv_free(parent_alloc, data);
557 struct anv_wsi_interaface;
559 #define VK_ICD_WSI_PLATFORM_MAX 5
561 struct anv_physical_device {
562 VK_LOADER_DATA _loader_data;
564 struct anv_instance * instance;
568 struct gen_device_info info;
569 uint64_t aperture_size;
570 struct brw_compiler * compiler;
571 struct isl_device isl_dev;
572 int cmd_parser_version;
575 uint32_t subslice_total;
577 struct anv_wsi_interface * wsi[VK_ICD_WSI_PLATFORM_MAX];
580 struct anv_instance {
581 VK_LOADER_DATA _loader_data;
583 VkAllocationCallbacks alloc;
586 int physicalDeviceCount;
587 struct anv_physical_device physicalDevice;
590 VkResult anv_init_wsi(struct anv_physical_device *physical_device);
591 void anv_finish_wsi(struct anv_physical_device *physical_device);
594 VK_LOADER_DATA _loader_data;
596 struct anv_device * device;
598 struct anv_state_pool * pool;
601 struct anv_pipeline_cache {
602 struct anv_device * device;
603 pthread_mutex_t mutex;
605 struct hash_table * cache;
608 struct anv_pipeline_bind_map;
610 void anv_pipeline_cache_init(struct anv_pipeline_cache *cache,
611 struct anv_device *device,
613 void anv_pipeline_cache_finish(struct anv_pipeline_cache *cache);
615 struct anv_shader_bin *
616 anv_pipeline_cache_search(struct anv_pipeline_cache *cache,
617 const void *key, uint32_t key_size);
618 struct anv_shader_bin *
619 anv_pipeline_cache_upload_kernel(struct anv_pipeline_cache *cache,
620 const void *key_data, uint32_t key_size,
621 const void *kernel_data, uint32_t kernel_size,
622 const void *prog_data, uint32_t prog_data_size,
623 const struct anv_pipeline_bind_map *bind_map);
626 VK_LOADER_DATA _loader_data;
628 VkAllocationCallbacks alloc;
630 struct anv_instance * instance;
632 struct gen_device_info info;
633 struct isl_device isl_dev;
636 bool can_chain_batches;
637 bool robust_buffer_access;
639 struct anv_bo_pool batch_bo_pool;
641 struct anv_block_pool dynamic_state_block_pool;
642 struct anv_state_pool dynamic_state_pool;
644 struct anv_block_pool instruction_block_pool;
645 struct anv_state_pool instruction_state_pool;
647 struct anv_block_pool surface_state_block_pool;
648 struct anv_state_pool surface_state_pool;
650 struct anv_bo workaround_bo;
652 struct anv_pipeline_cache blorp_shader_cache;
653 struct blorp_context blorp;
655 struct anv_state border_colors;
657 struct anv_queue queue;
659 struct anv_scratch_pool scratch_pool;
661 uint32_t default_mocs;
663 pthread_mutex_t mutex;
666 void anv_device_get_cache_uuid(void *uuid);
668 void anv_device_init_blorp(struct anv_device *device);
669 void anv_device_finish_blorp(struct anv_device *device);
671 void* anv_gem_mmap(struct anv_device *device,
672 uint32_t gem_handle, uint64_t offset, uint64_t size, uint32_t flags);
673 void anv_gem_munmap(void *p, uint64_t size);
674 uint32_t anv_gem_create(struct anv_device *device, size_t size);
675 void anv_gem_close(struct anv_device *device, uint32_t gem_handle);
676 uint32_t anv_gem_userptr(struct anv_device *device, void *mem, size_t size);
677 int anv_gem_wait(struct anv_device *device, uint32_t gem_handle, int64_t *timeout_ns);
678 int anv_gem_execbuffer(struct anv_device *device,
679 struct drm_i915_gem_execbuffer2 *execbuf);
680 int anv_gem_set_tiling(struct anv_device *device, uint32_t gem_handle,
681 uint32_t stride, uint32_t tiling);
682 int anv_gem_create_context(struct anv_device *device);
683 int anv_gem_destroy_context(struct anv_device *device, int context);
684 int anv_gem_get_param(int fd, uint32_t param);
685 bool anv_gem_get_bit6_swizzle(int fd, uint32_t tiling);
686 int anv_gem_get_aperture(int fd, uint64_t *size);
687 int anv_gem_handle_to_fd(struct anv_device *device, uint32_t gem_handle);
688 uint32_t anv_gem_fd_to_handle(struct anv_device *device, int fd);
689 int anv_gem_set_caching(struct anv_device *device, uint32_t gem_handle, uint32_t caching);
690 int anv_gem_set_domain(struct anv_device *device, uint32_t gem_handle,
691 uint32_t read_domains, uint32_t write_domain);
693 VkResult anv_bo_init_new(struct anv_bo *bo, struct anv_device *device, uint64_t size);
695 struct anv_reloc_list {
698 struct drm_i915_gem_relocation_entry * relocs;
699 struct anv_bo ** reloc_bos;
702 VkResult anv_reloc_list_init(struct anv_reloc_list *list,
703 const VkAllocationCallbacks *alloc);
704 void anv_reloc_list_finish(struct anv_reloc_list *list,
705 const VkAllocationCallbacks *alloc);
707 uint64_t anv_reloc_list_add(struct anv_reloc_list *list,
708 const VkAllocationCallbacks *alloc,
709 uint32_t offset, struct anv_bo *target_bo,
712 struct anv_batch_bo {
713 /* Link in the anv_cmd_buffer.owned_batch_bos list */
714 struct list_head link;
718 /* Bytes actually consumed in this batch BO */
721 /* Last seen surface state block pool bo offset */
722 uint32_t last_ss_pool_bo_offset;
724 struct anv_reloc_list relocs;
728 const VkAllocationCallbacks * alloc;
734 struct anv_reloc_list * relocs;
736 /* This callback is called (with the associated user data) in the event
737 * that the batch runs out of space.
739 VkResult (*extend_cb)(struct anv_batch *, void *);
743 void *anv_batch_emit_dwords(struct anv_batch *batch, int num_dwords);
744 void anv_batch_emit_batch(struct anv_batch *batch, struct anv_batch *other);
745 uint64_t anv_batch_emit_reloc(struct anv_batch *batch,
746 void *location, struct anv_bo *bo, uint32_t offset);
747 VkResult anv_device_submit_simple_batch(struct anv_device *device,
748 struct anv_batch *batch);
755 static inline uint64_t
756 _anv_combine_address(struct anv_batch *batch, void *location,
757 const struct anv_address address, uint32_t delta)
759 if (address.bo == NULL) {
760 return address.offset + delta;
762 assert(batch->start <= location && location < batch->end);
764 return anv_batch_emit_reloc(batch, location, address.bo, address.offset + delta);
768 #define __gen_address_type struct anv_address
769 #define __gen_user_data struct anv_batch
770 #define __gen_combine_address _anv_combine_address
772 /* Wrapper macros needed to work around preprocessor argument issues. In
773 * particular, arguments don't get pre-evaluated if they are concatenated.
774 * This means that, if you pass GENX(3DSTATE_PS) into the emit macro, the
775 * GENX macro won't get evaluated if the emit macro contains "cmd ## foo".
776 * We can work around this easily enough with these helpers.
778 #define __anv_cmd_length(cmd) cmd ## _length
779 #define __anv_cmd_length_bias(cmd) cmd ## _length_bias
780 #define __anv_cmd_header(cmd) cmd ## _header
781 #define __anv_cmd_pack(cmd) cmd ## _pack
782 #define __anv_reg_num(reg) reg ## _num
784 #define anv_pack_struct(dst, struc, ...) do { \
785 struct struc __template = { \
788 __anv_cmd_pack(struc)(NULL, dst, &__template); \
789 VG(VALGRIND_CHECK_MEM_IS_DEFINED(dst, __anv_cmd_length(struc) * 4)); \
792 #define anv_batch_emitn(batch, n, cmd, ...) ({ \
793 void *__dst = anv_batch_emit_dwords(batch, n); \
794 struct cmd __template = { \
795 __anv_cmd_header(cmd), \
796 .DWordLength = n - __anv_cmd_length_bias(cmd), \
799 __anv_cmd_pack(cmd)(batch, __dst, &__template); \
803 #define anv_batch_emit_merge(batch, dwords0, dwords1) \
807 static_assert(ARRAY_SIZE(dwords0) == ARRAY_SIZE(dwords1), "mismatch merge"); \
808 dw = anv_batch_emit_dwords((batch), ARRAY_SIZE(dwords0)); \
809 for (uint32_t i = 0; i < ARRAY_SIZE(dwords0); i++) \
810 dw[i] = (dwords0)[i] | (dwords1)[i]; \
811 VG(VALGRIND_CHECK_MEM_IS_DEFINED(dw, ARRAY_SIZE(dwords0) * 4));\
814 #define anv_batch_emit(batch, cmd, name) \
815 for (struct cmd name = { __anv_cmd_header(cmd) }, \
816 *_dst = anv_batch_emit_dwords(batch, __anv_cmd_length(cmd)); \
817 __builtin_expect(_dst != NULL, 1); \
818 ({ __anv_cmd_pack(cmd)(batch, _dst, &name); \
819 VG(VALGRIND_CHECK_MEM_IS_DEFINED(_dst, __anv_cmd_length(cmd) * 4)); \
823 #define anv_state_pool_emit(pool, cmd, align, ...) ({ \
824 const uint32_t __size = __anv_cmd_length(cmd) * 4; \
825 struct anv_state __state = \
826 anv_state_pool_alloc((pool), __size, align); \
827 struct cmd __template = { \
830 __anv_cmd_pack(cmd)(NULL, __state.map, &__template); \
831 VG(VALGRIND_CHECK_MEM_IS_DEFINED(__state.map, __anv_cmd_length(cmd) * 4)); \
832 if (!(pool)->block_pool->device->info.has_llc) \
833 anv_state_clflush(__state); \
837 #define GEN7_MOCS (struct GEN7_MEMORY_OBJECT_CONTROL_STATE) { \
838 .GraphicsDataTypeGFDT = 0, \
839 .LLCCacheabilityControlLLCCC = 0, \
840 .L3CacheabilityControlL3CC = 1, \
843 #define GEN75_MOCS (struct GEN75_MEMORY_OBJECT_CONTROL_STATE) { \
844 .LLCeLLCCacheabilityControlLLCCC = 0, \
845 .L3CacheabilityControlL3CC = 1, \
848 #define GEN8_MOCS (struct GEN8_MEMORY_OBJECT_CONTROL_STATE) { \
849 .MemoryTypeLLCeLLCCacheabilityControl = WB, \
850 .TargetCache = L3DefertoPATforLLCeLLCselection, \
854 /* Skylake: MOCS is now an index into an array of 62 different caching
855 * configurations programmed by the kernel.
858 #define GEN9_MOCS (struct GEN9_MEMORY_OBJECT_CONTROL_STATE) { \
859 /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */ \
860 .IndextoMOCSTables = 2 \
863 #define GEN9_MOCS_PTE { \
864 /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */ \
865 .IndextoMOCSTables = 1 \
868 struct anv_device_memory {
871 VkDeviceSize map_size;
876 * Header for Vertex URB Entry (VUE)
878 struct anv_vue_header {
880 uint32_t RTAIndex; /* RenderTargetArrayIndex */
881 uint32_t ViewportIndex;
885 struct anv_descriptor_set_binding_layout {
887 /* The type of the descriptors in this binding */
888 VkDescriptorType type;
891 /* Number of array elements in this binding */
894 /* Index into the flattend descriptor set */
895 uint16_t descriptor_index;
897 /* Index into the dynamic state array for a dynamic buffer */
898 int16_t dynamic_offset_index;
900 /* Index into the descriptor set buffer views */
901 int16_t buffer_index;
904 /* Index into the binding table for the associated surface */
905 int16_t surface_index;
907 /* Index into the sampler table for the associated sampler */
908 int16_t sampler_index;
910 /* Index into the image table for the associated image */
912 } stage[MESA_SHADER_STAGES];
914 /* Immutable samplers (or NULL if no immutable samplers) */
915 struct anv_sampler **immutable_samplers;
918 struct anv_descriptor_set_layout {
919 /* Number of bindings in this descriptor set */
920 uint16_t binding_count;
922 /* Total size of the descriptor set with room for all array entries */
925 /* Shader stages affected by this descriptor set */
926 uint16_t shader_stages;
928 /* Number of buffers in this descriptor set */
929 uint16_t buffer_count;
931 /* Number of dynamic offsets used by this descriptor set */
932 uint16_t dynamic_offset_count;
934 /* Bindings in this descriptor set */
935 struct anv_descriptor_set_binding_layout binding[0];
938 struct anv_descriptor {
939 VkDescriptorType type;
943 struct anv_image_view *image_view;
944 struct anv_sampler *sampler;
947 struct anv_buffer_view *buffer_view;
951 struct anv_descriptor_set {
952 const struct anv_descriptor_set_layout *layout;
954 uint32_t buffer_count;
955 struct anv_buffer_view *buffer_views;
956 struct anv_descriptor descriptors[0];
959 struct anv_descriptor_pool {
964 struct anv_state_stream surface_state_stream;
965 void *surface_state_free_list;
971 anv_descriptor_set_create(struct anv_device *device,
972 struct anv_descriptor_pool *pool,
973 const struct anv_descriptor_set_layout *layout,
974 struct anv_descriptor_set **out_set);
977 anv_descriptor_set_destroy(struct anv_device *device,
978 struct anv_descriptor_pool *pool,
979 struct anv_descriptor_set *set);
981 #define ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS UINT8_MAX
983 struct anv_pipeline_binding {
984 /* The descriptor set this surface corresponds to. The special value of
985 * ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS indicates that the offset refers
986 * to a color attachment and not a regular descriptor.
990 /* Binding in the descriptor set */
993 /* Index in the binding */
997 struct anv_pipeline_layout {
999 struct anv_descriptor_set_layout *layout;
1000 uint32_t dynamic_offset_start;
1006 bool has_dynamic_offsets;
1007 } stage[MESA_SHADER_STAGES];
1009 unsigned char sha1[20];
1013 struct anv_device * device;
1016 VkBufferUsageFlags usage;
1018 /* Set when bound */
1020 VkDeviceSize offset;
1023 enum anv_cmd_dirty_bits {
1024 ANV_CMD_DIRTY_DYNAMIC_VIEWPORT = 1 << 0, /* VK_DYNAMIC_STATE_VIEWPORT */
1025 ANV_CMD_DIRTY_DYNAMIC_SCISSOR = 1 << 1, /* VK_DYNAMIC_STATE_SCISSOR */
1026 ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH = 1 << 2, /* VK_DYNAMIC_STATE_LINE_WIDTH */
1027 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS = 1 << 3, /* VK_DYNAMIC_STATE_DEPTH_BIAS */
1028 ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS = 1 << 4, /* VK_DYNAMIC_STATE_BLEND_CONSTANTS */
1029 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS = 1 << 5, /* VK_DYNAMIC_STATE_DEPTH_BOUNDS */
1030 ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK = 1 << 6, /* VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK */
1031 ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK = 1 << 7, /* VK_DYNAMIC_STATE_STENCIL_WRITE_MASK */
1032 ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE = 1 << 8, /* VK_DYNAMIC_STATE_STENCIL_REFERENCE */
1033 ANV_CMD_DIRTY_DYNAMIC_ALL = (1 << 9) - 1,
1034 ANV_CMD_DIRTY_PIPELINE = 1 << 9,
1035 ANV_CMD_DIRTY_INDEX_BUFFER = 1 << 10,
1036 ANV_CMD_DIRTY_RENDER_TARGETS = 1 << 11,
1038 typedef uint32_t anv_cmd_dirty_mask_t;
1040 enum anv_pipe_bits {
1041 ANV_PIPE_DEPTH_CACHE_FLUSH_BIT = (1 << 0),
1042 ANV_PIPE_STALL_AT_SCOREBOARD_BIT = (1 << 1),
1043 ANV_PIPE_STATE_CACHE_INVALIDATE_BIT = (1 << 2),
1044 ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT = (1 << 3),
1045 ANV_PIPE_VF_CACHE_INVALIDATE_BIT = (1 << 4),
1046 ANV_PIPE_DATA_CACHE_FLUSH_BIT = (1 << 5),
1047 ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT = (1 << 10),
1048 ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT = (1 << 11),
1049 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT = (1 << 12),
1050 ANV_PIPE_DEPTH_STALL_BIT = (1 << 13),
1051 ANV_PIPE_CS_STALL_BIT = (1 << 20),
1053 /* This bit does not exist directly in PIPE_CONTROL. Instead it means that
1054 * a flush has happened but not a CS stall. The next time we do any sort
1055 * of invalidation we need to insert a CS stall at that time. Otherwise,
1056 * we would have to CS stall on every flush which could be bad.
1058 ANV_PIPE_NEEDS_CS_STALL_BIT = (1 << 21),
1061 #define ANV_PIPE_FLUSH_BITS ( \
1062 ANV_PIPE_DEPTH_CACHE_FLUSH_BIT | \
1063 ANV_PIPE_DATA_CACHE_FLUSH_BIT | \
1064 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT)
1066 #define ANV_PIPE_STALL_BITS ( \
1067 ANV_PIPE_STALL_AT_SCOREBOARD_BIT | \
1068 ANV_PIPE_DEPTH_STALL_BIT | \
1069 ANV_PIPE_CS_STALL_BIT)
1071 #define ANV_PIPE_INVALIDATE_BITS ( \
1072 ANV_PIPE_STATE_CACHE_INVALIDATE_BIT | \
1073 ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT | \
1074 ANV_PIPE_VF_CACHE_INVALIDATE_BIT | \
1075 ANV_PIPE_DATA_CACHE_FLUSH_BIT | \
1076 ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT | \
1077 ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT)
1079 struct anv_vertex_binding {
1080 struct anv_buffer * buffer;
1081 VkDeviceSize offset;
1084 struct anv_push_constants {
1085 /* Current allocated size of this push constants data structure.
1086 * Because a decent chunk of it may not be used (images on SKL, for
1087 * instance), we won't actually allocate the entire structure up-front.
1091 /* Push constant data provided by the client through vkPushConstants */
1092 uint8_t client_data[MAX_PUSH_CONSTANTS_SIZE];
1094 /* Our hardware only provides zero-based vertex and instance id so, in
1095 * order to satisfy the vulkan requirements, we may have to push one or
1096 * both of these into the shader.
1098 uint32_t base_vertex;
1099 uint32_t base_instance;
1101 /* Offsets and ranges for dynamically bound buffers */
1105 } dynamic[MAX_DYNAMIC_BUFFERS];
1107 /* Image data for image_load_store on pre-SKL */
1108 struct brw_image_param images[MAX_IMAGES];
1111 struct anv_dynamic_state {
1114 VkViewport viewports[MAX_VIEWPORTS];
1119 VkRect2D scissors[MAX_SCISSORS];
1130 float blend_constants[4];
1140 } stencil_compare_mask;
1145 } stencil_write_mask;
1150 } stencil_reference;
1153 extern const struct anv_dynamic_state default_dynamic_state;
1155 void anv_dynamic_state_copy(struct anv_dynamic_state *dest,
1156 const struct anv_dynamic_state *src,
1157 uint32_t copy_mask);
1160 * Attachment state when recording a renderpass instance.
1162 * The clear value is valid only if there exists a pending clear.
1164 struct anv_attachment_state {
1165 VkImageAspectFlags pending_clear_aspects;
1166 VkClearValue clear_value;
1169 /** State required while building cmd buffer */
1170 struct anv_cmd_state {
1171 /* PIPELINE_SELECT.PipelineSelection */
1172 uint32_t current_pipeline;
1173 const struct gen_l3_config * current_l3_config;
1175 anv_cmd_dirty_mask_t dirty;
1176 anv_cmd_dirty_mask_t compute_dirty;
1177 enum anv_pipe_bits pending_pipe_bits;
1178 uint32_t num_workgroups_offset;
1179 struct anv_bo *num_workgroups_bo;
1180 VkShaderStageFlags descriptors_dirty;
1181 VkShaderStageFlags push_constants_dirty;
1182 uint32_t scratch_size;
1183 struct anv_pipeline * pipeline;
1184 struct anv_pipeline * compute_pipeline;
1185 struct anv_framebuffer * framebuffer;
1186 struct anv_render_pass * pass;
1187 struct anv_subpass * subpass;
1188 VkRect2D render_area;
1189 uint32_t restart_index;
1190 struct anv_vertex_binding vertex_bindings[MAX_VBS];
1191 struct anv_descriptor_set * descriptors[MAX_SETS];
1192 VkShaderStageFlags push_constant_stages;
1193 struct anv_push_constants * push_constants[MESA_SHADER_STAGES];
1194 struct anv_state binding_tables[MESA_SHADER_STAGES];
1195 struct anv_state samplers[MESA_SHADER_STAGES];
1196 struct anv_dynamic_state dynamic;
1200 * Array length is anv_cmd_state::pass::attachment_count. Array content is
1201 * valid only when recording a render pass instance.
1203 struct anv_attachment_state * attachments;
1206 struct anv_buffer * index_buffer;
1207 uint32_t index_type; /**< 3DSTATE_INDEX_BUFFER.IndexFormat */
1208 uint32_t index_offset;
1212 struct anv_cmd_pool {
1213 VkAllocationCallbacks alloc;
1214 struct list_head cmd_buffers;
1217 #define ANV_CMD_BUFFER_BATCH_SIZE 8192
1219 enum anv_cmd_buffer_exec_mode {
1220 ANV_CMD_BUFFER_EXEC_MODE_PRIMARY,
1221 ANV_CMD_BUFFER_EXEC_MODE_EMIT,
1222 ANV_CMD_BUFFER_EXEC_MODE_GROW_AND_EMIT,
1223 ANV_CMD_BUFFER_EXEC_MODE_CHAIN,
1224 ANV_CMD_BUFFER_EXEC_MODE_COPY_AND_CHAIN,
1227 struct anv_cmd_buffer {
1228 VK_LOADER_DATA _loader_data;
1230 struct anv_device * device;
1232 struct anv_cmd_pool * pool;
1233 struct list_head pool_link;
1235 struct anv_batch batch;
1237 /* Fields required for the actual chain of anv_batch_bo's.
1239 * These fields are initialized by anv_cmd_buffer_init_batch_bo_chain().
1241 struct list_head batch_bos;
1242 enum anv_cmd_buffer_exec_mode exec_mode;
1244 /* A vector of anv_batch_bo pointers for every batch or surface buffer
1245 * referenced by this command buffer
1247 * initialized by anv_cmd_buffer_init_batch_bo_chain()
1249 struct anv_vector seen_bbos;
1251 /* A vector of int32_t's for every block of binding tables.
1253 * initialized by anv_cmd_buffer_init_batch_bo_chain()
1255 struct anv_vector bt_blocks;
1257 struct anv_reloc_list surface_relocs;
1259 /* Information needed for execbuf
1261 * These fields are generated by anv_cmd_buffer_prepare_execbuf().
1264 struct drm_i915_gem_execbuffer2 execbuf;
1266 struct drm_i915_gem_exec_object2 * objects;
1268 struct anv_bo ** bos;
1270 /* Allocated length of the 'objects' and 'bos' arrays */
1271 uint32_t array_length;
1276 /* Serial for tracking buffer completion */
1279 /* Stream objects for storing temporary data */
1280 struct anv_state_stream surface_state_stream;
1281 struct anv_state_stream dynamic_state_stream;
1283 VkCommandBufferUsageFlags usage_flags;
1284 VkCommandBufferLevel level;
1286 struct anv_cmd_state state;
1289 VkResult anv_cmd_buffer_init_batch_bo_chain(struct anv_cmd_buffer *cmd_buffer);
1290 void anv_cmd_buffer_fini_batch_bo_chain(struct anv_cmd_buffer *cmd_buffer);
1291 void anv_cmd_buffer_reset_batch_bo_chain(struct anv_cmd_buffer *cmd_buffer);
1292 void anv_cmd_buffer_end_batch_buffer(struct anv_cmd_buffer *cmd_buffer);
1293 void anv_cmd_buffer_add_secondary(struct anv_cmd_buffer *primary,
1294 struct anv_cmd_buffer *secondary);
1295 void anv_cmd_buffer_prepare_execbuf(struct anv_cmd_buffer *cmd_buffer);
1297 VkResult anv_cmd_buffer_emit_binding_table(struct anv_cmd_buffer *cmd_buffer,
1298 unsigned stage, struct anv_state *bt_state);
1299 VkResult anv_cmd_buffer_emit_samplers(struct anv_cmd_buffer *cmd_buffer,
1300 unsigned stage, struct anv_state *state);
1301 uint32_t anv_cmd_buffer_flush_descriptor_sets(struct anv_cmd_buffer *cmd_buffer);
1303 struct anv_state anv_cmd_buffer_emit_dynamic(struct anv_cmd_buffer *cmd_buffer,
1304 const void *data, uint32_t size, uint32_t alignment);
1305 struct anv_state anv_cmd_buffer_merge_dynamic(struct anv_cmd_buffer *cmd_buffer,
1306 uint32_t *a, uint32_t *b,
1307 uint32_t dwords, uint32_t alignment);
1310 anv_cmd_buffer_surface_base_address(struct anv_cmd_buffer *cmd_buffer);
1312 anv_cmd_buffer_alloc_binding_table(struct anv_cmd_buffer *cmd_buffer,
1313 uint32_t entries, uint32_t *state_offset);
1315 anv_cmd_buffer_alloc_surface_state(struct anv_cmd_buffer *cmd_buffer);
1317 anv_cmd_buffer_alloc_dynamic_state(struct anv_cmd_buffer *cmd_buffer,
1318 uint32_t size, uint32_t alignment);
1321 anv_cmd_buffer_new_binding_table_block(struct anv_cmd_buffer *cmd_buffer);
1323 void gen8_cmd_buffer_emit_viewport(struct anv_cmd_buffer *cmd_buffer);
1324 void gen8_cmd_buffer_emit_depth_viewport(struct anv_cmd_buffer *cmd_buffer,
1325 bool depth_clamp_enable);
1326 void gen7_cmd_buffer_emit_scissor(struct anv_cmd_buffer *cmd_buffer);
1328 void anv_cmd_buffer_emit_state_base_address(struct anv_cmd_buffer *cmd_buffer);
1330 void anv_cmd_state_setup_attachments(struct anv_cmd_buffer *cmd_buffer,
1331 const VkRenderPassBeginInfo *info);
1334 anv_cmd_buffer_push_constants(struct anv_cmd_buffer *cmd_buffer,
1335 gl_shader_stage stage);
1337 anv_cmd_buffer_cs_push_constants(struct anv_cmd_buffer *cmd_buffer);
1339 void anv_cmd_buffer_clear_subpass(struct anv_cmd_buffer *cmd_buffer);
1340 void anv_cmd_buffer_resolve_subpass(struct anv_cmd_buffer *cmd_buffer);
1342 const struct anv_image_view *
1343 anv_cmd_buffer_get_depth_stencil_view(const struct anv_cmd_buffer *cmd_buffer);
1345 void anv_cmd_buffer_dump(struct anv_cmd_buffer *cmd_buffer);
1349 struct drm_i915_gem_execbuffer2 execbuf;
1350 struct drm_i915_gem_exec_object2 exec2_objects[1];
1356 struct anv_state state;
1361 struct anv_shader_module {
1362 struct nir_shader * nir;
1364 unsigned char sha1[20];
1369 void anv_hash_shader(unsigned char *hash, const void *key, size_t key_size,
1370 struct anv_shader_module *module,
1371 const char *entrypoint,
1372 const struct anv_pipeline_layout *pipeline_layout,
1373 const VkSpecializationInfo *spec_info);
1375 static inline gl_shader_stage
1376 vk_to_mesa_shader_stage(VkShaderStageFlagBits vk_stage)
1378 assert(__builtin_popcount(vk_stage) == 1);
1379 return ffs(vk_stage) - 1;
1382 static inline VkShaderStageFlagBits
1383 mesa_to_vk_shader_stage(gl_shader_stage mesa_stage)
1385 return (1 << mesa_stage);
1388 #define ANV_STAGE_MASK ((1 << MESA_SHADER_STAGES) - 1)
1390 #define anv_foreach_stage(stage, stage_bits) \
1391 for (gl_shader_stage stage, \
1392 __tmp = (gl_shader_stage)((stage_bits) & ANV_STAGE_MASK); \
1393 stage = __builtin_ffs(__tmp) - 1, __tmp; \
1394 __tmp &= ~(1 << (stage)))
1396 struct anv_pipeline_bind_map {
1397 uint32_t surface_count;
1398 uint32_t sampler_count;
1399 uint32_t image_count;
1401 struct anv_pipeline_binding * surface_to_descriptor;
1402 struct anv_pipeline_binding * sampler_to_descriptor;
1405 struct anv_shader_bin {
1408 struct anv_state kernel;
1409 uint32_t kernel_size;
1411 struct anv_pipeline_bind_map bind_map;
1413 uint32_t prog_data_size;
1415 /* Prog data follows, then the key, both aligned to 8-bytes */
1418 struct anv_shader_bin *
1419 anv_shader_bin_create(struct anv_device *device,
1420 const void *key, uint32_t key_size,
1421 const void *kernel, uint32_t kernel_size,
1422 const void *prog_data, uint32_t prog_data_size,
1423 const struct anv_pipeline_bind_map *bind_map);
1426 anv_shader_bin_destroy(struct anv_device *device, struct anv_shader_bin *shader);
1429 anv_shader_bin_ref(struct anv_shader_bin *shader)
1431 assert(shader->ref_cnt >= 1);
1432 __sync_fetch_and_add(&shader->ref_cnt, 1);
1436 anv_shader_bin_unref(struct anv_device *device, struct anv_shader_bin *shader)
1438 assert(shader->ref_cnt >= 1);
1439 if (__sync_fetch_and_add(&shader->ref_cnt, -1) == 1)
1440 anv_shader_bin_destroy(device, shader);
1443 static inline const struct brw_stage_prog_data *
1444 anv_shader_bin_get_prog_data(const struct anv_shader_bin *shader)
1446 const void *data = shader;
1447 data += align_u32(sizeof(struct anv_shader_bin), 8);
1451 struct anv_pipeline {
1452 struct anv_device * device;
1453 struct anv_batch batch;
1454 uint32_t batch_data[512];
1455 struct anv_reloc_list batch_relocs;
1456 uint32_t dynamic_state_mask;
1457 struct anv_dynamic_state dynamic_state;
1459 struct anv_pipeline_layout * layout;
1461 bool needs_data_cache;
1463 struct anv_shader_bin * shaders[MESA_SHADER_STAGES];
1466 const struct gen_l3_config * l3_config;
1467 uint32_t total_size;
1470 VkShaderStageFlags active_stages;
1471 struct anv_state blend_state;
1479 uint32_t binding_stride[MAX_VBS];
1480 bool instancing_enable[MAX_VBS];
1481 bool primitive_restart;
1484 uint32_t cs_right_mask;
1486 bool depth_clamp_enable;
1490 uint32_t depth_stencil_state[3];
1496 uint32_t wm_depth_stencil[3];
1500 uint32_t wm_depth_stencil[4];
1505 anv_pipeline_has_stage(const struct anv_pipeline *pipeline,
1506 gl_shader_stage stage)
1508 return (pipeline->active_stages & mesa_to_vk_shader_stage(stage)) != 0;
1511 #define ANV_DECL_GET_PROG_DATA_FUNC(prefix, stage) \
1512 static inline const struct brw_##prefix##_prog_data * \
1513 get_##prefix##_prog_data(struct anv_pipeline *pipeline) \
1515 if (anv_pipeline_has_stage(pipeline, stage)) { \
1516 return (const struct brw_##prefix##_prog_data *) \
1517 anv_shader_bin_get_prog_data(pipeline->shaders[stage]); \
1523 ANV_DECL_GET_PROG_DATA_FUNC(vs, MESA_SHADER_VERTEX)
1524 ANV_DECL_GET_PROG_DATA_FUNC(gs, MESA_SHADER_GEOMETRY)
1525 ANV_DECL_GET_PROG_DATA_FUNC(wm, MESA_SHADER_FRAGMENT)
1526 ANV_DECL_GET_PROG_DATA_FUNC(cs, MESA_SHADER_COMPUTE)
1529 anv_pipeline_init(struct anv_pipeline *pipeline, struct anv_device *device,
1530 struct anv_pipeline_cache *cache,
1531 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1532 const VkAllocationCallbacks *alloc);
1535 anv_pipeline_compile_cs(struct anv_pipeline *pipeline,
1536 struct anv_pipeline_cache *cache,
1537 const VkComputePipelineCreateInfo *info,
1538 struct anv_shader_module *module,
1539 const char *entrypoint,
1540 const VkSpecializationInfo *spec_info);
1543 anv_graphics_pipeline_create(VkDevice device,
1544 VkPipelineCache cache,
1545 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1546 const VkAllocationCallbacks *alloc,
1547 VkPipeline *pPipeline);
1550 enum isl_format isl_format:16;
1551 struct isl_swizzle swizzle;
1555 anv_get_format(const struct gen_device_info *devinfo, VkFormat format,
1556 VkImageAspectFlags aspect, VkImageTiling tiling);
1558 static inline enum isl_format
1559 anv_get_isl_format(const struct gen_device_info *devinfo, VkFormat vk_format,
1560 VkImageAspectFlags aspect, VkImageTiling tiling)
1562 return anv_get_format(devinfo, vk_format, aspect, tiling).isl_format;
1566 anv_pipeline_setup_l3_config(struct anv_pipeline *pipeline, bool needs_slm);
1569 * Subsurface of an anv_image.
1571 struct anv_surface {
1572 /** Valid only if isl_surf::size > 0. */
1573 struct isl_surf isl;
1576 * Offset from VkImage's base address, as bound by vkBindImageMemory().
1583 /* The original VkFormat provided by the client. This may not match any
1584 * of the actual surface formats.
1587 VkImageAspectFlags aspects;
1590 uint32_t array_size;
1591 uint32_t samples; /**< VkImageCreateInfo::samples */
1592 VkImageUsageFlags usage; /**< Superset of VkImageCreateInfo::usage. */
1593 VkImageTiling tiling; /** VkImageCreateInfo::tiling */
1598 /* Set when bound */
1600 VkDeviceSize offset;
1605 * For each foo, anv_image::foo_surface is valid if and only if
1606 * anv_image::aspects has a foo aspect.
1608 * The hardware requires that the depth buffer and stencil buffer be
1609 * separate surfaces. From Vulkan's perspective, though, depth and stencil
1610 * reside in the same VkImage. To satisfy both the hardware and Vulkan, we
1611 * allocate the depth and stencil buffers as separate surfaces in the same
1615 struct anv_surface color_surface;
1618 struct anv_surface depth_surface;
1619 struct anv_surface hiz_surface;
1620 struct anv_surface stencil_surface;
1625 static inline uint32_t
1626 anv_get_layerCount(const struct anv_image *image,
1627 const VkImageSubresourceRange *range)
1629 return range->layerCount == VK_REMAINING_ARRAY_LAYERS ?
1630 image->array_size - range->baseArrayLayer : range->layerCount;
1633 static inline uint32_t
1634 anv_get_levelCount(const struct anv_image *image,
1635 const VkImageSubresourceRange *range)
1637 return range->levelCount == VK_REMAINING_MIP_LEVELS ?
1638 image->levels - range->baseMipLevel : range->levelCount;
1642 struct anv_image_view {
1643 const struct anv_image *image; /**< VkImageViewCreateInfo::image */
1645 uint32_t offset; /**< Offset into bo. */
1647 struct isl_view isl;
1649 VkImageAspectFlags aspect_mask;
1651 VkExtent3D extent; /**< Extent of VkImageViewCreateInfo::baseMipLevel. */
1653 /** RENDER_SURFACE_STATE when using image as a color render target. */
1654 struct anv_state color_rt_surface_state;
1656 /** RENDER_SURFACE_STATE when using image as a sampler surface. */
1657 struct anv_state sampler_surface_state;
1659 /** RENDER_SURFACE_STATE when using image as a storage image. */
1660 struct anv_state storage_surface_state;
1662 struct brw_image_param storage_image_param;
1665 struct anv_image_create_info {
1666 const VkImageCreateInfo *vk_info;
1668 /** An opt-in bitmask which filters an ISL-mapping of the Vulkan tiling. */
1669 isl_tiling_flags_t isl_tiling_flags;
1674 VkResult anv_image_create(VkDevice _device,
1675 const struct anv_image_create_info *info,
1676 const VkAllocationCallbacks* alloc,
1679 const struct anv_surface *
1680 anv_image_get_surface_for_aspect_mask(const struct anv_image *image,
1681 VkImageAspectFlags aspect_mask);
1684 anv_image_has_hiz(const struct anv_image *image)
1686 /* We must check the aspect because anv_image::hiz_surface belongs to
1689 return (image->aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
1690 image->hiz_surface.isl.size > 0;
1693 void anv_image_view_init(struct anv_image_view *view,
1694 struct anv_device *device,
1695 const VkImageViewCreateInfo* pCreateInfo,
1696 struct anv_cmd_buffer *cmd_buffer,
1697 VkImageUsageFlags usage_mask);
1699 struct anv_buffer_view {
1700 enum isl_format format; /**< VkBufferViewCreateInfo::format */
1702 uint32_t offset; /**< Offset into bo. */
1703 uint64_t range; /**< VkBufferViewCreateInfo::range */
1705 struct anv_state surface_state;
1706 struct anv_state storage_surface_state;
1708 struct brw_image_param storage_image_param;
1711 void anv_buffer_view_init(struct anv_buffer_view *view,
1712 struct anv_device *device,
1713 const VkBufferViewCreateInfo* pCreateInfo,
1714 struct anv_cmd_buffer *cmd_buffer);
1717 anv_isl_format_for_descriptor_type(VkDescriptorType type);
1719 static inline struct VkExtent3D
1720 anv_sanitize_image_extent(const VkImageType imageType,
1721 const struct VkExtent3D imageExtent)
1723 switch (imageType) {
1724 case VK_IMAGE_TYPE_1D:
1725 return (VkExtent3D) { imageExtent.width, 1, 1 };
1726 case VK_IMAGE_TYPE_2D:
1727 return (VkExtent3D) { imageExtent.width, imageExtent.height, 1 };
1728 case VK_IMAGE_TYPE_3D:
1731 unreachable("invalid image type");
1735 static inline struct VkOffset3D
1736 anv_sanitize_image_offset(const VkImageType imageType,
1737 const struct VkOffset3D imageOffset)
1739 switch (imageType) {
1740 case VK_IMAGE_TYPE_1D:
1741 return (VkOffset3D) { imageOffset.x, 0, 0 };
1742 case VK_IMAGE_TYPE_2D:
1743 return (VkOffset3D) { imageOffset.x, imageOffset.y, 0 };
1744 case VK_IMAGE_TYPE_3D:
1747 unreachable("invalid image type");
1752 void anv_fill_buffer_surface_state(struct anv_device *device,
1753 struct anv_state state,
1754 enum isl_format format,
1755 uint32_t offset, uint32_t range,
1758 void anv_image_view_fill_image_param(struct anv_device *device,
1759 struct anv_image_view *view,
1760 struct brw_image_param *param);
1761 void anv_buffer_view_fill_image_param(struct anv_device *device,
1762 struct anv_buffer_view *view,
1763 struct brw_image_param *param);
1765 struct anv_sampler {
1769 struct anv_framebuffer {
1774 uint32_t attachment_count;
1775 struct anv_image_view * attachments[0];
1778 struct anv_subpass {
1779 uint32_t input_count;
1780 uint32_t * input_attachments;
1781 uint32_t color_count;
1782 uint32_t * color_attachments;
1783 uint32_t * resolve_attachments;
1784 uint32_t depth_stencil_attachment;
1786 /** Subpass has at least one resolve attachment */
1790 struct anv_render_pass_attachment {
1793 VkAttachmentLoadOp load_op;
1794 VkAttachmentStoreOp store_op;
1795 VkAttachmentLoadOp stencil_load_op;
1798 struct anv_render_pass {
1799 uint32_t attachment_count;
1800 uint32_t subpass_count;
1801 uint32_t * subpass_attachments;
1802 struct anv_render_pass_attachment * attachments;
1803 struct anv_subpass subpasses[0];
1806 struct anv_query_pool_slot {
1812 struct anv_query_pool {
1818 void *anv_lookup_entrypoint(const char *name);
1820 void anv_dump_image_to_ppm(struct anv_device *device,
1821 struct anv_image *image, unsigned miplevel,
1822 unsigned array_layer, VkImageAspectFlagBits aspect,
1823 const char *filename);
1825 enum anv_dump_action {
1826 ANV_DUMP_FRAMEBUFFERS_BIT = 0x1,
1829 void anv_dump_start(struct anv_device *device, enum anv_dump_action actions);
1830 void anv_dump_finish(void);
1832 void anv_dump_add_framebuffer(struct anv_cmd_buffer *cmd_buffer,
1833 struct anv_framebuffer *fb);
1835 #define ANV_DEFINE_HANDLE_CASTS(__anv_type, __VkType) \
1837 static inline struct __anv_type * \
1838 __anv_type ## _from_handle(__VkType _handle) \
1840 return (struct __anv_type *) _handle; \
1843 static inline __VkType \
1844 __anv_type ## _to_handle(struct __anv_type *_obj) \
1846 return (__VkType) _obj; \
1849 #define ANV_DEFINE_NONDISP_HANDLE_CASTS(__anv_type, __VkType) \
1851 static inline struct __anv_type * \
1852 __anv_type ## _from_handle(__VkType _handle) \
1854 return (struct __anv_type *)(uintptr_t) _handle; \
1857 static inline __VkType \
1858 __anv_type ## _to_handle(struct __anv_type *_obj) \
1860 return (__VkType)(uintptr_t) _obj; \
1863 #define ANV_FROM_HANDLE(__anv_type, __name, __handle) \
1864 struct __anv_type *__name = __anv_type ## _from_handle(__handle)
1866 ANV_DEFINE_HANDLE_CASTS(anv_cmd_buffer, VkCommandBuffer)
1867 ANV_DEFINE_HANDLE_CASTS(anv_device, VkDevice)
1868 ANV_DEFINE_HANDLE_CASTS(anv_instance, VkInstance)
1869 ANV_DEFINE_HANDLE_CASTS(anv_physical_device, VkPhysicalDevice)
1870 ANV_DEFINE_HANDLE_CASTS(anv_queue, VkQueue)
1872 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_cmd_pool, VkCommandPool)
1873 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_buffer, VkBuffer)
1874 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_buffer_view, VkBufferView)
1875 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_pool, VkDescriptorPool)
1876 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_set, VkDescriptorSet)
1877 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_set_layout, VkDescriptorSetLayout)
1878 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_device_memory, VkDeviceMemory)
1879 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_fence, VkFence)
1880 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_event, VkEvent)
1881 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_framebuffer, VkFramebuffer)
1882 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_image, VkImage)
1883 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_image_view, VkImageView);
1884 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_pipeline_cache, VkPipelineCache)
1885 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_pipeline, VkPipeline)
1886 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_pipeline_layout, VkPipelineLayout)
1887 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_query_pool, VkQueryPool)
1888 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_render_pass, VkRenderPass)
1889 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_sampler, VkSampler)
1890 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_shader_module, VkShaderModule)
1892 #define ANV_DEFINE_STRUCT_CASTS(__anv_type, __VkType) \
1894 static inline const __VkType * \
1895 __anv_type ## _to_ ## __VkType(const struct __anv_type *__anv_obj) \
1897 return (const __VkType *) __anv_obj; \
1900 #define ANV_COMMON_TO_STRUCT(__VkType, __vk_name, __common_name) \
1901 const __VkType *__vk_name = anv_common_to_ ## __VkType(__common_name)
1903 ANV_DEFINE_STRUCT_CASTS(anv_common, VkMemoryBarrier)
1904 ANV_DEFINE_STRUCT_CASTS(anv_common, VkBufferMemoryBarrier)
1905 ANV_DEFINE_STRUCT_CASTS(anv_common, VkImageMemoryBarrier)
1907 /* Gen-specific function declarations */
1909 # include "anv_genX.h"
1911 # define genX(x) gen7_##x
1912 # include "anv_genX.h"
1914 # define genX(x) gen75_##x
1915 # include "anv_genX.h"
1917 # define genX(x) gen8_##x
1918 # include "anv_genX.h"
1920 # define genX(x) gen9_##x
1921 # include "anv_genX.h"
1929 #endif /* ANV_PRIVATE_H */