2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
38 #define __gen_validate_value(x) VALGRIND_CHECK_MEM_IS_DEFINED(&(x), sizeof(x))
43 #include "brw_device_info.h"
44 #include "brw_compiler.h"
45 #include "util/macros.h"
46 #include "util/list.h"
48 /* Pre-declarations needed for WSI entrypoints */
51 typedef struct xcb_connection_t xcb_connection_t;
52 typedef uint32_t xcb_visualid_t;
53 typedef uint32_t xcb_window_t;
55 #define VK_USE_PLATFORM_XCB_KHR
56 #define VK_USE_PLATFORM_WAYLAND_KHR
59 #include <vulkan/vulkan.h>
60 #include <vulkan/vulkan_intel.h>
61 #include <vulkan/vk_icd.h>
63 #include "anv_entrypoints.h"
64 #include "brw_context.h"
74 #define MAX_VIEWPORTS 16
75 #define MAX_SCISSORS 16
76 #define MAX_PUSH_CONSTANTS_SIZE 128
77 #define MAX_DYNAMIC_BUFFERS 16
79 #define MAX_SAMPLES_LOG2 4 /* SKL supports 16 samples */
81 #define anv_noreturn __attribute__((__noreturn__))
82 #define anv_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
84 #define MIN(a, b) ((a) < (b) ? (a) : (b))
85 #define MAX(a, b) ((a) > (b) ? (a) : (b))
87 static inline uint32_t
88 align_u32(uint32_t v, uint32_t a)
90 assert(a != 0 && a == (a & -a));
91 return (v + a - 1) & ~(a - 1);
94 static inline uint64_t
95 align_u64(uint64_t v, uint64_t a)
97 assert(a != 0 && a == (a & -a));
98 return (v + a - 1) & ~(a - 1);
101 static inline int32_t
102 align_i32(int32_t v, int32_t a)
104 assert(a != 0 && a == (a & -a));
105 return (v + a - 1) & ~(a - 1);
108 /** Alignment must be a power of 2. */
110 anv_is_aligned(uintmax_t n, uintmax_t a)
112 assert(a == (a & -a));
113 return (n & (a - 1)) == 0;
116 static inline uint32_t
117 anv_minify(uint32_t n, uint32_t levels)
119 if (unlikely(n == 0))
122 return MAX(n >> levels, 1);
126 anv_clamp_f(float f, float min, float max)
139 anv_clear_mask(uint32_t *inout_mask, uint32_t clear_mask)
141 if (*inout_mask & clear_mask) {
142 *inout_mask &= ~clear_mask;
149 #define for_each_bit(b, dword) \
150 for (uint32_t __dword = (dword); \
151 (b) = __builtin_ffs(__dword) - 1, __dword; \
152 __dword &= ~(1 << (b)))
154 #define typed_memcpy(dest, src, count) ({ \
155 static_assert(sizeof(*src) == sizeof(*dest), ""); \
156 memcpy((dest), (src), (count) * sizeof(*(src))); \
159 #define zero(x) (memset(&(x), 0, sizeof(x)))
161 /* Define no kernel as 1, since that's an illegal offset for a kernel */
165 VkStructureType sType;
169 /* Whenever we generate an error, pass it through this function. Useful for
170 * debugging, where we can break on it. Only call at error site, not when
171 * propagating errors. Might be useful to plug in a stack trace here.
174 VkResult __vk_errorf(VkResult error, const char *file, int line, const char *format, ...);
177 #define vk_error(error) __vk_errorf(error, __FILE__, __LINE__, NULL);
178 #define vk_errorf(error, format, ...) __vk_errorf(error, __FILE__, __LINE__, format, ## __VA_ARGS__);
180 #define vk_error(error) error
181 #define vk_errorf(error, format, ...) error
184 void __anv_finishme(const char *file, int line, const char *format, ...)
185 anv_printflike(3, 4);
186 void anv_loge(const char *format, ...) anv_printflike(1, 2);
187 void anv_loge_v(const char *format, va_list va);
190 * Print a FINISHME message, including its source location.
192 #define anv_finishme(format, ...) \
193 __anv_finishme(__FILE__, __LINE__, format, ##__VA_ARGS__);
195 /* A non-fatal assert. Useful for debugging. */
197 #define anv_assert(x) ({ \
198 if (unlikely(!(x))) \
199 fprintf(stderr, "%s:%d ASSERT: %s\n", __FILE__, __LINE__, #x); \
202 #define anv_assert(x)
206 * If a block of code is annotated with anv_validate, then the block runs only
210 #define anv_validate if (1)
212 #define anv_validate if (0)
215 void anv_abortf(const char *format, ...) anv_noreturn anv_printflike(1, 2);
216 void anv_abortfv(const char *format, va_list va) anv_noreturn;
218 #define stub_return(v) \
220 anv_finishme("stub %s", __func__); \
226 anv_finishme("stub %s", __func__); \
231 * A dynamically growable, circular buffer. Elements are added at head and
232 * removed from tail. head and tail are free-running uint32_t indices and we
233 * only compute the modulo with size when accessing the array. This way,
234 * number of bytes in the queue is always head - tail, even in case of
241 uint32_t element_size;
246 int anv_vector_init(struct anv_vector *queue, uint32_t element_size, uint32_t size);
247 void *anv_vector_add(struct anv_vector *queue);
248 void *anv_vector_remove(struct anv_vector *queue);
251 anv_vector_length(struct anv_vector *queue)
253 return (queue->head - queue->tail) / queue->element_size;
257 anv_vector_head(struct anv_vector *vector)
259 assert(vector->tail < vector->head);
260 return (void *)((char *)vector->data +
261 ((vector->head - vector->element_size) &
262 (vector->size - 1)));
266 anv_vector_tail(struct anv_vector *vector)
268 return (void *)((char *)vector->data + (vector->tail & (vector->size - 1)));
272 anv_vector_finish(struct anv_vector *queue)
277 #define anv_vector_foreach(elem, queue) \
278 static_assert(__builtin_types_compatible_p(__typeof__(queue), struct anv_vector *), ""); \
279 for (uint32_t __anv_vector_offset = (queue)->tail; \
280 elem = (queue)->data + (__anv_vector_offset & ((queue)->size - 1)), __anv_vector_offset < (queue)->head; \
281 __anv_vector_offset += (queue)->element_size)
286 /* Index into the current validation list. This is used by the
287 * validation list building alrogithm to track which buffers are already
288 * in the validation list so that we can ensure uniqueness.
292 /* Last known offset. This value is provided by the kernel when we
293 * execbuf and is used as the presumed offset for the next bunch of
301 /* We need to set the WRITE flag on winsys bos so GEM will know we're
302 * writing to them and synchronize uses on other rings (eg if the display
303 * server uses the blitter ring).
308 /* Represents a lock-free linked list of "free" things. This is used by
309 * both the block pool and the state pools. Unfortunately, in order to
310 * solve the ABA problem, we can't use a single uint32_t head.
312 union anv_free_list {
316 /* A simple count that is incremented every time the head changes. */
322 #define ANV_FREE_LIST_EMPTY ((union anv_free_list) { { 1, 0 } })
324 struct anv_block_state {
334 struct anv_block_pool {
335 struct anv_device *device;
339 /* The offset from the start of the bo to the "center" of the block
340 * pool. Pointers to allocated blocks are given by
341 * bo.map + center_bo_offset + offsets.
343 uint32_t center_bo_offset;
345 /* Current memory map of the block pool. This pointer may or may not
346 * point to the actual beginning of the block pool memory. If
347 * anv_block_pool_alloc_back has ever been called, then this pointer
348 * will point to the "center" position of the buffer and all offsets
349 * (negative or positive) given out by the block pool alloc functions
350 * will be valid relative to this pointer.
352 * In particular, map == bo.map + center_offset
358 * Array of mmaps and gem handles owned by the block pool, reclaimed when
359 * the block pool is destroyed.
361 struct anv_vector mmap_cleanups;
365 union anv_free_list free_list;
366 struct anv_block_state state;
368 union anv_free_list back_free_list;
369 struct anv_block_state back_state;
372 /* Block pools are backed by a fixed-size 2GB memfd */
373 #define BLOCK_POOL_MEMFD_SIZE (1ull << 32)
375 /* The center of the block pool is also the middle of the memfd. This may
376 * change in the future if we decide differently for some reason.
378 #define BLOCK_POOL_MEMFD_CENTER (BLOCK_POOL_MEMFD_SIZE / 2)
380 static inline uint32_t
381 anv_block_pool_size(struct anv_block_pool *pool)
383 return pool->state.end + pool->back_state.end;
392 struct anv_fixed_size_state_pool {
394 union anv_free_list free_list;
395 struct anv_block_state block;
398 #define ANV_MIN_STATE_SIZE_LOG2 6
399 #define ANV_MAX_STATE_SIZE_LOG2 10
401 #define ANV_STATE_BUCKETS (ANV_MAX_STATE_SIZE_LOG2 - ANV_MIN_STATE_SIZE_LOG2)
403 struct anv_state_pool {
404 struct anv_block_pool *block_pool;
405 struct anv_fixed_size_state_pool buckets[ANV_STATE_BUCKETS];
408 struct anv_state_stream_block;
410 struct anv_state_stream {
411 struct anv_block_pool *block_pool;
413 /* The current working block */
414 struct anv_state_stream_block *block;
416 /* Offset at which the current block starts */
418 /* Offset at which to allocate the next state */
420 /* Offset at which the current block ends */
424 #define CACHELINE_SIZE 64
425 #define CACHELINE_MASK 63
428 anv_clflush_range(void *start, size_t size)
430 void *p = (void *) (((uintptr_t) start) & ~CACHELINE_MASK);
431 void *end = start + size;
433 __builtin_ia32_mfence();
435 __builtin_ia32_clflush(p);
441 anv_state_clflush(struct anv_state state)
443 anv_clflush_range(state.map, state.alloc_size);
446 void anv_block_pool_init(struct anv_block_pool *pool,
447 struct anv_device *device, uint32_t block_size);
448 void anv_block_pool_finish(struct anv_block_pool *pool);
449 int32_t anv_block_pool_alloc(struct anv_block_pool *pool);
450 int32_t anv_block_pool_alloc_back(struct anv_block_pool *pool);
451 void anv_block_pool_free(struct anv_block_pool *pool, int32_t offset);
452 void anv_state_pool_init(struct anv_state_pool *pool,
453 struct anv_block_pool *block_pool);
454 void anv_state_pool_finish(struct anv_state_pool *pool);
455 struct anv_state anv_state_pool_alloc(struct anv_state_pool *pool,
456 size_t state_size, size_t alignment);
457 void anv_state_pool_free(struct anv_state_pool *pool, struct anv_state state);
458 void anv_state_stream_init(struct anv_state_stream *stream,
459 struct anv_block_pool *block_pool);
460 void anv_state_stream_finish(struct anv_state_stream *stream);
461 struct anv_state anv_state_stream_alloc(struct anv_state_stream *stream,
462 uint32_t size, uint32_t alignment);
465 * Implements a pool of re-usable BOs. The interface is identical to that
466 * of block_pool except that each block is its own BO.
469 struct anv_device *device;
476 void anv_bo_pool_init(struct anv_bo_pool *pool,
477 struct anv_device *device, uint32_t block_size);
478 void anv_bo_pool_finish(struct anv_bo_pool *pool);
479 VkResult anv_bo_pool_alloc(struct anv_bo_pool *pool, struct anv_bo *bo,
481 void anv_bo_pool_free(struct anv_bo_pool *pool, const struct anv_bo *bo);
484 void *anv_resolve_entrypoint(uint32_t index);
486 extern struct anv_dispatch_table dtable;
488 #define ANV_CALL(func) ({ \
489 if (dtable.func == NULL) { \
490 size_t idx = offsetof(struct anv_dispatch_table, func) / sizeof(void *); \
491 dtable.entrypoints[idx] = anv_resolve_entrypoint(idx); \
497 anv_alloc(const VkAllocationCallbacks *alloc,
498 size_t size, size_t align,
499 VkSystemAllocationScope scope)
501 return alloc->pfnAllocation(alloc->pUserData, size, align, scope);
505 anv_realloc(const VkAllocationCallbacks *alloc,
506 void *ptr, size_t size, size_t align,
507 VkSystemAllocationScope scope)
509 return alloc->pfnReallocation(alloc->pUserData, ptr, size, align, scope);
513 anv_free(const VkAllocationCallbacks *alloc, void *data)
515 alloc->pfnFree(alloc->pUserData, data);
519 anv_alloc2(const VkAllocationCallbacks *parent_alloc,
520 const VkAllocationCallbacks *alloc,
521 size_t size, size_t align,
522 VkSystemAllocationScope scope)
525 return anv_alloc(alloc, size, align, scope);
527 return anv_alloc(parent_alloc, size, align, scope);
531 anv_free2(const VkAllocationCallbacks *parent_alloc,
532 const VkAllocationCallbacks *alloc,
536 anv_free(alloc, data);
538 anv_free(parent_alloc, data);
541 struct anv_physical_device {
542 VK_LOADER_DATA _loader_data;
544 struct anv_instance * instance;
548 const struct brw_device_info * info;
549 uint64_t aperture_size;
550 struct brw_compiler * compiler;
551 struct isl_device isl_dev;
554 struct anv_wsi_interaface;
556 #define VK_ICD_WSI_PLATFORM_MAX 5
558 struct anv_instance {
559 VK_LOADER_DATA _loader_data;
561 VkAllocationCallbacks alloc;
564 int physicalDeviceCount;
565 struct anv_physical_device physicalDevice;
567 struct anv_wsi_interface * wsi[VK_ICD_WSI_PLATFORM_MAX];
570 VkResult anv_init_wsi(struct anv_instance *instance);
571 void anv_finish_wsi(struct anv_instance *instance);
573 struct anv_meta_state {
574 VkAllocationCallbacks alloc;
577 * Use array element `i` for images with `2^i` samples.
581 * Pipeline N is used to clear color attachment N of the current
584 * HACK: We use one pipeline per color attachment to work around the
585 * compiler's inability to dynamically set the render target index of
586 * the render target write message.
588 struct anv_pipeline *color_pipelines[MAX_RTS];
590 struct anv_pipeline *depth_only_pipeline;
591 struct anv_pipeline *stencil_only_pipeline;
592 struct anv_pipeline *depthstencil_pipeline;
593 } clear[1 + MAX_SAMPLES_LOG2];
596 VkRenderPass render_pass;
598 /** Pipeline that blits from a 1D image. */
599 VkPipeline pipeline_1d_src;
601 /** Pipeline that blits from a 2D image. */
602 VkPipeline pipeline_2d_src;
604 /** Pipeline that blits from a 3D image. */
605 VkPipeline pipeline_3d_src;
607 VkPipelineLayout pipeline_layout;
608 VkDescriptorSetLayout ds_layout;
612 VkRenderPass render_pass;
614 /** Pipeline that copies from a 2D image. */
615 VkPipeline pipeline_2d_src;
617 VkPipelineLayout pipeline_layout;
618 VkDescriptorSetLayout ds_layout;
622 /** Pipeline [i] resolves an image with 2^(i+1) samples. */
623 VkPipeline pipelines[MAX_SAMPLES_LOG2];
626 VkPipelineLayout pipeline_layout;
627 VkDescriptorSetLayout ds_layout;
632 VK_LOADER_DATA _loader_data;
634 struct anv_device * device;
636 struct anv_state_pool * pool;
639 struct anv_pipeline_cache {
640 struct anv_device * device;
641 struct anv_state_stream program_stream;
642 pthread_mutex_t mutex;
646 uint32_t kernel_count;
647 uint32_t * hash_table;
650 struct anv_pipeline_bind_map;
652 void anv_pipeline_cache_init(struct anv_pipeline_cache *cache,
653 struct anv_device *device);
654 void anv_pipeline_cache_finish(struct anv_pipeline_cache *cache);
655 uint32_t anv_pipeline_cache_search(struct anv_pipeline_cache *cache,
656 const unsigned char *sha1,
657 const struct brw_stage_prog_data **prog_data,
658 struct anv_pipeline_bind_map *map);
659 uint32_t anv_pipeline_cache_upload_kernel(struct anv_pipeline_cache *cache,
660 const unsigned char *sha1,
663 const struct brw_stage_prog_data **prog_data,
664 size_t prog_data_size,
665 struct anv_pipeline_bind_map *map);
668 VK_LOADER_DATA _loader_data;
670 VkAllocationCallbacks alloc;
672 struct anv_instance * instance;
674 struct brw_device_info info;
675 struct isl_device isl_dev;
679 struct anv_bo_pool batch_bo_pool;
681 struct anv_block_pool dynamic_state_block_pool;
682 struct anv_state_pool dynamic_state_pool;
684 struct anv_block_pool instruction_block_pool;
685 struct anv_pipeline_cache default_pipeline_cache;
687 struct anv_block_pool surface_state_block_pool;
688 struct anv_state_pool surface_state_pool;
690 struct anv_bo workaround_bo;
692 struct anv_meta_state meta_state;
694 struct anv_state border_colors;
696 struct anv_queue queue;
698 struct anv_block_pool scratch_block_pool;
700 uint32_t default_mocs;
702 pthread_mutex_t mutex;
705 void anv_device_get_cache_uuid(void *uuid);
708 void* anv_gem_mmap(struct anv_device *device,
709 uint32_t gem_handle, uint64_t offset, uint64_t size, uint32_t flags);
710 void anv_gem_munmap(void *p, uint64_t size);
711 uint32_t anv_gem_create(struct anv_device *device, size_t size);
712 void anv_gem_close(struct anv_device *device, uint32_t gem_handle);
713 uint32_t anv_gem_userptr(struct anv_device *device, void *mem, size_t size);
714 int anv_gem_wait(struct anv_device *device, uint32_t gem_handle, int64_t *timeout_ns);
715 int anv_gem_execbuffer(struct anv_device *device,
716 struct drm_i915_gem_execbuffer2 *execbuf);
717 int anv_gem_set_tiling(struct anv_device *device, uint32_t gem_handle,
718 uint32_t stride, uint32_t tiling);
719 int anv_gem_create_context(struct anv_device *device);
720 int anv_gem_destroy_context(struct anv_device *device, int context);
721 int anv_gem_get_param(int fd, uint32_t param);
722 bool anv_gem_get_bit6_swizzle(int fd, uint32_t tiling);
723 int anv_gem_get_aperture(int fd, uint64_t *size);
724 int anv_gem_handle_to_fd(struct anv_device *device, uint32_t gem_handle);
725 uint32_t anv_gem_fd_to_handle(struct anv_device *device, int fd);
726 int anv_gem_set_caching(struct anv_device *device, uint32_t gem_handle, uint32_t caching);
727 int anv_gem_set_domain(struct anv_device *device, uint32_t gem_handle,
728 uint32_t read_domains, uint32_t write_domain);
730 VkResult anv_bo_init_new(struct anv_bo *bo, struct anv_device *device, uint64_t size);
732 struct anv_reloc_list {
735 struct drm_i915_gem_relocation_entry * relocs;
736 struct anv_bo ** reloc_bos;
739 VkResult anv_reloc_list_init(struct anv_reloc_list *list,
740 const VkAllocationCallbacks *alloc);
741 void anv_reloc_list_finish(struct anv_reloc_list *list,
742 const VkAllocationCallbacks *alloc);
744 uint64_t anv_reloc_list_add(struct anv_reloc_list *list,
745 const VkAllocationCallbacks *alloc,
746 uint32_t offset, struct anv_bo *target_bo,
749 struct anv_batch_bo {
750 /* Link in the anv_cmd_buffer.owned_batch_bos list */
751 struct list_head link;
755 /* Bytes actually consumed in this batch BO */
758 /* Last seen surface state block pool bo offset */
759 uint32_t last_ss_pool_bo_offset;
761 struct anv_reloc_list relocs;
765 const VkAllocationCallbacks * alloc;
771 struct anv_reloc_list * relocs;
773 /* This callback is called (with the associated user data) in the event
774 * that the batch runs out of space.
776 VkResult (*extend_cb)(struct anv_batch *, void *);
780 void *anv_batch_emit_dwords(struct anv_batch *batch, int num_dwords);
781 void anv_batch_emit_batch(struct anv_batch *batch, struct anv_batch *other);
782 uint64_t anv_batch_emit_reloc(struct anv_batch *batch,
783 void *location, struct anv_bo *bo, uint32_t offset);
784 VkResult anv_device_submit_simple_batch(struct anv_device *device,
785 struct anv_batch *batch);
792 #define __gen_address_type struct anv_address
793 #define __gen_user_data struct anv_batch
795 static inline uint64_t
796 __gen_combine_address(struct anv_batch *batch, void *location,
797 const struct anv_address address, uint32_t delta)
799 if (address.bo == NULL) {
800 return address.offset + delta;
802 assert(batch->start <= location && location < batch->end);
804 return anv_batch_emit_reloc(batch, location, address.bo, address.offset + delta);
808 /* Wrapper macros needed to work around preprocessor argument issues. In
809 * particular, arguments don't get pre-evaluated if they are concatenated.
810 * This means that, if you pass GENX(3DSTATE_PS) into the emit macro, the
811 * GENX macro won't get evaluated if the emit macro contains "cmd ## foo".
812 * We can work around this easily enough with these helpers.
814 #define __anv_cmd_length(cmd) cmd ## _length
815 #define __anv_cmd_length_bias(cmd) cmd ## _length_bias
816 #define __anv_cmd_header(cmd) cmd ## _header
817 #define __anv_cmd_pack(cmd) cmd ## _pack
819 #define anv_batch_emit(batch, cmd, ...) do { \
820 void *__dst = anv_batch_emit_dwords(batch, __anv_cmd_length(cmd)); \
821 struct cmd __template = { \
822 __anv_cmd_header(cmd), \
825 __anv_cmd_pack(cmd)(batch, __dst, &__template); \
826 VG(VALGRIND_CHECK_MEM_IS_DEFINED(__dst, __anv_cmd_length(cmd) * 4)); \
829 #define anv_batch_emitn(batch, n, cmd, ...) ({ \
830 void *__dst = anv_batch_emit_dwords(batch, n); \
831 struct cmd __template = { \
832 __anv_cmd_header(cmd), \
833 .DWordLength = n - __anv_cmd_length_bias(cmd), \
836 __anv_cmd_pack(cmd)(batch, __dst, &__template); \
840 #define anv_batch_emit_merge(batch, dwords0, dwords1) \
844 static_assert(ARRAY_SIZE(dwords0) == ARRAY_SIZE(dwords1), "mismatch merge"); \
845 dw = anv_batch_emit_dwords((batch), ARRAY_SIZE(dwords0)); \
846 for (uint32_t i = 0; i < ARRAY_SIZE(dwords0); i++) \
847 dw[i] = (dwords0)[i] | (dwords1)[i]; \
848 VG(VALGRIND_CHECK_MEM_IS_DEFINED(dw, ARRAY_SIZE(dwords0) * 4));\
851 #define anv_state_pool_emit(pool, cmd, align, ...) ({ \
852 const uint32_t __size = __anv_cmd_length(cmd) * 4; \
853 struct anv_state __state = \
854 anv_state_pool_alloc((pool), __size, align); \
855 struct cmd __template = { \
858 __anv_cmd_pack(cmd)(NULL, __state.map, &__template); \
859 VG(VALGRIND_CHECK_MEM_IS_DEFINED(__state.map, __anv_cmd_length(cmd) * 4)); \
860 if (!(pool)->block_pool->device->info.has_llc) \
861 anv_state_clflush(__state); \
865 #define GEN7_MOCS (struct GEN7_MEMORY_OBJECT_CONTROL_STATE) { \
866 .GraphicsDataTypeGFDT = 0, \
867 .LLCCacheabilityControlLLCCC = 0, \
868 .L3CacheabilityControlL3CC = 1, \
871 #define GEN75_MOCS (struct GEN75_MEMORY_OBJECT_CONTROL_STATE) { \
872 .LLCeLLCCacheabilityControlLLCCC = 0, \
873 .L3CacheabilityControlL3CC = 1, \
876 #define GEN8_MOCS (struct GEN8_MEMORY_OBJECT_CONTROL_STATE) { \
877 .MemoryTypeLLCeLLCCacheabilityControl = WB, \
878 .TargetCache = L3DefertoPATforLLCeLLCselection, \
882 /* Skylake: MOCS is now an index into an array of 62 different caching
883 * configurations programmed by the kernel.
886 #define GEN9_MOCS (struct GEN9_MEMORY_OBJECT_CONTROL_STATE) { \
887 /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */ \
888 .IndextoMOCSTables = 2 \
891 #define GEN9_MOCS_PTE { \
892 /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */ \
893 .IndextoMOCSTables = 1 \
896 struct anv_device_memory {
899 VkDeviceSize map_size;
904 * Header for Vertex URB Entry (VUE)
906 struct anv_vue_header {
908 uint32_t RTAIndex; /* RenderTargetArrayIndex */
909 uint32_t ViewportIndex;
913 struct anv_descriptor_set_binding_layout {
914 /* Number of array elements in this binding */
917 /* Index into the flattend descriptor set */
918 uint16_t descriptor_index;
920 /* Index into the dynamic state array for a dynamic buffer */
921 int16_t dynamic_offset_index;
923 /* Index into the descriptor set buffer views */
924 int16_t buffer_index;
927 /* Index into the binding table for the associated surface */
928 int16_t surface_index;
930 /* Index into the sampler table for the associated sampler */
931 int16_t sampler_index;
933 /* Index into the image table for the associated image */
935 } stage[MESA_SHADER_STAGES];
937 /* Immutable samplers (or NULL if no immutable samplers) */
938 struct anv_sampler **immutable_samplers;
941 struct anv_descriptor_set_layout {
942 /* Number of bindings in this descriptor set */
943 uint16_t binding_count;
945 /* Total size of the descriptor set with room for all array entries */
948 /* Shader stages affected by this descriptor set */
949 uint16_t shader_stages;
951 /* Number of buffers in this descriptor set */
952 uint16_t buffer_count;
954 /* Number of dynamic offsets used by this descriptor set */
955 uint16_t dynamic_offset_count;
957 /* Bindings in this descriptor set */
958 struct anv_descriptor_set_binding_layout binding[0];
961 struct anv_descriptor {
962 VkDescriptorType type;
966 struct anv_image_view *image_view;
967 struct anv_sampler *sampler;
970 struct anv_buffer_view *buffer_view;
974 struct anv_descriptor_set {
975 const struct anv_descriptor_set_layout *layout;
977 uint32_t buffer_count;
978 struct anv_buffer_view *buffer_views;
979 struct anv_descriptor descriptors[0];
982 struct anv_descriptor_pool {
987 struct anv_state_stream surface_state_stream;
988 void *surface_state_free_list;
994 anv_descriptor_set_create(struct anv_device *device,
995 struct anv_descriptor_pool *pool,
996 const struct anv_descriptor_set_layout *layout,
997 struct anv_descriptor_set **out_set);
1000 anv_descriptor_set_destroy(struct anv_device *device,
1001 struct anv_descriptor_pool *pool,
1002 struct anv_descriptor_set *set);
1004 #define ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS UINT16_MAX
1006 struct anv_pipeline_binding {
1007 /* The descriptor set this surface corresponds to. The special value of
1008 * ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS indicates that the offset refers
1009 * to a color attachment and not a regular descriptor.
1013 /* Offset into the descriptor set or attachment list. */
1017 struct anv_pipeline_layout {
1019 struct anv_descriptor_set_layout *layout;
1020 uint32_t dynamic_offset_start;
1026 bool has_dynamic_offsets;
1027 } stage[MESA_SHADER_STAGES];
1031 struct anv_device * device;
1034 VkBufferUsageFlags usage;
1036 /* Set when bound */
1038 VkDeviceSize offset;
1041 enum anv_cmd_dirty_bits {
1042 ANV_CMD_DIRTY_DYNAMIC_VIEWPORT = 1 << 0, /* VK_DYNAMIC_STATE_VIEWPORT */
1043 ANV_CMD_DIRTY_DYNAMIC_SCISSOR = 1 << 1, /* VK_DYNAMIC_STATE_SCISSOR */
1044 ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH = 1 << 2, /* VK_DYNAMIC_STATE_LINE_WIDTH */
1045 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS = 1 << 3, /* VK_DYNAMIC_STATE_DEPTH_BIAS */
1046 ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS = 1 << 4, /* VK_DYNAMIC_STATE_BLEND_CONSTANTS */
1047 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS = 1 << 5, /* VK_DYNAMIC_STATE_DEPTH_BOUNDS */
1048 ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK = 1 << 6, /* VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK */
1049 ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK = 1 << 7, /* VK_DYNAMIC_STATE_STENCIL_WRITE_MASK */
1050 ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE = 1 << 8, /* VK_DYNAMIC_STATE_STENCIL_REFERENCE */
1051 ANV_CMD_DIRTY_DYNAMIC_ALL = (1 << 9) - 1,
1052 ANV_CMD_DIRTY_PIPELINE = 1 << 9,
1053 ANV_CMD_DIRTY_INDEX_BUFFER = 1 << 10,
1054 ANV_CMD_DIRTY_RENDER_TARGETS = 1 << 11,
1056 typedef uint32_t anv_cmd_dirty_mask_t;
1058 struct anv_vertex_binding {
1059 struct anv_buffer * buffer;
1060 VkDeviceSize offset;
1063 struct anv_push_constants {
1064 /* Current allocated size of this push constants data structure.
1065 * Because a decent chunk of it may not be used (images on SKL, for
1066 * instance), we won't actually allocate the entire structure up-front.
1070 /* Push constant data provided by the client through vkPushConstants */
1071 uint8_t client_data[MAX_PUSH_CONSTANTS_SIZE];
1073 /* Our hardware only provides zero-based vertex and instance id so, in
1074 * order to satisfy the vulkan requirements, we may have to push one or
1075 * both of these into the shader.
1077 uint32_t base_vertex;
1078 uint32_t base_instance;
1080 /* Offsets and ranges for dynamically bound buffers */
1084 } dynamic[MAX_DYNAMIC_BUFFERS];
1086 /* Image data for image_load_store on pre-SKL */
1087 struct brw_image_param images[MAX_IMAGES];
1090 struct anv_dynamic_state {
1093 VkViewport viewports[MAX_VIEWPORTS];
1098 VkRect2D scissors[MAX_SCISSORS];
1109 float blend_constants[4];
1119 } stencil_compare_mask;
1124 } stencil_write_mask;
1129 } stencil_reference;
1132 extern const struct anv_dynamic_state default_dynamic_state;
1134 void anv_dynamic_state_copy(struct anv_dynamic_state *dest,
1135 const struct anv_dynamic_state *src,
1136 uint32_t copy_mask);
1139 * Attachment state when recording a renderpass instance.
1141 * The clear value is valid only if there exists a pending clear.
1143 struct anv_attachment_state {
1144 VkImageAspectFlags pending_clear_aspects;
1145 VkClearValue clear_value;
1148 /** State required while building cmd buffer */
1149 struct anv_cmd_state {
1150 /* PIPELINE_SELECT.PipelineSelection */
1151 uint32_t current_pipeline;
1152 uint32_t current_l3_config;
1154 anv_cmd_dirty_mask_t dirty;
1155 anv_cmd_dirty_mask_t compute_dirty;
1156 uint32_t num_workgroups_offset;
1157 struct anv_bo *num_workgroups_bo;
1158 VkShaderStageFlags descriptors_dirty;
1159 VkShaderStageFlags push_constants_dirty;
1160 uint32_t scratch_size;
1161 struct anv_pipeline * pipeline;
1162 struct anv_pipeline * compute_pipeline;
1163 struct anv_framebuffer * framebuffer;
1164 struct anv_render_pass * pass;
1165 struct anv_subpass * subpass;
1166 uint32_t restart_index;
1167 struct anv_vertex_binding vertex_bindings[MAX_VBS];
1168 struct anv_descriptor_set * descriptors[MAX_SETS];
1169 struct anv_push_constants * push_constants[MESA_SHADER_STAGES];
1170 struct anv_state binding_tables[MESA_SHADER_STAGES];
1171 struct anv_state samplers[MESA_SHADER_STAGES];
1172 struct anv_dynamic_state dynamic;
1176 * Array length is anv_cmd_state::pass::attachment_count. Array content is
1177 * valid only when recording a render pass instance.
1179 struct anv_attachment_state * attachments;
1182 struct anv_buffer * index_buffer;
1183 uint32_t index_type; /**< 3DSTATE_INDEX_BUFFER.IndexFormat */
1184 uint32_t index_offset;
1188 struct anv_cmd_pool {
1189 VkAllocationCallbacks alloc;
1190 struct list_head cmd_buffers;
1193 #define ANV_CMD_BUFFER_BATCH_SIZE 8192
1195 enum anv_cmd_buffer_exec_mode {
1196 ANV_CMD_BUFFER_EXEC_MODE_PRIMARY,
1197 ANV_CMD_BUFFER_EXEC_MODE_EMIT,
1198 ANV_CMD_BUFFER_EXEC_MODE_CHAIN,
1199 ANV_CMD_BUFFER_EXEC_MODE_COPY_AND_CHAIN,
1202 struct anv_cmd_buffer {
1203 VK_LOADER_DATA _loader_data;
1205 struct anv_device * device;
1207 struct anv_cmd_pool * pool;
1208 struct list_head pool_link;
1210 struct anv_batch batch;
1212 /* Fields required for the actual chain of anv_batch_bo's.
1214 * These fields are initialized by anv_cmd_buffer_init_batch_bo_chain().
1216 struct list_head batch_bos;
1217 enum anv_cmd_buffer_exec_mode exec_mode;
1219 /* A vector of anv_batch_bo pointers for every batch or surface buffer
1220 * referenced by this command buffer
1222 * initialized by anv_cmd_buffer_init_batch_bo_chain()
1224 struct anv_vector seen_bbos;
1226 /* A vector of int32_t's for every block of binding tables.
1228 * initialized by anv_cmd_buffer_init_batch_bo_chain()
1230 struct anv_vector bt_blocks;
1232 struct anv_reloc_list surface_relocs;
1234 /* Information needed for execbuf
1236 * These fields are generated by anv_cmd_buffer_prepare_execbuf().
1239 struct drm_i915_gem_execbuffer2 execbuf;
1241 struct drm_i915_gem_exec_object2 * objects;
1243 struct anv_bo ** bos;
1245 /* Allocated length of the 'objects' and 'bos' arrays */
1246 uint32_t array_length;
1251 /* Serial for tracking buffer completion */
1254 /* Stream objects for storing temporary data */
1255 struct anv_state_stream surface_state_stream;
1256 struct anv_state_stream dynamic_state_stream;
1258 VkCommandBufferUsageFlags usage_flags;
1259 VkCommandBufferLevel level;
1261 struct anv_cmd_state state;
1264 VkResult anv_cmd_buffer_init_batch_bo_chain(struct anv_cmd_buffer *cmd_buffer);
1265 void anv_cmd_buffer_fini_batch_bo_chain(struct anv_cmd_buffer *cmd_buffer);
1266 void anv_cmd_buffer_reset_batch_bo_chain(struct anv_cmd_buffer *cmd_buffer);
1267 void anv_cmd_buffer_end_batch_buffer(struct anv_cmd_buffer *cmd_buffer);
1268 void anv_cmd_buffer_add_secondary(struct anv_cmd_buffer *primary,
1269 struct anv_cmd_buffer *secondary);
1270 void anv_cmd_buffer_prepare_execbuf(struct anv_cmd_buffer *cmd_buffer);
1272 VkResult anv_cmd_buffer_emit_binding_table(struct anv_cmd_buffer *cmd_buffer,
1273 unsigned stage, struct anv_state *bt_state);
1274 VkResult anv_cmd_buffer_emit_samplers(struct anv_cmd_buffer *cmd_buffer,
1275 unsigned stage, struct anv_state *state);
1276 uint32_t gen7_cmd_buffer_flush_descriptor_sets(struct anv_cmd_buffer *cmd_buffer);
1277 void gen7_cmd_buffer_emit_descriptor_pointers(struct anv_cmd_buffer *cmd_buffer,
1280 struct anv_state anv_cmd_buffer_emit_dynamic(struct anv_cmd_buffer *cmd_buffer,
1281 const void *data, uint32_t size, uint32_t alignment);
1282 struct anv_state anv_cmd_buffer_merge_dynamic(struct anv_cmd_buffer *cmd_buffer,
1283 uint32_t *a, uint32_t *b,
1284 uint32_t dwords, uint32_t alignment);
1287 anv_cmd_buffer_surface_base_address(struct anv_cmd_buffer *cmd_buffer);
1289 anv_cmd_buffer_alloc_binding_table(struct anv_cmd_buffer *cmd_buffer,
1290 uint32_t entries, uint32_t *state_offset);
1292 anv_cmd_buffer_alloc_surface_state(struct anv_cmd_buffer *cmd_buffer);
1294 anv_cmd_buffer_alloc_dynamic_state(struct anv_cmd_buffer *cmd_buffer,
1295 uint32_t size, uint32_t alignment);
1298 anv_cmd_buffer_new_binding_table_block(struct anv_cmd_buffer *cmd_buffer);
1300 void gen8_cmd_buffer_emit_viewport(struct anv_cmd_buffer *cmd_buffer);
1301 void gen7_cmd_buffer_emit_scissor(struct anv_cmd_buffer *cmd_buffer);
1303 void anv_cmd_buffer_emit_state_base_address(struct anv_cmd_buffer *cmd_buffer);
1305 void anv_cmd_state_setup_attachments(struct anv_cmd_buffer *cmd_buffer,
1306 const VkRenderPassBeginInfo *info);
1308 void anv_cmd_buffer_set_subpass(struct anv_cmd_buffer *cmd_buffer,
1309 struct anv_subpass *subpass);
1312 anv_cmd_buffer_push_constants(struct anv_cmd_buffer *cmd_buffer,
1313 gl_shader_stage stage);
1315 anv_cmd_buffer_cs_push_constants(struct anv_cmd_buffer *cmd_buffer);
1317 void anv_cmd_buffer_clear_subpass(struct anv_cmd_buffer *cmd_buffer);
1318 void anv_cmd_buffer_resolve_subpass(struct anv_cmd_buffer *cmd_buffer);
1320 const struct anv_image_view *
1321 anv_cmd_buffer_get_depth_stencil_view(const struct anv_cmd_buffer *cmd_buffer);
1323 void anv_cmd_buffer_dump(struct anv_cmd_buffer *cmd_buffer);
1327 struct drm_i915_gem_execbuffer2 execbuf;
1328 struct drm_i915_gem_exec_object2 exec2_objects[1];
1334 struct anv_state state;
1339 struct anv_shader_module {
1340 struct nir_shader * nir;
1342 unsigned char sha1[20];
1347 void anv_hash_shader(unsigned char *hash, const void *key, size_t key_size,
1348 struct anv_shader_module *module,
1349 const char *entrypoint,
1350 const VkSpecializationInfo *spec_info);
1352 static inline gl_shader_stage
1353 vk_to_mesa_shader_stage(VkShaderStageFlagBits vk_stage)
1355 assert(__builtin_popcount(vk_stage) == 1);
1356 return ffs(vk_stage) - 1;
1359 static inline VkShaderStageFlagBits
1360 mesa_to_vk_shader_stage(gl_shader_stage mesa_stage)
1362 return (1 << mesa_stage);
1365 #define ANV_STAGE_MASK ((1 << MESA_SHADER_STAGES) - 1)
1367 #define anv_foreach_stage(stage, stage_bits) \
1368 for (gl_shader_stage stage, \
1369 __tmp = (gl_shader_stage)((stage_bits) & ANV_STAGE_MASK); \
1370 stage = __builtin_ffs(__tmp) - 1, __tmp; \
1371 __tmp &= ~(1 << (stage)))
1373 struct anv_pipeline_bind_map {
1374 uint32_t surface_count;
1375 uint32_t sampler_count;
1376 uint32_t image_count;
1377 uint32_t attachment_count;
1379 struct anv_pipeline_binding * surface_to_descriptor;
1380 struct anv_pipeline_binding * sampler_to_descriptor;
1381 uint32_t * surface_to_attachment;
1384 struct anv_pipeline {
1385 struct anv_device * device;
1386 struct anv_batch batch;
1387 uint32_t batch_data[512];
1388 struct anv_reloc_list batch_relocs;
1389 uint32_t dynamic_state_mask;
1390 struct anv_dynamic_state dynamic_state;
1392 struct anv_pipeline_layout * layout;
1393 struct anv_pipeline_bind_map bindings[MESA_SHADER_STAGES];
1397 const struct brw_stage_prog_data * prog_data[MESA_SHADER_STAGES];
1398 uint32_t scratch_start[MESA_SHADER_STAGES];
1399 uint32_t total_scratch;
1401 uint8_t push_size[MESA_SHADER_FRAGMENT + 1];
1402 uint32_t start[MESA_SHADER_GEOMETRY + 1];
1403 uint32_t size[MESA_SHADER_GEOMETRY + 1];
1404 uint32_t entries[MESA_SHADER_GEOMETRY + 1];
1407 VkShaderStageFlags active_stages;
1408 struct anv_state blend_state;
1415 uint32_t ps_grf_start0;
1416 uint32_t ps_grf_start2;
1421 uint32_t binding_stride[MAX_VBS];
1422 bool instancing_enable[MAX_VBS];
1423 bool primitive_restart;
1426 uint32_t cs_thread_width_max;
1427 uint32_t cs_right_mask;
1431 uint32_t depth_stencil_state[3];
1437 uint32_t wm_depth_stencil[3];
1441 uint32_t wm_depth_stencil[4];
1445 static inline const struct brw_vs_prog_data *
1446 get_vs_prog_data(struct anv_pipeline *pipeline)
1448 return (const struct brw_vs_prog_data *) pipeline->prog_data[MESA_SHADER_VERTEX];
1451 static inline const struct brw_gs_prog_data *
1452 get_gs_prog_data(struct anv_pipeline *pipeline)
1454 return (const struct brw_gs_prog_data *) pipeline->prog_data[MESA_SHADER_GEOMETRY];
1457 static inline const struct brw_wm_prog_data *
1458 get_wm_prog_data(struct anv_pipeline *pipeline)
1460 return (const struct brw_wm_prog_data *) pipeline->prog_data[MESA_SHADER_FRAGMENT];
1463 static inline const struct brw_cs_prog_data *
1464 get_cs_prog_data(struct anv_pipeline *pipeline)
1466 return (const struct brw_cs_prog_data *) pipeline->prog_data[MESA_SHADER_COMPUTE];
1469 struct anv_graphics_pipeline_create_info {
1471 * If non-negative, overrides the color attachment count of the pipeline's
1474 int8_t color_attachment_count;
1477 bool disable_viewport;
1478 bool disable_scissor;
1484 anv_pipeline_init(struct anv_pipeline *pipeline, struct anv_device *device,
1485 struct anv_pipeline_cache *cache,
1486 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1487 const struct anv_graphics_pipeline_create_info *extra,
1488 const VkAllocationCallbacks *alloc);
1491 anv_pipeline_compile_cs(struct anv_pipeline *pipeline,
1492 struct anv_pipeline_cache *cache,
1493 const VkComputePipelineCreateInfo *info,
1494 struct anv_shader_module *module,
1495 const char *entrypoint,
1496 const VkSpecializationInfo *spec_info);
1499 anv_graphics_pipeline_create(VkDevice device,
1500 VkPipelineCache cache,
1501 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1502 const struct anv_graphics_pipeline_create_info *extra,
1503 const VkAllocationCallbacks *alloc,
1504 VkPipeline *pPipeline);
1506 struct anv_format_swizzle {
1514 const VkFormat vk_format;
1516 enum isl_format isl_format; /**< RENDER_SURFACE_STATE.SurfaceFormat */
1517 const struct isl_format_layout *isl_layout;
1518 struct anv_format_swizzle swizzle;
1523 const struct anv_format *
1524 anv_format_for_vk_format(VkFormat format);
1527 anv_get_isl_format(VkFormat format, VkImageAspectFlags aspect,
1528 VkImageTiling tiling, struct anv_format_swizzle *swizzle);
1531 anv_format_is_color(const struct anv_format *format)
1533 return !format->has_depth && !format->has_stencil;
1537 anv_format_is_depth_or_stencil(const struct anv_format *format)
1539 return format->has_depth || format->has_stencil;
1543 * Subsurface of an anv_image.
1545 struct anv_surface {
1546 struct isl_surf isl;
1549 * Offset from VkImage's base address, as bound by vkBindImageMemory().
1556 /* The original VkFormat provided by the client. This may not match any
1557 * of the actual surface formats.
1560 const struct anv_format *format;
1563 uint32_t array_size;
1564 uint32_t samples; /**< VkImageCreateInfo::samples */
1565 VkImageUsageFlags usage; /**< Superset of VkImageCreateInfo::usage. */
1566 VkImageTiling tiling; /** VkImageCreateInfo::tiling */
1571 /* Set when bound */
1573 VkDeviceSize offset;
1578 * For each foo, anv_image::foo_surface is valid if and only if
1579 * anv_image::format has a foo aspect.
1581 * The hardware requires that the depth buffer and stencil buffer be
1582 * separate surfaces. From Vulkan's perspective, though, depth and stencil
1583 * reside in the same VkImage. To satisfy both the hardware and Vulkan, we
1584 * allocate the depth and stencil buffers as separate surfaces in the same
1588 struct anv_surface color_surface;
1591 struct anv_surface depth_surface;
1592 struct anv_surface stencil_surface;
1597 static inline uint32_t
1598 anv_get_layerCount(const struct anv_image *image,
1599 const VkImageSubresourceRange *range)
1601 return range->layerCount == VK_REMAINING_ARRAY_LAYERS ?
1602 image->array_size - range->baseArrayLayer : range->layerCount;
1605 static inline uint32_t
1606 anv_get_levelCount(const struct anv_image *image,
1607 const VkImageSubresourceRange *range)
1609 return range->levelCount == VK_REMAINING_MIP_LEVELS ?
1610 image->levels - range->baseMipLevel : range->levelCount;
1614 struct anv_image_view {
1615 const struct anv_image *image; /**< VkImageViewCreateInfo::image */
1617 uint32_t offset; /**< Offset into bo. */
1619 VkImageAspectFlags aspect_mask;
1621 uint32_t base_layer;
1623 VkExtent3D extent; /**< Extent of VkImageViewCreateInfo::baseMipLevel. */
1625 /** RENDER_SURFACE_STATE when using image as a color render target. */
1626 struct anv_state color_rt_surface_state;
1628 /** RENDER_SURFACE_STATE when using image as a sampler surface. */
1629 struct anv_state sampler_surface_state;
1631 /** RENDER_SURFACE_STATE when using image as a storage image. */
1632 struct anv_state storage_surface_state;
1634 struct brw_image_param storage_image_param;
1637 struct anv_image_create_info {
1638 const VkImageCreateInfo *vk_info;
1639 isl_tiling_flags_t isl_tiling_flags;
1643 VkResult anv_image_create(VkDevice _device,
1644 const struct anv_image_create_info *info,
1645 const VkAllocationCallbacks* alloc,
1648 struct anv_surface *
1649 anv_image_get_surface_for_aspect_mask(struct anv_image *image,
1650 VkImageAspectFlags aspect_mask);
1652 void anv_image_view_init(struct anv_image_view *view,
1653 struct anv_device *device,
1654 const VkImageViewCreateInfo* pCreateInfo,
1655 struct anv_cmd_buffer *cmd_buffer,
1657 VkImageUsageFlags usage_mask);
1659 struct anv_buffer_view {
1660 enum isl_format format; /**< VkBufferViewCreateInfo::format */
1662 uint32_t offset; /**< Offset into bo. */
1663 uint64_t range; /**< VkBufferViewCreateInfo::range */
1665 struct anv_state surface_state;
1666 struct anv_state storage_surface_state;
1668 struct brw_image_param storage_image_param;
1671 const struct anv_format *
1672 anv_format_for_descriptor_type(VkDescriptorType type);
1674 void anv_fill_buffer_surface_state(struct anv_device *device,
1675 struct anv_state state,
1676 enum isl_format format,
1677 uint32_t offset, uint32_t range,
1680 void anv_image_view_fill_image_param(struct anv_device *device,
1681 struct anv_image_view *view,
1682 struct brw_image_param *param);
1683 void anv_buffer_view_fill_image_param(struct anv_device *device,
1684 struct anv_buffer_view *view,
1685 struct brw_image_param *param);
1687 struct anv_sampler {
1691 struct anv_framebuffer {
1696 uint32_t attachment_count;
1697 struct anv_image_view * attachments[0];
1700 struct anv_subpass {
1701 uint32_t input_count;
1702 uint32_t * input_attachments;
1703 uint32_t color_count;
1704 uint32_t * color_attachments;
1705 uint32_t * resolve_attachments;
1706 uint32_t depth_stencil_attachment;
1708 /** Subpass has at least one resolve attachment */
1712 struct anv_render_pass_attachment {
1713 const struct anv_format *format;
1715 VkAttachmentLoadOp load_op;
1716 VkAttachmentLoadOp stencil_load_op;
1719 struct anv_render_pass {
1720 uint32_t attachment_count;
1721 uint32_t subpass_count;
1722 uint32_t * subpass_attachments;
1723 struct anv_render_pass_attachment * attachments;
1724 struct anv_subpass subpasses[0];
1727 extern struct anv_render_pass anv_meta_dummy_renderpass;
1729 struct anv_query_pool_slot {
1735 struct anv_query_pool {
1741 VkResult anv_device_init_meta(struct anv_device *device);
1742 void anv_device_finish_meta(struct anv_device *device);
1744 void *anv_lookup_entrypoint(const char *name);
1746 void anv_dump_image_to_ppm(struct anv_device *device,
1747 struct anv_image *image, unsigned miplevel,
1748 unsigned array_layer, const char *filename);
1750 #define ANV_DEFINE_HANDLE_CASTS(__anv_type, __VkType) \
1752 static inline struct __anv_type * \
1753 __anv_type ## _from_handle(__VkType _handle) \
1755 return (struct __anv_type *) _handle; \
1758 static inline __VkType \
1759 __anv_type ## _to_handle(struct __anv_type *_obj) \
1761 return (__VkType) _obj; \
1764 #define ANV_DEFINE_NONDISP_HANDLE_CASTS(__anv_type, __VkType) \
1766 static inline struct __anv_type * \
1767 __anv_type ## _from_handle(__VkType _handle) \
1769 return (struct __anv_type *)(uintptr_t) _handle; \
1772 static inline __VkType \
1773 __anv_type ## _to_handle(struct __anv_type *_obj) \
1775 return (__VkType)(uintptr_t) _obj; \
1778 #define ANV_FROM_HANDLE(__anv_type, __name, __handle) \
1779 struct __anv_type *__name = __anv_type ## _from_handle(__handle)
1781 ANV_DEFINE_HANDLE_CASTS(anv_cmd_buffer, VkCommandBuffer)
1782 ANV_DEFINE_HANDLE_CASTS(anv_device, VkDevice)
1783 ANV_DEFINE_HANDLE_CASTS(anv_instance, VkInstance)
1784 ANV_DEFINE_HANDLE_CASTS(anv_physical_device, VkPhysicalDevice)
1785 ANV_DEFINE_HANDLE_CASTS(anv_queue, VkQueue)
1787 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_cmd_pool, VkCommandPool)
1788 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_buffer, VkBuffer)
1789 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_buffer_view, VkBufferView)
1790 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_pool, VkDescriptorPool)
1791 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_set, VkDescriptorSet)
1792 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_set_layout, VkDescriptorSetLayout)
1793 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_device_memory, VkDeviceMemory)
1794 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_fence, VkFence)
1795 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_event, VkEvent)
1796 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_framebuffer, VkFramebuffer)
1797 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_image, VkImage)
1798 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_image_view, VkImageView);
1799 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_pipeline_cache, VkPipelineCache)
1800 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_pipeline, VkPipeline)
1801 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_pipeline_layout, VkPipelineLayout)
1802 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_query_pool, VkQueryPool)
1803 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_render_pass, VkRenderPass)
1804 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_sampler, VkSampler)
1805 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_shader_module, VkShaderModule)
1807 #define ANV_DEFINE_STRUCT_CASTS(__anv_type, __VkType) \
1809 static inline const __VkType * \
1810 __anv_type ## _to_ ## __VkType(const struct __anv_type *__anv_obj) \
1812 return (const __VkType *) __anv_obj; \
1815 #define ANV_COMMON_TO_STRUCT(__VkType, __vk_name, __common_name) \
1816 const __VkType *__vk_name = anv_common_to_ ## __VkType(__common_name)
1818 ANV_DEFINE_STRUCT_CASTS(anv_common, VkMemoryBarrier)
1819 ANV_DEFINE_STRUCT_CASTS(anv_common, VkBufferMemoryBarrier)
1820 ANV_DEFINE_STRUCT_CASTS(anv_common, VkImageMemoryBarrier)
1822 /* Gen-specific function declarations */
1824 # include "anv_genX.h"
1826 # define genX(x) gen7_##x
1827 # include "anv_genX.h"
1829 # define genX(x) gen75_##x
1830 # include "anv_genX.h"
1832 # define genX(x) gen8_##x
1833 # include "anv_genX.h"
1835 # define genX(x) gen9_##x
1836 # include "anv_genX.h"