2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
38 #define __gen_validate_value(x) VALGRIND_CHECK_MEM_IS_DEFINED(&(x), sizeof(x))
43 #include "brw_device_info.h"
44 #include "brw_compiler.h"
45 #include "util/macros.h"
46 #include "util/list.h"
48 /* Pre-declarations needed for WSI entrypoints */
51 typedef struct xcb_connection_t xcb_connection_t;
52 typedef uint32_t xcb_visualid_t;
53 typedef uint32_t xcb_window_t;
56 #include <vulkan/vulkan.h>
57 #include <vulkan/vulkan_intel.h>
58 #include <vulkan/vk_icd.h>
60 #include "anv_entrypoints.h"
61 #include "brw_context.h"
71 #define MAX_VIEWPORTS 16
72 #define MAX_SCISSORS 16
73 #define MAX_PUSH_CONSTANTS_SIZE 128
74 #define MAX_DYNAMIC_BUFFERS 16
76 #define MAX_SAMPLES_LOG2 4 /* SKL supports 16 samples */
78 #define anv_noreturn __attribute__((__noreturn__))
79 #define anv_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
81 #define MIN(a, b) ((a) < (b) ? (a) : (b))
82 #define MAX(a, b) ((a) > (b) ? (a) : (b))
84 static inline uint32_t
85 align_u32(uint32_t v, uint32_t a)
87 assert(a != 0 && a == (a & -a));
88 return (v + a - 1) & ~(a - 1);
91 static inline uint64_t
92 align_u64(uint64_t v, uint64_t a)
94 assert(a != 0 && a == (a & -a));
95 return (v + a - 1) & ~(a - 1);
99 align_i32(int32_t v, int32_t a)
101 assert(a != 0 && a == (a & -a));
102 return (v + a - 1) & ~(a - 1);
105 /** Alignment must be a power of 2. */
107 anv_is_aligned(uintmax_t n, uintmax_t a)
109 assert(a == (a & -a));
110 return (n & (a - 1)) == 0;
113 static inline uint32_t
114 anv_minify(uint32_t n, uint32_t levels)
116 if (unlikely(n == 0))
119 return MAX(n >> levels, 1);
123 anv_clamp_f(float f, float min, float max)
136 anv_clear_mask(uint32_t *inout_mask, uint32_t clear_mask)
138 if (*inout_mask & clear_mask) {
139 *inout_mask &= ~clear_mask;
146 #define for_each_bit(b, dword) \
147 for (uint32_t __dword = (dword); \
148 (b) = __builtin_ffs(__dword) - 1, __dword; \
149 __dword &= ~(1 << (b)))
151 #define typed_memcpy(dest, src, count) ({ \
152 static_assert(sizeof(*src) == sizeof(*dest), ""); \
153 memcpy((dest), (src), (count) * sizeof(*(src))); \
156 #define zero(x) (memset(&(x), 0, sizeof(x)))
158 /* Define no kernel as 1, since that's an illegal offset for a kernel */
162 VkStructureType sType;
166 /* Whenever we generate an error, pass it through this function. Useful for
167 * debugging, where we can break on it. Only call at error site, not when
168 * propagating errors. Might be useful to plug in a stack trace here.
171 VkResult __vk_errorf(VkResult error, const char *file, int line, const char *format, ...);
174 #define vk_error(error) __vk_errorf(error, __FILE__, __LINE__, NULL);
175 #define vk_errorf(error, format, ...) __vk_errorf(error, __FILE__, __LINE__, format, ## __VA_ARGS__);
177 #define vk_error(error) error
178 #define vk_errorf(error, format, ...) error
181 void __anv_finishme(const char *file, int line, const char *format, ...)
182 anv_printflike(3, 4);
183 void anv_loge(const char *format, ...) anv_printflike(1, 2);
184 void anv_loge_v(const char *format, va_list va);
187 * Print a FINISHME message, including its source location.
189 #define anv_finishme(format, ...) \
190 __anv_finishme(__FILE__, __LINE__, format, ##__VA_ARGS__);
192 /* A non-fatal assert. Useful for debugging. */
194 #define anv_assert(x) ({ \
195 if (unlikely(!(x))) \
196 fprintf(stderr, "%s:%d ASSERT: %s\n", __FILE__, __LINE__, #x); \
199 #define anv_assert(x)
203 * If a block of code is annotated with anv_validate, then the block runs only
207 #define anv_validate if (1)
209 #define anv_validate if (0)
212 void anv_abortf(const char *format, ...) anv_noreturn anv_printflike(1, 2);
213 void anv_abortfv(const char *format, va_list va) anv_noreturn;
215 #define stub_return(v) \
217 anv_finishme("stub %s", __func__); \
223 anv_finishme("stub %s", __func__); \
228 * A dynamically growable, circular buffer. Elements are added at head and
229 * removed from tail. head and tail are free-running uint32_t indices and we
230 * only compute the modulo with size when accessing the array. This way,
231 * number of bytes in the queue is always head - tail, even in case of
238 uint32_t element_size;
243 int anv_vector_init(struct anv_vector *queue, uint32_t element_size, uint32_t size);
244 void *anv_vector_add(struct anv_vector *queue);
245 void *anv_vector_remove(struct anv_vector *queue);
248 anv_vector_length(struct anv_vector *queue)
250 return (queue->head - queue->tail) / queue->element_size;
254 anv_vector_head(struct anv_vector *vector)
256 assert(vector->tail < vector->head);
257 return (void *)((char *)vector->data +
258 ((vector->head - vector->element_size) &
259 (vector->size - 1)));
263 anv_vector_tail(struct anv_vector *vector)
265 return (void *)((char *)vector->data + (vector->tail & (vector->size - 1)));
269 anv_vector_finish(struct anv_vector *queue)
274 #define anv_vector_foreach(elem, queue) \
275 static_assert(__builtin_types_compatible_p(__typeof__(queue), struct anv_vector *), ""); \
276 for (uint32_t __anv_vector_offset = (queue)->tail; \
277 elem = (queue)->data + (__anv_vector_offset & ((queue)->size - 1)), __anv_vector_offset < (queue)->head; \
278 __anv_vector_offset += (queue)->element_size)
283 /* Index into the current validation list. This is used by the
284 * validation list building alrogithm to track which buffers are already
285 * in the validation list so that we can ensure uniqueness.
289 /* Last known offset. This value is provided by the kernel when we
290 * execbuf and is used as the presumed offset for the next bunch of
298 /* We need to set the WRITE flag on winsys bos so GEM will know we're
299 * writing to them and synchronize uses on other rings (eg if the display
300 * server uses the blitter ring).
305 /* Represents a lock-free linked list of "free" things. This is used by
306 * both the block pool and the state pools. Unfortunately, in order to
307 * solve the ABA problem, we can't use a single uint32_t head.
309 union anv_free_list {
313 /* A simple count that is incremented every time the head changes. */
319 #define ANV_FREE_LIST_EMPTY ((union anv_free_list) { { 1, 0 } })
321 struct anv_block_state {
331 struct anv_block_pool {
332 struct anv_device *device;
336 /* The offset from the start of the bo to the "center" of the block
337 * pool. Pointers to allocated blocks are given by
338 * bo.map + center_bo_offset + offsets.
340 uint32_t center_bo_offset;
342 /* Current memory map of the block pool. This pointer may or may not
343 * point to the actual beginning of the block pool memory. If
344 * anv_block_pool_alloc_back has ever been called, then this pointer
345 * will point to the "center" position of the buffer and all offsets
346 * (negative or positive) given out by the block pool alloc functions
347 * will be valid relative to this pointer.
349 * In particular, map == bo.map + center_offset
355 * Array of mmaps and gem handles owned by the block pool, reclaimed when
356 * the block pool is destroyed.
358 struct anv_vector mmap_cleanups;
362 union anv_free_list free_list;
363 struct anv_block_state state;
365 union anv_free_list back_free_list;
366 struct anv_block_state back_state;
369 /* Block pools are backed by a fixed-size 2GB memfd */
370 #define BLOCK_POOL_MEMFD_SIZE (1ull << 32)
372 /* The center of the block pool is also the middle of the memfd. This may
373 * change in the future if we decide differently for some reason.
375 #define BLOCK_POOL_MEMFD_CENTER (BLOCK_POOL_MEMFD_SIZE / 2)
377 static inline uint32_t
378 anv_block_pool_size(struct anv_block_pool *pool)
380 return pool->state.end + pool->back_state.end;
389 struct anv_fixed_size_state_pool {
391 union anv_free_list free_list;
392 struct anv_block_state block;
395 #define ANV_MIN_STATE_SIZE_LOG2 6
396 #define ANV_MAX_STATE_SIZE_LOG2 10
398 #define ANV_STATE_BUCKETS (ANV_MAX_STATE_SIZE_LOG2 - ANV_MIN_STATE_SIZE_LOG2)
400 struct anv_state_pool {
401 struct anv_block_pool *block_pool;
402 struct anv_fixed_size_state_pool buckets[ANV_STATE_BUCKETS];
405 struct anv_state_stream_block;
407 struct anv_state_stream {
408 struct anv_block_pool *block_pool;
410 /* The current working block */
411 struct anv_state_stream_block *block;
413 /* Offset at which the current block starts */
415 /* Offset at which to allocate the next state */
417 /* Offset at which the current block ends */
421 #define CACHELINE_SIZE 64
422 #define CACHELINE_MASK 63
425 anv_clflush_range(void *start, size_t size)
427 void *p = (void *) (((uintptr_t) start) & ~CACHELINE_MASK);
428 void *end = start + size;
430 __builtin_ia32_mfence();
432 __builtin_ia32_clflush(p);
438 anv_state_clflush(struct anv_state state)
440 anv_clflush_range(state.map, state.alloc_size);
443 void anv_block_pool_init(struct anv_block_pool *pool,
444 struct anv_device *device, uint32_t block_size);
445 void anv_block_pool_finish(struct anv_block_pool *pool);
446 int32_t anv_block_pool_alloc(struct anv_block_pool *pool);
447 int32_t anv_block_pool_alloc_back(struct anv_block_pool *pool);
448 void anv_block_pool_free(struct anv_block_pool *pool, int32_t offset);
449 void anv_state_pool_init(struct anv_state_pool *pool,
450 struct anv_block_pool *block_pool);
451 void anv_state_pool_finish(struct anv_state_pool *pool);
452 struct anv_state anv_state_pool_alloc(struct anv_state_pool *pool,
453 size_t state_size, size_t alignment);
454 void anv_state_pool_free(struct anv_state_pool *pool, struct anv_state state);
455 void anv_state_stream_init(struct anv_state_stream *stream,
456 struct anv_block_pool *block_pool);
457 void anv_state_stream_finish(struct anv_state_stream *stream);
458 struct anv_state anv_state_stream_alloc(struct anv_state_stream *stream,
459 uint32_t size, uint32_t alignment);
462 * Implements a pool of re-usable BOs. The interface is identical to that
463 * of block_pool except that each block is its own BO.
466 struct anv_device *device;
471 void anv_bo_pool_init(struct anv_bo_pool *pool, struct anv_device *device);
472 void anv_bo_pool_finish(struct anv_bo_pool *pool);
473 VkResult anv_bo_pool_alloc(struct anv_bo_pool *pool, struct anv_bo *bo,
475 void anv_bo_pool_free(struct anv_bo_pool *pool, const struct anv_bo *bo);
478 void *anv_resolve_entrypoint(uint32_t index);
480 extern struct anv_dispatch_table dtable;
482 #define ANV_CALL(func) ({ \
483 if (dtable.func == NULL) { \
484 size_t idx = offsetof(struct anv_dispatch_table, func) / sizeof(void *); \
485 dtable.entrypoints[idx] = anv_resolve_entrypoint(idx); \
491 anv_alloc(const VkAllocationCallbacks *alloc,
492 size_t size, size_t align,
493 VkSystemAllocationScope scope)
495 return alloc->pfnAllocation(alloc->pUserData, size, align, scope);
499 anv_realloc(const VkAllocationCallbacks *alloc,
500 void *ptr, size_t size, size_t align,
501 VkSystemAllocationScope scope)
503 return alloc->pfnReallocation(alloc->pUserData, ptr, size, align, scope);
507 anv_free(const VkAllocationCallbacks *alloc, void *data)
509 alloc->pfnFree(alloc->pUserData, data);
513 anv_alloc2(const VkAllocationCallbacks *parent_alloc,
514 const VkAllocationCallbacks *alloc,
515 size_t size, size_t align,
516 VkSystemAllocationScope scope)
519 return anv_alloc(alloc, size, align, scope);
521 return anv_alloc(parent_alloc, size, align, scope);
525 anv_free2(const VkAllocationCallbacks *parent_alloc,
526 const VkAllocationCallbacks *alloc,
530 anv_free(alloc, data);
532 anv_free(parent_alloc, data);
535 struct anv_wsi_interaface;
537 #define VK_ICD_WSI_PLATFORM_MAX 5
539 struct anv_physical_device {
540 VK_LOADER_DATA _loader_data;
542 struct anv_instance * instance;
546 const struct brw_device_info * info;
547 uint64_t aperture_size;
548 struct brw_compiler * compiler;
549 struct isl_device isl_dev;
550 int cmd_parser_version;
552 struct anv_wsi_interface * wsi[VK_ICD_WSI_PLATFORM_MAX];
555 struct anv_instance {
556 VK_LOADER_DATA _loader_data;
558 VkAllocationCallbacks alloc;
561 int physicalDeviceCount;
562 struct anv_physical_device physicalDevice;
565 VkResult anv_init_wsi(struct anv_physical_device *physical_device);
566 void anv_finish_wsi(struct anv_physical_device *physical_device);
568 struct anv_meta_state {
569 VkAllocationCallbacks alloc;
572 * Use array element `i` for images with `2^i` samples.
576 * Pipeline N is used to clear color attachment N of the current
579 * HACK: We use one pipeline per color attachment to work around the
580 * compiler's inability to dynamically set the render target index of
581 * the render target write message.
583 struct anv_pipeline *color_pipelines[MAX_RTS];
585 struct anv_pipeline *depth_only_pipeline;
586 struct anv_pipeline *stencil_only_pipeline;
587 struct anv_pipeline *depthstencil_pipeline;
588 } clear[1 + MAX_SAMPLES_LOG2];
591 VkRenderPass render_pass;
593 /** Pipeline that blits from a 1D image. */
594 VkPipeline pipeline_1d_src;
596 /** Pipeline that blits from a 2D image. */
597 VkPipeline pipeline_2d_src;
599 /** Pipeline that blits from a 3D image. */
600 VkPipeline pipeline_3d_src;
602 VkPipelineLayout pipeline_layout;
603 VkDescriptorSetLayout ds_layout;
607 VkRenderPass render_pass;
609 VkPipelineLayout img_p_layout;
610 VkDescriptorSetLayout img_ds_layout;
611 VkPipelineLayout buf_p_layout;
612 VkDescriptorSetLayout buf_ds_layout;
614 /* Pipelines indexed by source and destination type. See the
615 * blit2d_src_type and blit2d_dst_type enums in anv_meta_blit2d.c to
616 * see what these mean.
618 VkPipeline pipelines[2][3];
622 /** Pipeline [i] resolves an image with 2^(i+1) samples. */
623 VkPipeline pipelines[MAX_SAMPLES_LOG2];
626 VkPipelineLayout pipeline_layout;
627 VkDescriptorSetLayout ds_layout;
632 VK_LOADER_DATA _loader_data;
634 struct anv_device * device;
636 struct anv_state_pool * pool;
639 struct anv_pipeline_cache {
640 struct anv_device * device;
641 struct anv_state_stream program_stream;
642 pthread_mutex_t mutex;
646 uint32_t kernel_count;
647 uint32_t * hash_table;
650 struct anv_pipeline_bind_map;
652 void anv_pipeline_cache_init(struct anv_pipeline_cache *cache,
653 struct anv_device *device);
654 void anv_pipeline_cache_finish(struct anv_pipeline_cache *cache);
655 uint32_t anv_pipeline_cache_search(struct anv_pipeline_cache *cache,
656 const unsigned char *sha1,
657 const struct brw_stage_prog_data **prog_data,
658 struct anv_pipeline_bind_map *map);
659 uint32_t anv_pipeline_cache_upload_kernel(struct anv_pipeline_cache *cache,
660 const unsigned char *sha1,
663 const struct brw_stage_prog_data **prog_data,
664 size_t prog_data_size,
665 struct anv_pipeline_bind_map *map);
668 VK_LOADER_DATA _loader_data;
670 VkAllocationCallbacks alloc;
672 struct anv_instance * instance;
674 struct brw_device_info info;
675 struct isl_device isl_dev;
678 bool can_chain_batches;
680 struct anv_bo_pool batch_bo_pool;
682 struct anv_block_pool dynamic_state_block_pool;
683 struct anv_state_pool dynamic_state_pool;
685 struct anv_block_pool instruction_block_pool;
686 struct anv_pipeline_cache default_pipeline_cache;
688 struct anv_block_pool surface_state_block_pool;
689 struct anv_state_pool surface_state_pool;
691 struct anv_bo workaround_bo;
693 struct anv_meta_state meta_state;
695 struct anv_state border_colors;
697 struct anv_queue queue;
699 struct anv_block_pool scratch_block_pool;
701 uint32_t default_mocs;
703 pthread_mutex_t mutex;
706 void anv_device_get_cache_uuid(void *uuid);
709 void* anv_gem_mmap(struct anv_device *device,
710 uint32_t gem_handle, uint64_t offset, uint64_t size, uint32_t flags);
711 void anv_gem_munmap(void *p, uint64_t size);
712 uint32_t anv_gem_create(struct anv_device *device, size_t size);
713 void anv_gem_close(struct anv_device *device, uint32_t gem_handle);
714 uint32_t anv_gem_userptr(struct anv_device *device, void *mem, size_t size);
715 int anv_gem_wait(struct anv_device *device, uint32_t gem_handle, int64_t *timeout_ns);
716 int anv_gem_execbuffer(struct anv_device *device,
717 struct drm_i915_gem_execbuffer2 *execbuf);
718 int anv_gem_set_tiling(struct anv_device *device, uint32_t gem_handle,
719 uint32_t stride, uint32_t tiling);
720 int anv_gem_create_context(struct anv_device *device);
721 int anv_gem_destroy_context(struct anv_device *device, int context);
722 int anv_gem_get_param(int fd, uint32_t param);
723 bool anv_gem_get_bit6_swizzle(int fd, uint32_t tiling);
724 int anv_gem_get_aperture(int fd, uint64_t *size);
725 int anv_gem_handle_to_fd(struct anv_device *device, uint32_t gem_handle);
726 uint32_t anv_gem_fd_to_handle(struct anv_device *device, int fd);
727 int anv_gem_set_caching(struct anv_device *device, uint32_t gem_handle, uint32_t caching);
728 int anv_gem_set_domain(struct anv_device *device, uint32_t gem_handle,
729 uint32_t read_domains, uint32_t write_domain);
731 VkResult anv_bo_init_new(struct anv_bo *bo, struct anv_device *device, uint64_t size);
733 struct anv_reloc_list {
736 struct drm_i915_gem_relocation_entry * relocs;
737 struct anv_bo ** reloc_bos;
740 VkResult anv_reloc_list_init(struct anv_reloc_list *list,
741 const VkAllocationCallbacks *alloc);
742 void anv_reloc_list_finish(struct anv_reloc_list *list,
743 const VkAllocationCallbacks *alloc);
745 uint64_t anv_reloc_list_add(struct anv_reloc_list *list,
746 const VkAllocationCallbacks *alloc,
747 uint32_t offset, struct anv_bo *target_bo,
750 struct anv_batch_bo {
751 /* Link in the anv_cmd_buffer.owned_batch_bos list */
752 struct list_head link;
756 /* Bytes actually consumed in this batch BO */
759 /* Last seen surface state block pool bo offset */
760 uint32_t last_ss_pool_bo_offset;
762 struct anv_reloc_list relocs;
766 const VkAllocationCallbacks * alloc;
772 struct anv_reloc_list * relocs;
774 /* This callback is called (with the associated user data) in the event
775 * that the batch runs out of space.
777 VkResult (*extend_cb)(struct anv_batch *, void *);
781 void *anv_batch_emit_dwords(struct anv_batch *batch, int num_dwords);
782 void anv_batch_emit_batch(struct anv_batch *batch, struct anv_batch *other);
783 uint64_t anv_batch_emit_reloc(struct anv_batch *batch,
784 void *location, struct anv_bo *bo, uint32_t offset);
785 VkResult anv_device_submit_simple_batch(struct anv_device *device,
786 struct anv_batch *batch);
793 #define __gen_address_type struct anv_address
794 #define __gen_user_data struct anv_batch
796 static inline uint64_t
797 __gen_combine_address(struct anv_batch *batch, void *location,
798 const struct anv_address address, uint32_t delta)
800 if (address.bo == NULL) {
801 return address.offset + delta;
803 assert(batch->start <= location && location < batch->end);
805 return anv_batch_emit_reloc(batch, location, address.bo, address.offset + delta);
809 /* Wrapper macros needed to work around preprocessor argument issues. In
810 * particular, arguments don't get pre-evaluated if they are concatenated.
811 * This means that, if you pass GENX(3DSTATE_PS) into the emit macro, the
812 * GENX macro won't get evaluated if the emit macro contains "cmd ## foo".
813 * We can work around this easily enough with these helpers.
815 #define __anv_cmd_length(cmd) cmd ## _length
816 #define __anv_cmd_length_bias(cmd) cmd ## _length_bias
817 #define __anv_cmd_header(cmd) cmd ## _header
818 #define __anv_cmd_pack(cmd) cmd ## _pack
819 #define __anv_reg_num(reg) reg ## _num
821 #define anv_pack_struct(dst, struc, ...) do { \
822 struct struc __template = { \
825 __anv_cmd_pack(struc)(NULL, dst, &__template); \
826 VG(VALGRIND_CHECK_MEM_IS_DEFINED(dst, __anv_cmd_length(struc) * 4)); \
829 #define anv_batch_emitn(batch, n, cmd, ...) ({ \
830 void *__dst = anv_batch_emit_dwords(batch, n); \
831 struct cmd __template = { \
832 __anv_cmd_header(cmd), \
833 .DWordLength = n - __anv_cmd_length_bias(cmd), \
836 __anv_cmd_pack(cmd)(batch, __dst, &__template); \
840 #define anv_batch_emit_merge(batch, dwords0, dwords1) \
844 static_assert(ARRAY_SIZE(dwords0) == ARRAY_SIZE(dwords1), "mismatch merge"); \
845 dw = anv_batch_emit_dwords((batch), ARRAY_SIZE(dwords0)); \
846 for (uint32_t i = 0; i < ARRAY_SIZE(dwords0); i++) \
847 dw[i] = (dwords0)[i] | (dwords1)[i]; \
848 VG(VALGRIND_CHECK_MEM_IS_DEFINED(dw, ARRAY_SIZE(dwords0) * 4));\
851 #define anv_batch_emit(batch, cmd, name) \
852 for (struct cmd name = { __anv_cmd_header(cmd) }, \
853 *_dst = anv_batch_emit_dwords(batch, __anv_cmd_length(cmd)); \
854 __builtin_expect(_dst != NULL, 1); \
855 ({ __anv_cmd_pack(cmd)(batch, _dst, &name); \
856 VG(VALGRIND_CHECK_MEM_IS_DEFINED(_dst, __anv_cmd_length(cmd) * 4)); \
860 #define anv_state_pool_emit(pool, cmd, align, ...) ({ \
861 const uint32_t __size = __anv_cmd_length(cmd) * 4; \
862 struct anv_state __state = \
863 anv_state_pool_alloc((pool), __size, align); \
864 struct cmd __template = { \
867 __anv_cmd_pack(cmd)(NULL, __state.map, &__template); \
868 VG(VALGRIND_CHECK_MEM_IS_DEFINED(__state.map, __anv_cmd_length(cmd) * 4)); \
869 if (!(pool)->block_pool->device->info.has_llc) \
870 anv_state_clflush(__state); \
874 #define GEN7_MOCS (struct GEN7_MEMORY_OBJECT_CONTROL_STATE) { \
875 .GraphicsDataTypeGFDT = 0, \
876 .LLCCacheabilityControlLLCCC = 0, \
877 .L3CacheabilityControlL3CC = 1, \
880 #define GEN75_MOCS (struct GEN75_MEMORY_OBJECT_CONTROL_STATE) { \
881 .LLCeLLCCacheabilityControlLLCCC = 0, \
882 .L3CacheabilityControlL3CC = 1, \
885 #define GEN8_MOCS (struct GEN8_MEMORY_OBJECT_CONTROL_STATE) { \
886 .MemoryTypeLLCeLLCCacheabilityControl = WB, \
887 .TargetCache = L3DefertoPATforLLCeLLCselection, \
891 /* Skylake: MOCS is now an index into an array of 62 different caching
892 * configurations programmed by the kernel.
895 #define GEN9_MOCS (struct GEN9_MEMORY_OBJECT_CONTROL_STATE) { \
896 /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */ \
897 .IndextoMOCSTables = 2 \
900 #define GEN9_MOCS_PTE { \
901 /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */ \
902 .IndextoMOCSTables = 1 \
905 struct anv_device_memory {
908 VkDeviceSize map_size;
913 * Header for Vertex URB Entry (VUE)
915 struct anv_vue_header {
917 uint32_t RTAIndex; /* RenderTargetArrayIndex */
918 uint32_t ViewportIndex;
922 struct anv_descriptor_set_binding_layout {
923 /* Number of array elements in this binding */
926 /* Index into the flattend descriptor set */
927 uint16_t descriptor_index;
929 /* Index into the dynamic state array for a dynamic buffer */
930 int16_t dynamic_offset_index;
932 /* Index into the descriptor set buffer views */
933 int16_t buffer_index;
936 /* Index into the binding table for the associated surface */
937 int16_t surface_index;
939 /* Index into the sampler table for the associated sampler */
940 int16_t sampler_index;
942 /* Index into the image table for the associated image */
944 } stage[MESA_SHADER_STAGES];
946 /* Immutable samplers (or NULL if no immutable samplers) */
947 struct anv_sampler **immutable_samplers;
950 struct anv_descriptor_set_layout {
951 /* Number of bindings in this descriptor set */
952 uint16_t binding_count;
954 /* Total size of the descriptor set with room for all array entries */
957 /* Shader stages affected by this descriptor set */
958 uint16_t shader_stages;
960 /* Number of buffers in this descriptor set */
961 uint16_t buffer_count;
963 /* Number of dynamic offsets used by this descriptor set */
964 uint16_t dynamic_offset_count;
966 /* Bindings in this descriptor set */
967 struct anv_descriptor_set_binding_layout binding[0];
970 struct anv_descriptor {
971 VkDescriptorType type;
975 struct anv_image_view *image_view;
976 struct anv_sampler *sampler;
979 struct anv_buffer_view *buffer_view;
983 struct anv_descriptor_set {
984 const struct anv_descriptor_set_layout *layout;
986 uint32_t buffer_count;
987 struct anv_buffer_view *buffer_views;
988 struct anv_descriptor descriptors[0];
991 struct anv_descriptor_pool {
996 struct anv_state_stream surface_state_stream;
997 void *surface_state_free_list;
1003 anv_descriptor_set_create(struct anv_device *device,
1004 struct anv_descriptor_pool *pool,
1005 const struct anv_descriptor_set_layout *layout,
1006 struct anv_descriptor_set **out_set);
1009 anv_descriptor_set_destroy(struct anv_device *device,
1010 struct anv_descriptor_pool *pool,
1011 struct anv_descriptor_set *set);
1013 #define ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS UINT16_MAX
1015 struct anv_pipeline_binding {
1016 /* The descriptor set this surface corresponds to. The special value of
1017 * ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS indicates that the offset refers
1018 * to a color attachment and not a regular descriptor.
1022 /* Offset into the descriptor set or attachment list. */
1026 struct anv_pipeline_layout {
1028 struct anv_descriptor_set_layout *layout;
1029 uint32_t dynamic_offset_start;
1035 bool has_dynamic_offsets;
1036 } stage[MESA_SHADER_STAGES];
1040 struct anv_device * device;
1043 VkBufferUsageFlags usage;
1045 /* Set when bound */
1047 VkDeviceSize offset;
1050 enum anv_cmd_dirty_bits {
1051 ANV_CMD_DIRTY_DYNAMIC_VIEWPORT = 1 << 0, /* VK_DYNAMIC_STATE_VIEWPORT */
1052 ANV_CMD_DIRTY_DYNAMIC_SCISSOR = 1 << 1, /* VK_DYNAMIC_STATE_SCISSOR */
1053 ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH = 1 << 2, /* VK_DYNAMIC_STATE_LINE_WIDTH */
1054 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS = 1 << 3, /* VK_DYNAMIC_STATE_DEPTH_BIAS */
1055 ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS = 1 << 4, /* VK_DYNAMIC_STATE_BLEND_CONSTANTS */
1056 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS = 1 << 5, /* VK_DYNAMIC_STATE_DEPTH_BOUNDS */
1057 ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK = 1 << 6, /* VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK */
1058 ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK = 1 << 7, /* VK_DYNAMIC_STATE_STENCIL_WRITE_MASK */
1059 ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE = 1 << 8, /* VK_DYNAMIC_STATE_STENCIL_REFERENCE */
1060 ANV_CMD_DIRTY_DYNAMIC_ALL = (1 << 9) - 1,
1061 ANV_CMD_DIRTY_PIPELINE = 1 << 9,
1062 ANV_CMD_DIRTY_INDEX_BUFFER = 1 << 10,
1063 ANV_CMD_DIRTY_RENDER_TARGETS = 1 << 11,
1065 typedef uint32_t anv_cmd_dirty_mask_t;
1067 struct anv_vertex_binding {
1068 struct anv_buffer * buffer;
1069 VkDeviceSize offset;
1072 struct anv_push_constants {
1073 /* Current allocated size of this push constants data structure.
1074 * Because a decent chunk of it may not be used (images on SKL, for
1075 * instance), we won't actually allocate the entire structure up-front.
1079 /* Push constant data provided by the client through vkPushConstants */
1080 uint8_t client_data[MAX_PUSH_CONSTANTS_SIZE];
1082 /* Our hardware only provides zero-based vertex and instance id so, in
1083 * order to satisfy the vulkan requirements, we may have to push one or
1084 * both of these into the shader.
1086 uint32_t base_vertex;
1087 uint32_t base_instance;
1089 /* Offsets and ranges for dynamically bound buffers */
1093 } dynamic[MAX_DYNAMIC_BUFFERS];
1095 /* Image data for image_load_store on pre-SKL */
1096 struct brw_image_param images[MAX_IMAGES];
1099 struct anv_dynamic_state {
1102 VkViewport viewports[MAX_VIEWPORTS];
1107 VkRect2D scissors[MAX_SCISSORS];
1118 float blend_constants[4];
1128 } stencil_compare_mask;
1133 } stencil_write_mask;
1138 } stencil_reference;
1141 extern const struct anv_dynamic_state default_dynamic_state;
1143 void anv_dynamic_state_copy(struct anv_dynamic_state *dest,
1144 const struct anv_dynamic_state *src,
1145 uint32_t copy_mask);
1148 * Attachment state when recording a renderpass instance.
1150 * The clear value is valid only if there exists a pending clear.
1152 struct anv_attachment_state {
1153 VkImageAspectFlags pending_clear_aspects;
1154 VkClearValue clear_value;
1157 /** State required while building cmd buffer */
1158 struct anv_cmd_state {
1159 /* PIPELINE_SELECT.PipelineSelection */
1160 uint32_t current_pipeline;
1161 uint32_t current_l3_config;
1163 anv_cmd_dirty_mask_t dirty;
1164 anv_cmd_dirty_mask_t compute_dirty;
1165 uint32_t num_workgroups_offset;
1166 struct anv_bo *num_workgroups_bo;
1167 VkShaderStageFlags descriptors_dirty;
1168 VkShaderStageFlags push_constants_dirty;
1169 uint32_t scratch_size;
1170 struct anv_pipeline * pipeline;
1171 struct anv_pipeline * compute_pipeline;
1172 struct anv_framebuffer * framebuffer;
1173 struct anv_render_pass * pass;
1174 struct anv_subpass * subpass;
1175 uint32_t restart_index;
1176 struct anv_vertex_binding vertex_bindings[MAX_VBS];
1177 struct anv_descriptor_set * descriptors[MAX_SETS];
1178 struct anv_push_constants * push_constants[MESA_SHADER_STAGES];
1179 struct anv_state binding_tables[MESA_SHADER_STAGES];
1180 struct anv_state samplers[MESA_SHADER_STAGES];
1181 struct anv_dynamic_state dynamic;
1185 * Array length is anv_cmd_state::pass::attachment_count. Array content is
1186 * valid only when recording a render pass instance.
1188 struct anv_attachment_state * attachments;
1191 struct anv_buffer * index_buffer;
1192 uint32_t index_type; /**< 3DSTATE_INDEX_BUFFER.IndexFormat */
1193 uint32_t index_offset;
1197 struct anv_cmd_pool {
1198 VkAllocationCallbacks alloc;
1199 struct list_head cmd_buffers;
1202 #define ANV_CMD_BUFFER_BATCH_SIZE 8192
1204 enum anv_cmd_buffer_exec_mode {
1205 ANV_CMD_BUFFER_EXEC_MODE_PRIMARY,
1206 ANV_CMD_BUFFER_EXEC_MODE_EMIT,
1207 ANV_CMD_BUFFER_EXEC_MODE_GROW_AND_EMIT,
1208 ANV_CMD_BUFFER_EXEC_MODE_CHAIN,
1209 ANV_CMD_BUFFER_EXEC_MODE_COPY_AND_CHAIN,
1212 struct anv_cmd_buffer {
1213 VK_LOADER_DATA _loader_data;
1215 struct anv_device * device;
1217 struct anv_cmd_pool * pool;
1218 struct list_head pool_link;
1220 struct anv_batch batch;
1222 /* Fields required for the actual chain of anv_batch_bo's.
1224 * These fields are initialized by anv_cmd_buffer_init_batch_bo_chain().
1226 struct list_head batch_bos;
1227 enum anv_cmd_buffer_exec_mode exec_mode;
1229 /* A vector of anv_batch_bo pointers for every batch or surface buffer
1230 * referenced by this command buffer
1232 * initialized by anv_cmd_buffer_init_batch_bo_chain()
1234 struct anv_vector seen_bbos;
1236 /* A vector of int32_t's for every block of binding tables.
1238 * initialized by anv_cmd_buffer_init_batch_bo_chain()
1240 struct anv_vector bt_blocks;
1242 struct anv_reloc_list surface_relocs;
1244 /* Information needed for execbuf
1246 * These fields are generated by anv_cmd_buffer_prepare_execbuf().
1249 struct drm_i915_gem_execbuffer2 execbuf;
1251 struct drm_i915_gem_exec_object2 * objects;
1253 struct anv_bo ** bos;
1255 /* Allocated length of the 'objects' and 'bos' arrays */
1256 uint32_t array_length;
1261 /* Serial for tracking buffer completion */
1264 /* Stream objects for storing temporary data */
1265 struct anv_state_stream surface_state_stream;
1266 struct anv_state_stream dynamic_state_stream;
1268 VkCommandBufferUsageFlags usage_flags;
1269 VkCommandBufferLevel level;
1271 struct anv_cmd_state state;
1274 VkResult anv_cmd_buffer_init_batch_bo_chain(struct anv_cmd_buffer *cmd_buffer);
1275 void anv_cmd_buffer_fini_batch_bo_chain(struct anv_cmd_buffer *cmd_buffer);
1276 void anv_cmd_buffer_reset_batch_bo_chain(struct anv_cmd_buffer *cmd_buffer);
1277 void anv_cmd_buffer_end_batch_buffer(struct anv_cmd_buffer *cmd_buffer);
1278 void anv_cmd_buffer_add_secondary(struct anv_cmd_buffer *primary,
1279 struct anv_cmd_buffer *secondary);
1280 void anv_cmd_buffer_prepare_execbuf(struct anv_cmd_buffer *cmd_buffer);
1282 VkResult anv_cmd_buffer_emit_binding_table(struct anv_cmd_buffer *cmd_buffer,
1283 unsigned stage, struct anv_state *bt_state);
1284 VkResult anv_cmd_buffer_emit_samplers(struct anv_cmd_buffer *cmd_buffer,
1285 unsigned stage, struct anv_state *state);
1286 uint32_t gen7_cmd_buffer_flush_descriptor_sets(struct anv_cmd_buffer *cmd_buffer);
1287 void gen7_cmd_buffer_emit_descriptor_pointers(struct anv_cmd_buffer *cmd_buffer,
1290 struct anv_state anv_cmd_buffer_emit_dynamic(struct anv_cmd_buffer *cmd_buffer,
1291 const void *data, uint32_t size, uint32_t alignment);
1292 struct anv_state anv_cmd_buffer_merge_dynamic(struct anv_cmd_buffer *cmd_buffer,
1293 uint32_t *a, uint32_t *b,
1294 uint32_t dwords, uint32_t alignment);
1297 anv_cmd_buffer_surface_base_address(struct anv_cmd_buffer *cmd_buffer);
1299 anv_cmd_buffer_alloc_binding_table(struct anv_cmd_buffer *cmd_buffer,
1300 uint32_t entries, uint32_t *state_offset);
1302 anv_cmd_buffer_alloc_surface_state(struct anv_cmd_buffer *cmd_buffer);
1304 anv_cmd_buffer_alloc_dynamic_state(struct anv_cmd_buffer *cmd_buffer,
1305 uint32_t size, uint32_t alignment);
1308 anv_cmd_buffer_new_binding_table_block(struct anv_cmd_buffer *cmd_buffer);
1310 void gen8_cmd_buffer_emit_viewport(struct anv_cmd_buffer *cmd_buffer);
1311 void gen7_cmd_buffer_emit_scissor(struct anv_cmd_buffer *cmd_buffer);
1313 void anv_cmd_buffer_emit_state_base_address(struct anv_cmd_buffer *cmd_buffer);
1315 void anv_cmd_state_setup_attachments(struct anv_cmd_buffer *cmd_buffer,
1316 const VkRenderPassBeginInfo *info);
1318 void anv_cmd_buffer_set_subpass(struct anv_cmd_buffer *cmd_buffer,
1319 struct anv_subpass *subpass);
1322 anv_cmd_buffer_push_constants(struct anv_cmd_buffer *cmd_buffer,
1323 gl_shader_stage stage);
1325 anv_cmd_buffer_cs_push_constants(struct anv_cmd_buffer *cmd_buffer);
1327 void anv_cmd_buffer_clear_subpass(struct anv_cmd_buffer *cmd_buffer);
1328 void anv_cmd_buffer_resolve_subpass(struct anv_cmd_buffer *cmd_buffer);
1330 const struct anv_image_view *
1331 anv_cmd_buffer_get_depth_stencil_view(const struct anv_cmd_buffer *cmd_buffer);
1333 void anv_cmd_buffer_dump(struct anv_cmd_buffer *cmd_buffer);
1337 struct drm_i915_gem_execbuffer2 execbuf;
1338 struct drm_i915_gem_exec_object2 exec2_objects[1];
1344 struct anv_state state;
1349 struct anv_shader_module {
1350 struct nir_shader * nir;
1352 unsigned char sha1[20];
1357 void anv_hash_shader(unsigned char *hash, const void *key, size_t key_size,
1358 struct anv_shader_module *module,
1359 const char *entrypoint,
1360 const VkSpecializationInfo *spec_info);
1362 static inline gl_shader_stage
1363 vk_to_mesa_shader_stage(VkShaderStageFlagBits vk_stage)
1365 assert(__builtin_popcount(vk_stage) == 1);
1366 return ffs(vk_stage) - 1;
1369 static inline VkShaderStageFlagBits
1370 mesa_to_vk_shader_stage(gl_shader_stage mesa_stage)
1372 return (1 << mesa_stage);
1375 #define ANV_STAGE_MASK ((1 << MESA_SHADER_STAGES) - 1)
1377 #define anv_foreach_stage(stage, stage_bits) \
1378 for (gl_shader_stage stage, \
1379 __tmp = (gl_shader_stage)((stage_bits) & ANV_STAGE_MASK); \
1380 stage = __builtin_ffs(__tmp) - 1, __tmp; \
1381 __tmp &= ~(1 << (stage)))
1383 struct anv_pipeline_bind_map {
1384 uint32_t surface_count;
1385 uint32_t sampler_count;
1386 uint32_t image_count;
1387 uint32_t attachment_count;
1389 struct anv_pipeline_binding * surface_to_descriptor;
1390 struct anv_pipeline_binding * sampler_to_descriptor;
1391 uint32_t * surface_to_attachment;
1394 struct anv_pipeline {
1395 struct anv_device * device;
1396 struct anv_batch batch;
1397 uint32_t batch_data[512];
1398 struct anv_reloc_list batch_relocs;
1399 uint32_t dynamic_state_mask;
1400 struct anv_dynamic_state dynamic_state;
1402 struct anv_pipeline_layout * layout;
1403 struct anv_pipeline_bind_map bindings[MESA_SHADER_STAGES];
1407 const struct brw_stage_prog_data * prog_data[MESA_SHADER_STAGES];
1408 uint32_t scratch_start[MESA_SHADER_STAGES];
1409 uint32_t total_scratch;
1411 uint8_t push_size[MESA_SHADER_FRAGMENT + 1];
1412 uint32_t start[MESA_SHADER_GEOMETRY + 1];
1413 uint32_t size[MESA_SHADER_GEOMETRY + 1];
1414 uint32_t entries[MESA_SHADER_GEOMETRY + 1];
1417 VkShaderStageFlags active_stages;
1418 struct anv_state blend_state;
1426 uint32_t binding_stride[MAX_VBS];
1427 bool instancing_enable[MAX_VBS];
1428 bool primitive_restart;
1431 uint32_t cs_thread_width_max;
1432 uint32_t cs_right_mask;
1436 uint32_t depth_stencil_state[3];
1442 uint32_t wm_depth_stencil[3];
1446 uint32_t wm_depth_stencil[4];
1450 static inline const struct brw_vs_prog_data *
1451 get_vs_prog_data(struct anv_pipeline *pipeline)
1453 return (const struct brw_vs_prog_data *) pipeline->prog_data[MESA_SHADER_VERTEX];
1456 static inline const struct brw_gs_prog_data *
1457 get_gs_prog_data(struct anv_pipeline *pipeline)
1459 return (const struct brw_gs_prog_data *) pipeline->prog_data[MESA_SHADER_GEOMETRY];
1462 static inline const struct brw_wm_prog_data *
1463 get_wm_prog_data(struct anv_pipeline *pipeline)
1465 return (const struct brw_wm_prog_data *) pipeline->prog_data[MESA_SHADER_FRAGMENT];
1468 static inline const struct brw_cs_prog_data *
1469 get_cs_prog_data(struct anv_pipeline *pipeline)
1471 return (const struct brw_cs_prog_data *) pipeline->prog_data[MESA_SHADER_COMPUTE];
1474 struct anv_graphics_pipeline_create_info {
1476 * If non-negative, overrides the color attachment count of the pipeline's
1479 int8_t color_attachment_count;
1487 anv_pipeline_init(struct anv_pipeline *pipeline, struct anv_device *device,
1488 struct anv_pipeline_cache *cache,
1489 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1490 const struct anv_graphics_pipeline_create_info *extra,
1491 const VkAllocationCallbacks *alloc);
1494 anv_pipeline_compile_cs(struct anv_pipeline *pipeline,
1495 struct anv_pipeline_cache *cache,
1496 const VkComputePipelineCreateInfo *info,
1497 struct anv_shader_module *module,
1498 const char *entrypoint,
1499 const VkSpecializationInfo *spec_info);
1502 anv_graphics_pipeline_create(VkDevice device,
1503 VkPipelineCache cache,
1504 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1505 const struct anv_graphics_pipeline_create_info *extra,
1506 const VkAllocationCallbacks *alloc,
1507 VkPipeline *pPipeline);
1509 struct anv_format_swizzle {
1517 const VkFormat vk_format;
1519 enum isl_format isl_format; /**< RENDER_SURFACE_STATE.SurfaceFormat */
1520 const struct isl_format_layout *isl_layout;
1521 struct anv_format_swizzle swizzle;
1526 const struct anv_format *
1527 anv_format_for_vk_format(VkFormat format);
1530 anv_get_isl_format(VkFormat format, VkImageAspectFlags aspect,
1531 VkImageTiling tiling, struct anv_format_swizzle *swizzle);
1534 anv_format_is_color(const struct anv_format *format)
1536 return !format->has_depth && !format->has_stencil;
1540 anv_format_is_depth_or_stencil(const struct anv_format *format)
1542 return format->has_depth || format->has_stencil;
1546 * Subsurface of an anv_image.
1548 struct anv_surface {
1549 struct isl_surf isl;
1552 * Offset from VkImage's base address, as bound by vkBindImageMemory().
1559 /* The original VkFormat provided by the client. This may not match any
1560 * of the actual surface formats.
1563 const struct anv_format *format;
1566 uint32_t array_size;
1567 uint32_t samples; /**< VkImageCreateInfo::samples */
1568 VkImageUsageFlags usage; /**< Superset of VkImageCreateInfo::usage. */
1569 VkImageTiling tiling; /** VkImageCreateInfo::tiling */
1574 /* Set when bound */
1576 VkDeviceSize offset;
1581 * For each foo, anv_image::foo_surface is valid if and only if
1582 * anv_image::format has a foo aspect.
1584 * The hardware requires that the depth buffer and stencil buffer be
1585 * separate surfaces. From Vulkan's perspective, though, depth and stencil
1586 * reside in the same VkImage. To satisfy both the hardware and Vulkan, we
1587 * allocate the depth and stencil buffers as separate surfaces in the same
1591 struct anv_surface color_surface;
1594 struct anv_surface depth_surface;
1595 struct anv_surface stencil_surface;
1600 static inline uint32_t
1601 anv_get_layerCount(const struct anv_image *image,
1602 const VkImageSubresourceRange *range)
1604 return range->layerCount == VK_REMAINING_ARRAY_LAYERS ?
1605 image->array_size - range->baseArrayLayer : range->layerCount;
1608 static inline uint32_t
1609 anv_get_levelCount(const struct anv_image *image,
1610 const VkImageSubresourceRange *range)
1612 return range->levelCount == VK_REMAINING_MIP_LEVELS ?
1613 image->levels - range->baseMipLevel : range->levelCount;
1617 struct anv_image_view {
1618 const struct anv_image *image; /**< VkImageViewCreateInfo::image */
1620 uint32_t offset; /**< Offset into bo. */
1622 VkImageAspectFlags aspect_mask;
1624 uint32_t base_layer;
1626 VkExtent3D extent; /**< Extent of VkImageViewCreateInfo::baseMipLevel. */
1628 /** RENDER_SURFACE_STATE when using image as a color render target. */
1629 struct anv_state color_rt_surface_state;
1631 /** RENDER_SURFACE_STATE when using image as a sampler surface. */
1632 struct anv_state sampler_surface_state;
1634 /** RENDER_SURFACE_STATE when using image as a storage image. */
1635 struct anv_state storage_surface_state;
1637 struct brw_image_param storage_image_param;
1640 struct anv_image_create_info {
1641 const VkImageCreateInfo *vk_info;
1642 isl_tiling_flags_t isl_tiling_flags;
1646 VkResult anv_image_create(VkDevice _device,
1647 const struct anv_image_create_info *info,
1648 const VkAllocationCallbacks* alloc,
1651 struct anv_surface *
1652 anv_image_get_surface_for_aspect_mask(struct anv_image *image,
1653 VkImageAspectFlags aspect_mask);
1655 void anv_image_view_init(struct anv_image_view *view,
1656 struct anv_device *device,
1657 const VkImageViewCreateInfo* pCreateInfo,
1658 struct anv_cmd_buffer *cmd_buffer,
1659 VkImageUsageFlags usage_mask);
1661 struct anv_buffer_view {
1662 enum isl_format format; /**< VkBufferViewCreateInfo::format */
1664 uint32_t offset; /**< Offset into bo. */
1665 uint64_t range; /**< VkBufferViewCreateInfo::range */
1667 struct anv_state surface_state;
1668 struct anv_state storage_surface_state;
1670 struct brw_image_param storage_image_param;
1673 void anv_buffer_view_init(struct anv_buffer_view *view,
1674 struct anv_device *device,
1675 const VkBufferViewCreateInfo* pCreateInfo,
1676 struct anv_cmd_buffer *cmd_buffer);
1678 const struct anv_format *
1679 anv_format_for_descriptor_type(VkDescriptorType type);
1681 static inline struct VkExtent3D
1682 anv_sanitize_image_extent(const VkImageType imageType,
1683 const struct VkExtent3D imageExtent)
1685 switch (imageType) {
1686 case VK_IMAGE_TYPE_1D:
1687 return (VkExtent3D) { imageExtent.width, 1, 1 };
1688 case VK_IMAGE_TYPE_2D:
1689 return (VkExtent3D) { imageExtent.width, imageExtent.height, 1 };
1690 case VK_IMAGE_TYPE_3D:
1693 unreachable("invalid image type");
1697 static inline struct VkOffset3D
1698 anv_sanitize_image_offset(const VkImageType imageType,
1699 const struct VkOffset3D imageOffset)
1701 switch (imageType) {
1702 case VK_IMAGE_TYPE_1D:
1703 return (VkOffset3D) { imageOffset.x, 0, 0 };
1704 case VK_IMAGE_TYPE_2D:
1705 return (VkOffset3D) { imageOffset.x, imageOffset.y, 0 };
1706 case VK_IMAGE_TYPE_3D:
1709 unreachable("invalid image type");
1714 void anv_fill_buffer_surface_state(struct anv_device *device,
1715 struct anv_state state,
1716 enum isl_format format,
1717 uint32_t offset, uint32_t range,
1720 void anv_image_view_fill_image_param(struct anv_device *device,
1721 struct anv_image_view *view,
1722 struct brw_image_param *param);
1723 void anv_buffer_view_fill_image_param(struct anv_device *device,
1724 struct anv_buffer_view *view,
1725 struct brw_image_param *param);
1727 struct anv_sampler {
1731 struct anv_framebuffer {
1736 uint32_t attachment_count;
1737 struct anv_image_view * attachments[0];
1740 struct anv_subpass {
1741 uint32_t input_count;
1742 uint32_t * input_attachments;
1743 uint32_t color_count;
1744 uint32_t * color_attachments;
1745 uint32_t * resolve_attachments;
1746 uint32_t depth_stencil_attachment;
1748 /** Subpass has at least one resolve attachment */
1752 struct anv_render_pass_attachment {
1753 const struct anv_format *format;
1755 VkAttachmentLoadOp load_op;
1756 VkAttachmentLoadOp stencil_load_op;
1759 struct anv_render_pass {
1760 uint32_t attachment_count;
1761 uint32_t subpass_count;
1762 uint32_t * subpass_attachments;
1763 struct anv_render_pass_attachment * attachments;
1764 struct anv_subpass subpasses[0];
1767 extern struct anv_render_pass anv_meta_dummy_renderpass;
1769 struct anv_query_pool_slot {
1775 struct anv_query_pool {
1781 VkResult anv_device_init_meta(struct anv_device *device);
1782 void anv_device_finish_meta(struct anv_device *device);
1784 void *anv_lookup_entrypoint(const char *name);
1786 void anv_dump_image_to_ppm(struct anv_device *device,
1787 struct anv_image *image, unsigned miplevel,
1788 unsigned array_layer, const char *filename);
1790 #define ANV_DEFINE_HANDLE_CASTS(__anv_type, __VkType) \
1792 static inline struct __anv_type * \
1793 __anv_type ## _from_handle(__VkType _handle) \
1795 return (struct __anv_type *) _handle; \
1798 static inline __VkType \
1799 __anv_type ## _to_handle(struct __anv_type *_obj) \
1801 return (__VkType) _obj; \
1804 #define ANV_DEFINE_NONDISP_HANDLE_CASTS(__anv_type, __VkType) \
1806 static inline struct __anv_type * \
1807 __anv_type ## _from_handle(__VkType _handle) \
1809 return (struct __anv_type *)(uintptr_t) _handle; \
1812 static inline __VkType \
1813 __anv_type ## _to_handle(struct __anv_type *_obj) \
1815 return (__VkType)(uintptr_t) _obj; \
1818 #define ANV_FROM_HANDLE(__anv_type, __name, __handle) \
1819 struct __anv_type *__name = __anv_type ## _from_handle(__handle)
1821 ANV_DEFINE_HANDLE_CASTS(anv_cmd_buffer, VkCommandBuffer)
1822 ANV_DEFINE_HANDLE_CASTS(anv_device, VkDevice)
1823 ANV_DEFINE_HANDLE_CASTS(anv_instance, VkInstance)
1824 ANV_DEFINE_HANDLE_CASTS(anv_physical_device, VkPhysicalDevice)
1825 ANV_DEFINE_HANDLE_CASTS(anv_queue, VkQueue)
1827 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_cmd_pool, VkCommandPool)
1828 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_buffer, VkBuffer)
1829 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_buffer_view, VkBufferView)
1830 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_pool, VkDescriptorPool)
1831 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_set, VkDescriptorSet)
1832 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_set_layout, VkDescriptorSetLayout)
1833 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_device_memory, VkDeviceMemory)
1834 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_fence, VkFence)
1835 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_event, VkEvent)
1836 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_framebuffer, VkFramebuffer)
1837 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_image, VkImage)
1838 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_image_view, VkImageView);
1839 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_pipeline_cache, VkPipelineCache)
1840 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_pipeline, VkPipeline)
1841 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_pipeline_layout, VkPipelineLayout)
1842 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_query_pool, VkQueryPool)
1843 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_render_pass, VkRenderPass)
1844 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_sampler, VkSampler)
1845 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_shader_module, VkShaderModule)
1847 #define ANV_DEFINE_STRUCT_CASTS(__anv_type, __VkType) \
1849 static inline const __VkType * \
1850 __anv_type ## _to_ ## __VkType(const struct __anv_type *__anv_obj) \
1852 return (const __VkType *) __anv_obj; \
1855 #define ANV_COMMON_TO_STRUCT(__VkType, __vk_name, __common_name) \
1856 const __VkType *__vk_name = anv_common_to_ ## __VkType(__common_name)
1858 ANV_DEFINE_STRUCT_CASTS(anv_common, VkMemoryBarrier)
1859 ANV_DEFINE_STRUCT_CASTS(anv_common, VkBufferMemoryBarrier)
1860 ANV_DEFINE_STRUCT_CASTS(anv_common, VkImageMemoryBarrier)
1862 /* Gen-specific function declarations */
1864 # include "anv_genX.h"
1866 # define genX(x) gen7_##x
1867 # include "anv_genX.h"
1869 # define genX(x) gen75_##x
1870 # include "anv_genX.h"
1872 # define genX(x) gen8_##x
1873 # include "anv_genX.h"
1875 # define genX(x) gen9_##x
1876 # include "anv_genX.h"