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30 #include "anv_private.h"
32 #include "genxml/gen_macros.h"
33 #include "genxml/genX_pack.h"
36 clamp_int64(int64_t x, int64_t min, int64_t max)
46 #if GEN_GEN == 7 && !GEN_IS_HASWELL
48 gen7_cmd_buffer_emit_scissor(struct anv_cmd_buffer *cmd_buffer)
50 uint32_t count = cmd_buffer->state.dynamic.scissor.count;
51 const VkRect2D *scissors = cmd_buffer->state.dynamic.scissor.scissors;
52 struct anv_state scissor_state =
53 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer, count * 8, 32);
55 for (uint32_t i = 0; i < count; i++) {
56 const VkRect2D *s = &scissors[i];
58 /* Since xmax and ymax are inclusive, we have to have xmax < xmin or
59 * ymax < ymin for empty clips. In case clip x, y, width height are all
60 * 0, the clamps below produce 0 for xmin, ymin, xmax, ymax, which isn't
61 * what we want. Just special case empty clips and produce a canonical
63 static const struct GEN7_SCISSOR_RECT empty_scissor = {
64 .ScissorRectangleYMin = 1,
65 .ScissorRectangleXMin = 1,
66 .ScissorRectangleYMax = 0,
67 .ScissorRectangleXMax = 0
70 const int max = 0xffff;
71 struct GEN7_SCISSOR_RECT scissor = {
72 /* Do this math using int64_t so overflow gets clamped correctly. */
73 .ScissorRectangleYMin = clamp_int64(s->offset.y, 0, max),
74 .ScissorRectangleXMin = clamp_int64(s->offset.x, 0, max),
75 .ScissorRectangleYMax = clamp_int64((uint64_t) s->offset.y + s->extent.height - 1, 0, max),
76 .ScissorRectangleXMax = clamp_int64((uint64_t) s->offset.x + s->extent.width - 1, 0, max)
79 if (s->extent.width <= 0 || s->extent.height <= 0) {
80 GEN7_SCISSOR_RECT_pack(NULL, scissor_state.map + i * 8,
83 GEN7_SCISSOR_RECT_pack(NULL, scissor_state.map + i * 8, &scissor);
87 anv_batch_emit(&cmd_buffer->batch,
88 GEN7_3DSTATE_SCISSOR_STATE_POINTERS, ssp) {
89 ssp.ScissorRectPointer = scissor_state.offset;
92 if (!cmd_buffer->device->info.has_llc)
93 anv_state_clflush(scissor_state);
97 static const uint32_t vk_to_gen_index_type[] = {
98 [VK_INDEX_TYPE_UINT16] = INDEX_WORD,
99 [VK_INDEX_TYPE_UINT32] = INDEX_DWORD,
102 static const uint32_t restart_index_for_type[] = {
103 [VK_INDEX_TYPE_UINT16] = UINT16_MAX,
104 [VK_INDEX_TYPE_UINT32] = UINT32_MAX,
107 void genX(CmdBindIndexBuffer)(
108 VkCommandBuffer commandBuffer,
111 VkIndexType indexType)
113 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
114 ANV_FROM_HANDLE(anv_buffer, buffer, _buffer);
116 cmd_buffer->state.dirty |= ANV_CMD_DIRTY_INDEX_BUFFER;
118 cmd_buffer->state.restart_index = restart_index_for_type[indexType];
119 cmd_buffer->state.gen7.index_buffer = buffer;
120 cmd_buffer->state.gen7.index_type = vk_to_gen_index_type[indexType];
121 cmd_buffer->state.gen7.index_offset = offset;
125 flush_compute_descriptor_set(struct anv_cmd_buffer *cmd_buffer)
127 struct anv_device *device = cmd_buffer->device;
128 struct anv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
129 struct anv_state surfaces = { 0, }, samplers = { 0, };
132 result = anv_cmd_buffer_emit_samplers(cmd_buffer,
133 MESA_SHADER_COMPUTE, &samplers);
134 if (result != VK_SUCCESS)
136 result = anv_cmd_buffer_emit_binding_table(cmd_buffer,
137 MESA_SHADER_COMPUTE, &surfaces);
138 if (result != VK_SUCCESS)
141 struct anv_state push_state = anv_cmd_buffer_cs_push_constants(cmd_buffer);
143 const struct brw_cs_prog_data *cs_prog_data = get_cs_prog_data(pipeline);
144 const struct brw_stage_prog_data *prog_data = &cs_prog_data->base;
146 if (push_state.alloc_size) {
147 anv_batch_emit(&cmd_buffer->batch, GENX(MEDIA_CURBE_LOAD), curbe) {
148 curbe.CURBETotalDataLength = push_state.alloc_size;
149 curbe.CURBEDataStartAddress = push_state.offset;
153 const uint32_t slm_size = encode_slm_size(GEN_GEN, prog_data->total_shared);
155 struct anv_state state =
156 anv_state_pool_emit(&device->dynamic_state_pool,
157 GENX(INTERFACE_DESCRIPTOR_DATA), 64,
158 .KernelStartPointer = pipeline->cs_simd,
159 .BindingTablePointer = surfaces.offset,
160 .SamplerStatePointer = samplers.offset,
161 .ConstantURBEntryReadLength =
162 cs_prog_data->push.per_thread.regs,
164 .CrossThreadConstantDataReadLength =
165 cs_prog_data->push.cross_thread.regs,
167 .ConstantURBEntryReadOffset = 0,
169 .BarrierEnable = cs_prog_data->uses_barrier,
170 .SharedLocalMemorySize = slm_size,
171 .NumberofThreadsinGPGPUThreadGroup =
172 cs_prog_data->threads);
174 const uint32_t size = GENX(INTERFACE_DESCRIPTOR_DATA_length) * sizeof(uint32_t);
175 anv_batch_emit(&cmd_buffer->batch,
176 GENX(MEDIA_INTERFACE_DESCRIPTOR_LOAD), idl) {
177 idl.InterfaceDescriptorTotalLength = size;
178 idl.InterfaceDescriptorDataStartAddress = state.offset;
185 genX(cmd_buffer_flush_compute_state)(struct anv_cmd_buffer *cmd_buffer)
187 struct anv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
188 MAYBE_UNUSED VkResult result;
190 assert(pipeline->active_stages == VK_SHADER_STAGE_COMPUTE_BIT);
192 genX(cmd_buffer_config_l3)(cmd_buffer, pipeline);
194 genX(flush_pipeline_select_gpgpu)(cmd_buffer);
196 if (cmd_buffer->state.compute_dirty & ANV_CMD_DIRTY_PIPELINE)
197 anv_batch_emit_batch(&cmd_buffer->batch, &pipeline->batch);
199 if ((cmd_buffer->state.descriptors_dirty & VK_SHADER_STAGE_COMPUTE_BIT) ||
200 (cmd_buffer->state.compute_dirty & ANV_CMD_DIRTY_PIPELINE)) {
201 /* FIXME: figure out descriptors for gen7 */
202 result = flush_compute_descriptor_set(cmd_buffer);
203 assert(result == VK_SUCCESS);
204 cmd_buffer->state.descriptors_dirty &= ~VK_SHADER_STAGE_COMPUTE_BIT;
207 cmd_buffer->state.compute_dirty = 0;
209 genX(cmd_buffer_apply_pipe_flushes)(cmd_buffer);
213 genX(cmd_buffer_flush_dynamic_state)(struct anv_cmd_buffer *cmd_buffer)
215 struct anv_pipeline *pipeline = cmd_buffer->state.pipeline;
217 if (cmd_buffer->state.dirty & (ANV_CMD_DIRTY_PIPELINE |
218 ANV_CMD_DIRTY_RENDER_TARGETS |
219 ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH |
220 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS)) {
222 const struct anv_image_view *iview =
223 anv_cmd_buffer_get_depth_stencil_view(cmd_buffer);
224 const struct anv_image *image = iview ? iview->image : NULL;
225 const bool has_depth =
226 image && (image->aspects & VK_IMAGE_ASPECT_DEPTH_BIT);
227 const uint32_t depth_format = has_depth ?
228 isl_surf_get_depth_format(&cmd_buffer->device->isl_dev,
229 &image->depth_surface.isl) : D16_UNORM;
231 uint32_t sf_dw[GENX(3DSTATE_SF_length)];
232 struct GENX(3DSTATE_SF) sf = {
233 GENX(3DSTATE_SF_header),
234 .DepthBufferSurfaceFormat = depth_format,
235 .LineWidth = cmd_buffer->state.dynamic.line_width,
236 .GlobalDepthOffsetConstant = cmd_buffer->state.dynamic.depth_bias.bias,
237 .GlobalDepthOffsetScale = cmd_buffer->state.dynamic.depth_bias.slope,
238 .GlobalDepthOffsetClamp = cmd_buffer->state.dynamic.depth_bias.clamp
240 GENX(3DSTATE_SF_pack)(NULL, sf_dw, &sf);
242 anv_batch_emit_merge(&cmd_buffer->batch, sf_dw, pipeline->gen7.sf);
245 if (cmd_buffer->state.dirty & (ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS |
246 ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE)) {
247 struct anv_dynamic_state *d = &cmd_buffer->state.dynamic;
248 struct anv_state cc_state =
249 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer,
250 GENX(COLOR_CALC_STATE_length) * 4,
252 struct GENX(COLOR_CALC_STATE) cc = {
253 .BlendConstantColorRed = cmd_buffer->state.dynamic.blend_constants[0],
254 .BlendConstantColorGreen = cmd_buffer->state.dynamic.blend_constants[1],
255 .BlendConstantColorBlue = cmd_buffer->state.dynamic.blend_constants[2],
256 .BlendConstantColorAlpha = cmd_buffer->state.dynamic.blend_constants[3],
257 .StencilReferenceValue = d->stencil_reference.front & 0xff,
258 .BackfaceStencilReferenceValue = d->stencil_reference.back & 0xff,
260 GENX(COLOR_CALC_STATE_pack)(NULL, cc_state.map, &cc);
261 if (!cmd_buffer->device->info.has_llc)
262 anv_state_clflush(cc_state);
264 anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_CC_STATE_POINTERS), ccp) {
265 ccp.ColorCalcStatePointer = cc_state.offset;
269 if (cmd_buffer->state.dirty & (ANV_CMD_DIRTY_PIPELINE |
270 ANV_CMD_DIRTY_RENDER_TARGETS |
271 ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK |
272 ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK)) {
273 uint32_t depth_stencil_dw[GENX(DEPTH_STENCIL_STATE_length)];
274 struct anv_dynamic_state *d = &cmd_buffer->state.dynamic;
276 struct GENX(DEPTH_STENCIL_STATE) depth_stencil = {
277 .StencilTestMask = d->stencil_compare_mask.front & 0xff,
278 .StencilWriteMask = d->stencil_write_mask.front & 0xff,
280 .BackfaceStencilTestMask = d->stencil_compare_mask.back & 0xff,
281 .BackfaceStencilWriteMask = d->stencil_write_mask.back & 0xff,
283 GENX(DEPTH_STENCIL_STATE_pack)(NULL, depth_stencil_dw, &depth_stencil);
285 struct anv_state ds_state =
286 anv_cmd_buffer_merge_dynamic(cmd_buffer, depth_stencil_dw,
287 pipeline->gen7.depth_stencil_state,
288 GENX(DEPTH_STENCIL_STATE_length), 64);
290 anv_batch_emit(&cmd_buffer->batch,
291 GENX(3DSTATE_DEPTH_STENCIL_STATE_POINTERS), dsp) {
292 dsp.PointertoDEPTH_STENCIL_STATE = ds_state.offset;
296 if (cmd_buffer->state.gen7.index_buffer &&
297 cmd_buffer->state.dirty & (ANV_CMD_DIRTY_PIPELINE |
298 ANV_CMD_DIRTY_INDEX_BUFFER)) {
299 struct anv_buffer *buffer = cmd_buffer->state.gen7.index_buffer;
300 uint32_t offset = cmd_buffer->state.gen7.index_offset;
303 anv_batch_emit(&cmd_buffer->batch, GEN75_3DSTATE_VF, vf) {
304 vf.IndexedDrawCutIndexEnable = pipeline->primitive_restart;
305 vf.CutIndex = cmd_buffer->state.restart_index;
309 anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_INDEX_BUFFER), ib) {
311 ib.CutIndexEnable = pipeline->primitive_restart;
313 ib.IndexFormat = cmd_buffer->state.gen7.index_type;
314 ib.MemoryObjectControlState = GENX(MOCS);
316 ib.BufferStartingAddress =
317 (struct anv_address) { buffer->bo, buffer->offset + offset };
318 ib.BufferEndingAddress =
319 (struct anv_address) { buffer->bo, buffer->offset + buffer->size };
323 cmd_buffer->state.dirty = 0;
326 void genX(CmdSetEvent)(
327 VkCommandBuffer commandBuffer,
329 VkPipelineStageFlags stageMask)
334 void genX(CmdResetEvent)(
335 VkCommandBuffer commandBuffer,
337 VkPipelineStageFlags stageMask)
342 void genX(CmdWaitEvents)(
343 VkCommandBuffer commandBuffer,
345 const VkEvent* pEvents,
346 VkPipelineStageFlags srcStageMask,
347 VkPipelineStageFlags destStageMask,
348 uint32_t memoryBarrierCount,
349 const VkMemoryBarrier* pMemoryBarriers,
350 uint32_t bufferMemoryBarrierCount,
351 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
352 uint32_t imageMemoryBarrierCount,
353 const VkImageMemoryBarrier* pImageMemoryBarriers)
357 genX(CmdPipelineBarrier)(commandBuffer, srcStageMask, destStageMask,
358 false, /* byRegion */
359 memoryBarrierCount, pMemoryBarriers,
360 bufferMemoryBarrierCount, pBufferMemoryBarriers,
361 imageMemoryBarrierCount, pImageMemoryBarriers);