2 * Copyright © 2015 Intel Corporation
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5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
30 #include "anv_private.h"
31 #include "vk_format_info.h"
33 #include "genxml/gen_macros.h"
34 #include "genxml/genX_pack.h"
36 #if GEN_GEN == 7 && !GEN_IS_HASWELL
38 clamp_int64(int64_t x, int64_t min, int64_t max)
49 gen7_cmd_buffer_emit_scissor(struct anv_cmd_buffer *cmd_buffer)
51 struct anv_framebuffer *fb = cmd_buffer->state.framebuffer;
52 uint32_t count = cmd_buffer->state.gfx.dynamic.scissor.count;
53 const VkRect2D *scissors = cmd_buffer->state.gfx.dynamic.scissor.scissors;
54 struct anv_state scissor_state =
55 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer, count * 8, 32);
57 for (uint32_t i = 0; i < count; i++) {
58 const VkRect2D *s = &scissors[i];
60 /* Since xmax and ymax are inclusive, we have to have xmax < xmin or
61 * ymax < ymin for empty clips. In case clip x, y, width height are all
62 * 0, the clamps below produce 0 for xmin, ymin, xmax, ymax, which isn't
63 * what we want. Just special case empty clips and produce a canonical
65 static const struct GEN7_SCISSOR_RECT empty_scissor = {
66 .ScissorRectangleYMin = 1,
67 .ScissorRectangleXMin = 1,
68 .ScissorRectangleYMax = 0,
69 .ScissorRectangleXMax = 0
72 const int max = 0xffff;
74 uint32_t y_min = s->offset.y;
75 uint32_t x_min = s->offset.x;
76 uint32_t y_max = s->offset.y + s->extent.height - 1;
77 uint32_t x_max = s->offset.x + s->extent.width - 1;
79 /* Do this math using int64_t so overflow gets clamped correctly. */
80 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY) {
81 y_min = clamp_int64((uint64_t) y_min,
82 cmd_buffer->state.render_area.offset.y, max);
83 x_min = clamp_int64((uint64_t) x_min,
84 cmd_buffer->state.render_area.offset.x, max);
85 y_max = clamp_int64((uint64_t) y_max, 0,
86 cmd_buffer->state.render_area.offset.y +
87 cmd_buffer->state.render_area.extent.height - 1);
88 x_max = clamp_int64((uint64_t) x_max, 0,
89 cmd_buffer->state.render_area.offset.x +
90 cmd_buffer->state.render_area.extent.width - 1);
92 y_min = clamp_int64((uint64_t) y_min, 0, max);
93 x_min = clamp_int64((uint64_t) x_min, 0, max);
94 y_max = clamp_int64((uint64_t) y_max, 0, fb->height - 1);
95 x_max = clamp_int64((uint64_t) x_max, 0, fb->width - 1);
98 struct GEN7_SCISSOR_RECT scissor = {
99 .ScissorRectangleYMin = y_min,
100 .ScissorRectangleXMin = x_min,
101 .ScissorRectangleYMax = y_max,
102 .ScissorRectangleXMax = x_max
105 if (s->extent.width <= 0 || s->extent.height <= 0) {
106 GEN7_SCISSOR_RECT_pack(NULL, scissor_state.map + i * 8,
109 GEN7_SCISSOR_RECT_pack(NULL, scissor_state.map + i * 8, &scissor);
113 anv_batch_emit(&cmd_buffer->batch,
114 GEN7_3DSTATE_SCISSOR_STATE_POINTERS, ssp) {
115 ssp.ScissorRectPointer = scissor_state.offset;
118 anv_state_flush(cmd_buffer->device, scissor_state);
122 static const uint32_t vk_to_gen_index_type[] = {
123 [VK_INDEX_TYPE_UINT16] = INDEX_WORD,
124 [VK_INDEX_TYPE_UINT32] = INDEX_DWORD,
127 static const uint32_t restart_index_for_type[] = {
128 [VK_INDEX_TYPE_UINT16] = UINT16_MAX,
129 [VK_INDEX_TYPE_UINT32] = UINT32_MAX,
132 void genX(CmdBindIndexBuffer)(
133 VkCommandBuffer commandBuffer,
136 VkIndexType indexType)
138 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
139 ANV_FROM_HANDLE(anv_buffer, buffer, _buffer);
141 cmd_buffer->state.gfx.dirty |= ANV_CMD_DIRTY_INDEX_BUFFER;
143 cmd_buffer->state.restart_index = restart_index_for_type[indexType];
144 cmd_buffer->state.gfx.gen7.index_buffer = buffer;
145 cmd_buffer->state.gfx.gen7.index_type = vk_to_gen_index_type[indexType];
146 cmd_buffer->state.gfx.gen7.index_offset = offset;
150 get_depth_format(struct anv_cmd_buffer *cmd_buffer)
152 const struct anv_render_pass *pass = cmd_buffer->state.pass;
153 const struct anv_subpass *subpass = cmd_buffer->state.subpass;
155 if (!subpass->depth_stencil_attachment)
158 struct anv_render_pass_attachment *att =
159 &pass->attachments[subpass->depth_stencil_attachment->attachment];
161 switch (att->format) {
162 case VK_FORMAT_D16_UNORM:
163 case VK_FORMAT_D16_UNORM_S8_UINT:
166 case VK_FORMAT_X8_D24_UNORM_PACK32:
167 case VK_FORMAT_D24_UNORM_S8_UINT:
168 return D24_UNORM_X8_UINT;
170 case VK_FORMAT_D32_SFLOAT:
171 case VK_FORMAT_D32_SFLOAT_S8_UINT:
180 genX(cmd_buffer_flush_dynamic_state)(struct anv_cmd_buffer *cmd_buffer)
182 struct anv_pipeline *pipeline = cmd_buffer->state.gfx.base.pipeline;
183 struct anv_dynamic_state *d = &cmd_buffer->state.gfx.dynamic;
185 if (cmd_buffer->state.gfx.dirty & (ANV_CMD_DIRTY_PIPELINE |
186 ANV_CMD_DIRTY_RENDER_TARGETS |
187 ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH |
188 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS)) {
189 uint32_t sf_dw[GENX(3DSTATE_SF_length)];
190 struct GENX(3DSTATE_SF) sf = {
191 GENX(3DSTATE_SF_header),
192 .DepthBufferSurfaceFormat = get_depth_format(cmd_buffer),
193 .LineWidth = d->line_width,
194 .GlobalDepthOffsetConstant = d->depth_bias.bias,
195 .GlobalDepthOffsetScale = d->depth_bias.slope,
196 .GlobalDepthOffsetClamp = d->depth_bias.clamp
198 GENX(3DSTATE_SF_pack)(NULL, sf_dw, &sf);
200 anv_batch_emit_merge(&cmd_buffer->batch, sf_dw, pipeline->gen7.sf);
203 if (cmd_buffer->state.gfx.dirty & (ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS |
204 ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE)) {
205 struct anv_state cc_state =
206 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer,
207 GENX(COLOR_CALC_STATE_length) * 4,
209 struct GENX(COLOR_CALC_STATE) cc = {
210 .BlendConstantColorRed = d->blend_constants[0],
211 .BlendConstantColorGreen = d->blend_constants[1],
212 .BlendConstantColorBlue = d->blend_constants[2],
213 .BlendConstantColorAlpha = d->blend_constants[3],
214 .StencilReferenceValue = d->stencil_reference.front & 0xff,
215 .BackfaceStencilReferenceValue = d->stencil_reference.back & 0xff,
217 GENX(COLOR_CALC_STATE_pack)(NULL, cc_state.map, &cc);
218 anv_state_flush(cmd_buffer->device, cc_state);
220 anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_CC_STATE_POINTERS), ccp) {
221 ccp.ColorCalcStatePointer = cc_state.offset;
225 if (cmd_buffer->state.gfx.dirty & (ANV_CMD_DIRTY_PIPELINE |
226 ANV_CMD_DIRTY_RENDER_TARGETS |
227 ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK |
228 ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK)) {
229 uint32_t depth_stencil_dw[GENX(DEPTH_STENCIL_STATE_length)];
231 struct GENX(DEPTH_STENCIL_STATE) depth_stencil = {
232 .StencilTestMask = d->stencil_compare_mask.front & 0xff,
233 .StencilWriteMask = d->stencil_write_mask.front & 0xff,
235 .BackfaceStencilTestMask = d->stencil_compare_mask.back & 0xff,
236 .BackfaceStencilWriteMask = d->stencil_write_mask.back & 0xff,
238 .StencilBufferWriteEnable =
239 (d->stencil_write_mask.front || d->stencil_write_mask.back) &&
240 pipeline->writes_stencil,
242 GENX(DEPTH_STENCIL_STATE_pack)(NULL, depth_stencil_dw, &depth_stencil);
244 struct anv_state ds_state =
245 anv_cmd_buffer_merge_dynamic(cmd_buffer, depth_stencil_dw,
246 pipeline->gen7.depth_stencil_state,
247 GENX(DEPTH_STENCIL_STATE_length), 64);
249 anv_batch_emit(&cmd_buffer->batch,
250 GENX(3DSTATE_DEPTH_STENCIL_STATE_POINTERS), dsp) {
251 dsp.PointertoDEPTH_STENCIL_STATE = ds_state.offset;
255 if (cmd_buffer->state.gfx.gen7.index_buffer &&
256 cmd_buffer->state.gfx.dirty & (ANV_CMD_DIRTY_PIPELINE |
257 ANV_CMD_DIRTY_INDEX_BUFFER)) {
258 struct anv_buffer *buffer = cmd_buffer->state.gfx.gen7.index_buffer;
259 uint32_t offset = cmd_buffer->state.gfx.gen7.index_offset;
262 anv_batch_emit(&cmd_buffer->batch, GEN75_3DSTATE_VF, vf) {
263 vf.IndexedDrawCutIndexEnable = pipeline->primitive_restart;
264 vf.CutIndex = cmd_buffer->state.restart_index;
268 anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_INDEX_BUFFER), ib) {
270 ib.CutIndexEnable = pipeline->primitive_restart;
272 ib.IndexFormat = cmd_buffer->state.gfx.gen7.index_type;
273 ib.IndexBufferMOCS = anv_mocs_for_bo(cmd_buffer->device,
276 ib.BufferStartingAddress = anv_address_add(buffer->address,
278 ib.BufferEndingAddress = anv_address_add(buffer->address,
283 cmd_buffer->state.gfx.dirty = 0;
287 genX(cmd_buffer_enable_pma_fix)(struct anv_cmd_buffer *cmd_buffer,
290 /* The NP PMA fix doesn't exist on gen7 */
293 void genX(CmdSetEvent)(
294 VkCommandBuffer commandBuffer,
296 VkPipelineStageFlags stageMask)
298 anv_finishme("Implement events on gen7");
301 void genX(CmdResetEvent)(
302 VkCommandBuffer commandBuffer,
304 VkPipelineStageFlags stageMask)
306 anv_finishme("Implement events on gen7");
309 void genX(CmdWaitEvents)(
310 VkCommandBuffer commandBuffer,
312 const VkEvent* pEvents,
313 VkPipelineStageFlags srcStageMask,
314 VkPipelineStageFlags destStageMask,
315 uint32_t memoryBarrierCount,
316 const VkMemoryBarrier* pMemoryBarriers,
317 uint32_t bufferMemoryBarrierCount,
318 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
319 uint32_t imageMemoryBarrierCount,
320 const VkImageMemoryBarrier* pImageMemoryBarriers)
322 anv_finishme("Implement events on gen7");
324 genX(CmdPipelineBarrier)(commandBuffer, srcStageMask, destStageMask,
325 false, /* byRegion */
326 memoryBarrierCount, pMemoryBarriers,
327 bufferMemoryBarrierCount, pBufferMemoryBarriers,
328 imageMemoryBarrierCount, pImageMemoryBarriers);