2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
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8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
30 #include "anv_private.h"
32 #include "genxml/gen_macros.h"
33 #include "genxml/genX_pack.h"
37 gen8_cmd_buffer_emit_viewport(struct anv_cmd_buffer *cmd_buffer)
39 uint32_t count = cmd_buffer->state.dynamic.viewport.count;
40 const VkViewport *viewports = cmd_buffer->state.dynamic.viewport.viewports;
41 struct anv_state sf_clip_state =
42 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer, count * 64, 64);
43 struct anv_state cc_state =
44 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer, count * 8, 32);
46 for (uint32_t i = 0; i < count; i++) {
47 const VkViewport *vp = &viewports[i];
49 /* The gen7 state struct has just the matrix and guardband fields, the
50 * gen8 struct adds the min/max viewport fields. */
51 struct GENX(SF_CLIP_VIEWPORT) sf_clip_viewport = {
52 .ViewportMatrixElementm00 = vp->width / 2,
53 .ViewportMatrixElementm11 = vp->height / 2,
54 .ViewportMatrixElementm22 = 1.0,
55 .ViewportMatrixElementm30 = vp->x + vp->width / 2,
56 .ViewportMatrixElementm31 = vp->y + vp->height / 2,
57 .ViewportMatrixElementm32 = 0.0,
58 .XMinClipGuardband = -1.0f,
59 .XMaxClipGuardband = 1.0f,
60 .YMinClipGuardband = -1.0f,
61 .YMaxClipGuardband = 1.0f,
62 .XMinViewPort = vp->x,
63 .XMaxViewPort = vp->x + vp->width - 1,
64 .YMinViewPort = vp->y,
65 .YMaxViewPort = vp->y + vp->height - 1,
68 struct GENX(CC_VIEWPORT) cc_viewport = {
69 .MinimumDepth = vp->minDepth,
70 .MaximumDepth = vp->maxDepth
73 GENX(SF_CLIP_VIEWPORT_pack)(NULL, sf_clip_state.map + i * 64,
75 GENX(CC_VIEWPORT_pack)(NULL, cc_state.map + i * 8, &cc_viewport);
78 if (!cmd_buffer->device->info.has_llc) {
79 anv_state_clflush(sf_clip_state);
80 anv_state_clflush(cc_state);
83 anv_batch_emit(&cmd_buffer->batch,
84 GENX(3DSTATE_VIEWPORT_STATE_POINTERS_CC), cc) {
85 cc.CCViewportPointer = cc_state.offset;
87 anv_batch_emit(&cmd_buffer->batch,
88 GENX(3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP), clip) {
89 clip.SFClipViewportPointer = sf_clip_state.offset;
95 __emit_genx_sf_state(struct anv_cmd_buffer *cmd_buffer)
97 uint32_t sf_dw[GENX(3DSTATE_SF_length)];
98 struct GENX(3DSTATE_SF) sf = {
99 GENX(3DSTATE_SF_header),
100 .LineWidth = cmd_buffer->state.dynamic.line_width,
102 GENX(3DSTATE_SF_pack)(NULL, sf_dw, &sf);
104 anv_batch_emit_merge(&cmd_buffer->batch, sf_dw,
105 cmd_buffer->state.pipeline->gen8.sf);
108 #include "genxml/gen9_pack.h"
110 __emit_gen9_sf_state(struct anv_cmd_buffer *cmd_buffer)
112 uint32_t sf_dw[GENX(3DSTATE_SF_length)];
113 struct GEN9_3DSTATE_SF sf = {
114 GEN9_3DSTATE_SF_header,
115 .LineWidth = cmd_buffer->state.dynamic.line_width,
117 GEN9_3DSTATE_SF_pack(NULL, sf_dw, &sf);
119 anv_batch_emit_merge(&cmd_buffer->batch, sf_dw,
120 cmd_buffer->state.pipeline->gen8.sf);
124 __emit_sf_state(struct anv_cmd_buffer *cmd_buffer)
126 if (cmd_buffer->device->info.is_cherryview)
127 __emit_gen9_sf_state(cmd_buffer);
129 __emit_genx_sf_state(cmd_buffer);
133 genX(cmd_buffer_flush_dynamic_state)(struct anv_cmd_buffer *cmd_buffer)
135 struct anv_pipeline *pipeline = cmd_buffer->state.pipeline;
137 if (cmd_buffer->state.dirty & (ANV_CMD_DIRTY_PIPELINE |
138 ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH)) {
139 __emit_sf_state(cmd_buffer);
142 if (cmd_buffer->state.dirty & (ANV_CMD_DIRTY_PIPELINE |
143 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS)){
144 uint32_t raster_dw[GENX(3DSTATE_RASTER_length)];
145 struct GENX(3DSTATE_RASTER) raster = {
146 GENX(3DSTATE_RASTER_header),
147 .GlobalDepthOffsetConstant = cmd_buffer->state.dynamic.depth_bias.bias,
148 .GlobalDepthOffsetScale = cmd_buffer->state.dynamic.depth_bias.slope,
149 .GlobalDepthOffsetClamp = cmd_buffer->state.dynamic.depth_bias.clamp
151 GENX(3DSTATE_RASTER_pack)(NULL, raster_dw, &raster);
152 anv_batch_emit_merge(&cmd_buffer->batch, raster_dw,
153 pipeline->gen8.raster);
156 /* Stencil reference values moved from COLOR_CALC_STATE in gen8 to
157 * 3DSTATE_WM_DEPTH_STENCIL in gen9. That means the dirty bits gets split
158 * across different state packets for gen8 and gen9. We handle that by
159 * using a big old #if switch here.
162 if (cmd_buffer->state.dirty & (ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS |
163 ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE)) {
164 struct anv_dynamic_state *d = &cmd_buffer->state.dynamic;
165 struct anv_state cc_state =
166 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer,
167 GENX(COLOR_CALC_STATE_length) * 4,
169 struct GENX(COLOR_CALC_STATE) cc = {
170 .BlendConstantColorRed = cmd_buffer->state.dynamic.blend_constants[0],
171 .BlendConstantColorGreen = cmd_buffer->state.dynamic.blend_constants[1],
172 .BlendConstantColorBlue = cmd_buffer->state.dynamic.blend_constants[2],
173 .BlendConstantColorAlpha = cmd_buffer->state.dynamic.blend_constants[3],
174 .StencilReferenceValue = d->stencil_reference.front & 0xff,
175 .BackFaceStencilReferenceValue = d->stencil_reference.back & 0xff,
177 GENX(COLOR_CALC_STATE_pack)(NULL, cc_state.map, &cc);
179 if (!cmd_buffer->device->info.has_llc)
180 anv_state_clflush(cc_state);
182 anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_CC_STATE_POINTERS), ccp) {
183 ccp.ColorCalcStatePointer = cc_state.offset;
184 ccp.ColorCalcStatePointerValid = true;
188 if (cmd_buffer->state.dirty & (ANV_CMD_DIRTY_PIPELINE |
189 ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK |
190 ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK)) {
191 uint32_t wm_depth_stencil_dw[GENX(3DSTATE_WM_DEPTH_STENCIL_length)];
192 struct anv_dynamic_state *d = &cmd_buffer->state.dynamic;
194 struct GENX(3DSTATE_WM_DEPTH_STENCIL wm_depth_stencil) = {
195 GENX(3DSTATE_WM_DEPTH_STENCIL_header),
197 .StencilTestMask = d->stencil_compare_mask.front & 0xff,
198 .StencilWriteMask = d->stencil_write_mask.front & 0xff,
200 .BackfaceStencilTestMask = d->stencil_compare_mask.back & 0xff,
201 .BackfaceStencilWriteMask = d->stencil_write_mask.back & 0xff,
203 GENX(3DSTATE_WM_DEPTH_STENCIL_pack)(NULL, wm_depth_stencil_dw,
206 anv_batch_emit_merge(&cmd_buffer->batch, wm_depth_stencil_dw,
207 pipeline->gen8.wm_depth_stencil);
210 if (cmd_buffer->state.dirty & ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS) {
211 struct anv_state cc_state =
212 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer,
213 GEN9_COLOR_CALC_STATE_length * 4,
215 struct GEN9_COLOR_CALC_STATE cc = {
216 .BlendConstantColorRed = cmd_buffer->state.dynamic.blend_constants[0],
217 .BlendConstantColorGreen = cmd_buffer->state.dynamic.blend_constants[1],
218 .BlendConstantColorBlue = cmd_buffer->state.dynamic.blend_constants[2],
219 .BlendConstantColorAlpha = cmd_buffer->state.dynamic.blend_constants[3],
221 GEN9_COLOR_CALC_STATE_pack(NULL, cc_state.map, &cc);
223 if (!cmd_buffer->device->info.has_llc)
224 anv_state_clflush(cc_state);
226 anv_batch_emit(&cmd_buffer->batch, GEN9_3DSTATE_CC_STATE_POINTERS, ccp) {
227 ccp.ColorCalcStatePointer = cc_state.offset;
228 ccp.ColorCalcStatePointerValid = true;
232 if (cmd_buffer->state.dirty & (ANV_CMD_DIRTY_PIPELINE |
233 ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK |
234 ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK |
235 ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE)) {
236 uint32_t dwords[GEN9_3DSTATE_WM_DEPTH_STENCIL_length];
237 struct anv_dynamic_state *d = &cmd_buffer->state.dynamic;
238 struct GEN9_3DSTATE_WM_DEPTH_STENCIL wm_depth_stencil = {
239 GEN9_3DSTATE_WM_DEPTH_STENCIL_header,
241 .StencilTestMask = d->stencil_compare_mask.front & 0xff,
242 .StencilWriteMask = d->stencil_write_mask.front & 0xff,
244 .BackfaceStencilTestMask = d->stencil_compare_mask.back & 0xff,
245 .BackfaceStencilWriteMask = d->stencil_write_mask.back & 0xff,
247 .StencilReferenceValue = d->stencil_reference.front & 0xff,
248 .BackfaceStencilReferenceValue = d->stencil_reference.back & 0xff,
250 GEN9_3DSTATE_WM_DEPTH_STENCIL_pack(NULL, dwords, &wm_depth_stencil);
252 anv_batch_emit_merge(&cmd_buffer->batch, dwords,
253 pipeline->gen9.wm_depth_stencil);
257 if (cmd_buffer->state.dirty & (ANV_CMD_DIRTY_PIPELINE |
258 ANV_CMD_DIRTY_INDEX_BUFFER)) {
259 anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_VF), vf) {
260 vf.IndexedDrawCutIndexEnable = pipeline->primitive_restart;
261 vf.CutIndex = cmd_buffer->state.restart_index;
265 cmd_buffer->state.dirty = 0;
268 void genX(CmdBindIndexBuffer)(
269 VkCommandBuffer commandBuffer,
272 VkIndexType indexType)
274 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
275 ANV_FROM_HANDLE(anv_buffer, buffer, _buffer);
277 static const uint32_t vk_to_gen_index_type[] = {
278 [VK_INDEX_TYPE_UINT16] = INDEX_WORD,
279 [VK_INDEX_TYPE_UINT32] = INDEX_DWORD,
282 static const uint32_t restart_index_for_type[] = {
283 [VK_INDEX_TYPE_UINT16] = UINT16_MAX,
284 [VK_INDEX_TYPE_UINT32] = UINT32_MAX,
287 cmd_buffer->state.restart_index = restart_index_for_type[indexType];
289 anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_INDEX_BUFFER), ib) {
290 ib.IndexFormat = vk_to_gen_index_type[indexType];
291 ib.MemoryObjectControlState = GENX(MOCS);
292 ib.BufferStartingAddress =
293 (struct anv_address) { buffer->bo, buffer->offset + offset };
294 ib.BufferSize = buffer->size - offset;
297 cmd_buffer->state.dirty |= ANV_CMD_DIRTY_INDEX_BUFFER;
301 flush_compute_descriptor_set(struct anv_cmd_buffer *cmd_buffer)
303 struct anv_device *device = cmd_buffer->device;
304 struct anv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
305 struct anv_state surfaces = { 0, }, samplers = { 0, };
308 result = anv_cmd_buffer_emit_samplers(cmd_buffer,
309 MESA_SHADER_COMPUTE, &samplers);
310 if (result != VK_SUCCESS)
312 result = anv_cmd_buffer_emit_binding_table(cmd_buffer,
313 MESA_SHADER_COMPUTE, &surfaces);
314 if (result != VK_SUCCESS)
317 struct anv_state push_state = anv_cmd_buffer_cs_push_constants(cmd_buffer);
319 const struct brw_cs_prog_data *cs_prog_data = get_cs_prog_data(pipeline);
320 const struct brw_stage_prog_data *prog_data = &cs_prog_data->base;
322 unsigned local_id_dwords = cs_prog_data->local_invocation_id_regs * 8;
323 unsigned push_constant_data_size =
324 (prog_data->nr_params + local_id_dwords) * 4;
325 unsigned reg_aligned_constant_size = ALIGN(push_constant_data_size, 32);
326 unsigned push_constant_regs = reg_aligned_constant_size / 32;
328 if (push_state.alloc_size) {
329 anv_batch_emit(&cmd_buffer->batch, GENX(MEDIA_CURBE_LOAD), curbe) {
330 curbe.CURBETotalDataLength = push_state.alloc_size;
331 curbe.CURBEDataStartAddress = push_state.offset;
335 assert(prog_data->total_shared <= 64 * 1024);
336 uint32_t slm_size = 0;
337 if (prog_data->total_shared > 0) {
338 /* slm_size is in 4k increments, but must be a power of 2. */
340 while (slm_size < prog_data->total_shared)
342 slm_size /= 4 * 1024;
345 struct anv_state state =
346 anv_state_pool_emit(&device->dynamic_state_pool,
347 GENX(INTERFACE_DESCRIPTOR_DATA), 64,
348 .KernelStartPointer = pipeline->cs_simd,
349 .KernelStartPointerHigh = 0,
350 .BindingTablePointer = surfaces.offset,
351 .BindingTableEntryCount = 0,
352 .SamplerStatePointer = samplers.offset,
354 .ConstantIndirectURBEntryReadLength = push_constant_regs,
355 .ConstantURBEntryReadOffset = 0,
356 .BarrierEnable = cs_prog_data->uses_barrier,
357 .SharedLocalMemorySize = slm_size,
358 .NumberofThreadsinGPGPUThreadGroup =
359 pipeline->cs_thread_width_max);
361 uint32_t size = GENX(INTERFACE_DESCRIPTOR_DATA_length) * sizeof(uint32_t);
362 anv_batch_emit(&cmd_buffer->batch,
363 GENX(MEDIA_INTERFACE_DESCRIPTOR_LOAD), mid) {
364 mid.InterfaceDescriptorTotalLength = size;
365 mid.InterfaceDescriptorDataStartAddress = state.offset;
372 genX(cmd_buffer_flush_compute_state)(struct anv_cmd_buffer *cmd_buffer)
374 struct anv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
375 const struct brw_cs_prog_data *cs_prog_data = get_cs_prog_data(pipeline);
376 MAYBE_UNUSED VkResult result;
378 assert(pipeline->active_stages == VK_SHADER_STAGE_COMPUTE_BIT);
380 genX(cmd_buffer_config_l3)(cmd_buffer, pipeline);
382 genX(flush_pipeline_select_gpgpu)(cmd_buffer);
384 if (cmd_buffer->state.compute_dirty & ANV_CMD_DIRTY_PIPELINE)
385 anv_batch_emit_batch(&cmd_buffer->batch, &pipeline->batch);
387 if ((cmd_buffer->state.descriptors_dirty & VK_SHADER_STAGE_COMPUTE_BIT) ||
388 (cmd_buffer->state.compute_dirty & ANV_CMD_DIRTY_PIPELINE)) {
389 result = flush_compute_descriptor_set(cmd_buffer);
390 assert(result == VK_SUCCESS);
391 cmd_buffer->state.descriptors_dirty &= ~VK_SHADER_STAGE_COMPUTE_BIT;
394 cmd_buffer->state.compute_dirty = 0;
397 void genX(CmdSetEvent)(
398 VkCommandBuffer commandBuffer,
400 VkPipelineStageFlags stageMask)
402 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
403 ANV_FROM_HANDLE(anv_event, event, _event);
405 anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
406 pc.DestinationAddressType = DAT_PPGTT,
407 pc.PostSyncOperation = WriteImmediateData,
408 pc.Address = (struct anv_address) {
409 &cmd_buffer->device->dynamic_state_block_pool.bo,
412 pc.ImmediateData = VK_EVENT_SET;
416 void genX(CmdResetEvent)(
417 VkCommandBuffer commandBuffer,
419 VkPipelineStageFlags stageMask)
421 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
422 ANV_FROM_HANDLE(anv_event, event, _event);
424 anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
425 pc.DestinationAddressType = DAT_PPGTT;
426 pc.PostSyncOperation = WriteImmediateData;
427 pc.Address = (struct anv_address) {
428 &cmd_buffer->device->dynamic_state_block_pool.bo,
431 pc.ImmediateData = VK_EVENT_RESET;
435 void genX(CmdWaitEvents)(
436 VkCommandBuffer commandBuffer,
438 const VkEvent* pEvents,
439 VkPipelineStageFlags srcStageMask,
440 VkPipelineStageFlags destStageMask,
441 uint32_t memoryBarrierCount,
442 const VkMemoryBarrier* pMemoryBarriers,
443 uint32_t bufferMemoryBarrierCount,
444 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
445 uint32_t imageMemoryBarrierCount,
446 const VkImageMemoryBarrier* pImageMemoryBarriers)
448 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
449 for (uint32_t i = 0; i < eventCount; i++) {
450 ANV_FROM_HANDLE(anv_event, event, pEvents[i]);
452 anv_batch_emit(&cmd_buffer->batch, GENX(MI_SEMAPHORE_WAIT), sem) {
453 sem.WaitMode = PollingMode,
454 sem.CompareOperation = COMPARE_SAD_EQUAL_SDD,
455 sem.SemaphoreDataDword = VK_EVENT_SET,
456 sem.SemaphoreAddress = (struct anv_address) {
457 &cmd_buffer->device->dynamic_state_block_pool.bo,
463 genX(CmdPipelineBarrier)(commandBuffer, srcStageMask, destStageMask,
464 false, /* byRegion */
465 memoryBarrierCount, pMemoryBarriers,
466 bufferMemoryBarrierCount, pBufferMemoryBarriers,
467 imageMemoryBarrierCount, pImageMemoryBarriers);