2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include "anv_private.h"
26 #include "genxml/gen_macros.h"
27 #include "genxml/genX_pack.h"
29 #include "common/gen_l3_config.h"
30 #include "common/gen_sample_positions.h"
31 #include "vk_format_info.h"
34 vertex_element_comp_control(enum isl_format format, unsigned comp)
38 case 0: bits = isl_format_layouts[format].channels.r.bits; break;
39 case 1: bits = isl_format_layouts[format].channels.g.bits; break;
40 case 2: bits = isl_format_layouts[format].channels.b.bits; break;
41 case 3: bits = isl_format_layouts[format].channels.a.bits; break;
42 default: unreachable("Invalid component");
46 * Take in account hardware restrictions when dealing with 64-bit floats.
48 * From Broadwell spec, command reference structures, page 586:
49 * "When SourceElementFormat is set to one of the *64*_PASSTHRU formats,
50 * 64-bit components are stored * in the URB without any conversion. In
51 * this case, vertex elements must be written as 128 or 256 bits, with
52 * VFCOMP_STORE_0 being used to pad the output as required. E.g., if
53 * R64_PASSTHRU is used to copy a 64-bit Red component into the URB,
54 * Component 1 must be specified as VFCOMP_STORE_0 (with Components 2,3
55 * set to VFCOMP_NOSTORE) in order to output a 128-bit vertex element, or
56 * Components 1-3 must be specified as VFCOMP_STORE_0 in order to output
57 * a 256-bit vertex element. Likewise, use of R64G64B64_PASSTHRU requires
58 * Component 3 to be specified as VFCOMP_STORE_0 in order to output a
59 * 256-bit vertex element."
62 return VFCOMP_STORE_SRC;
63 } else if (comp >= 2 &&
64 !isl_format_layouts[format].channels.b.bits &&
65 isl_format_layouts[format].channels.r.type == ISL_RAW) {
66 /* When emitting 64-bit attributes, we need to write either 128 or 256
67 * bit chunks, using VFCOMP_NOSTORE when not writing the chunk, and
68 * VFCOMP_STORE_0 to pad the written chunk */
69 return VFCOMP_NOSTORE;
70 } else if (comp < 3 ||
71 isl_format_layouts[format].channels.r.type == ISL_RAW) {
72 /* Note we need to pad with value 0, not 1, due hardware restrictions
73 * (see comment above) */
74 return VFCOMP_STORE_0;
75 } else if (isl_format_layouts[format].channels.r.type == ISL_UINT ||
76 isl_format_layouts[format].channels.r.type == ISL_SINT) {
78 return VFCOMP_STORE_1_INT;
81 return VFCOMP_STORE_1_FP;
86 emit_vertex_input(struct anv_pipeline *pipeline,
87 const VkPipelineVertexInputStateCreateInfo *info)
89 const struct brw_vs_prog_data *vs_prog_data = get_vs_prog_data(pipeline);
91 /* Pull inputs_read out of the VS prog data */
92 const uint64_t inputs_read = vs_prog_data->inputs_read;
93 const uint64_t double_inputs_read = vs_prog_data->double_inputs_read;
94 assert((inputs_read & ((1 << VERT_ATTRIB_GENERIC0) - 1)) == 0);
95 const uint32_t elements = inputs_read >> VERT_ATTRIB_GENERIC0;
96 const uint32_t elements_double = double_inputs_read >> VERT_ATTRIB_GENERIC0;
97 const bool needs_svgs_elem = vs_prog_data->uses_vertexid ||
98 vs_prog_data->uses_instanceid ||
99 vs_prog_data->uses_basevertex ||
100 vs_prog_data->uses_baseinstance;
102 uint32_t elem_count = __builtin_popcount(elements) -
103 __builtin_popcount(elements_double) / 2;
105 const uint32_t total_elems =
106 elem_count + needs_svgs_elem + vs_prog_data->uses_drawid;
107 if (total_elems == 0)
112 const uint32_t num_dwords = 1 + total_elems * 2;
113 p = anv_batch_emitn(&pipeline->batch, num_dwords,
114 GENX(3DSTATE_VERTEX_ELEMENTS));
117 memset(p + 1, 0, (num_dwords - 1) * 4);
119 for (uint32_t i = 0; i < info->vertexAttributeDescriptionCount; i++) {
120 const VkVertexInputAttributeDescription *desc =
121 &info->pVertexAttributeDescriptions[i];
122 enum isl_format format = anv_get_isl_format(&pipeline->device->info,
124 VK_IMAGE_ASPECT_COLOR_BIT,
125 VK_IMAGE_TILING_LINEAR);
127 assert(desc->binding < MAX_VBS);
129 if ((elements & (1 << desc->location)) == 0)
130 continue; /* Binding unused */
133 __builtin_popcount(elements & ((1 << desc->location) - 1)) -
134 DIV_ROUND_UP(__builtin_popcount(elements_double &
135 ((1 << desc->location) -1)), 2);
137 struct GENX(VERTEX_ELEMENT_STATE) element = {
138 .VertexBufferIndex = desc->binding,
140 .SourceElementFormat = format,
141 .EdgeFlagEnable = false,
142 .SourceElementOffset = desc->offset,
143 .Component0Control = vertex_element_comp_control(format, 0),
144 .Component1Control = vertex_element_comp_control(format, 1),
145 .Component2Control = vertex_element_comp_control(format, 2),
146 .Component3Control = vertex_element_comp_control(format, 3),
148 GENX(VERTEX_ELEMENT_STATE_pack)(NULL, &p[1 + slot * 2], &element);
151 /* On Broadwell and later, we have a separate VF_INSTANCING packet
152 * that controls instancing. On Haswell and prior, that's part of
153 * VERTEX_BUFFER_STATE which we emit later.
155 anv_batch_emit(&pipeline->batch, GENX(3DSTATE_VF_INSTANCING), vfi) {
156 vfi.InstancingEnable = pipeline->instancing_enable[desc->binding];
157 vfi.VertexElementIndex = slot;
158 /* Vulkan so far doesn't have an instance divisor, so
159 * this is always 1 (ignored if not instancing). */
160 vfi.InstanceDataStepRate = 1;
165 const uint32_t id_slot = elem_count;
166 if (needs_svgs_elem) {
167 /* From the Broadwell PRM for the 3D_Vertex_Component_Control enum:
168 * "Within a VERTEX_ELEMENT_STATE structure, if a Component
169 * Control field is set to something other than VFCOMP_STORE_SRC,
170 * no higher-numbered Component Control fields may be set to
173 * This means, that if we have BaseInstance, we need BaseVertex as
174 * well. Just do all or nothing.
176 uint32_t base_ctrl = (vs_prog_data->uses_basevertex ||
177 vs_prog_data->uses_baseinstance) ?
178 VFCOMP_STORE_SRC : VFCOMP_STORE_0;
180 struct GENX(VERTEX_ELEMENT_STATE) element = {
181 .VertexBufferIndex = ANV_SVGS_VB_INDEX,
183 .SourceElementFormat = ISL_FORMAT_R32G32_UINT,
184 .Component0Control = base_ctrl,
185 .Component1Control = base_ctrl,
187 .Component2Control = VFCOMP_STORE_0,
188 .Component3Control = VFCOMP_STORE_0,
190 .Component2Control = VFCOMP_STORE_VID,
191 .Component3Control = VFCOMP_STORE_IID,
194 GENX(VERTEX_ELEMENT_STATE_pack)(NULL, &p[1 + id_slot * 2], &element);
198 anv_batch_emit(&pipeline->batch, GENX(3DSTATE_VF_SGVS), sgvs) {
199 sgvs.VertexIDEnable = vs_prog_data->uses_vertexid;
200 sgvs.VertexIDComponentNumber = 2;
201 sgvs.VertexIDElementOffset = id_slot;
202 sgvs.InstanceIDEnable = vs_prog_data->uses_instanceid;
203 sgvs.InstanceIDComponentNumber = 3;
204 sgvs.InstanceIDElementOffset = id_slot;
208 const uint32_t drawid_slot = elem_count + needs_svgs_elem;
209 if (vs_prog_data->uses_drawid) {
210 struct GENX(VERTEX_ELEMENT_STATE) element = {
211 .VertexBufferIndex = ANV_DRAWID_VB_INDEX,
213 .SourceElementFormat = ISL_FORMAT_R32_UINT,
214 .Component0Control = VFCOMP_STORE_SRC,
215 .Component1Control = VFCOMP_STORE_0,
216 .Component2Control = VFCOMP_STORE_0,
217 .Component3Control = VFCOMP_STORE_0,
219 GENX(VERTEX_ELEMENT_STATE_pack)(NULL,
220 &p[1 + drawid_slot * 2],
224 anv_batch_emit(&pipeline->batch, GENX(3DSTATE_VF_INSTANCING), vfi) {
225 vfi.VertexElementIndex = drawid_slot;
232 genX(emit_urb_setup)(struct anv_device *device, struct anv_batch *batch,
233 const struct gen_l3_config *l3_config,
234 VkShaderStageFlags active_stages,
235 const unsigned entry_size[4])
237 const struct gen_device_info *devinfo = &device->info;
239 const unsigned push_constant_kb = devinfo->gt == 3 ? 32 : 16;
241 const unsigned push_constant_kb = GEN_GEN >= 8 ? 32 : 16;
244 const unsigned urb_size_kb = gen_get_l3_config_urb_size(devinfo, l3_config);
248 gen_get_urb_config(devinfo,
249 1024 * push_constant_kb, 1024 * urb_size_kb,
251 VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT,
252 active_stages & VK_SHADER_STAGE_GEOMETRY_BIT,
253 entry_size, entries, start);
255 #if GEN_GEN == 7 && !GEN_IS_HASWELL
256 /* From the IVB PRM Vol. 2, Part 1, Section 3.2.1:
258 * "A PIPE_CONTROL with Post-Sync Operation set to 1h and a depth stall
259 * needs to be sent just prior to any 3DSTATE_VS, 3DSTATE_URB_VS,
260 * 3DSTATE_CONSTANT_VS, 3DSTATE_BINDING_TABLE_POINTER_VS,
261 * 3DSTATE_SAMPLER_STATE_POINTER_VS command. Only one PIPE_CONTROL
262 * needs to be sent before any combination of VS associated 3DSTATE."
264 anv_batch_emit(batch, GEN7_PIPE_CONTROL, pc) {
265 pc.DepthStallEnable = true;
266 pc.PostSyncOperation = WriteImmediateData;
267 pc.Address = (struct anv_address) { &device->workaround_bo, 0 };
271 for (int i = 0; i <= MESA_SHADER_GEOMETRY; i++) {
272 anv_batch_emit(batch, GENX(3DSTATE_URB_VS), urb) {
273 urb._3DCommandSubOpcode += i;
274 urb.VSURBStartingAddress = start[i];
275 urb.VSURBEntryAllocationSize = entry_size[i] - 1;
276 urb.VSNumberofURBEntries = entries[i];
282 emit_urb_setup(struct anv_pipeline *pipeline)
284 unsigned entry_size[4];
285 for (int i = MESA_SHADER_VERTEX; i <= MESA_SHADER_GEOMETRY; i++) {
286 const struct brw_vue_prog_data *prog_data =
287 !anv_pipeline_has_stage(pipeline, i) ? NULL :
288 (const struct brw_vue_prog_data *) pipeline->shaders[i]->prog_data;
290 entry_size[i] = prog_data ? prog_data->urb_entry_size : 1;
293 genX(emit_urb_setup)(pipeline->device, &pipeline->batch,
294 pipeline->urb.l3_config,
295 pipeline->active_stages, entry_size);
299 emit_3dstate_sbe(struct anv_pipeline *pipeline)
301 const struct brw_wm_prog_data *wm_prog_data = get_wm_prog_data(pipeline);
303 if (!anv_pipeline_has_stage(pipeline, MESA_SHADER_FRAGMENT)) {
304 anv_batch_emit(&pipeline->batch, GENX(3DSTATE_SBE), sbe);
306 anv_batch_emit(&pipeline->batch, GENX(3DSTATE_SBE_SWIZ), sbe);
311 const struct brw_vue_map *fs_input_map =
312 &anv_pipeline_get_last_vue_prog_data(pipeline)->vue_map;
314 struct GENX(3DSTATE_SBE) sbe = {
315 GENX(3DSTATE_SBE_header),
316 .AttributeSwizzleEnable = true,
317 .PointSpriteTextureCoordinateOrigin = UPPERLEFT,
318 .NumberofSFOutputAttributes = wm_prog_data->num_varying_inputs,
319 .ConstantInterpolationEnable = wm_prog_data->flat_inputs,
323 for (unsigned i = 0; i < 32; i++)
324 sbe.AttributeActiveComponentFormat[i] = ACF_XYZW;
328 /* On Broadwell, they broke 3DSTATE_SBE into two packets */
329 struct GENX(3DSTATE_SBE_SWIZ) swiz = {
330 GENX(3DSTATE_SBE_SWIZ_header),
336 /* Skip the VUE header and position slots by default */
337 unsigned urb_entry_read_offset = 1;
338 int max_source_attr = 0;
339 for (int attr = 0; attr < VARYING_SLOT_MAX; attr++) {
340 int input_index = wm_prog_data->urb_setup[attr];
345 /* gl_Layer is stored in the VUE header */
346 if (attr == VARYING_SLOT_LAYER) {
347 urb_entry_read_offset = 0;
351 if (attr == VARYING_SLOT_PNTC) {
352 sbe.PointSpriteTextureCoordinateEnable = 1 << input_index;
356 const int slot = fs_input_map->varying_to_slot[attr];
358 if (input_index >= 16)
362 /* This attribute does not exist in the VUE--that means that the
363 * vertex shader did not write to it. It could be that it's a
364 * regular varying read by the fragment shader but not written by
365 * the vertex shader or it's gl_PrimitiveID. In the first case the
366 * value is undefined, in the second it needs to be
369 swiz.Attribute[input_index].ConstantSource = PRIM_ID;
370 swiz.Attribute[input_index].ComponentOverrideX = true;
371 swiz.Attribute[input_index].ComponentOverrideY = true;
372 swiz.Attribute[input_index].ComponentOverrideZ = true;
373 swiz.Attribute[input_index].ComponentOverrideW = true;
375 /* We have to subtract two slots to accout for the URB entry output
376 * read offset in the VS and GS stages.
379 const int source_attr = slot - 2 * urb_entry_read_offset;
380 max_source_attr = MAX2(max_source_attr, source_attr);
381 swiz.Attribute[input_index].SourceAttribute = source_attr;
385 sbe.VertexURBEntryReadOffset = urb_entry_read_offset;
386 sbe.VertexURBEntryReadLength = DIV_ROUND_UP(max_source_attr + 1, 2);
388 sbe.ForceVertexURBEntryReadOffset = true;
389 sbe.ForceVertexURBEntryReadLength = true;
392 uint32_t *dw = anv_batch_emit_dwords(&pipeline->batch,
393 GENX(3DSTATE_SBE_length));
396 GENX(3DSTATE_SBE_pack)(&pipeline->batch, dw, &sbe);
399 dw = anv_batch_emit_dwords(&pipeline->batch, GENX(3DSTATE_SBE_SWIZ_length));
402 GENX(3DSTATE_SBE_SWIZ_pack)(&pipeline->batch, dw, &swiz);
406 static const uint32_t vk_to_gen_cullmode[] = {
407 [VK_CULL_MODE_NONE] = CULLMODE_NONE,
408 [VK_CULL_MODE_FRONT_BIT] = CULLMODE_FRONT,
409 [VK_CULL_MODE_BACK_BIT] = CULLMODE_BACK,
410 [VK_CULL_MODE_FRONT_AND_BACK] = CULLMODE_BOTH
413 static const uint32_t vk_to_gen_fillmode[] = {
414 [VK_POLYGON_MODE_FILL] = FILL_MODE_SOLID,
415 [VK_POLYGON_MODE_LINE] = FILL_MODE_WIREFRAME,
416 [VK_POLYGON_MODE_POINT] = FILL_MODE_POINT,
419 static const uint32_t vk_to_gen_front_face[] = {
420 [VK_FRONT_FACE_COUNTER_CLOCKWISE] = 1,
421 [VK_FRONT_FACE_CLOCKWISE] = 0
425 emit_rs_state(struct anv_pipeline *pipeline,
426 const VkPipelineRasterizationStateCreateInfo *rs_info,
427 const VkPipelineMultisampleStateCreateInfo *ms_info,
428 const struct anv_render_pass *pass,
429 const struct anv_subpass *subpass)
431 struct GENX(3DSTATE_SF) sf = {
432 GENX(3DSTATE_SF_header),
435 sf.ViewportTransformEnable = true;
436 sf.StatisticsEnable = true;
437 sf.TriangleStripListProvokingVertexSelect = 0;
438 sf.LineStripListProvokingVertexSelect = 0;
439 sf.TriangleFanProvokingVertexSelect = 1;
441 const struct brw_vue_prog_data *last_vue_prog_data =
442 anv_pipeline_get_last_vue_prog_data(pipeline);
444 if (last_vue_prog_data->vue_map.slots_valid & VARYING_BIT_PSIZ) {
445 sf.PointWidthSource = Vertex;
447 sf.PointWidthSource = State;
452 struct GENX(3DSTATE_RASTER) raster = {
453 GENX(3DSTATE_RASTER_header),
459 /* For details on 3DSTATE_RASTER multisample state, see the BSpec table
460 * "Multisample Modes State".
463 raster.DXMultisampleRasterizationEnable = true;
464 /* NOTE: 3DSTATE_RASTER::ForcedSampleCount affects the BDW and SKL PMA fix
465 * computations. If we ever set this bit to a different value, they will
466 * need to be updated accordingly.
468 raster.ForcedSampleCount = FSC_NUMRASTSAMPLES_0;
469 raster.ForceMultisampling = false;
471 raster.MultisampleRasterizationMode =
472 (ms_info && ms_info->rasterizationSamples > 1) ?
473 MSRASTMODE_ON_PATTERN : MSRASTMODE_OFF_PIXEL;
476 raster.FrontWinding = vk_to_gen_front_face[rs_info->frontFace];
477 raster.CullMode = vk_to_gen_cullmode[rs_info->cullMode];
478 raster.FrontFaceFillMode = vk_to_gen_fillmode[rs_info->polygonMode];
479 raster.BackFaceFillMode = vk_to_gen_fillmode[rs_info->polygonMode];
480 raster.ScissorRectangleEnable = true;
483 /* GEN9+ splits ViewportZClipTestEnable into near and far enable bits */
484 raster.ViewportZFarClipTestEnable = !pipeline->depth_clamp_enable;
485 raster.ViewportZNearClipTestEnable = !pipeline->depth_clamp_enable;
487 raster.ViewportZClipTestEnable = !pipeline->depth_clamp_enable;
490 raster.GlobalDepthOffsetEnableSolid = rs_info->depthBiasEnable;
491 raster.GlobalDepthOffsetEnableWireframe = rs_info->depthBiasEnable;
492 raster.GlobalDepthOffsetEnablePoint = rs_info->depthBiasEnable;
495 /* Gen7 requires that we provide the depth format in 3DSTATE_SF so that it
496 * can get the depth offsets correct.
498 if (subpass->depth_stencil_attachment.attachment < pass->attachment_count) {
500 pass->attachments[subpass->depth_stencil_attachment.attachment].format;
501 assert(vk_format_is_depth_or_stencil(vk_format));
502 if (vk_format_aspects(vk_format) & VK_IMAGE_ASPECT_DEPTH_BIT) {
503 enum isl_format isl_format =
504 anv_get_isl_format(&pipeline->device->info, vk_format,
505 VK_IMAGE_ASPECT_DEPTH_BIT,
506 VK_IMAGE_TILING_OPTIMAL);
507 sf.DepthBufferSurfaceFormat =
508 isl_format_get_depth_format(isl_format, false);
514 GENX(3DSTATE_SF_pack)(NULL, pipeline->gen8.sf, &sf);
515 GENX(3DSTATE_RASTER_pack)(NULL, pipeline->gen8.raster, &raster);
518 GENX(3DSTATE_SF_pack)(NULL, &pipeline->gen7.sf, &sf);
523 emit_ms_state(struct anv_pipeline *pipeline,
524 const VkPipelineMultisampleStateCreateInfo *info)
526 uint32_t samples = 1;
527 uint32_t log2_samples = 0;
529 /* From the Vulkan 1.0 spec:
530 * If pSampleMask is NULL, it is treated as if the mask has all bits
531 * enabled, i.e. no coverage is removed from fragments.
533 * 3DSTATE_SAMPLE_MASK.SampleMask is 16 bits.
536 uint32_t sample_mask = 0xffff;
538 uint32_t sample_mask = 0xff;
542 samples = info->rasterizationSamples;
543 log2_samples = __builtin_ffs(samples) - 1;
546 if (info && info->pSampleMask)
547 sample_mask &= info->pSampleMask[0];
549 anv_batch_emit(&pipeline->batch, GENX(3DSTATE_MULTISAMPLE), ms) {
550 ms.NumberofMultisamples = log2_samples;
553 /* The PRM says that this bit is valid only for DX9:
555 * SW can choose to set this bit only for DX9 API. DX10/OGL API's
556 * should not have any effect by setting or not setting this bit.
558 ms.PixelPositionOffsetEnable = false;
559 ms.PixelLocation = CENTER;
561 ms.PixelLocation = PIXLOC_CENTER;
565 GEN_SAMPLE_POS_1X(ms.Sample);
568 GEN_SAMPLE_POS_2X(ms.Sample);
571 GEN_SAMPLE_POS_4X(ms.Sample);
574 GEN_SAMPLE_POS_8X(ms.Sample);
582 anv_batch_emit(&pipeline->batch, GENX(3DSTATE_SAMPLE_MASK), sm) {
583 sm.SampleMask = sample_mask;
587 static const uint32_t vk_to_gen_logic_op[] = {
588 [VK_LOGIC_OP_COPY] = LOGICOP_COPY,
589 [VK_LOGIC_OP_CLEAR] = LOGICOP_CLEAR,
590 [VK_LOGIC_OP_AND] = LOGICOP_AND,
591 [VK_LOGIC_OP_AND_REVERSE] = LOGICOP_AND_REVERSE,
592 [VK_LOGIC_OP_AND_INVERTED] = LOGICOP_AND_INVERTED,
593 [VK_LOGIC_OP_NO_OP] = LOGICOP_NOOP,
594 [VK_LOGIC_OP_XOR] = LOGICOP_XOR,
595 [VK_LOGIC_OP_OR] = LOGICOP_OR,
596 [VK_LOGIC_OP_NOR] = LOGICOP_NOR,
597 [VK_LOGIC_OP_EQUIVALENT] = LOGICOP_EQUIV,
598 [VK_LOGIC_OP_INVERT] = LOGICOP_INVERT,
599 [VK_LOGIC_OP_OR_REVERSE] = LOGICOP_OR_REVERSE,
600 [VK_LOGIC_OP_COPY_INVERTED] = LOGICOP_COPY_INVERTED,
601 [VK_LOGIC_OP_OR_INVERTED] = LOGICOP_OR_INVERTED,
602 [VK_LOGIC_OP_NAND] = LOGICOP_NAND,
603 [VK_LOGIC_OP_SET] = LOGICOP_SET,
606 static const uint32_t vk_to_gen_blend[] = {
607 [VK_BLEND_FACTOR_ZERO] = BLENDFACTOR_ZERO,
608 [VK_BLEND_FACTOR_ONE] = BLENDFACTOR_ONE,
609 [VK_BLEND_FACTOR_SRC_COLOR] = BLENDFACTOR_SRC_COLOR,
610 [VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR] = BLENDFACTOR_INV_SRC_COLOR,
611 [VK_BLEND_FACTOR_DST_COLOR] = BLENDFACTOR_DST_COLOR,
612 [VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR] = BLENDFACTOR_INV_DST_COLOR,
613 [VK_BLEND_FACTOR_SRC_ALPHA] = BLENDFACTOR_SRC_ALPHA,
614 [VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA] = BLENDFACTOR_INV_SRC_ALPHA,
615 [VK_BLEND_FACTOR_DST_ALPHA] = BLENDFACTOR_DST_ALPHA,
616 [VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA] = BLENDFACTOR_INV_DST_ALPHA,
617 [VK_BLEND_FACTOR_CONSTANT_COLOR] = BLENDFACTOR_CONST_COLOR,
618 [VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR]= BLENDFACTOR_INV_CONST_COLOR,
619 [VK_BLEND_FACTOR_CONSTANT_ALPHA] = BLENDFACTOR_CONST_ALPHA,
620 [VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA]= BLENDFACTOR_INV_CONST_ALPHA,
621 [VK_BLEND_FACTOR_SRC_ALPHA_SATURATE] = BLENDFACTOR_SRC_ALPHA_SATURATE,
622 [VK_BLEND_FACTOR_SRC1_COLOR] = BLENDFACTOR_SRC1_COLOR,
623 [VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR] = BLENDFACTOR_INV_SRC1_COLOR,
624 [VK_BLEND_FACTOR_SRC1_ALPHA] = BLENDFACTOR_SRC1_ALPHA,
625 [VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA] = BLENDFACTOR_INV_SRC1_ALPHA,
628 static const uint32_t vk_to_gen_blend_op[] = {
629 [VK_BLEND_OP_ADD] = BLENDFUNCTION_ADD,
630 [VK_BLEND_OP_SUBTRACT] = BLENDFUNCTION_SUBTRACT,
631 [VK_BLEND_OP_REVERSE_SUBTRACT] = BLENDFUNCTION_REVERSE_SUBTRACT,
632 [VK_BLEND_OP_MIN] = BLENDFUNCTION_MIN,
633 [VK_BLEND_OP_MAX] = BLENDFUNCTION_MAX,
636 static const uint32_t vk_to_gen_compare_op[] = {
637 [VK_COMPARE_OP_NEVER] = PREFILTEROPNEVER,
638 [VK_COMPARE_OP_LESS] = PREFILTEROPLESS,
639 [VK_COMPARE_OP_EQUAL] = PREFILTEROPEQUAL,
640 [VK_COMPARE_OP_LESS_OR_EQUAL] = PREFILTEROPLEQUAL,
641 [VK_COMPARE_OP_GREATER] = PREFILTEROPGREATER,
642 [VK_COMPARE_OP_NOT_EQUAL] = PREFILTEROPNOTEQUAL,
643 [VK_COMPARE_OP_GREATER_OR_EQUAL] = PREFILTEROPGEQUAL,
644 [VK_COMPARE_OP_ALWAYS] = PREFILTEROPALWAYS,
647 static const uint32_t vk_to_gen_stencil_op[] = {
648 [VK_STENCIL_OP_KEEP] = STENCILOP_KEEP,
649 [VK_STENCIL_OP_ZERO] = STENCILOP_ZERO,
650 [VK_STENCIL_OP_REPLACE] = STENCILOP_REPLACE,
651 [VK_STENCIL_OP_INCREMENT_AND_CLAMP] = STENCILOP_INCRSAT,
652 [VK_STENCIL_OP_DECREMENT_AND_CLAMP] = STENCILOP_DECRSAT,
653 [VK_STENCIL_OP_INVERT] = STENCILOP_INVERT,
654 [VK_STENCIL_OP_INCREMENT_AND_WRAP] = STENCILOP_INCR,
655 [VK_STENCIL_OP_DECREMENT_AND_WRAP] = STENCILOP_DECR,
658 /* This function sanitizes the VkStencilOpState by looking at the compare ops
659 * and trying to determine whether or not a given stencil op can ever actually
660 * occur. Stencil ops which can never occur are set to VK_STENCIL_OP_KEEP.
661 * This function returns true if, after sanitation, any of the stencil ops are
662 * set to something other than VK_STENCIL_OP_KEEP.
665 sanitize_stencil_face(VkStencilOpState *face,
666 VkCompareOp depthCompareOp)
668 /* If compareOp is ALWAYS then the stencil test will never fail and failOp
669 * will never happen. Set failOp to KEEP in this case.
671 if (face->compareOp == VK_COMPARE_OP_ALWAYS)
672 face->failOp = VK_STENCIL_OP_KEEP;
674 /* If compareOp is NEVER or depthCompareOp is NEVER then one of the depth
675 * or stencil tests will fail and passOp will never happen.
677 if (face->compareOp == VK_COMPARE_OP_NEVER ||
678 depthCompareOp == VK_COMPARE_OP_NEVER)
679 face->passOp = VK_STENCIL_OP_KEEP;
681 /* If compareOp is NEVER or depthCompareOp is ALWAYS then either the
682 * stencil test will fail or the depth test will pass. In either case,
683 * depthFailOp will never happen.
685 if (face->compareOp == VK_COMPARE_OP_NEVER ||
686 depthCompareOp == VK_COMPARE_OP_ALWAYS)
687 face->depthFailOp = VK_STENCIL_OP_KEEP;
689 return face->failOp != VK_STENCIL_OP_KEEP ||
690 face->depthFailOp != VK_STENCIL_OP_KEEP ||
691 face->passOp != VK_STENCIL_OP_KEEP;
694 /* Intel hardware is fairly sensitive to whether or not depth/stencil writes
695 * are enabled. In the presence of discards, it's fairly easy to get into the
696 * non-promoted case which means a fairly big performance hit. From the Iron
697 * Lake PRM, Vol 2, pt. 1, section 8.4.3.2, "Early Depth Test Cases":
699 * "Non-promoted depth (N) is active whenever the depth test can be done
700 * early but it cannot determine whether or not to write source depth to
701 * the depth buffer, therefore the depth write must be performed post pixel
702 * shader. This includes cases where the pixel shader can kill pixels,
703 * including via sampler chroma key, as well as cases where the alpha test
704 * function is enabled, which kills pixels based on a programmable alpha
705 * test. In this case, even if the depth test fails, the pixel cannot be
706 * killed if a stencil write is indicated. Whether or not the stencil write
707 * happens depends on whether or not the pixel is killed later. In these
708 * cases if stencil test fails and stencil writes are off, the pixels can
709 * also be killed early. If stencil writes are enabled, the pixels must be
710 * treated as Computed depth (described above)."
712 * The same thing as mentioned in the stencil case can happen in the depth
713 * case as well if it thinks it writes depth but, thanks to the depth test
714 * being GL_EQUAL, the write doesn't actually matter. A little extra work
715 * up-front to try and disable depth and stencil writes can make a big
718 * Unfortunately, the way depth and stencil testing is specified, there are
719 * many case where, regardless of depth/stencil writes being enabled, nothing
720 * actually gets written due to some other bit of state being set. This
721 * function attempts to "sanitize" the depth stencil state and disable writes
722 * and sometimes even testing whenever possible.
725 sanitize_ds_state(VkPipelineDepthStencilStateCreateInfo *state,
726 bool *stencilWriteEnable,
727 VkImageAspectFlags ds_aspects)
729 *stencilWriteEnable = state->stencilTestEnable;
731 /* If the depth test is disabled, we won't be writing anything. */
732 if (!state->depthTestEnable)
733 state->depthWriteEnable = false;
735 /* The Vulkan spec requires that if either depth or stencil is not present,
736 * the pipeline is to act as if the test silently passes.
738 if (!(ds_aspects & VK_IMAGE_ASPECT_DEPTH_BIT)) {
739 state->depthWriteEnable = false;
740 state->depthCompareOp = VK_COMPARE_OP_ALWAYS;
743 if (!(ds_aspects & VK_IMAGE_ASPECT_STENCIL_BIT)) {
744 *stencilWriteEnable = false;
745 state->front.compareOp = VK_COMPARE_OP_ALWAYS;
746 state->back.compareOp = VK_COMPARE_OP_ALWAYS;
749 /* If the stencil test is enabled and always fails, then we will never get
750 * to the depth test so we can just disable the depth test entirely.
752 if (state->stencilTestEnable &&
753 state->front.compareOp == VK_COMPARE_OP_NEVER &&
754 state->back.compareOp == VK_COMPARE_OP_NEVER) {
755 state->depthTestEnable = false;
756 state->depthWriteEnable = false;
759 /* If depthCompareOp is EQUAL then the value we would be writing to the
760 * depth buffer is the same as the value that's already there so there's no
761 * point in writing it.
763 if (state->depthCompareOp == VK_COMPARE_OP_EQUAL)
764 state->depthWriteEnable = false;
766 /* If the stencil ops are such that we don't actually ever modify the
767 * stencil buffer, we should disable writes.
769 if (!sanitize_stencil_face(&state->front, state->depthCompareOp) &&
770 !sanitize_stencil_face(&state->back, state->depthCompareOp))
771 *stencilWriteEnable = false;
773 /* If the depth test always passes and we never write out depth, that's the
774 * same as if the depth test is disabled entirely.
776 if (state->depthCompareOp == VK_COMPARE_OP_ALWAYS &&
777 !state->depthWriteEnable)
778 state->depthTestEnable = false;
780 /* If the stencil test always passes and we never write out stencil, that's
781 * the same as if the stencil test is disabled entirely.
783 if (state->front.compareOp == VK_COMPARE_OP_ALWAYS &&
784 state->back.compareOp == VK_COMPARE_OP_ALWAYS &&
785 !*stencilWriteEnable)
786 state->stencilTestEnable = false;
790 emit_ds_state(struct anv_pipeline *pipeline,
791 const VkPipelineDepthStencilStateCreateInfo *pCreateInfo,
792 const struct anv_render_pass *pass,
793 const struct anv_subpass *subpass)
796 # define depth_stencil_dw pipeline->gen7.depth_stencil_state
798 # define depth_stencil_dw pipeline->gen8.wm_depth_stencil
800 # define depth_stencil_dw pipeline->gen9.wm_depth_stencil
803 if (pCreateInfo == NULL) {
804 /* We're going to OR this together with the dynamic state. We need
805 * to make sure it's initialized to something useful.
807 pipeline->writes_stencil = false;
808 pipeline->stencil_test_enable = false;
809 pipeline->writes_depth = false;
810 pipeline->depth_test_enable = false;
811 memset(depth_stencil_dw, 0, sizeof(depth_stencil_dw));
815 VkImageAspectFlags ds_aspects = 0;
816 if (subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
817 VkFormat depth_stencil_format =
818 pass->attachments[subpass->depth_stencil_attachment.attachment].format;
819 ds_aspects = vk_format_aspects(depth_stencil_format);
822 VkPipelineDepthStencilStateCreateInfo info = *pCreateInfo;
823 sanitize_ds_state(&info, &pipeline->writes_stencil, ds_aspects);
824 pipeline->stencil_test_enable = info.stencilTestEnable;
825 pipeline->writes_depth = info.depthWriteEnable;
826 pipeline->depth_test_enable = info.depthTestEnable;
828 /* VkBool32 depthBoundsTestEnable; // optional (depth_bounds_test) */
831 struct GENX(DEPTH_STENCIL_STATE) depth_stencil = {
833 struct GENX(3DSTATE_WM_DEPTH_STENCIL) depth_stencil = {
835 .DepthTestEnable = info.depthTestEnable,
836 .DepthBufferWriteEnable = info.depthWriteEnable,
837 .DepthTestFunction = vk_to_gen_compare_op[info.depthCompareOp],
838 .DoubleSidedStencilEnable = true,
840 .StencilTestEnable = info.stencilTestEnable,
841 .StencilFailOp = vk_to_gen_stencil_op[info.front.failOp],
842 .StencilPassDepthPassOp = vk_to_gen_stencil_op[info.front.passOp],
843 .StencilPassDepthFailOp = vk_to_gen_stencil_op[info.front.depthFailOp],
844 .StencilTestFunction = vk_to_gen_compare_op[info.front.compareOp],
845 .BackfaceStencilFailOp = vk_to_gen_stencil_op[info.back.failOp],
846 .BackfaceStencilPassDepthPassOp = vk_to_gen_stencil_op[info.back.passOp],
847 .BackfaceStencilPassDepthFailOp =vk_to_gen_stencil_op[info.back.depthFailOp],
848 .BackfaceStencilTestFunction = vk_to_gen_compare_op[info.back.compareOp],
852 GENX(DEPTH_STENCIL_STATE_pack)(NULL, depth_stencil_dw, &depth_stencil);
854 GENX(3DSTATE_WM_DEPTH_STENCIL_pack)(NULL, depth_stencil_dw, &depth_stencil);
859 emit_cb_state(struct anv_pipeline *pipeline,
860 const VkPipelineColorBlendStateCreateInfo *info,
861 const VkPipelineMultisampleStateCreateInfo *ms_info)
863 struct anv_device *device = pipeline->device;
866 struct GENX(BLEND_STATE) blend_state = {
868 .AlphaToCoverageEnable = ms_info && ms_info->alphaToCoverageEnable,
869 .AlphaToOneEnable = ms_info && ms_info->alphaToOneEnable,
873 uint32_t surface_count = 0;
874 struct anv_pipeline_bind_map *map;
875 if (anv_pipeline_has_stage(pipeline, MESA_SHADER_FRAGMENT)) {
876 map = &pipeline->shaders[MESA_SHADER_FRAGMENT]->bind_map;
877 surface_count = map->surface_count;
880 const uint32_t num_dwords = GENX(BLEND_STATE_length) +
881 GENX(BLEND_STATE_ENTRY_length) * surface_count;
882 pipeline->blend_state =
883 anv_state_pool_alloc(&device->dynamic_state_pool, num_dwords * 4, 64);
885 bool has_writeable_rt = false;
886 uint32_t *state_pos = pipeline->blend_state.map;
887 state_pos += GENX(BLEND_STATE_length);
889 struct GENX(BLEND_STATE_ENTRY) bs0 = { 0 };
891 for (unsigned i = 0; i < surface_count; i++) {
892 struct anv_pipeline_binding *binding = &map->surface_to_descriptor[i];
894 /* All color attachments are at the beginning of the binding table */
895 if (binding->set != ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS)
898 /* We can have at most 8 attachments */
901 if (info == NULL || binding->index >= info->attachmentCount) {
902 /* Default everything to disabled */
903 struct GENX(BLEND_STATE_ENTRY) entry = {
904 .WriteDisableAlpha = true,
905 .WriteDisableRed = true,
906 .WriteDisableGreen = true,
907 .WriteDisableBlue = true,
909 GENX(BLEND_STATE_ENTRY_pack)(NULL, state_pos, &entry);
910 state_pos += GENX(BLEND_STATE_ENTRY_length);
914 assert(binding->binding == 0);
915 const VkPipelineColorBlendAttachmentState *a =
916 &info->pAttachments[binding->index];
918 struct GENX(BLEND_STATE_ENTRY) entry = {
920 .AlphaToCoverageEnable = ms_info && ms_info->alphaToCoverageEnable,
921 .AlphaToOneEnable = ms_info && ms_info->alphaToOneEnable,
923 .LogicOpEnable = info->logicOpEnable,
924 .LogicOpFunction = vk_to_gen_logic_op[info->logicOp],
925 .ColorBufferBlendEnable = a->blendEnable,
926 .ColorClampRange = COLORCLAMP_RTFORMAT,
927 .PreBlendColorClampEnable = true,
928 .PostBlendColorClampEnable = true,
929 .SourceBlendFactor = vk_to_gen_blend[a->srcColorBlendFactor],
930 .DestinationBlendFactor = vk_to_gen_blend[a->dstColorBlendFactor],
931 .ColorBlendFunction = vk_to_gen_blend_op[a->colorBlendOp],
932 .SourceAlphaBlendFactor = vk_to_gen_blend[a->srcAlphaBlendFactor],
933 .DestinationAlphaBlendFactor = vk_to_gen_blend[a->dstAlphaBlendFactor],
934 .AlphaBlendFunction = vk_to_gen_blend_op[a->alphaBlendOp],
935 .WriteDisableAlpha = !(a->colorWriteMask & VK_COLOR_COMPONENT_A_BIT),
936 .WriteDisableRed = !(a->colorWriteMask & VK_COLOR_COMPONENT_R_BIT),
937 .WriteDisableGreen = !(a->colorWriteMask & VK_COLOR_COMPONENT_G_BIT),
938 .WriteDisableBlue = !(a->colorWriteMask & VK_COLOR_COMPONENT_B_BIT),
941 if (a->srcColorBlendFactor != a->srcAlphaBlendFactor ||
942 a->dstColorBlendFactor != a->dstAlphaBlendFactor ||
943 a->colorBlendOp != a->alphaBlendOp) {
945 blend_state.IndependentAlphaBlendEnable = true;
947 entry.IndependentAlphaBlendEnable = true;
951 if (a->colorWriteMask != 0)
952 has_writeable_rt = true;
954 /* Our hardware applies the blend factor prior to the blend function
955 * regardless of what function is used. Technically, this means the
956 * hardware can do MORE than GL or Vulkan specify. However, it also
957 * means that, for MIN and MAX, we have to stomp the blend factor to
958 * ONE to make it a no-op.
960 if (a->colorBlendOp == VK_BLEND_OP_MIN ||
961 a->colorBlendOp == VK_BLEND_OP_MAX) {
962 entry.SourceBlendFactor = BLENDFACTOR_ONE;
963 entry.DestinationBlendFactor = BLENDFACTOR_ONE;
965 if (a->alphaBlendOp == VK_BLEND_OP_MIN ||
966 a->alphaBlendOp == VK_BLEND_OP_MAX) {
967 entry.SourceAlphaBlendFactor = BLENDFACTOR_ONE;
968 entry.DestinationAlphaBlendFactor = BLENDFACTOR_ONE;
970 GENX(BLEND_STATE_ENTRY_pack)(NULL, state_pos, &entry);
971 state_pos += GENX(BLEND_STATE_ENTRY_length);
979 anv_batch_emit(&pipeline->batch, GENX(3DSTATE_PS_BLEND), blend) {
980 blend.AlphaToCoverageEnable = blend_state.AlphaToCoverageEnable;
981 blend.HasWriteableRT = has_writeable_rt;
982 blend.ColorBufferBlendEnable = bs0.ColorBufferBlendEnable;
983 blend.SourceAlphaBlendFactor = bs0.SourceAlphaBlendFactor;
984 blend.DestinationAlphaBlendFactor = bs0.DestinationAlphaBlendFactor;
985 blend.SourceBlendFactor = bs0.SourceBlendFactor;
986 blend.DestinationBlendFactor = bs0.DestinationBlendFactor;
987 blend.AlphaTestEnable = false;
988 blend.IndependentAlphaBlendEnable =
989 blend_state.IndependentAlphaBlendEnable;
992 (void)has_writeable_rt;
995 GENX(BLEND_STATE_pack)(NULL, pipeline->blend_state.map, &blend_state);
996 anv_state_flush(device, pipeline->blend_state);
998 anv_batch_emit(&pipeline->batch, GENX(3DSTATE_BLEND_STATE_POINTERS), bsp) {
999 bsp.BlendStatePointer = pipeline->blend_state.offset;
1001 bsp.BlendStatePointerValid = true;
1007 emit_3dstate_clip(struct anv_pipeline *pipeline,
1008 const VkPipelineViewportStateCreateInfo *vp_info,
1009 const VkPipelineRasterizationStateCreateInfo *rs_info)
1011 const struct brw_wm_prog_data *wm_prog_data = get_wm_prog_data(pipeline);
1012 (void) wm_prog_data;
1013 anv_batch_emit(&pipeline->batch, GENX(3DSTATE_CLIP), clip) {
1014 clip.ClipEnable = true;
1015 clip.StatisticsEnable = true;
1016 clip.EarlyCullEnable = true;
1017 clip.APIMode = APIMODE_D3D,
1018 clip.ViewportXYClipTestEnable = true;
1020 clip.ClipMode = CLIPMODE_NORMAL;
1022 clip.TriangleStripListProvokingVertexSelect = 0;
1023 clip.LineStripListProvokingVertexSelect = 0;
1024 clip.TriangleFanProvokingVertexSelect = 1;
1026 clip.MinimumPointWidth = 0.125;
1027 clip.MaximumPointWidth = 255.875;
1029 const struct brw_vue_prog_data *last =
1030 anv_pipeline_get_last_vue_prog_data(pipeline);
1032 /* From the Vulkan 1.0.45 spec:
1034 * "If the last active vertex processing stage shader entry point's
1035 * interface does not include a variable decorated with
1036 * ViewportIndex, then the first viewport is used."
1038 if (vp_info && (last->vue_map.slots_valid & VARYING_BIT_VIEWPORT)) {
1039 clip.MaximumVPIndex = vp_info->viewportCount - 1;
1041 clip.MaximumVPIndex = 0;
1044 /* From the Vulkan 1.0.45 spec:
1046 * "If the last active vertex processing stage shader entry point's
1047 * interface does not include a variable decorated with Layer, then
1048 * the first layer is used."
1050 clip.ForceZeroRTAIndexEnable =
1051 !(last->vue_map.slots_valid & VARYING_BIT_LAYER);
1054 clip.FrontWinding = vk_to_gen_front_face[rs_info->frontFace];
1055 clip.CullMode = vk_to_gen_cullmode[rs_info->cullMode];
1056 clip.ViewportZClipTestEnable = !pipeline->depth_clamp_enable;
1058 clip.UserClipDistanceClipTestEnableBitmask = last->clip_distance_mask;
1059 clip.UserClipDistanceCullTestEnableBitmask = last->cull_distance_mask;
1062 clip.NonPerspectiveBarycentricEnable = wm_prog_data ?
1063 (wm_prog_data->barycentric_interp_modes & 0x38) != 0 : 0;
1069 emit_3dstate_streamout(struct anv_pipeline *pipeline,
1070 const VkPipelineRasterizationStateCreateInfo *rs_info)
1072 anv_batch_emit(&pipeline->batch, GENX(3DSTATE_STREAMOUT), so) {
1073 so.RenderingDisable = rs_info->rasterizerDiscardEnable;
1077 static inline uint32_t
1078 get_sampler_count(const struct anv_shader_bin *bin)
1080 return DIV_ROUND_UP(bin->bind_map.sampler_count, 4);
1083 static inline uint32_t
1084 get_binding_table_entry_count(const struct anv_shader_bin *bin)
1086 return DIV_ROUND_UP(bin->bind_map.surface_count, 32);
1089 static inline struct anv_address
1090 get_scratch_address(struct anv_pipeline *pipeline,
1091 gl_shader_stage stage,
1092 const struct anv_shader_bin *bin)
1094 return (struct anv_address) {
1095 .bo = anv_scratch_pool_alloc(pipeline->device,
1096 &pipeline->device->scratch_pool,
1097 stage, bin->prog_data->total_scratch),
1102 static inline uint32_t
1103 get_scratch_space(const struct anv_shader_bin *bin)
1105 return ffs(bin->prog_data->total_scratch / 2048);
1108 static inline uint32_t
1109 get_urb_output_offset()
1111 /* Skip the VUE header and position slots */
1115 static inline uint32_t
1116 get_urb_output_length(const struct anv_shader_bin *bin)
1118 const struct brw_vue_prog_data *prog_data =
1119 (const struct brw_vue_prog_data *)bin->prog_data;
1121 return (prog_data->vue_map.num_slots + 1) / 2 - get_urb_output_offset();
1125 emit_3dstate_vs(struct anv_pipeline *pipeline)
1127 const struct gen_device_info *devinfo = &pipeline->device->info;
1128 const struct brw_vs_prog_data *vs_prog_data = get_vs_prog_data(pipeline);
1129 const struct anv_shader_bin *vs_bin =
1130 pipeline->shaders[MESA_SHADER_VERTEX];
1132 assert(anv_pipeline_has_stage(pipeline, MESA_SHADER_VERTEX));
1134 anv_batch_emit(&pipeline->batch, GENX(3DSTATE_VS), vs) {
1135 vs.FunctionEnable = true;
1136 vs.StatisticsEnable = true;
1137 vs.KernelStartPointer = vs_bin->kernel.offset;
1139 vs.SIMD8DispatchEnable =
1140 vs_prog_data->base.dispatch_mode == DISPATCH_MODE_SIMD8;
1143 assert(!vs_prog_data->base.base.use_alt_mode);
1144 vs.SingleVertexDispatch = false;
1145 vs.VectorMaskEnable = false;
1146 vs.SamplerCount = get_sampler_count(vs_bin);
1147 vs.BindingTableEntryCount = get_binding_table_entry_count(vs_bin);
1148 vs.FloatingPointMode = IEEE754;
1149 vs.IllegalOpcodeExceptionEnable = false;
1150 vs.SoftwareExceptionEnable = false;
1151 vs.MaximumNumberofThreads = devinfo->max_vs_threads - 1;
1152 vs.VertexCacheDisable = false;
1154 vs.VertexURBEntryReadLength = vs_prog_data->base.urb_read_length;
1155 vs.VertexURBEntryReadOffset = 0;
1156 vs.DispatchGRFStartRegisterForURBData =
1157 vs_prog_data->base.base.dispatch_grf_start_reg;
1160 vs.VertexURBEntryOutputReadOffset = get_urb_output_offset();
1161 vs.VertexURBEntryOutputLength = get_urb_output_length(vs_bin);
1163 vs.UserClipDistanceClipTestEnableBitmask =
1164 vs_prog_data->base.clip_distance_mask;
1165 vs.UserClipDistanceCullTestEnableBitmask =
1166 vs_prog_data->base.cull_distance_mask;
1169 vs.PerThreadScratchSpace = get_scratch_space(vs_bin);
1170 vs.ScratchSpaceBasePointer =
1171 get_scratch_address(pipeline, MESA_SHADER_VERTEX, vs_bin);
1176 emit_3dstate_hs_te_ds(struct anv_pipeline *pipeline)
1178 if (!anv_pipeline_has_stage(pipeline, MESA_SHADER_TESS_EVAL)) {
1179 anv_batch_emit(&pipeline->batch, GENX(3DSTATE_HS), hs);
1180 anv_batch_emit(&pipeline->batch, GENX(3DSTATE_TE), te);
1181 anv_batch_emit(&pipeline->batch, GENX(3DSTATE_DS), ds);
1185 const struct gen_device_info *devinfo = &pipeline->device->info;
1186 const struct anv_shader_bin *tcs_bin =
1187 pipeline->shaders[MESA_SHADER_TESS_CTRL];
1188 const struct anv_shader_bin *tes_bin =
1189 pipeline->shaders[MESA_SHADER_TESS_EVAL];
1191 const struct brw_tcs_prog_data *tcs_prog_data = get_tcs_prog_data(pipeline);
1192 const struct brw_tes_prog_data *tes_prog_data = get_tes_prog_data(pipeline);
1194 anv_batch_emit(&pipeline->batch, GENX(3DSTATE_HS), hs) {
1195 hs.FunctionEnable = true;
1196 hs.StatisticsEnable = true;
1197 hs.KernelStartPointer = tcs_bin->kernel.offset;
1199 hs.SamplerCount = get_sampler_count(tcs_bin);
1200 hs.BindingTableEntryCount = get_binding_table_entry_count(tcs_bin);
1201 hs.MaximumNumberofThreads = devinfo->max_tcs_threads - 1;
1202 hs.IncludeVertexHandles = true;
1203 hs.InstanceCount = tcs_prog_data->instances - 1;
1205 hs.VertexURBEntryReadLength = 0;
1206 hs.VertexURBEntryReadOffset = 0;
1207 hs.DispatchGRFStartRegisterForURBData =
1208 tcs_prog_data->base.base.dispatch_grf_start_reg;
1210 hs.PerThreadScratchSpace = get_scratch_space(tcs_bin);
1211 hs.ScratchSpaceBasePointer =
1212 get_scratch_address(pipeline, MESA_SHADER_TESS_CTRL, tcs_bin);
1215 anv_batch_emit(&pipeline->batch, GENX(3DSTATE_TE), te) {
1216 te.Partitioning = tes_prog_data->partitioning;
1217 te.OutputTopology = tes_prog_data->output_topology;
1218 te.TEDomain = tes_prog_data->domain;
1220 te.MaximumTessellationFactorOdd = 63.0;
1221 te.MaximumTessellationFactorNotOdd = 64.0;
1224 anv_batch_emit(&pipeline->batch, GENX(3DSTATE_DS), ds) {
1225 ds.FunctionEnable = true;
1226 ds.StatisticsEnable = true;
1227 ds.KernelStartPointer = tes_bin->kernel.offset;
1229 ds.SamplerCount = get_sampler_count(tes_bin);
1230 ds.BindingTableEntryCount = get_binding_table_entry_count(tes_bin);
1231 ds.MaximumNumberofThreads = devinfo->max_tes_threads - 1;
1233 ds.ComputeWCoordinateEnable =
1234 tes_prog_data->domain == BRW_TESS_DOMAIN_TRI;
1236 ds.PatchURBEntryReadLength = tes_prog_data->base.urb_read_length;
1237 ds.PatchURBEntryReadOffset = 0;
1238 ds.DispatchGRFStartRegisterForURBData =
1239 tes_prog_data->base.base.dispatch_grf_start_reg;
1242 ds.VertexURBEntryOutputReadOffset = 1;
1243 ds.VertexURBEntryOutputLength =
1244 (tes_prog_data->base.vue_map.num_slots + 1) / 2 - 1;
1247 tes_prog_data->base.dispatch_mode == DISPATCH_MODE_SIMD8 ?
1248 DISPATCH_MODE_SIMD8_SINGLE_PATCH :
1249 DISPATCH_MODE_SIMD4X2;
1251 ds.UserClipDistanceClipTestEnableBitmask =
1252 tes_prog_data->base.clip_distance_mask;
1253 ds.UserClipDistanceCullTestEnableBitmask =
1254 tes_prog_data->base.cull_distance_mask;
1257 ds.PerThreadScratchSpace = get_scratch_space(tes_bin);
1258 ds.ScratchSpaceBasePointer =
1259 get_scratch_address(pipeline, MESA_SHADER_TESS_EVAL, tes_bin);
1264 emit_3dstate_gs(struct anv_pipeline *pipeline)
1266 const struct gen_device_info *devinfo = &pipeline->device->info;
1267 const struct anv_shader_bin *gs_bin =
1268 pipeline->shaders[MESA_SHADER_GEOMETRY];
1270 if (!anv_pipeline_has_stage(pipeline, MESA_SHADER_GEOMETRY)) {
1271 anv_batch_emit(&pipeline->batch, GENX(3DSTATE_GS), gs);
1275 const struct brw_gs_prog_data *gs_prog_data = get_gs_prog_data(pipeline);
1277 anv_batch_emit(&pipeline->batch, GENX(3DSTATE_GS), gs) {
1278 gs.FunctionEnable = true;
1279 gs.StatisticsEnable = true;
1280 gs.KernelStartPointer = gs_bin->kernel.offset;
1281 gs.DispatchMode = gs_prog_data->base.dispatch_mode;
1283 gs.SingleProgramFlow = false;
1284 gs.VectorMaskEnable = false;
1285 gs.SamplerCount = get_sampler_count(gs_bin);
1286 gs.BindingTableEntryCount = get_binding_table_entry_count(gs_bin);
1287 gs.IncludeVertexHandles = gs_prog_data->base.include_vue_handles;
1288 gs.IncludePrimitiveID = gs_prog_data->include_primitive_id;
1291 /* Broadwell is weird. It needs us to divide by 2. */
1292 gs.MaximumNumberofThreads = devinfo->max_gs_threads / 2 - 1;
1294 gs.MaximumNumberofThreads = devinfo->max_gs_threads - 1;
1297 gs.OutputVertexSize = gs_prog_data->output_vertex_size_hwords * 2 - 1;
1298 gs.OutputTopology = gs_prog_data->output_topology;
1299 gs.VertexURBEntryReadLength = gs_prog_data->base.urb_read_length;
1300 gs.ControlDataFormat = gs_prog_data->control_data_format;
1301 gs.ControlDataHeaderSize = gs_prog_data->control_data_header_size_hwords;
1302 gs.InstanceControl = MAX2(gs_prog_data->invocations, 1) - 1;
1303 #if GEN_GEN >= 8 || GEN_IS_HASWELL
1304 gs.ReorderMode = TRAILING;
1306 gs.ReorderEnable = true;
1310 gs.ExpectedVertexCount = gs_prog_data->vertices_in;
1311 gs.StaticOutput = gs_prog_data->static_vertex_count >= 0;
1312 gs.StaticOutputVertexCount = gs_prog_data->static_vertex_count >= 0 ?
1313 gs_prog_data->static_vertex_count : 0;
1316 gs.VertexURBEntryReadOffset = 0;
1317 gs.VertexURBEntryReadLength = gs_prog_data->base.urb_read_length;
1318 gs.DispatchGRFStartRegisterForURBData =
1319 gs_prog_data->base.base.dispatch_grf_start_reg;
1322 gs.VertexURBEntryOutputReadOffset = get_urb_output_offset();
1323 gs.VertexURBEntryOutputLength = get_urb_output_length(gs_bin);
1325 gs.UserClipDistanceClipTestEnableBitmask =
1326 gs_prog_data->base.clip_distance_mask;
1327 gs.UserClipDistanceCullTestEnableBitmask =
1328 gs_prog_data->base.cull_distance_mask;
1331 gs.PerThreadScratchSpace = get_scratch_space(gs_bin);
1332 gs.ScratchSpaceBasePointer =
1333 get_scratch_address(pipeline, MESA_SHADER_GEOMETRY, gs_bin);
1338 has_color_buffer_write_enabled(const struct anv_pipeline *pipeline)
1340 const struct anv_shader_bin *shader_bin =
1341 pipeline->shaders[MESA_SHADER_FRAGMENT];
1345 const struct anv_pipeline_bind_map *bind_map = &shader_bin->bind_map;
1346 for (int i = 0; i < bind_map->surface_count; i++) {
1347 if (bind_map->surface_to_descriptor[i].set !=
1348 ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS)
1350 if (bind_map->surface_to_descriptor[i].index != UINT8_MAX)
1358 emit_3dstate_wm(struct anv_pipeline *pipeline, struct anv_subpass *subpass,
1359 const VkPipelineMultisampleStateCreateInfo *multisample)
1361 const struct brw_wm_prog_data *wm_prog_data = get_wm_prog_data(pipeline);
1363 MAYBE_UNUSED uint32_t samples =
1364 multisample ? multisample->rasterizationSamples : 1;
1366 anv_batch_emit(&pipeline->batch, GENX(3DSTATE_WM), wm) {
1367 wm.StatisticsEnable = true;
1368 wm.LineEndCapAntialiasingRegionWidth = _05pixels;
1369 wm.LineAntialiasingRegionWidth = _10pixels;
1370 wm.PointRasterizationRule = RASTRULE_UPPER_RIGHT;
1372 if (anv_pipeline_has_stage(pipeline, MESA_SHADER_FRAGMENT)) {
1373 if (wm_prog_data->early_fragment_tests) {
1374 wm.EarlyDepthStencilControl = EDSC_PREPS;
1375 } else if (wm_prog_data->has_side_effects) {
1376 wm.EarlyDepthStencilControl = EDSC_PSEXEC;
1378 wm.EarlyDepthStencilControl = EDSC_NORMAL;
1381 wm.BarycentricInterpolationMode =
1382 wm_prog_data->barycentric_interp_modes;
1385 wm.PixelShaderComputedDepthMode = wm_prog_data->computed_depth_mode;
1386 wm.PixelShaderUsesSourceDepth = wm_prog_data->uses_src_depth;
1387 wm.PixelShaderUsesSourceW = wm_prog_data->uses_src_w;
1388 wm.PixelShaderUsesInputCoverageMask = wm_prog_data->uses_sample_mask;
1390 /* If the subpass has a depth or stencil self-dependency, then we
1391 * need to force the hardware to do the depth/stencil write *after*
1392 * fragment shader execution. Otherwise, the writes may hit memory
1393 * before we get around to fetching from the input attachment and we
1394 * may get the depth or stencil value from the current draw rather
1395 * than the previous one.
1397 wm.PixelShaderKillsPixel = subpass->has_ds_self_dep ||
1398 wm_prog_data->uses_kill;
1400 if (wm.PixelShaderComputedDepthMode != PSCDEPTH_OFF ||
1401 wm_prog_data->has_side_effects ||
1402 wm.PixelShaderKillsPixel ||
1403 has_color_buffer_write_enabled(pipeline))
1404 wm.ThreadDispatchEnable = true;
1407 wm.MultisampleRasterizationMode = MSRASTMODE_ON_PATTERN;
1408 if (wm_prog_data->persample_dispatch) {
1409 wm.MultisampleDispatchMode = MSDISPMODE_PERSAMPLE;
1411 wm.MultisampleDispatchMode = MSDISPMODE_PERPIXEL;
1414 wm.MultisampleRasterizationMode = MSRASTMODE_OFF_PIXEL;
1415 wm.MultisampleDispatchMode = MSDISPMODE_PERSAMPLE;
1423 is_dual_src_blend_factor(VkBlendFactor factor)
1425 return factor == VK_BLEND_FACTOR_SRC1_COLOR ||
1426 factor == VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR ||
1427 factor == VK_BLEND_FACTOR_SRC1_ALPHA ||
1428 factor == VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA;
1432 emit_3dstate_ps(struct anv_pipeline *pipeline,
1433 const VkPipelineColorBlendStateCreateInfo *blend)
1435 MAYBE_UNUSED const struct gen_device_info *devinfo = &pipeline->device->info;
1436 const struct anv_shader_bin *fs_bin =
1437 pipeline->shaders[MESA_SHADER_FRAGMENT];
1439 if (!anv_pipeline_has_stage(pipeline, MESA_SHADER_FRAGMENT)) {
1440 anv_batch_emit(&pipeline->batch, GENX(3DSTATE_PS), ps) {
1442 /* Even if no fragments are ever dispatched, gen7 hardware hangs if
1443 * we don't at least set the maximum number of threads.
1445 ps.MaximumNumberofThreads = devinfo->max_wm_threads - 1;
1451 const struct brw_wm_prog_data *wm_prog_data = get_wm_prog_data(pipeline);
1454 /* The hardware wedges if you have this bit set but don't turn on any dual
1455 * source blend factors.
1457 bool dual_src_blend = false;
1458 if (wm_prog_data->dual_src_blend && blend) {
1459 for (uint32_t i = 0; i < blend->attachmentCount; i++) {
1460 const VkPipelineColorBlendAttachmentState *bstate =
1461 &blend->pAttachments[i];
1463 if (bstate->blendEnable &&
1464 (is_dual_src_blend_factor(bstate->srcColorBlendFactor) ||
1465 is_dual_src_blend_factor(bstate->dstColorBlendFactor) ||
1466 is_dual_src_blend_factor(bstate->srcAlphaBlendFactor) ||
1467 is_dual_src_blend_factor(bstate->dstAlphaBlendFactor))) {
1468 dual_src_blend = true;
1475 anv_batch_emit(&pipeline->batch, GENX(3DSTATE_PS), ps) {
1476 ps.KernelStartPointer0 = fs_bin->kernel.offset;
1477 ps.KernelStartPointer1 = 0;
1478 ps.KernelStartPointer2 = fs_bin->kernel.offset +
1479 wm_prog_data->prog_offset_2;
1480 ps._8PixelDispatchEnable = wm_prog_data->dispatch_8;
1481 ps._16PixelDispatchEnable = wm_prog_data->dispatch_16;
1482 ps._32PixelDispatchEnable = false;
1484 ps.SingleProgramFlow = false;
1485 ps.VectorMaskEnable = true;
1486 ps.SamplerCount = get_sampler_count(fs_bin);
1487 ps.BindingTableEntryCount = get_binding_table_entry_count(fs_bin);
1488 ps.PushConstantEnable = wm_prog_data->base.nr_params > 0;
1489 ps.PositionXYOffsetSelect = wm_prog_data->uses_pos_offset ?
1490 POSOFFSET_SAMPLE: POSOFFSET_NONE;
1492 ps.AttributeEnable = wm_prog_data->num_varying_inputs > 0;
1493 ps.oMaskPresenttoRenderTarget = wm_prog_data->uses_omask;
1494 ps.DualSourceBlendEnable = dual_src_blend;
1498 /* Haswell requires the sample mask to be set in this packet as well
1499 * as in 3DSTATE_SAMPLE_MASK; the values should match.
1501 ps.SampleMask = 0xff;
1505 ps.MaximumNumberofThreadsPerPSD = 64 - 1;
1507 ps.MaximumNumberofThreadsPerPSD = 64 - 2;
1509 ps.MaximumNumberofThreads = devinfo->max_wm_threads - 1;
1512 ps.DispatchGRFStartRegisterForConstantSetupData0 =
1513 wm_prog_data->base.dispatch_grf_start_reg;
1514 ps.DispatchGRFStartRegisterForConstantSetupData1 = 0;
1515 ps.DispatchGRFStartRegisterForConstantSetupData2 =
1516 wm_prog_data->dispatch_grf_start_reg_2;
1518 ps.PerThreadScratchSpace = get_scratch_space(fs_bin);
1519 ps.ScratchSpaceBasePointer =
1520 get_scratch_address(pipeline, MESA_SHADER_FRAGMENT, fs_bin);
1526 emit_3dstate_ps_extra(struct anv_pipeline *pipeline,
1527 struct anv_subpass *subpass)
1529 const struct brw_wm_prog_data *wm_prog_data = get_wm_prog_data(pipeline);
1531 if (!anv_pipeline_has_stage(pipeline, MESA_SHADER_FRAGMENT)) {
1532 anv_batch_emit(&pipeline->batch, GENX(3DSTATE_PS_EXTRA), ps);
1536 anv_batch_emit(&pipeline->batch, GENX(3DSTATE_PS_EXTRA), ps) {
1537 ps.PixelShaderValid = true;
1538 ps.AttributeEnable = wm_prog_data->num_varying_inputs > 0;
1539 ps.oMaskPresenttoRenderTarget = wm_prog_data->uses_omask;
1540 ps.PixelShaderIsPerSample = wm_prog_data->persample_dispatch;
1541 ps.PixelShaderComputedDepthMode = wm_prog_data->computed_depth_mode;
1542 ps.PixelShaderUsesSourceDepth = wm_prog_data->uses_src_depth;
1543 ps.PixelShaderUsesSourceW = wm_prog_data->uses_src_w;
1545 /* If the subpass has a depth or stencil self-dependency, then we need
1546 * to force the hardware to do the depth/stencil write *after* fragment
1547 * shader execution. Otherwise, the writes may hit memory before we get
1548 * around to fetching from the input attachment and we may get the depth
1549 * or stencil value from the current draw rather than the previous one.
1551 ps.PixelShaderKillsPixel = subpass->has_ds_self_dep ||
1552 wm_prog_data->uses_kill;
1554 /* The stricter cross-primitive coherency guarantees that the hardware
1555 * gives us with the "Accesses UAV" bit set for at least one shader stage
1556 * and the "UAV coherency required" bit set on the 3DPRIMITIVE command are
1557 * redundant within the current image, atomic counter and SSBO GL APIs,
1558 * which all have very loose ordering and coherency requirements and
1559 * generally rely on the application to insert explicit barriers when a
1560 * shader invocation is expected to see the memory writes performed by the
1561 * invocations of some previous primitive. Regardless of the value of
1562 * "UAV coherency required", the "Accesses UAV" bits will implicitly cause
1563 * an in most cases useless DC flush when the lowermost stage with the bit
1564 * set finishes execution.
1566 * It would be nice to disable it, but in some cases we can't because on
1567 * Gen8+ it also has an influence on rasterization via the PS UAV-only
1568 * signal (which could be set independently from the coherency mechanism
1569 * in the 3DSTATE_WM command on Gen7), and because in some cases it will
1570 * determine whether the hardware skips execution of the fragment shader
1571 * or not via the ThreadDispatchEnable signal. However if we know that
1572 * GEN8_PS_BLEND_HAS_WRITEABLE_RT is going to be set and
1573 * GEN8_PSX_PIXEL_SHADER_NO_RT_WRITE is not set it shouldn't make any
1574 * difference so we may just disable it here.
1576 * Gen8 hardware tries to compute ThreadDispatchEnable for us but doesn't
1577 * take into account KillPixels when no depth or stencil writes are
1578 * enabled. In order for occlusion queries to work correctly with no
1579 * attachments, we need to force-enable here.
1581 if ((wm_prog_data->has_side_effects || wm_prog_data->uses_kill) &&
1582 !has_color_buffer_write_enabled(pipeline))
1583 ps.PixelShaderHasUAV = true;
1586 ps.PixelShaderPullsBary = wm_prog_data->pulls_bary;
1587 ps.InputCoverageMaskState = wm_prog_data->uses_sample_mask ?
1588 ICMS_INNER_CONSERVATIVE : ICMS_NONE;
1590 ps.PixelShaderUsesInputCoverageMask = wm_prog_data->uses_sample_mask;
1596 emit_3dstate_vf_topology(struct anv_pipeline *pipeline)
1598 anv_batch_emit(&pipeline->batch, GENX(3DSTATE_VF_TOPOLOGY), vft) {
1599 vft.PrimitiveTopologyType = pipeline->topology;
1605 emit_3dstate_vf_statistics(struct anv_pipeline *pipeline)
1607 anv_batch_emit(&pipeline->batch, GENX(3DSTATE_VF_STATISTICS), vfs) {
1608 vfs.StatisticsEnable = true;
1613 compute_kill_pixel(struct anv_pipeline *pipeline,
1614 const VkPipelineMultisampleStateCreateInfo *ms_info,
1615 const struct anv_subpass *subpass)
1617 if (!anv_pipeline_has_stage(pipeline, MESA_SHADER_FRAGMENT)) {
1618 pipeline->kill_pixel = false;
1622 const struct brw_wm_prog_data *wm_prog_data = get_wm_prog_data(pipeline);
1624 /* This computes the KillPixel portion of the computation for whether or
1625 * not we want to enable the PMA fix on gen8 or gen9. It's given by this
1626 * chunk of the giant formula:
1628 * (3DSTATE_PS_EXTRA::PixelShaderKillsPixels ||
1629 * 3DSTATE_PS_EXTRA::oMask Present to RenderTarget ||
1630 * 3DSTATE_PS_BLEND::AlphaToCoverageEnable ||
1631 * 3DSTATE_PS_BLEND::AlphaTestEnable ||
1632 * 3DSTATE_WM_CHROMAKEY::ChromaKeyKillEnable)
1634 * 3DSTATE_WM_CHROMAKEY::ChromaKeyKillEnable is always false and so is
1635 * 3DSTATE_PS_BLEND::AlphaTestEnable since Vulkan doesn't have a concept
1638 pipeline->kill_pixel =
1639 subpass->has_ds_self_dep || wm_prog_data->uses_kill ||
1640 wm_prog_data->uses_omask ||
1641 (ms_info && ms_info->alphaToCoverageEnable);
1645 genX(graphics_pipeline_create)(
1647 struct anv_pipeline_cache * cache,
1648 const VkGraphicsPipelineCreateInfo* pCreateInfo,
1649 const VkAllocationCallbacks* pAllocator,
1650 VkPipeline* pPipeline)
1652 ANV_FROM_HANDLE(anv_device, device, _device);
1653 ANV_FROM_HANDLE(anv_render_pass, pass, pCreateInfo->renderPass);
1654 struct anv_subpass *subpass = &pass->subpasses[pCreateInfo->subpass];
1655 struct anv_pipeline *pipeline;
1658 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO);
1660 pipeline = vk_alloc2(&device->alloc, pAllocator, sizeof(*pipeline), 8,
1661 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1662 if (pipeline == NULL)
1663 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
1665 result = anv_pipeline_init(pipeline, device, cache,
1666 pCreateInfo, pAllocator);
1667 if (result != VK_SUCCESS) {
1668 vk_free2(&device->alloc, pAllocator, pipeline);
1672 assert(pCreateInfo->pVertexInputState);
1673 emit_vertex_input(pipeline, pCreateInfo->pVertexInputState);
1674 assert(pCreateInfo->pRasterizationState);
1675 emit_rs_state(pipeline, pCreateInfo->pRasterizationState,
1676 pCreateInfo->pMultisampleState, pass, subpass);
1677 emit_ms_state(pipeline, pCreateInfo->pMultisampleState);
1678 emit_ds_state(pipeline, pCreateInfo->pDepthStencilState, pass, subpass);
1679 emit_cb_state(pipeline, pCreateInfo->pColorBlendState,
1680 pCreateInfo->pMultisampleState);
1681 compute_kill_pixel(pipeline, pCreateInfo->pMultisampleState, subpass);
1683 emit_urb_setup(pipeline);
1685 emit_3dstate_clip(pipeline, pCreateInfo->pViewportState,
1686 pCreateInfo->pRasterizationState);
1687 emit_3dstate_streamout(pipeline, pCreateInfo->pRasterizationState);
1690 /* From gen7_vs_state.c */
1693 * From Graphics BSpec: 3D-Media-GPGPU Engine > 3D Pipeline Stages >
1694 * Geometry > Geometry Shader > State:
1696 * "Note: Because of corruption in IVB:GT2, software needs to flush the
1697 * whole fixed function pipeline when the GS enable changes value in
1700 * The hardware architects have clarified that in this context "flush the
1701 * whole fixed function pipeline" means to emit a PIPE_CONTROL with the "CS
1704 if (!brw->is_haswell && !brw->is_baytrail)
1705 gen7_emit_vs_workaround_flush(brw);
1708 emit_3dstate_vs(pipeline);
1709 emit_3dstate_hs_te_ds(pipeline);
1710 emit_3dstate_gs(pipeline);
1711 emit_3dstate_sbe(pipeline);
1712 emit_3dstate_wm(pipeline, subpass, pCreateInfo->pMultisampleState);
1713 emit_3dstate_ps(pipeline, pCreateInfo->pColorBlendState);
1715 emit_3dstate_ps_extra(pipeline, subpass);
1716 emit_3dstate_vf_topology(pipeline);
1718 emit_3dstate_vf_statistics(pipeline);
1720 *pPipeline = anv_pipeline_to_handle(pipeline);
1722 return pipeline->batch.status;
1726 compute_pipeline_create(
1728 struct anv_pipeline_cache * cache,
1729 const VkComputePipelineCreateInfo* pCreateInfo,
1730 const VkAllocationCallbacks* pAllocator,
1731 VkPipeline* pPipeline)
1733 ANV_FROM_HANDLE(anv_device, device, _device);
1734 const struct anv_physical_device *physical_device =
1735 &device->instance->physicalDevice;
1736 const struct gen_device_info *devinfo = &physical_device->info;
1737 struct anv_pipeline *pipeline;
1740 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_COMPUTE_PIPELINE_CREATE_INFO);
1742 pipeline = vk_alloc2(&device->alloc, pAllocator, sizeof(*pipeline), 8,
1743 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1744 if (pipeline == NULL)
1745 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
1747 pipeline->device = device;
1748 pipeline->layout = anv_pipeline_layout_from_handle(pCreateInfo->layout);
1750 pipeline->blend_state.map = NULL;
1752 result = anv_reloc_list_init(&pipeline->batch_relocs,
1753 pAllocator ? pAllocator : &device->alloc);
1754 if (result != VK_SUCCESS) {
1755 vk_free2(&device->alloc, pAllocator, pipeline);
1758 pipeline->batch.next = pipeline->batch.start = pipeline->batch_data;
1759 pipeline->batch.end = pipeline->batch.start + sizeof(pipeline->batch_data);
1760 pipeline->batch.relocs = &pipeline->batch_relocs;
1761 pipeline->batch.status = VK_SUCCESS;
1763 /* When we free the pipeline, we detect stages based on the NULL status
1764 * of various prog_data pointers. Make them NULL by default.
1766 memset(pipeline->shaders, 0, sizeof(pipeline->shaders));
1768 pipeline->active_stages = 0;
1770 pipeline->needs_data_cache = false;
1772 assert(pCreateInfo->stage.stage == VK_SHADER_STAGE_COMPUTE_BIT);
1773 ANV_FROM_HANDLE(anv_shader_module, module, pCreateInfo->stage.module);
1774 result = anv_pipeline_compile_cs(pipeline, cache, pCreateInfo, module,
1775 pCreateInfo->stage.pName,
1776 pCreateInfo->stage.pSpecializationInfo);
1777 if (result != VK_SUCCESS) {
1778 vk_free2(&device->alloc, pAllocator, pipeline);
1782 const struct brw_cs_prog_data *cs_prog_data = get_cs_prog_data(pipeline);
1784 anv_pipeline_setup_l3_config(pipeline, cs_prog_data->base.total_shared > 0);
1786 uint32_t group_size = cs_prog_data->local_size[0] *
1787 cs_prog_data->local_size[1] * cs_prog_data->local_size[2];
1788 uint32_t remainder = group_size & (cs_prog_data->simd_size - 1);
1791 pipeline->cs_right_mask = ~0u >> (32 - remainder);
1793 pipeline->cs_right_mask = ~0u >> (32 - cs_prog_data->simd_size);
1795 const uint32_t vfe_curbe_allocation =
1796 ALIGN(cs_prog_data->push.per_thread.regs * cs_prog_data->threads +
1797 cs_prog_data->push.cross_thread.regs, 2);
1799 const uint32_t subslices = MAX2(physical_device->subslice_total, 1);
1801 const struct anv_shader_bin *cs_bin =
1802 pipeline->shaders[MESA_SHADER_COMPUTE];
1804 anv_batch_emit(&pipeline->batch, GENX(MEDIA_VFE_STATE), vfe) {
1808 vfe.GPGPUMode = true;
1810 vfe.MaximumNumberofThreads =
1811 devinfo->max_cs_threads * subslices - 1;
1812 vfe.NumberofURBEntries = GEN_GEN <= 7 ? 0 : 2;
1813 vfe.ResetGatewayTimer = true;
1815 vfe.BypassGatewayControl = true;
1817 vfe.URBEntryAllocationSize = GEN_GEN <= 7 ? 0 : 2;
1818 vfe.CURBEAllocationSize = vfe_curbe_allocation;
1820 vfe.PerThreadScratchSpace = get_scratch_space(cs_bin);
1821 vfe.ScratchSpaceBasePointer =
1822 get_scratch_address(pipeline, MESA_SHADER_COMPUTE, cs_bin);
1825 struct GENX(INTERFACE_DESCRIPTOR_DATA) desc = {
1826 .KernelStartPointer = cs_bin->kernel.offset,
1828 .SamplerCount = get_sampler_count(cs_bin),
1829 .BindingTableEntryCount = get_binding_table_entry_count(cs_bin),
1830 .BarrierEnable = cs_prog_data->uses_barrier,
1831 .SharedLocalMemorySize =
1832 encode_slm_size(GEN_GEN, cs_prog_data->base.total_shared),
1835 .ConstantURBEntryReadOffset = 0,
1837 .ConstantURBEntryReadLength = cs_prog_data->push.per_thread.regs,
1838 #if GEN_GEN >= 8 || GEN_IS_HASWELL
1839 .CrossThreadConstantDataReadLength =
1840 cs_prog_data->push.cross_thread.regs,
1843 .NumberofThreadsinGPGPUThreadGroup = cs_prog_data->threads,
1845 GENX(INTERFACE_DESCRIPTOR_DATA_pack)(NULL,
1846 pipeline->interface_descriptor_data,
1849 *pPipeline = anv_pipeline_to_handle(pipeline);
1851 return pipeline->batch.status;
1854 VkResult genX(CreateGraphicsPipelines)(
1856 VkPipelineCache pipelineCache,
1858 const VkGraphicsPipelineCreateInfo* pCreateInfos,
1859 const VkAllocationCallbacks* pAllocator,
1860 VkPipeline* pPipelines)
1862 ANV_FROM_HANDLE(anv_pipeline_cache, pipeline_cache, pipelineCache);
1864 VkResult result = VK_SUCCESS;
1867 for (i = 0; i < count; i++) {
1868 result = genX(graphics_pipeline_create)(_device,
1871 pAllocator, &pPipelines[i]);
1873 /* Bail out on the first error as it is not obvious what error should be
1874 * report upon 2 different failures. */
1875 if (result != VK_SUCCESS)
1879 for (; i < count; i++)
1880 pPipelines[i] = VK_NULL_HANDLE;
1885 VkResult genX(CreateComputePipelines)(
1887 VkPipelineCache pipelineCache,
1889 const VkComputePipelineCreateInfo* pCreateInfos,
1890 const VkAllocationCallbacks* pAllocator,
1891 VkPipeline* pPipelines)
1893 ANV_FROM_HANDLE(anv_pipeline_cache, pipeline_cache, pipelineCache);
1895 VkResult result = VK_SUCCESS;
1898 for (i = 0; i < count; i++) {
1899 result = compute_pipeline_create(_device, pipeline_cache,
1901 pAllocator, &pPipelines[i]);
1903 /* Bail out on the first error as it is not obvious what error should be
1904 * report upon 2 different failures. */
1905 if (result != VK_SUCCESS)
1909 for (; i < count; i++)
1910 pPipelines[i] = VK_NULL_HANDLE;