1 #ifndef _INTEL_DRIVER_H_
2 #define _INTEL_DRIVER_H_
11 #include <intel_bufmgr.h>
13 #include <va/va_backend.h>
14 #include "va_backend_compat.h"
16 #include "intel_compiler.h"
18 #define BATCH_SIZE 0x80000
19 #define BATCH_RESERVED 0x10
21 #define CMD_MI (0x0 << 29)
22 #define CMD_2D (0x2 << 29)
23 #define CMD_3D (0x3 << 29)
25 #define MI_NOOP (CMD_MI | 0)
27 #define MI_BATCH_BUFFER_END (CMD_MI | (0xA << 23))
28 #define MI_BATCH_BUFFER_START (CMD_MI | (0x31 << 23))
30 #define MI_FLUSH (CMD_MI | (0x4 << 23))
31 #define MI_FLUSH_STATE_INSTRUCTION_CACHE_INVALIDATE (0x1 << 0)
33 #define MI_FLUSH_DW (CMD_MI | (0x26 << 23) | 0x2)
34 #define MI_FLUSH_DW2 (CMD_MI | (0x26 << 23) | 0x3)
35 #define MI_FLUSH_DW_VIDEO_PIPELINE_CACHE_INVALIDATE (0x1 << 7)
36 #define MI_FLUSH_DW_NOWRITE (0 << 14)
37 #define MI_FLUSH_DW_WRITE_QWORD (1 << 14)
38 #define MI_FLUSH_DW_WRITE_TIME (3 << 14)
40 #define MI_STORE_DATA_IMM (CMD_MI | (0x20 << 23))
42 #define MI_STORE_REGISTER_MEM (CMD_MI | (0x24 << 23))
44 #define MI_LOAD_REGISTER_IMM (CMD_MI | (0x22 << 23))
46 #define MI_LOAD_REGISTER_MEM (CMD_MI | (0x29 << 23))
48 #define MI_LOAD_REGISTER_REG (CMD_MI | (0x2A << 23))
50 #define MI_MATH (CMD_MI | (0x1A << 23))
52 #define MI_CONDITIONAL_BATCH_BUFFER_END (CMD_MI | (0x36 << 23))
53 #define MI_COMPARE_MASK_MODE_ENANBLED (1 << 19)
55 #define XY_COLOR_BLT_CMD (CMD_2D | (0x50 << 22) | 0x04)
56 #define XY_COLOR_BLT_WRITE_ALPHA (1 << 21)
57 #define XY_COLOR_BLT_WRITE_RGB (1 << 20)
58 #define XY_COLOR_BLT_DST_TILED (1 << 11)
60 #define GEN8_XY_COLOR_BLT_CMD (CMD_2D | (0x50 << 22) | 0x05)
63 #define BR13_8 (0x0 << 24)
64 #define BR13_565 (0x1 << 24)
65 #define BR13_1555 (0x2 << 24)
66 #define BR13_8888 (0x3 << 24)
68 #define CMD_PIPE_CONTROL (CMD_3D | (3 << 27) | (2 << 24) | (0 << 16))
69 #define CMD_PIPE_CONTROL_CS_STALL (1 << 20)
70 #define CMD_PIPE_CONTROL_NOWRITE (0 << 14)
71 #define CMD_PIPE_CONTROL_WRITE_QWORD (1 << 14)
72 #define CMD_PIPE_CONTROL_WRITE_DEPTH (2 << 14)
73 #define CMD_PIPE_CONTROL_WRITE_TIME (3 << 14)
74 #define CMD_PIPE_CONTROL_DEPTH_STALL (1 << 13)
75 #define CMD_PIPE_CONTROL_WC_FLUSH (1 << 12)
76 #define CMD_PIPE_CONTROL_IS_FLUSH (1 << 11)
77 #define CMD_PIPE_CONTROL_TC_FLUSH (1 << 10)
78 #define CMD_PIPE_CONTROL_NOTIFY_ENABLE (1 << 8)
79 #define CMD_PIPE_CONTROL_FLUSH_ENABLE (1 << 7)
80 #define CMD_PIPE_CONTROL_DC_FLUSH (1 << 5)
81 #define CMD_PIPE_CONTROL_GLOBAL_GTT (1 << 2)
82 #define CMD_PIPE_CONTROL_LOCAL_PGTT (0 << 2)
83 #define CMD_PIPE_CONTROL_STALL_AT_SCOREBOARD (1 << 1)
84 #define CMD_PIPE_CONTROL_DEPTH_CACHE_FLUSH (1 << 0)
86 #define CMD_PIPE_CONTROL_GLOBAL_GTT_GEN8 (1 << 24)
87 #define CMD_PIPE_CONTROL_LOCAL_PGTT_GEN8 (0 << 24)
88 #define CMD_PIPE_CONTROL_VFC_INVALIDATION_GEN8 (1 << 4)
89 #define CMD_PIPE_CONTROL_CC_INVALIDATION_GEN8 (1 << 3)
90 #define CMD_PIPE_CONTROL_SC_INVALIDATION_GEN8 (1 << 2)
92 struct intel_batchbuffer;
94 #define ALIGN(i, n) (((i) + (n) - 1) & ~((n) - 1))
95 #define IS_ALIGNED(i, n) (((i) & ((n)-1)) == 0)
96 #define MIN(a, b) ((a) < (b) ? (a) : (b))
97 #define MAX(a, b) ((a) > (b) ? (a) : (b))
98 #define ARRAY_ELEMS(a) (sizeof(a) / sizeof((a)[0]))
99 #define CLAMP(min, max, a) ((a) < (min) ? (min) : ((a) > (max) ? (max) : (a)))
101 #define ALIGN_FLOOR(i, n) ((i) & ~((n) - 1))
107 extern uint32_t g_intel_debug_option_flags;
108 #define VA_INTEL_DEBUG_OPTION_ASSERT (1 << 0)
109 #define VA_INTEL_DEBUG_OPTION_BENCH (1 << 1)
110 #define VA_INTEL_DEBUG_OPTION_DUMP_AUB (1 << 2)
112 #define ASSERT_RET(value, fail_ret) do { \
114 if (g_intel_debug_option_flags & VA_INTEL_DEBUG_OPTION_ASSERT) \
120 #define SET_BLOCKED_SIGSET() do { \
122 sigfillset(&bl_mask); \
123 sigdelset(&bl_mask, SIGFPE); \
124 sigdelset(&bl_mask, SIGILL); \
125 sigdelset(&bl_mask, SIGSEGV); \
126 sigdelset(&bl_mask, SIGBUS); \
127 sigdelset(&bl_mask, SIGKILL); \
128 pthread_sigmask(SIG_SETMASK, &bl_mask, &intel->sa_mask); \
131 #define RESTORE_BLOCKED_SIGSET() do { \
132 pthread_sigmask(SIG_SETMASK, &intel->sa_mask, NULL); \
135 #define PPTHREAD_MUTEX_LOCK() do { \
136 SET_BLOCKED_SIGSET(); \
137 pthread_mutex_lock(&intel->ctxmutex); \
140 #define PPTHREAD_MUTEX_UNLOCK() do { \
141 pthread_mutex_unlock(&intel->ctxmutex); \
142 RESTORE_BLOCKED_SIGSET(); \
145 #define WARN_ONCE(...) do { \
146 static int g_once = 1; \
149 fprintf(stderr, "WARNING: " __VA_ARGS__); \
153 struct intel_device_info {
157 unsigned int urb_size;
158 unsigned int max_wm_threads;
160 unsigned int is_g4x : 1; /* gen4 */
161 unsigned int is_ivybridge : 1; /* gen7 */
162 unsigned int is_baytrail : 1; /* gen7 */
163 unsigned int is_haswell : 1; /* gen7 */
164 unsigned int is_cherryview : 1; /* gen8 */
165 unsigned int is_skylake : 1; /* gen9 */
166 unsigned int is_broxton : 1; /* gen9 */
167 unsigned int is_kabylake : 1; /* gen9p5 */
168 unsigned int is_glklake : 1; /* gen9p5 lp*/
171 struct intel_driver_data {
179 pthread_mutex_t ctxmutex;
184 unsigned int has_exec2 : 1; /* Flag: has execbuffer2? */
185 unsigned int has_bsd : 1; /* Flag: has bitstream decoder for H.264? */
186 unsigned int has_blt : 1; /* Flag: has BLT unit? */
187 unsigned int has_vebox : 1; /* Flag: has VEBOX unit */
188 unsigned int has_bsd2 : 1; /* Flag: has the second BSD video ring unit */
189 unsigned int has_huc : 1; /* Flag: has a fully loaded HuC firmware? */
193 const struct intel_device_info *device_info;
194 unsigned int mocs_state;
197 bool intel_driver_init(VADriverContextP ctx);
198 void intel_driver_terminate(VADriverContextP ctx);
200 static INLINE struct intel_driver_data *
201 intel_driver_data(VADriverContextP ctx)
203 return (struct intel_driver_data *)ctx->pDriverData;
206 struct intel_region {
214 unsigned int swizzle;
218 #define IS_G4X(device_info) (device_info->is_g4x)
220 #define IS_IRONLAKE(device_info) (device_info->gen == 5)
222 #define IS_GEN6(device_info) (device_info->gen == 6)
224 #define IS_HASWELL(device_info) (device_info->is_haswell)
225 #define IS_GEN7(device_info) (device_info->gen == 7)
227 #define IS_CHERRYVIEW(device_info) (device_info->is_cherryview)
228 #define IS_GEN8(device_info) (device_info->gen == 8)
230 #define IS_GEN9(device_info) (device_info->gen == 9)
232 #define IS_SKL(device_info) (device_info->is_skylake)
234 #define IS_BXT(device_info) (device_info->is_broxton)
236 #define IS_KBL(device_info) (device_info->is_kabylake)
238 #define IS_GLK(device_info) (device_info->is_glklake)
240 #endif /* _INTEL_DRIVER_H_ */