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29 #include "brw_device_info.h"
33 #define BDW_GT2_DEVID 0x161a
35 // An asssert that works regardless of NDEBUG.
36 #define t_assert(cond) \
39 fprintf(stderr, "%s:%d: assertion failed\n", __FILE__, __LINE__); \
45 t_assert_extent4d(const struct isl_extent4d *e, uint32_t width,
46 uint32_t height, uint32_t depth, uint32_t array_len)
48 t_assert(e->width == width);
49 t_assert(e->height == height);
50 t_assert(e->depth == depth);
51 t_assert(e->array_len == array_len);
55 t_assert_image_alignment_el(const struct isl_surf *surf,
56 uint32_t w, uint32_t h, uint32_t d)
58 struct isl_extent3d align_el;
60 align_el = isl_surf_get_image_alignment_el(surf);
61 t_assert(align_el.w == w);
62 t_assert(align_el.h == h);
63 t_assert(align_el.d == d);
68 t_assert_image_alignment_sa(const struct isl_surf *surf,
69 uint32_t w, uint32_t h, uint32_t d)
71 struct isl_extent3d align_sa;
73 align_sa = isl_surf_get_image_alignment_sa(surf);
74 t_assert(align_sa.w == w);
75 t_assert(align_sa.h == h);
76 t_assert(align_sa.d == d);
81 t_assert_offset(const struct isl_surf *surf,
83 uint32_t logical_array_layer,
84 uint32_t logical_z_offset_px,
85 uint32_t expected_x_offset_sa,
86 uint32_t expected_y_offset_sa)
89 isl_surf_get_image_offset_sa(surf, level, logical_array_layer,
90 logical_z_offset_px, &x, &y);
92 t_assert(x == expected_x_offset_sa);
93 t_assert(y == expected_y_offset_sa);
97 t_assert_phys_level0_sa(const struct isl_surf *surf, uint32_t width,
98 uint32_t height, uint32_t depth, uint32_t array_len)
100 t_assert_extent4d(&surf->phys_level0_sa, width, height, depth, array_len);
104 t_assert_gen4_3d_layer(const struct isl_surf *surf,
106 uint32_t aligned_width,
107 uint32_t aligned_height,
109 uint32_t horiz_layers,
110 uint32_t vert_layers,
113 for (uint32_t z = 0; z < depth; ++z) {
114 t_assert_offset(surf, level, 0, z,
115 aligned_width * (z % horiz_layers),
116 *base_y + aligned_height * (z / horiz_layers));
119 *base_y += aligned_height * vert_layers;
123 test_bdw_2d_r8g8b8a8_unorm_512x512_a1_s1_noaux_y0(void)
127 struct isl_device dev;
128 isl_device_init(&dev, brw_get_device_info(BDW_GT2_DEVID),
129 /*bit6_swizzle*/ false);
131 struct isl_surf surf;
132 ok = isl_surf_init(&dev, &surf,
133 .dim = ISL_SURF_DIM_2D,
134 .format = ISL_FORMAT_R8G8B8A8_UNORM,
141 .usage = ISL_SURF_USAGE_TEXTURE_BIT |
142 ISL_SURF_USAGE_DISABLE_AUX_BIT,
143 .tiling_flags = ISL_TILING_Y0_BIT);
146 t_assert_image_alignment_el(&surf, 4, 4, 1);
147 t_assert_image_alignment_sa(&surf, 4, 4, 1);
148 t_assert_phys_level0_sa(&surf, 512, 512, 1, 1);
149 t_assert(isl_surf_get_array_pitch_el_rows(&surf) >= 772);
150 t_assert(isl_surf_get_array_pitch_sa_rows(&surf) >= 772);
152 t_assert_offset(&surf, 0, 0, 0, 0, 0); // +0, +0
153 t_assert_offset(&surf, 1, 0, 0, 0, 512); // +0, +512
154 t_assert_offset(&surf, 2, 0, 0, 256, 512); // +256, +0
155 t_assert_offset(&surf, 3, 0, 0, 256, 640); // +0, +128
156 t_assert_offset(&surf, 4, 0, 0, 256, 704); // +0, +64
157 t_assert_offset(&surf, 5, 0, 0, 256, 736); // +0, +32
158 t_assert_offset(&surf, 6, 0, 0, 256, 752); // +0, +16
159 t_assert_offset(&surf, 7, 0, 0, 256, 760); // +0, +8
160 t_assert_offset(&surf, 8, 0, 0, 256, 764); // +0, +4
161 t_assert_offset(&surf, 9, 0, 0, 256, 768); // +0, +4
165 test_bdw_2d_r8g8b8a8_unorm_1024x1024_a6_s1_noaux_y0(void)
169 struct isl_device dev;
170 isl_device_init(&dev, brw_get_device_info(BDW_GT2_DEVID),
171 /*bit6_swizzle*/ false);
173 struct isl_surf surf;
174 ok = isl_surf_init(&dev, &surf,
175 .dim = ISL_SURF_DIM_2D,
176 .format = ISL_FORMAT_R8G8B8A8_UNORM,
183 .usage = ISL_SURF_USAGE_TEXTURE_BIT |
184 ISL_SURF_USAGE_DISABLE_AUX_BIT,
185 .tiling_flags = ISL_TILING_Y0_BIT);
188 t_assert_image_alignment_el(&surf, 4, 4, 1);
189 t_assert_image_alignment_sa(&surf, 4, 4, 1);
190 t_assert(isl_surf_get_array_pitch_el_rows(&surf) >= 1540);
191 t_assert(isl_surf_get_array_pitch_sa_rows(&surf) >= 1540);
193 for (uint32_t a = 0; a < 6; ++a) {
194 uint32_t b = a * isl_surf_get_array_pitch_sa_rows(&surf);
196 t_assert_offset(&surf, 0, a, 0, 0, b + 0); // +0, +0
197 t_assert_offset(&surf, 1, a, 0, 0, b + 1024); // +0, +1024
198 t_assert_offset(&surf, 2, a, 0, 512, b + 1024); // +512, +0
199 t_assert_offset(&surf, 3, a, 0, 512, b + 1280); // +0, +256
200 t_assert_offset(&surf, 4, a, 0, 512, b + 1408); // +0, +128
201 t_assert_offset(&surf, 5, a, 0, 512, b + 1472); // +0, +64
202 t_assert_offset(&surf, 6, a, 0, 512, b + 1504); // +0, +32
203 t_assert_offset(&surf, 7, a, 0, 512, b + 1520); // +0, +16
204 t_assert_offset(&surf, 8, a, 0, 512, b + 1528); // +0, +8
205 t_assert_offset(&surf, 9, a, 0, 512, b + 1532); // +0, +4
206 t_assert_offset(&surf, 10, a, 0, 512, b + 1536); // +0, +4
211 test_bdw_3d_r8g8b8a8_unorm_256x256x256_levels09_tiley0(void)
215 struct isl_device dev;
216 isl_device_init(&dev, brw_get_device_info(BDW_GT2_DEVID),
217 /*bit6_swizzle*/ false);
219 struct isl_surf surf;
220 ok = isl_surf_init(&dev, &surf,
221 .dim = ISL_SURF_DIM_3D,
222 .format = ISL_FORMAT_R8G8B8A8_UNORM,
229 .usage = ISL_SURF_USAGE_TEXTURE_BIT |
230 ISL_SURF_USAGE_DISABLE_AUX_BIT,
231 .tiling_flags = ISL_TILING_Y0_BIT);
234 t_assert_image_alignment_el(&surf, 4, 4, 1);
235 t_assert_image_alignment_sa(&surf, 4, 4, 1);
236 t_assert(isl_surf_get_array_pitch_el_rows(&surf) == 74916);
237 t_assert(isl_surf_get_array_pitch_sa_rows(&surf) ==
238 isl_surf_get_array_pitch_el_rows(&surf));
242 t_assert_gen4_3d_layer(&surf, 0, 256, 256, 256, 1, 256, &base_y);
243 t_assert_gen4_3d_layer(&surf, 1, 128, 128, 128, 2, 64, &base_y);
244 t_assert_gen4_3d_layer(&surf, 2, 64, 64, 64, 4, 16, &base_y);
245 t_assert_gen4_3d_layer(&surf, 3, 32, 32, 32, 8, 4, &base_y);
246 t_assert_gen4_3d_layer(&surf, 4, 16, 16, 16, 16, 1, &base_y);
247 t_assert_gen4_3d_layer(&surf, 5, 8, 8, 8, 32, 1, &base_y);
248 t_assert_gen4_3d_layer(&surf, 6, 4, 4, 4, 64, 1, &base_y);
249 t_assert_gen4_3d_layer(&surf, 7, 4, 4, 2, 128, 1, &base_y);
250 t_assert_gen4_3d_layer(&surf, 8, 4, 4, 1, 256, 1, &base_y);
255 /* FINISHME: Add tests for npot sizes */
256 /* FINISHME: Add tests for 1D surfaces */
258 test_bdw_2d_r8g8b8a8_unorm_512x512_a1_s1_noaux_y0();
259 test_bdw_2d_r8g8b8a8_unorm_1024x1024_a6_s1_noaux_y0();
260 test_bdw_3d_r8g8b8a8_unorm_256x256x256_levels09_tiley0();