src/mesa/drivers/dri/i915/i915_context.h

   1  /**************************************************************************
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   3  * Copyright 2003 VMware, Inc.
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   5  *
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  15  * next paragraph) shall be included in all copies or substantial portions
  16  * of the Software.
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  27
  28 #ifndef I915CONTEXT_INC
  29 #define I915CONTEXT_INC
  30
  31 #include "intel_context.h"
  32
  33 #define I915_FALLBACK_TEXTURE            0x1000
  34 #define I915_FALLBACK_COLORMASK          0x2000
  35 #define I915_FALLBACK_STENCIL            0x4000
  36 #define I915_FALLBACK_STIPPLE            0x8000
  37 #define I915_FALLBACK_PROGRAM            0x10000
  38 #define I915_FALLBACK_LOGICOP            0x20000
  39 #define I915_FALLBACK_POLYGON_SMOOTH     0x40000
  40 #define I915_FALLBACK_POINT_SMOOTH       0x80000
  41 #define I915_FALLBACK_POINT_SPRITE_COORD_ORIGIN  0x100000
  42 #define I915_FALLBACK_DRAW_OFFSET        0x200000
  43 #define I915_FALLBACK_COORD_REPLACE      0x400000
  44
  45 #define I915_UPLOAD_CTX              0x1
  46 #define I915_UPLOAD_BUFFERS          0x2
  47 #define I915_UPLOAD_STIPPLE          0x4
  48 #define I915_UPLOAD_PROGRAM          0x8
  49 #define I915_UPLOAD_CONSTANTS        0x10
  50 #define I915_UPLOAD_INVARIENT        0x40
  51 #define I915_UPLOAD_DEFAULTS         0x80
  52 #define I915_UPLOAD_RASTER_RULES     0x100
  53 #define I915_UPLOAD_BLEND            0x200
  54 #define I915_UPLOAD_TEX(i)           (0x00010000<<(i))
  55 #define I915_UPLOAD_TEX_ALL          (0x00ff0000)
  56 #define I915_UPLOAD_TEX_0_SHIFT      16
  57
  58
  59 /* State structure offsets - these will probably disappear.
  60  */
  61 #define I915_DESTREG_CBUFADDR0 0
  62 #define I915_DESTREG_CBUFADDR1 1
  63 #define I915_DESTREG_DBUFADDR0 3
  64 #define I915_DESTREG_DBUFADDR1 4
  65 #define I915_DESTREG_DV0 6
  66 #define I915_DESTREG_DV1 7
  67 #define I915_DESTREG_SR0 8
  68 #define I915_DESTREG_SR1 9
  69 #define I915_DESTREG_SR2 10
  70 #define I915_DESTREG_SENABLE 11
  71 #define I915_DESTREG_DRAWRECT0 12
  72 #define I915_DESTREG_DRAWRECT1 13
  73 #define I915_DESTREG_DRAWRECT2 14
  74 #define I915_DESTREG_DRAWRECT3 15
  75 #define I915_DESTREG_DRAWRECT4 16
  76 #define I915_DESTREG_DRAWRECT5 17
  77 #define I915_DEST_SETUP_SIZE 18
  78
  79 #define I915_CTXREG_STATE4              0
  80 #define I915_CTXREG_LI                  1
  81 #define I915_CTXREG_LIS2                2
  82 #define I915_CTXREG_LIS4                3
  83 #define I915_CTXREG_LIS5                4
  84 #define I915_CTXREG_LIS6                5
  85 #define I915_CTXREG_BF_STENCIL_OPS      6
  86 #define I915_CTXREG_BF_STENCIL_MASKS    7
  87 #define I915_CTX_SETUP_SIZE             8
  88
  89 #define I915_BLENDREG_IAB               0
  90 #define I915_BLENDREG_BLENDCOLOR0       1
  91 #define I915_BLENDREG_BLENDCOLOR1       2
  92 #define I915_BLEND_SETUP_SIZE           3
  93
  94 #define I915_STPREG_ST0        0
  95 #define I915_STPREG_ST1        1
  96 #define I915_STP_SETUP_SIZE    2
  97
  98 #define I915_TEXREG_MS3        1
  99 #define I915_TEXREG_MS4        2
 100 #define I915_TEXREG_SS2        3
 101 #define I915_TEXREG_SS3        4
 102 #define I915_TEXREG_SS4        5
 103 #define I915_TEX_SETUP_SIZE    6
 104
 105 #define I915_DEFREG_C0    0
 106 #define I915_DEFREG_C1    1
 107 #define I915_DEFREG_S0    2
 108 #define I915_DEFREG_S1    3
 109 #define I915_DEFREG_Z0    4
 110 #define I915_DEFREG_Z1    5
 111 #define I915_DEF_SETUP_SIZE    6
 112
 113 enum {
 114    I915_RASTER_RULES,
 115    I915_RASTER_RULES_SETUP_SIZE,
 116 };
 117
 118 #define I915_TEX_UNITS 8
 119
 120 #define I915_MAX_CONSTANT      32
 121 #define I915_CONSTANT_SIZE     (2+(4*I915_MAX_CONSTANT))
 122
 123 #define I915_MAX_TEX_INDIRECT 4
 124 #define I915_MAX_TEX_INSN     32
 125 #define I915_MAX_ALU_INSN     64
 126 #define I915_MAX_DECL_INSN    27
 127 #define I915_MAX_TEMPORARY    16
 128
 129 #define I915_MAX_INSN          (I915_MAX_DECL_INSN + \
 130                                 I915_MAX_TEX_INSN + \
 131                                 I915_MAX_ALU_INSN)
 132
 133 /* Maximum size of the program packet, which matches the limits on
 134  * decl, tex, and ALU instructions.
 135  */
 136 #define I915_PROGRAM_SIZE      (I915_MAX_INSN * 3 + 1)
 137
 138 /* Hardware version of a parsed fragment program.  "Derived" from the
 139  * mesa fragment_program struct.
 140  */
 141 struct i915_fragment_program
 142 {
 143    struct gl_fragment_program FragProg;
 144
 145    bool translated;
 146    bool params_uptodate;
 147    bool on_hardware;
 148    bool error;             /* If program is malformed for any reason. */
 149
 150    /** Record of which phases R registers were last written in. */
 151    GLuint register_phases[16];
 152    GLuint indirections;
 153    GLuint nr_tex_indirect;
 154    GLuint nr_tex_insn;
 155    GLuint nr_alu_insn;
 156    GLuint nr_decl_insn;
 157
 158
 159
 160
 161    /* TODO: split between the stored representation of a program and
 162     * the state used to build that representation.
 163     */
 164    struct gl_context *ctx;
 165
 166    /* declarations contains the packet header. */
 167    GLuint declarations[I915_MAX_DECL_INSN * 3 + 1];
 168    GLuint program[(I915_MAX_TEX_INSN + I915_MAX_ALU_INSN) * 3];
 169
 170    GLfloat constant[I915_MAX_CONSTANT][4];
 171    GLuint constant_flags[I915_MAX_CONSTANT];
 172    GLuint nr_constants;
 173
 174    GLuint *csr;                 /* Cursor, points into program.
 175                                  */
 176
 177    GLuint *decl;                /* Cursor, points into declarations.
 178                                  */
 179
 180    GLuint decl_s;               /* flags for which s regs need to be decl'd */
 181    GLuint decl_t;               /* flags for which t regs need to be decl'd */
 182
 183    GLuint temp_flag;            /* Tracks temporary regs which are in
 184                                  * use.
 185                                  */
 186
 187    GLuint utemp_flag;           /* Tracks TYPE_U temporary regs which are in
 188                                  * use.
 189                                  */
 190
 191
 192    /* Track which R registers are "live" for each instruction.
 193     * A register is live between the time it's written to and the last time
 194     * it's read. */
 195    GLuint usedRegs[I915_MAX_INSN];
 196
 197    /* Helpers for i915_fragprog.c:
 198     */
 199    uint8_t texcoord_mapping[I915_TEX_UNITS];
 200    uint8_t wpos_tex;
 201    bool depth_written;
 202
 203    struct
 204    {
 205       GLuint reg;               /* Hardware constant idx */
 206       const GLfloat *values;    /* Pointer to tracked values */
 207    } param[I915_MAX_CONSTANT];
 208    GLuint nr_params;
 209 };
 210
 211 struct i915_hw_state
 212 {
 213    GLuint Ctx[I915_CTX_SETUP_SIZE];
 214    GLuint Blend[I915_BLEND_SETUP_SIZE];
 215    GLuint Buffer[I915_DEST_SETUP_SIZE];
 216    GLuint Stipple[I915_STP_SETUP_SIZE];
 217    GLuint Defaults[I915_DEF_SETUP_SIZE];
 218    GLuint RasterRules[I915_RASTER_RULES_SETUP_SIZE];
 219    GLuint Tex[I915_TEX_UNITS][I915_TEX_SETUP_SIZE];
 220    GLuint Constant[I915_CONSTANT_SIZE];
 221    GLuint ConstantSize;
 222    GLuint Program[I915_PROGRAM_SIZE];
 223    GLuint ProgramSize;
 224
 225    /* Region pointers for relocation:
 226     */
 227    struct intel_region *draw_region;
 228    struct intel_region *depth_region;
 229 /*    struct intel_region *tex_region[I915_TEX_UNITS]; */
 230
 231    /* Regions aren't actually that appropriate here as the memory may
 232     * be from a PBO or FBO.  Will have to do this for draw and depth for
 233     * FBO's...
 234     */
 235    drm_intel_bo *tex_buffer[I915_TEX_UNITS];
 236    GLuint tex_offset[I915_TEX_UNITS];
 237
 238
 239    GLuint active;               /* I915_UPLOAD_* */
 240    GLuint emitted;              /* I915_UPLOAD_* */
 241 };
 242
 243 struct i915_context
 244 {
 245    struct intel_context intel;
 246
 247    GLuint lodbias_ss2[MAX_TEXTURE_UNITS];
 248
 249
 250    struct i915_fragment_program *current_program;
 251
 252    drm_intel_bo *current_vb_bo;
 253    unsigned int current_vertex_size;
 254
 255    struct i915_hw_state state;
 256    uint32_t last_draw_offset;
 257    GLuint last_sampler;
 258 };
 259
 260
 261 #define I915_STATECHANGE(i915, flag)                                    \
 262 do {                                                                    \
 263    INTEL_FIREVERTICES( &(i915)->intel );                                        \
 264    (i915)->state.emitted &= ~(flag);                                    \
 265 } while (0)
 266
 267 #define I915_ACTIVESTATE(i915, flag, mode)                      \
 268 do {                                                            \
 269    INTEL_FIREVERTICES( &(i915)->intel );                                \
 270    if (mode)                                                    \
 271       (i915)->state.active |= (flag);                           \
 272    else                                                         \
 273       (i915)->state.active &= ~(flag);                          \
 274 } while (0)
 275
 276
 277 /*======================================================================
 278  * i915_vtbl.c
 279  */
 280 extern void i915InitVtbl(struct i915_context *i915);
 281
 282 extern void
 283 i915_state_draw_region(struct intel_context *intel,
 284                        struct i915_hw_state *state,
 285                        struct intel_region *color_region,
 286                        struct intel_region *depth_region);
 287
 288
 289
 290 #define SZ_TO_HW(sz)  ((sz-2)&0x3)
 291 #define EMIT_SZ(sz)   (EMIT_1F + (sz) - 1)
 292 #define EMIT_ATTR( ATTR, STYLE, S4, SZ )                                \
 293 do {                                                                    \
 294    intel->vertex_attrs[intel->vertex_attr_count].attrib = (ATTR);       \
 295    intel->vertex_attrs[intel->vertex_attr_count].format = (STYLE);      \
 296    s4 |= S4;                                                            \
 297    intel->vertex_attr_count++;                                          \
 298    offset += (SZ);                                                      \
 299 } while (0)
 300
 301 #define EMIT_PAD( N )                                                   \
 302 do {                                                                    \
 303    intel->vertex_attrs[intel->vertex_attr_count].attrib = 0;            \
 304    intel->vertex_attrs[intel->vertex_attr_count].format = EMIT_PAD;     \
 305    intel->vertex_attrs[intel->vertex_attr_count].offset = (N);          \
 306    intel->vertex_attr_count++;                                          \
 307    offset += (N);                                                       \
 308 } while (0)
 309
 310
 311
 312 /*======================================================================
 313  * i915_context.c
 314  */
 315 extern bool i915CreateContext(int api,
 316                               const struct gl_config * mesaVis,
 317                               __DRIcontext * driContextPriv,
 318                               unsigned major_version,
 319                               unsigned minor_version,
 320                               uint32_t flags,
 321                               unsigned *error,
 322                               void *sharedContextPrivate);
 323
 324
 325 /*======================================================================
 326  * i915_debug.c
 327  */
 328 extern void i915_disassemble_program(const GLuint * program, GLuint sz);
 329 extern void i915_print_ureg(const char *msg, GLuint ureg);
 330
 331
 332 /*======================================================================
 333  * i915_state.c
 334  */
 335 extern void i915InitStateFunctions(struct dd_function_table *functions);
 336 extern void i915InitState(struct i915_context *i915);
 337 extern void i915_update_stencil(struct gl_context * ctx);
 338 extern void i915_update_provoking_vertex(struct gl_context *ctx);
 339 extern void i915_update_sprite_point_enable(struct gl_context *ctx);
 340
 341
 342 /*======================================================================
 343  * i915_tex.c
 344  */
 345 extern void i915UpdateTextureState(struct intel_context *intel);
 346 extern void i915InitTextureFuncs(struct dd_function_table *functions);
 347
 348 /*======================================================================
 349  * i915_fragprog.c
 350  */
 351 extern void i915ValidateFragmentProgram(struct i915_context *i915);
 352 extern void i915InitFragProgFuncs(struct dd_function_table *functions);
 353
 354 /*======================================================================
 355  * Inline conversion functions.  These are better-typed than the
 356  * macros used previously:
 357  */
 358 static inline struct i915_context *
 359 i915_context(struct gl_context * ctx)
 360 {
 361    return (struct i915_context *) ctx;
 362 }
 363
 364
 365
 366 #define I915_CONTEXT(ctx)       i915_context(ctx)
 367
 368
 369
 370 #endif