1 /**************************************************************************
3 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **************************************************************************/
30 #include "main/glheader.h"
31 #include "main/mtypes.h"
32 #include "main/imports.h"
33 #include "main/macros.h"
34 #include "main/colormac.h"
35 #include "main/renderbuffer.h"
36 #include "main/framebuffer.h"
39 #include "tnl/t_context.h"
40 #include "tnl/t_vertex.h"
41 #include "swrast_setup/swrast_setup.h"
43 #include "intel_batchbuffer.h"
44 #include "intel_regions.h"
45 #include "intel_tris.h"
46 #include "intel_fbo.h"
47 #include "intel_buffers.h"
50 #include "i915_context.h"
53 i915_render_prevalidate(struct intel_context *intel)
55 struct i915_context *i915 = i915_context(&intel->ctx);
57 i915ValidateFragmentProgram(i915);
61 i915_render_start(struct intel_context *intel)
63 intel_prepare_render(intel);
68 i915_reduced_primitive_state(struct intel_context *intel, GLenum rprim)
70 struct i915_context *i915 = i915_context(&intel->ctx);
71 GLuint st1 = i915->state.Stipple[I915_STPREG_ST1];
76 case GL_QUADS: /* from RASTERIZE(GL_QUADS) in t_dd_tritemp.h */
78 if (intel->ctx.Polygon.StippleFlag && intel->hw_stipple)
87 i915->intel.reduced_primitive = rprim;
89 if (st1 != i915->state.Stipple[I915_STPREG_ST1]) {
90 INTEL_FIREVERTICES(intel);
92 I915_STATECHANGE(i915, I915_UPLOAD_STIPPLE);
93 i915->state.Stipple[I915_STPREG_ST1] = st1;
98 /* Pull apart the vertex format registers and figure out how large a
99 * vertex is supposed to be.
102 i915_check_vertex_size(struct intel_context *intel, GLuint expected)
104 struct i915_context *i915 = i915_context(&intel->ctx);
105 int lis2 = i915->state.Ctx[I915_CTXREG_LIS2];
106 int lis4 = i915->state.Ctx[I915_CTXREG_LIS4];
109 switch (lis4 & S4_VFMT_XYZW_MASK) {
123 fprintf(stderr, "no xyzw specified\n");
127 if (lis4 & S4_VFMT_SPEC_FOG)
129 if (lis4 & S4_VFMT_COLOR)
131 if (lis4 & S4_VFMT_DEPTH_OFFSET)
133 if (lis4 & S4_VFMT_POINT_WIDTH)
135 if (lis4 & S4_VFMT_FOG_PARAM)
138 for (i = 0; i < 8; i++) {
139 switch (lis2 & S2_TEXCOORD_FMT0_MASK) {
152 case TEXCOORDFMT_2D_16:
155 case TEXCOORDFMT_4D_16:
158 case TEXCOORDFMT_NOT_PRESENT:
161 fprintf(stderr, "bad texcoord fmt %d\n", i);
164 lis2 >>= S2_TEXCOORD_FMT1_SHIFT;
168 fprintf(stderr, "vertex size mismatch %d/%d\n", sz, expected);
170 return sz == expected;
175 i915_emit_invarient_state(struct intel_context *intel)
181 OUT_BATCH(_3DSTATE_AA_CMD |
182 AA_LINE_ECAAR_WIDTH_ENABLE |
183 AA_LINE_ECAAR_WIDTH_1_0 |
184 AA_LINE_REGION_WIDTH_ENABLE | AA_LINE_REGION_WIDTH_1_0);
186 OUT_BATCH(_3DSTATE_DFLT_DIFFUSE_CMD);
189 OUT_BATCH(_3DSTATE_DFLT_SPEC_CMD);
192 OUT_BATCH(_3DSTATE_DFLT_Z_CMD);
195 /* Don't support texture crossbar yet */
196 OUT_BATCH(_3DSTATE_COORD_SET_BINDINGS |
201 CSB_TCB(4, 4) | CSB_TCB(5, 5) | CSB_TCB(6, 6) | CSB_TCB(7, 7));
203 /* Need to initialize this to zero.
205 OUT_BATCH(_3DSTATE_LOAD_STATE_IMMEDIATE_1 | I1_LOAD_S(3) | (0));
209 OUT_BATCH(_3DSTATE_SCISSOR_ENABLE_CMD | DISABLE_SCISSOR_RECT);
211 OUT_BATCH(_3DSTATE_SCISSOR_RECT_0_CMD);
215 OUT_BATCH(_3DSTATE_DEPTH_SUBRECT_DISABLE);
217 OUT_BATCH(_3DSTATE_LOAD_INDIRECT | 0); /* disable indirect state */
224 #define emit(intel, state, size ) \
225 intel_batchbuffer_data(intel, state, size, false)
228 get_dirty(struct i915_hw_state *state)
232 /* Workaround the multitex hang - if one texture unit state is
233 * modified, emit all texture units.
235 dirty = state->active & ~state->emitted;
236 if (dirty & I915_UPLOAD_TEX_ALL)
237 state->emitted &= ~I915_UPLOAD_TEX_ALL;
238 dirty = state->active & ~state->emitted;
244 get_state_size(struct i915_hw_state *state)
246 GLuint dirty = get_dirty(state);
250 if (dirty & I915_UPLOAD_INVARIENT)
253 if (dirty & I915_UPLOAD_RASTER_RULES)
254 sz += sizeof(state->RasterRules);
256 if (dirty & I915_UPLOAD_CTX)
257 sz += sizeof(state->Ctx);
259 if (dirty & I915_UPLOAD_BLEND)
260 sz += sizeof(state->Blend);
262 if (dirty & I915_UPLOAD_BUFFERS)
263 sz += sizeof(state->Buffer);
265 if (dirty & I915_UPLOAD_STIPPLE)
266 sz += sizeof(state->Stipple);
268 if (dirty & I915_UPLOAD_TEX_ALL) {
270 for (i = 0; i < I915_TEX_UNITS; i++)
271 if (dirty & I915_UPLOAD_TEX(i))
274 sz += (2 + nr * 3) * sizeof(GLuint) * 2;
277 if (dirty & I915_UPLOAD_CONSTANTS)
278 sz += state->ConstantSize * sizeof(GLuint);
280 if (dirty & I915_UPLOAD_PROGRAM)
281 sz += state->ProgramSize * sizeof(GLuint);
286 /* Push the state into the sarea and/or texture memory.
289 i915_emit_state(struct intel_context *intel)
291 struct i915_context *i915 = i915_context(&intel->ctx);
292 struct i915_hw_state *state = &i915->state;
293 int i, count, aper_count;
295 drm_intel_bo *aper_array[3 + I915_TEX_UNITS];
296 GET_CURRENT_CONTEXT(ctx);
299 /* We don't hold the lock at this point, so want to make sure that
300 * there won't be a buffer wrap between the state emits and the primitive
303 * It might be better to talk about explicit places where
304 * scheduling is allowed, rather than assume that it is whenever a
305 * batchbuffer fills up.
307 intel_batchbuffer_require_space(intel,
308 get_state_size(state) + INTEL_PRIM_EMIT_SIZE,
312 if (intel->batch.bo == NULL) {
313 _mesa_error(ctx, GL_OUT_OF_MEMORY, "i915 emit state");
317 dirty = get_dirty(state);
319 aper_array[aper_count++] = intel->batch.bo;
320 if (dirty & I915_UPLOAD_BUFFERS) {
321 if (state->draw_region)
322 aper_array[aper_count++] = state->draw_region->buffer;
323 if (state->depth_region)
324 aper_array[aper_count++] = state->depth_region->buffer;
327 if (dirty & I915_UPLOAD_TEX_ALL) {
328 for (i = 0; i < I915_TEX_UNITS; i++) {
329 if (dirty & I915_UPLOAD_TEX(i)) {
330 if (state->tex_buffer[i]) {
331 aper_array[aper_count++] = state->tex_buffer[i];
337 if (dri_bufmgr_check_aperture_space(aper_array, aper_count)) {
340 intel_batchbuffer_flush(intel);
343 _mesa_error(ctx, GL_OUT_OF_MEMORY, "i915 emit state");
348 /* work out list of buffers to emit */
350 /* Do this here as we may have flushed the batchbuffer above,
351 * causing more state to be dirty!
353 dirty = get_dirty(state);
354 state->emitted |= dirty;
355 assert(get_dirty(state) == 0);
357 if (INTEL_DEBUG & DEBUG_STATE)
358 fprintf(stderr, "%s dirty: %x\n", __FUNCTION__, dirty);
360 if (dirty & I915_UPLOAD_INVARIENT) {
361 if (INTEL_DEBUG & DEBUG_STATE)
362 fprintf(stderr, "I915_UPLOAD_INVARIENT:\n");
363 i915_emit_invarient_state(intel);
366 if (dirty & I915_UPLOAD_RASTER_RULES) {
367 if (INTEL_DEBUG & DEBUG_STATE)
368 fprintf(stderr, "I915_UPLOAD_RASTER_RULES:\n");
369 emit(intel, state->RasterRules, sizeof(state->RasterRules));
372 if (dirty & I915_UPLOAD_CTX) {
373 if (INTEL_DEBUG & DEBUG_STATE)
374 fprintf(stderr, "I915_UPLOAD_CTX:\n");
376 emit(intel, state->Ctx, sizeof(state->Ctx));
379 if (dirty & I915_UPLOAD_BLEND) {
380 if (INTEL_DEBUG & DEBUG_STATE)
381 fprintf(stderr, "I915_UPLOAD_BLEND:\n");
383 emit(intel, state->Blend, sizeof(state->Blend));
386 if (dirty & I915_UPLOAD_BUFFERS) {
389 if (INTEL_DEBUG & DEBUG_STATE)
390 fprintf(stderr, "I915_UPLOAD_BUFFERS:\n");
393 if (state->Buffer[I915_DESTREG_DRAWRECT0] != MI_NOOP)
397 OUT_BATCH(state->Buffer[I915_DESTREG_CBUFADDR0]);
398 OUT_BATCH(state->Buffer[I915_DESTREG_CBUFADDR1]);
399 if (state->draw_region) {
400 OUT_RELOC(state->draw_region->buffer,
401 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0);
406 OUT_BATCH(state->Buffer[I915_DESTREG_DBUFADDR0]);
407 OUT_BATCH(state->Buffer[I915_DESTREG_DBUFADDR1]);
408 if (state->depth_region) {
409 OUT_RELOC(state->depth_region->buffer,
410 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0);
415 OUT_BATCH(state->Buffer[I915_DESTREG_DV0]);
416 OUT_BATCH(state->Buffer[I915_DESTREG_DV1]);
417 OUT_BATCH(state->Buffer[I915_DESTREG_SENABLE]);
418 OUT_BATCH(state->Buffer[I915_DESTREG_SR0]);
419 OUT_BATCH(state->Buffer[I915_DESTREG_SR1]);
420 OUT_BATCH(state->Buffer[I915_DESTREG_SR2]);
422 if (state->Buffer[I915_DESTREG_DRAWRECT0] != MI_NOOP)
423 OUT_BATCH(state->Buffer[I915_DESTREG_DRAWRECT0]);
424 OUT_BATCH(state->Buffer[I915_DESTREG_DRAWRECT1]);
425 OUT_BATCH(state->Buffer[I915_DESTREG_DRAWRECT2]);
426 OUT_BATCH(state->Buffer[I915_DESTREG_DRAWRECT3]);
427 OUT_BATCH(state->Buffer[I915_DESTREG_DRAWRECT4]);
428 OUT_BATCH(state->Buffer[I915_DESTREG_DRAWRECT5]);
433 if (dirty & I915_UPLOAD_STIPPLE) {
434 if (INTEL_DEBUG & DEBUG_STATE)
435 fprintf(stderr, "I915_UPLOAD_STIPPLE:\n");
436 emit(intel, state->Stipple, sizeof(state->Stipple));
439 /* Combine all the dirty texture state into a single command to
440 * avoid lockups on I915 hardware.
442 if (dirty & I915_UPLOAD_TEX_ALL) {
446 for (i = 0; i < I915_TEX_UNITS; i++)
447 if (dirty & I915_UPLOAD_TEX(i))
450 BEGIN_BATCH(2 + nr * 3);
451 OUT_BATCH(_3DSTATE_MAP_STATE | (3 * nr));
452 OUT_BATCH((dirty & I915_UPLOAD_TEX_ALL) >> I915_UPLOAD_TEX_0_SHIFT);
453 for (i = 0; i < I915_TEX_UNITS; i++)
454 if (dirty & I915_UPLOAD_TEX(i)) {
455 OUT_RELOC(state->tex_buffer[i],
456 I915_GEM_DOMAIN_SAMPLER, 0,
457 state->tex_offset[i]);
459 OUT_BATCH(state->Tex[i][I915_TEXREG_MS3]);
460 OUT_BATCH(state->Tex[i][I915_TEXREG_MS4]);
464 unwind = intel->batch.used;
465 BEGIN_BATCH(2 + nr * 3);
466 OUT_BATCH(_3DSTATE_SAMPLER_STATE | (3 * nr));
467 OUT_BATCH((dirty & I915_UPLOAD_TEX_ALL) >> I915_UPLOAD_TEX_0_SHIFT);
468 for (i = 0; i < I915_TEX_UNITS; i++)
469 if (dirty & I915_UPLOAD_TEX(i)) {
470 OUT_BATCH(state->Tex[i][I915_TEXREG_SS2]);
471 OUT_BATCH(state->Tex[i][I915_TEXREG_SS3]);
472 OUT_BATCH(state->Tex[i][I915_TEXREG_SS4]);
475 if (i915->last_sampler &&
476 memcmp(intel->batch.map + i915->last_sampler,
477 intel->batch.map + unwind,
478 (2 + nr*3)*sizeof(int)) == 0)
479 intel->batch.used = unwind;
481 i915->last_sampler = unwind;
484 if (dirty & I915_UPLOAD_CONSTANTS) {
485 if (INTEL_DEBUG & DEBUG_STATE)
486 fprintf(stderr, "I915_UPLOAD_CONSTANTS:\n");
487 emit(intel, state->Constant, state->ConstantSize * sizeof(GLuint));
490 if (dirty & I915_UPLOAD_PROGRAM) {
491 if (state->ProgramSize) {
492 if (INTEL_DEBUG & DEBUG_STATE)
493 fprintf(stderr, "I915_UPLOAD_PROGRAM:\n");
495 assert((state->Program[0] & 0x1ff) + 2 == state->ProgramSize);
497 emit(intel, state->Program, state->ProgramSize * sizeof(GLuint));
498 if (INTEL_DEBUG & DEBUG_STATE)
499 i915_disassemble_program(state->Program, state->ProgramSize);
503 assert(get_dirty(state) == 0);
507 i915_destroy_context(struct intel_context *intel)
510 struct i915_context *i915 = i915_context(&intel->ctx);
512 intel_region_release(&i915->state.draw_region);
513 intel_region_release(&i915->state.depth_region);
515 for (i = 0; i < I915_TEX_UNITS; i++) {
516 if (i915->state.tex_buffer[i] != NULL) {
517 drm_intel_bo_unreference(i915->state.tex_buffer[i]);
518 i915->state.tex_buffer[i] = NULL;
522 _tnl_free_vertices(&intel->ctx);
526 i915_set_buf_info_for_region(uint32_t *state, struct intel_region *region,
529 state[0] = _3DSTATE_BUF_INFO_CMD;
530 state[1] = buffer_id;
532 if (region != NULL) {
533 state[1] |= BUF_3D_PITCH(region->pitch * region->cpp);
535 if (region->tiling != I915_TILING_NONE) {
536 state[1] |= BUF_3D_TILED_SURFACE;
537 if (region->tiling == I915_TILING_Y)
538 state[1] |= BUF_3D_TILE_WALK_Y;
541 /* Fill in a default pitch, since 0 is invalid. We'll be
542 * setting the buffer offset to 0 and not referencing the
543 * buffer, so the pitch could really be any valid value.
545 state[1] |= BUF_3D_PITCH(4096);
549 static uint32_t i915_render_target_format_for_mesa_format[MESA_FORMAT_COUNT] =
551 [MESA_FORMAT_ARGB8888] = DV_PF_8888,
552 [MESA_FORMAT_XRGB8888] = DV_PF_8888,
553 [MESA_FORMAT_RGB565] = DV_PF_565 | DITHER_FULL_ALWAYS,
554 [MESA_FORMAT_ARGB1555] = DV_PF_1555 | DITHER_FULL_ALWAYS,
555 [MESA_FORMAT_ARGB4444] = DV_PF_4444 | DITHER_FULL_ALWAYS,
559 i915_render_target_supported(gl_format format)
561 if (format == MESA_FORMAT_S8_Z24 ||
562 format == MESA_FORMAT_X8_Z24 ||
563 format == MESA_FORMAT_Z16) {
567 return i915_render_target_format_for_mesa_format[format] != 0;
571 i915_set_draw_region(struct intel_context *intel,
572 struct intel_region *color_regions[],
573 struct intel_region *depth_region,
576 struct i915_context *i915 = i915_context(&intel->ctx);
577 struct gl_context *ctx = &intel->ctx;
578 struct gl_renderbuffer *rb = ctx->DrawBuffer->_ColorDrawBuffers[0];
579 struct intel_renderbuffer *irb = intel_renderbuffer(rb);
580 struct gl_renderbuffer *drb;
581 struct intel_renderbuffer *idrb = NULL;
583 struct i915_hw_state *state = &i915->state;
584 uint32_t draw_x, draw_y, draw_offset;
586 if (state->draw_region != color_regions[0]) {
587 intel_region_reference(&state->draw_region, color_regions[0]);
589 if (state->depth_region != depth_region) {
590 intel_region_reference(&state->depth_region, depth_region);
594 * Set stride/cpp values
596 i915_set_buf_info_for_region(&state->Buffer[I915_DESTREG_CBUFADDR0],
597 color_regions[0], BUF_3D_ID_COLOR_BACK);
599 i915_set_buf_info_for_region(&state->Buffer[I915_DESTREG_DBUFADDR0],
600 depth_region, BUF_3D_ID_DEPTH);
603 * Compute/set I915_DESTREG_DV1 value
605 value = (DSTORG_HORT_BIAS(0x8) | /* .5 */
606 DSTORG_VERT_BIAS(0x8) | /* .5 */
607 LOD_PRECLAMP_OGL | TEX_DEFAULT_COLOR_OGL);
609 value |= i915_render_target_format_for_mesa_format[irb->Base.Format];
614 /* This isn't quite safe, thus being hidden behind an option. When changing
615 * the value of this bit, the pipeline needs to be MI_FLUSHed. And it
616 * can only be set when a depth buffer is already defined.
618 if (intel->is_945 && intel->use_early_z &&
619 depth_region->tiling != I915_TILING_NONE)
620 value |= CLASSIC_EARLY_DEPTH;
622 if (depth_region && depth_region->cpp == 4) {
623 value |= DEPTH_FRMT_24_FIXED_8_OTHER;
626 value |= DEPTH_FRMT_16_FIXED;
628 state->Buffer[I915_DESTREG_DV1] = value;
630 drb = ctx->DrawBuffer->Attachment[BUFFER_DEPTH].Renderbuffer;
632 drb = ctx->DrawBuffer->Attachment[BUFFER_STENCIL].Renderbuffer;
635 idrb = intel_renderbuffer(drb);
637 /* We set up the drawing rectangle to be offset into the color
638 * region's location in the miptree. If it doesn't match with
639 * depth's offsets, we can't render to it.
641 * (Well, not actually true -- the hw grew a bit to let depth's
642 * offset get forced to 0,0. We may want to use that if people are
643 * hitting that case. Also, some configurations may be supportable
644 * by tweaking the start offset of the buffers around, which we
645 * can't do in general due to tiling)
647 FALLBACK(intel, I915_FALLBACK_DRAW_OFFSET,
648 idrb && irb && (idrb->draw_x != irb->draw_x ||
649 idrb->draw_y != irb->draw_y));
652 draw_x = irb->draw_x;
653 draw_y = irb->draw_y;
655 draw_x = idrb->draw_x;
656 draw_y = idrb->draw_y;
662 draw_offset = (draw_y << 16) | draw_x;
664 /* When changing drawing rectangle offset, an MI_FLUSH is first required. */
665 if (draw_offset != i915->last_draw_offset) {
666 FALLBACK(intel, I915_FALLBACK_DRAW_OFFSET,
667 (ctx->DrawBuffer->Width + draw_x > 2048) ||
668 (ctx->DrawBuffer->Height + draw_y > 2048));
670 state->Buffer[I915_DESTREG_DRAWRECT0] = MI_FLUSH | INHIBIT_FLUSH_RENDER_CACHE;
671 i915->last_draw_offset = draw_offset;
673 state->Buffer[I915_DESTREG_DRAWRECT0] = MI_NOOP;
675 state->Buffer[I915_DESTREG_DRAWRECT1] = _3DSTATE_DRAWRECT_INFO;
676 state->Buffer[I915_DESTREG_DRAWRECT2] = 0;
677 state->Buffer[I915_DESTREG_DRAWRECT3] = draw_offset;
678 state->Buffer[I915_DESTREG_DRAWRECT4] =
679 ((ctx->DrawBuffer->Width + draw_x - 1) & 0xffff) |
680 ((ctx->DrawBuffer->Height + draw_y - 1) << 16);
681 state->Buffer[I915_DESTREG_DRAWRECT5] = draw_offset;
683 I915_STATECHANGE(i915, I915_UPLOAD_BUFFERS);
687 i915_update_color_write_enable(struct i915_context *i915, bool enable)
689 uint32_t dw = i915->state.Ctx[I915_CTXREG_LIS6];
691 dw |= S6_COLOR_WRITE_ENABLE;
693 dw &= ~S6_COLOR_WRITE_ENABLE;
694 if (dw != i915->state.Ctx[I915_CTXREG_LIS6]) {
695 I915_STATECHANGE(i915, I915_UPLOAD_CTX);
696 i915->state.Ctx[I915_CTXREG_LIS6] = dw;
701 * Update the hardware state for drawing into a window or framebuffer object.
703 * Called by glDrawBuffer, glBindFramebufferEXT, MakeCurrent, and other
704 * places within the driver.
706 * Basically, this needs to be called any time the current framebuffer
707 * changes, the renderbuffers change, or we need to draw into different
711 i915_update_draw_buffer(struct intel_context *intel)
713 struct i915_context *i915 = (struct i915_context *)intel;
714 struct gl_context *ctx = &intel->ctx;
715 struct gl_framebuffer *fb = ctx->DrawBuffer;
716 struct intel_region *colorRegion = NULL, *depthRegion = NULL;
717 struct intel_renderbuffer *irbDepth = NULL, *irbStencil = NULL;
718 bool fb_has_hiz = intel_framebuffer_has_hiz(fb);
721 /* this can happen during the initial context initialization */
725 irbDepth = intel_get_renderbuffer(fb, BUFFER_DEPTH);
726 irbStencil = intel_get_renderbuffer(fb, BUFFER_STENCIL);
728 /* Do this here, not core Mesa, since this function is called from
729 * many places within the driver.
731 if (ctx->NewState & _NEW_BUFFERS) {
732 /* this updates the DrawBuffer->_NumColorDrawBuffers fields, etc */
733 _mesa_update_framebuffer(ctx);
734 /* this updates the DrawBuffer's Width/Height if it's a FBO */
735 _mesa_update_draw_buffer_bounds(ctx);
738 if (fb->_Status != GL_FRAMEBUFFER_COMPLETE_EXT) {
739 /* this may occur when we're called by glBindFrameBuffer() during
740 * the process of someone setting up renderbuffers, etc.
742 /*_mesa_debug(ctx, "DrawBuffer: incomplete user FBO\n");*/
746 /* How many color buffers are we drawing into?
748 * If there is more than one drawbuffer (GL_FRONT_AND_BACK), or the
749 * drawbuffers are too big, we have to fallback to software.
751 if ((fb->Width > ctx->Const.MaxRenderbufferSize)
752 || (fb->Height > ctx->Const.MaxRenderbufferSize)) {
753 FALLBACK(intel, INTEL_FALLBACK_DRAW_BUFFER, true);
754 } else if (fb->_NumColorDrawBuffers > 1) {
755 FALLBACK(intel, INTEL_FALLBACK_DRAW_BUFFER, true);
757 struct intel_renderbuffer *irb;
758 irb = intel_renderbuffer(fb->_ColorDrawBuffers[0]);
759 colorRegion = irb ? irb->region : NULL;
760 FALLBACK(intel, INTEL_FALLBACK_DRAW_BUFFER, false);
763 /* Check for depth fallback. */
764 if (irbDepth && irbDepth->region) {
765 assert(!fb_has_hiz || irbDepth->Base.Format != MESA_FORMAT_S8_Z24);
766 FALLBACK(intel, INTEL_FALLBACK_DEPTH_BUFFER, GL_FALSE);
767 depthRegion = irbDepth->region;
768 } else if (irbDepth && !irbDepth->region) {
769 FALLBACK(intel, INTEL_FALLBACK_DEPTH_BUFFER, GL_TRUE);
771 } else { /* !irbDepth */
772 /* No fallback is needed because there is no depth buffer. */
773 FALLBACK(intel, INTEL_FALLBACK_DEPTH_BUFFER, GL_FALSE);
777 /* Check for stencil fallback. */
778 if (irbStencil && irbStencil->region) {
779 assert(irbStencil->Base.Format == MESA_FORMAT_S8_Z24);
780 FALLBACK(intel, INTEL_FALLBACK_STENCIL_BUFFER, GL_FALSE);
781 } else if (irbStencil && !irbStencil->region) {
782 FALLBACK(intel, INTEL_FALLBACK_STENCIL_BUFFER, GL_TRUE);
783 } else { /* !irbStencil */
784 /* No fallback is needed because there is no stencil buffer. */
785 FALLBACK(intel, INTEL_FALLBACK_STENCIL_BUFFER, GL_FALSE);
788 /* If we have a (packed) stencil buffer attached but no depth buffer,
789 * we still need to set up the shared depth/stencil state so we can use it.
791 if (depthRegion == NULL && irbStencil && irbStencil->region
792 && irbStencil->Base.Format == MESA_FORMAT_S8_Z24) {
793 depthRegion = irbStencil->region;
797 * Update depth and stencil test state
799 ctx->Driver.Enable(ctx, GL_DEPTH_TEST, ctx->Depth.Test);
800 ctx->Driver.Enable(ctx, GL_STENCIL_TEST, ctx->Stencil.Enabled);
802 i915_update_color_write_enable(i915, colorRegion != NULL);
804 intel->vtbl.set_draw_region(intel, &colorRegion, depthRegion,
805 fb->_NumColorDrawBuffers);
806 intel->NewGLState |= _NEW_BUFFERS;
808 /* update viewport since it depends on window size */
809 intelCalcViewport(ctx);
811 /* Set state we know depends on drawable parameters:
813 ctx->Driver.Scissor(ctx, ctx->Scissor.X, ctx->Scissor.Y,
814 ctx->Scissor.Width, ctx->Scissor.Height);
815 ctx->Driver.DepthRange(ctx, ctx->Viewport.Near, ctx->Viewport.Far);
817 /* Update culling direction which changes depending on the
818 * orientation of the buffer:
820 ctx->Driver.FrontFace(ctx, ctx->Polygon.FrontFace);
824 i915_new_batch(struct intel_context *intel)
826 struct i915_context *i915 = i915_context(&intel->ctx);
828 /* Mark all state as needing to be emitted when starting a new batchbuffer.
829 * Using hardware contexts would be an alternative, but they have some
830 * difficulties associated with them (physical address requirements).
832 i915->state.emitted = 0;
833 i915->last_draw_offset = 0;
834 i915->last_sampler = 0;
836 i915->current_vb_bo = NULL;
837 i915->current_vertex_size = 0;
841 i915_assert_not_dirty( struct intel_context *intel )
843 struct i915_context *i915 = i915_context(&intel->ctx);
844 GLuint dirty = get_dirty(&i915->state);
849 /** Return false; i915 does not support HiZ. */
851 i915_is_hiz_depth_format(struct intel_context *intel,
858 i915_invalidate_state(struct intel_context *intel, GLuint new_state)
860 struct gl_context *ctx = &intel->ctx;
862 _swsetup_InvalidateState(ctx, new_state);
863 _tnl_InvalidateState(ctx, new_state);
864 _tnl_invalidate_vertex_state(ctx, new_state);
868 i915InitVtbl(struct i915_context *i915)
870 i915->intel.vtbl.check_vertex_size = i915_check_vertex_size;
871 i915->intel.vtbl.destroy = i915_destroy_context;
872 i915->intel.vtbl.emit_state = i915_emit_state;
873 i915->intel.vtbl.new_batch = i915_new_batch;
874 i915->intel.vtbl.reduced_primitive_state = i915_reduced_primitive_state;
875 i915->intel.vtbl.render_start = i915_render_start;
876 i915->intel.vtbl.render_prevalidate = i915_render_prevalidate;
877 i915->intel.vtbl.set_draw_region = i915_set_draw_region;
878 i915->intel.vtbl.update_draw_buffer = i915_update_draw_buffer;
879 i915->intel.vtbl.update_texture_state = i915UpdateTextureState;
880 i915->intel.vtbl.assert_not_dirty = i915_assert_not_dirty;
881 i915->intel.vtbl.finish_batch = intel_finish_vb;
882 i915->intel.vtbl.invalidate_state = i915_invalidate_state;
883 i915->intel.vtbl.render_target_supported = i915_render_target_supported;
884 i915->intel.vtbl.is_hiz_depth_format = i915_is_hiz_depth_format;