1 /**************************************************************************
3 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **************************************************************************/
30 #include "main/glheader.h"
31 #include "main/mtypes.h"
32 #include "main/imports.h"
33 #include "main/macros.h"
34 #include "main/colormac.h"
36 #include "tnl/t_context.h"
37 #include "tnl/t_vertex.h"
39 #include "intel_batchbuffer.h"
40 #include "intel_tex.h"
41 #include "intel_regions.h"
42 #include "intel_tris.h"
43 #include "intel_fbo.h"
44 #include "intel_chipset.h"
47 #include "i915_context.h"
50 i915_render_prevalidate(struct intel_context *intel)
52 struct i915_context *i915 = i915_context(&intel->ctx);
54 i915ValidateFragmentProgram(i915);
58 i915_render_start(struct intel_context *intel)
64 i915_reduced_primitive_state(struct intel_context *intel, GLenum rprim)
66 struct i915_context *i915 = i915_context(&intel->ctx);
67 GLuint st1 = i915->state.Stipple[I915_STPREG_ST1];
72 case GL_QUADS: /* from RASTERIZE(GL_QUADS) in t_dd_tritemp.h */
74 if (intel->ctx.Polygon.StippleFlag && intel->hw_stipple)
83 i915->intel.reduced_primitive = rprim;
85 if (st1 != i915->state.Stipple[I915_STPREG_ST1]) {
86 INTEL_FIREVERTICES(intel);
88 I915_STATECHANGE(i915, I915_UPLOAD_STIPPLE);
89 i915->state.Stipple[I915_STPREG_ST1] = st1;
94 /* Pull apart the vertex format registers and figure out how large a
95 * vertex is supposed to be.
98 i915_check_vertex_size(struct intel_context *intel, GLuint expected)
100 struct i915_context *i915 = i915_context(&intel->ctx);
101 int lis2 = i915->current->Ctx[I915_CTXREG_LIS2];
102 int lis4 = i915->current->Ctx[I915_CTXREG_LIS4];
105 switch (lis4 & S4_VFMT_XYZW_MASK) {
119 fprintf(stderr, "no xyzw specified\n");
123 if (lis4 & S4_VFMT_SPEC_FOG)
125 if (lis4 & S4_VFMT_COLOR)
127 if (lis4 & S4_VFMT_DEPTH_OFFSET)
129 if (lis4 & S4_VFMT_POINT_WIDTH)
131 if (lis4 & S4_VFMT_FOG_PARAM)
134 for (i = 0; i < 8; i++) {
135 switch (lis2 & S2_TEXCOORD_FMT0_MASK) {
148 case TEXCOORDFMT_2D_16:
151 case TEXCOORDFMT_4D_16:
154 case TEXCOORDFMT_NOT_PRESENT:
157 fprintf(stderr, "bad texcoord fmt %d\n", i);
160 lis2 >>= S2_TEXCOORD_FMT1_SHIFT;
164 fprintf(stderr, "vertex size mismatch %d/%d\n", sz, expected);
166 return sz == expected;
171 i915_emit_invarient_state(struct intel_context *intel)
177 OUT_BATCH(_3DSTATE_AA_CMD |
178 AA_LINE_ECAAR_WIDTH_ENABLE |
179 AA_LINE_ECAAR_WIDTH_1_0 |
180 AA_LINE_REGION_WIDTH_ENABLE | AA_LINE_REGION_WIDTH_1_0);
182 OUT_BATCH(_3DSTATE_DFLT_DIFFUSE_CMD);
185 OUT_BATCH(_3DSTATE_DFLT_SPEC_CMD);
188 OUT_BATCH(_3DSTATE_DFLT_Z_CMD);
191 /* Don't support texture crossbar yet */
192 OUT_BATCH(_3DSTATE_COORD_SET_BINDINGS |
197 CSB_TCB(4, 4) | CSB_TCB(5, 5) | CSB_TCB(6, 6) | CSB_TCB(7, 7));
199 /* Need to initialize this to zero.
201 OUT_BATCH(_3DSTATE_LOAD_STATE_IMMEDIATE_1 | I1_LOAD_S(3) | (0));
205 OUT_BATCH(_3DSTATE_SCISSOR_ENABLE_CMD | DISABLE_SCISSOR_RECT);
207 OUT_BATCH(_3DSTATE_SCISSOR_RECT_0_CMD);
211 OUT_BATCH(_3DSTATE_DEPTH_SUBRECT_DISABLE);
213 OUT_BATCH(_3DSTATE_LOAD_INDIRECT | 0); /* disable indirect state */
220 #define emit(intel, state, size ) \
221 intel_batchbuffer_data(intel->batch, state, size)
224 get_dirty(struct i915_hw_state *state)
228 /* Workaround the multitex hang - if one texture unit state is
229 * modified, emit all texture units.
231 dirty = state->active & ~state->emitted;
232 if (dirty & I915_UPLOAD_TEX_ALL)
233 state->emitted &= ~I915_UPLOAD_TEX_ALL;
234 dirty = state->active & ~state->emitted;
240 get_state_size(struct i915_hw_state *state)
242 GLuint dirty = get_dirty(state);
246 if (dirty & I915_UPLOAD_INVARIENT)
249 if (dirty & I915_UPLOAD_RASTER_RULES)
250 sz += sizeof(state->RasterRules);
252 if (dirty & I915_UPLOAD_CTX)
253 sz += sizeof(state->Ctx);
255 if (dirty & I915_UPLOAD_BUFFERS)
256 sz += sizeof(state->Buffer);
258 if (dirty & I915_UPLOAD_STIPPLE)
259 sz += sizeof(state->Stipple);
261 if (dirty & I915_UPLOAD_FOG)
262 sz += sizeof(state->Fog);
264 if (dirty & I915_UPLOAD_TEX_ALL) {
266 for (i = 0; i < I915_TEX_UNITS; i++)
267 if (dirty & I915_UPLOAD_TEX(i))
270 sz += (2 + nr * 3) * sizeof(GLuint) * 2;
273 if (dirty & I915_UPLOAD_CONSTANTS)
274 sz += state->ConstantSize * sizeof(GLuint);
276 if (dirty & I915_UPLOAD_PROGRAM)
277 sz += state->ProgramSize * sizeof(GLuint);
282 /* Push the state into the sarea and/or texture memory.
285 i915_emit_state(struct intel_context *intel)
287 struct i915_context *i915 = i915_context(&intel->ctx);
288 struct i915_hw_state *state = i915->current;
289 int i, count, aper_count;
291 dri_bo *aper_array[3 + I915_TEX_UNITS];
292 GET_CURRENT_CONTEXT(ctx);
295 /* We don't hold the lock at this point, so want to make sure that
296 * there won't be a buffer wrap between the state emits and the primitive
299 * It might be better to talk about explicit places where
300 * scheduling is allowed, rather than assume that it is whenever a
301 * batchbuffer fills up.
303 intel_batchbuffer_require_space(intel->batch,
304 get_state_size(state) + INTEL_PRIM_EMIT_SIZE);
308 dirty = get_dirty(state);
310 aper_array[aper_count++] = intel->batch->buf;
311 if (dirty & I915_UPLOAD_BUFFERS) {
312 aper_array[aper_count++] = state->draw_region->buffer;
313 if (state->depth_region)
314 aper_array[aper_count++] = state->depth_region->buffer;
317 if (dirty & I915_UPLOAD_TEX_ALL) {
318 for (i = 0; i < I915_TEX_UNITS; i++) {
319 if (dirty & I915_UPLOAD_TEX(i)) {
320 if (state->tex_buffer[i]) {
321 aper_array[aper_count++] = state->tex_buffer[i];
327 if (dri_bufmgr_check_aperture_space(aper_array, aper_count)) {
330 intel_batchbuffer_flush(intel->batch);
333 _mesa_error(ctx, GL_OUT_OF_MEMORY, "i915 emit state");
338 /* work out list of buffers to emit */
340 /* Do this here as we may have flushed the batchbuffer above,
341 * causing more state to be dirty!
343 dirty = get_dirty(state);
344 state->emitted |= dirty;
345 assert(get_dirty(state) == 0);
347 if (INTEL_DEBUG & DEBUG_STATE)
348 fprintf(stderr, "%s dirty: %x\n", __FUNCTION__, dirty);
350 if (dirty & I915_UPLOAD_INVARIENT) {
351 if (INTEL_DEBUG & DEBUG_STATE)
352 fprintf(stderr, "I915_UPLOAD_INVARIENT:\n");
353 i915_emit_invarient_state(intel);
356 if (dirty & I915_UPLOAD_RASTER_RULES) {
357 if (INTEL_DEBUG & DEBUG_STATE)
358 fprintf(stderr, "I915_UPLOAD_RASTER_RULES:\n");
359 emit(intel, state->RasterRules, sizeof(state->RasterRules));
362 if (dirty & I915_UPLOAD_CTX) {
363 if (INTEL_DEBUG & DEBUG_STATE)
364 fprintf(stderr, "I915_UPLOAD_CTX:\n");
366 emit(intel, state->Ctx, sizeof(state->Ctx));
369 if (dirty & I915_UPLOAD_BUFFERS) {
372 if (INTEL_DEBUG & DEBUG_STATE)
373 fprintf(stderr, "I915_UPLOAD_BUFFERS:\n");
375 if (state->depth_region)
379 OUT_BATCH(state->Buffer[I915_DESTREG_CBUFADDR0]);
380 OUT_BATCH(state->Buffer[I915_DESTREG_CBUFADDR1]);
381 OUT_RELOC(state->draw_region->buffer,
382 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
383 state->draw_region->draw_offset);
385 if (state->depth_region) {
386 OUT_BATCH(state->Buffer[I915_DESTREG_DBUFADDR0]);
387 OUT_BATCH(state->Buffer[I915_DESTREG_DBUFADDR1]);
388 OUT_RELOC(state->depth_region->buffer,
389 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
390 state->depth_region->draw_offset);
393 OUT_BATCH(state->Buffer[I915_DESTREG_DV0]);
394 OUT_BATCH(state->Buffer[I915_DESTREG_DV1]);
395 OUT_BATCH(state->Buffer[I915_DESTREG_SENABLE]);
396 OUT_BATCH(state->Buffer[I915_DESTREG_SR0]);
397 OUT_BATCH(state->Buffer[I915_DESTREG_SR1]);
398 OUT_BATCH(state->Buffer[I915_DESTREG_SR2]);
400 assert(state->Buffer[I915_DESTREG_DRAWRECT0] != MI_NOOP);
401 OUT_BATCH(state->Buffer[I915_DESTREG_DRAWRECT0]);
402 OUT_BATCH(state->Buffer[I915_DESTREG_DRAWRECT1]);
403 OUT_BATCH(state->Buffer[I915_DESTREG_DRAWRECT2]);
404 OUT_BATCH(state->Buffer[I915_DESTREG_DRAWRECT3]);
405 OUT_BATCH(state->Buffer[I915_DESTREG_DRAWRECT4]);
406 OUT_BATCH(state->Buffer[I915_DESTREG_DRAWRECT5]);
411 if (dirty & I915_UPLOAD_STIPPLE) {
412 if (INTEL_DEBUG & DEBUG_STATE)
413 fprintf(stderr, "I915_UPLOAD_STIPPLE:\n");
414 emit(intel, state->Stipple, sizeof(state->Stipple));
417 if (dirty & I915_UPLOAD_FOG) {
418 if (INTEL_DEBUG & DEBUG_STATE)
419 fprintf(stderr, "I915_UPLOAD_FOG:\n");
420 emit(intel, state->Fog, sizeof(state->Fog));
423 /* Combine all the dirty texture state into a single command to
424 * avoid lockups on I915 hardware.
426 if (dirty & I915_UPLOAD_TEX_ALL) {
429 for (i = 0; i < I915_TEX_UNITS; i++)
430 if (dirty & I915_UPLOAD_TEX(i))
433 BEGIN_BATCH(2 + nr * 3);
434 OUT_BATCH(_3DSTATE_MAP_STATE | (3 * nr));
435 OUT_BATCH((dirty & I915_UPLOAD_TEX_ALL) >> I915_UPLOAD_TEX_0_SHIFT);
436 for (i = 0; i < I915_TEX_UNITS; i++)
437 if (dirty & I915_UPLOAD_TEX(i)) {
439 if (state->tex_buffer[i]) {
440 OUT_RELOC(state->tex_buffer[i],
441 I915_GEM_DOMAIN_SAMPLER, 0,
442 state->tex_offset[i]);
444 else if (state == &i915->meta) {
449 OUT_BATCH(state->tex_offset[i]);
452 OUT_BATCH(state->Tex[i][I915_TEXREG_MS3]);
453 OUT_BATCH(state->Tex[i][I915_TEXREG_MS4]);
457 BEGIN_BATCH(2 + nr * 3);
458 OUT_BATCH(_3DSTATE_SAMPLER_STATE | (3 * nr));
459 OUT_BATCH((dirty & I915_UPLOAD_TEX_ALL) >> I915_UPLOAD_TEX_0_SHIFT);
460 for (i = 0; i < I915_TEX_UNITS; i++)
461 if (dirty & I915_UPLOAD_TEX(i)) {
462 OUT_BATCH(state->Tex[i][I915_TEXREG_SS2]);
463 OUT_BATCH(state->Tex[i][I915_TEXREG_SS3]);
464 OUT_BATCH(state->Tex[i][I915_TEXREG_SS4]);
469 if (dirty & I915_UPLOAD_CONSTANTS) {
470 if (INTEL_DEBUG & DEBUG_STATE)
471 fprintf(stderr, "I915_UPLOAD_CONSTANTS:\n");
472 emit(intel, state->Constant, state->ConstantSize * sizeof(GLuint));
475 if (dirty & I915_UPLOAD_PROGRAM) {
476 if (state->ProgramSize) {
477 if (INTEL_DEBUG & DEBUG_STATE)
478 fprintf(stderr, "I915_UPLOAD_PROGRAM:\n");
480 assert((state->Program[0] & 0x1ff) + 2 == state->ProgramSize);
482 emit(intel, state->Program, state->ProgramSize * sizeof(GLuint));
483 if (INTEL_DEBUG & DEBUG_STATE)
484 i915_disassemble_program(state->Program, state->ProgramSize);
488 intel->batch->dirty_state &= ~dirty;
489 assert(get_dirty(state) == 0);
490 assert((intel->batch->dirty_state & (1<<1)) == 0);
494 i915_destroy_context(struct intel_context *intel)
497 struct i915_context *i915 = i915_context(&intel->ctx);
499 intel_region_release(&i915->state.draw_region);
500 intel_region_release(&i915->state.depth_region);
501 intel_region_release(&i915->meta.draw_region);
502 intel_region_release(&i915->meta.depth_region);
503 intel_region_release(&i915->initial.draw_region);
504 intel_region_release(&i915->initial.depth_region);
506 for (i = 0; i < I915_TEX_UNITS; i++) {
507 if (i915->state.tex_buffer[i] != NULL) {
508 dri_bo_unreference(i915->state.tex_buffer[i]);
509 i915->state.tex_buffer[i] = NULL;
513 _tnl_free_vertices(&intel->ctx);
517 i915_set_buf_info_for_region(uint32_t *state, struct intel_region *region,
520 state[0] = _3DSTATE_BUF_INFO_CMD;
521 state[1] = buffer_id;
523 if (region != NULL) {
524 state[1] |= BUF_3D_PITCH(region->pitch * region->cpp);
526 if (region->tiling != I915_TILING_NONE) {
527 state[1] |= BUF_3D_TILED_SURFACE;
528 if (region->tiling == I915_TILING_Y)
529 state[1] |= BUF_3D_TILE_WALK_Y;
535 * Set the drawing regions for the color and depth/stencil buffers.
536 * This involves setting the pitch, cpp and buffer ID/location.
537 * Also set pixel format for color and Z rendering
538 * Used for setting both regular and meta state.
541 i915_state_draw_region(struct intel_context *intel,
542 struct i915_hw_state *state,
543 struct intel_region *color_region,
544 struct intel_region *depth_region)
546 struct i915_context *i915 = i915_context(&intel->ctx);
547 GLcontext *ctx = &intel->ctx;
548 struct gl_renderbuffer *rb = ctx->DrawBuffer->_ColorDrawBuffers[0];
549 struct intel_renderbuffer *irb = intel_renderbuffer(rb);
552 ASSERT(state == &i915->state || state == &i915->meta);
554 if (state->draw_region != color_region) {
555 intel_region_release(&state->draw_region);
556 intel_region_reference(&state->draw_region, color_region);
558 if (state->depth_region != depth_region) {
559 intel_region_release(&state->depth_region);
560 intel_region_reference(&state->depth_region, depth_region);
564 * Set stride/cpp values
566 i915_set_buf_info_for_region(&state->Buffer[I915_DESTREG_CBUFADDR0],
567 color_region, BUF_3D_ID_COLOR_BACK);
569 i915_set_buf_info_for_region(&state->Buffer[I915_DESTREG_DBUFADDR0],
570 depth_region, BUF_3D_ID_DEPTH);
573 * Compute/set I915_DESTREG_DV1 value
575 value = (DSTORG_HORT_BIAS(0x8) | /* .5 */
576 DSTORG_VERT_BIAS(0x8) | /* .5 */
577 LOD_PRECLAMP_OGL | TEX_DEFAULT_COLOR_OGL);
579 switch (irb->Base.Format) {
580 case MESA_FORMAT_ARGB8888:
581 case MESA_FORMAT_XRGB8888:
584 case MESA_FORMAT_RGB565:
585 value |= DV_PF_565 | DITHER_FULL_ALWAYS;
587 case MESA_FORMAT_ARGB1555:
588 value |= DV_PF_1555 | DITHER_FULL_ALWAYS;
590 case MESA_FORMAT_ARGB4444:
591 value |= DV_PF_4444 | DITHER_FULL_ALWAYS;
594 _mesa_problem(ctx, "Bad renderbuffer format: %d\n",
599 /* This isn't quite safe, thus being hidden behind an option. When changing
600 * the value of this bit, the pipeline needs to be MI_FLUSHed. And it
601 * can only be set when a depth buffer is already defined.
603 if (intel->is_945 && intel->use_early_z &&
604 depth_region->tiling != I915_TILING_NONE)
605 value |= CLASSIC_EARLY_DEPTH;
607 if (depth_region && depth_region->cpp == 4) {
608 value |= DEPTH_FRMT_24_FIXED_8_OTHER;
611 value |= DEPTH_FRMT_16_FIXED;
613 state->Buffer[I915_DESTREG_DV1] = value;
615 state->Buffer[I915_DESTREG_DRAWRECT0] = _3DSTATE_DRAWRECT_INFO;
616 state->Buffer[I915_DESTREG_DRAWRECT1] = 0;
617 state->Buffer[I915_DESTREG_DRAWRECT2] = 0; /* xmin, ymin */
618 state->Buffer[I915_DESTREG_DRAWRECT3] =
619 (ctx->DrawBuffer->Width & 0xffff) |
620 (ctx->DrawBuffer->Height << 16);
621 state->Buffer[I915_DESTREG_DRAWRECT4] = 0; /* xoff, yoff */
622 state->Buffer[I915_DESTREG_DRAWRECT5] = 0;
624 I915_STATECHANGE(i915, I915_UPLOAD_BUFFERS);
629 i915_set_draw_region(struct intel_context *intel,
630 struct intel_region *color_regions[],
631 struct intel_region *depth_region,
634 struct i915_context *i915 = i915_context(&intel->ctx);
635 i915_state_draw_region(intel, &i915->state, color_regions[0], depth_region);
641 i915_new_batch(struct intel_context *intel)
643 struct i915_context *i915 = i915_context(&intel->ctx);
645 /* Mark all state as needing to be emitted when starting a new batchbuffer.
646 * Using hardware contexts would be an alternative, but they have some
647 * difficulties associated with them (physical address requirements).
649 i915->state.emitted = 0;
653 i915_assert_not_dirty( struct intel_context *intel )
655 struct i915_context *i915 = i915_context(&intel->ctx);
656 struct i915_hw_state *state = i915->current;
657 GLuint dirty = get_dirty(state);
662 i915InitVtbl(struct i915_context *i915)
664 i915->intel.vtbl.check_vertex_size = i915_check_vertex_size;
665 i915->intel.vtbl.destroy = i915_destroy_context;
666 i915->intel.vtbl.emit_state = i915_emit_state;
667 i915->intel.vtbl.new_batch = i915_new_batch;
668 i915->intel.vtbl.reduced_primitive_state = i915_reduced_primitive_state;
669 i915->intel.vtbl.render_start = i915_render_start;
670 i915->intel.vtbl.render_prevalidate = i915_render_prevalidate;
671 i915->intel.vtbl.set_draw_region = i915_set_draw_region;
672 i915->intel.vtbl.update_texture_state = i915UpdateTextureState;
673 i915->intel.vtbl.assert_not_dirty = i915_assert_not_dirty;
674 i915->intel.vtbl.finish_batch = intel_finish_vb;