1 /**************************************************************************
3 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **************************************************************************/
30 #include "main/glheader.h"
31 #include "main/mtypes.h"
32 #include "main/imports.h"
33 #include "main/macros.h"
34 #include "main/colormac.h"
36 #include "tnl/t_context.h"
37 #include "tnl/t_vertex.h"
39 #include "intel_batchbuffer.h"
40 #include "intel_regions.h"
41 #include "intel_tris.h"
42 #include "intel_fbo.h"
43 #include "intel_chipset.h"
46 #include "i915_context.h"
49 i915_render_prevalidate(struct intel_context *intel)
51 struct i915_context *i915 = i915_context(&intel->ctx);
53 i915ValidateFragmentProgram(i915);
57 i915_render_start(struct intel_context *intel)
63 i915_reduced_primitive_state(struct intel_context *intel, GLenum rprim)
65 struct i915_context *i915 = i915_context(&intel->ctx);
66 GLuint st1 = i915->state.Stipple[I915_STPREG_ST1];
71 case GL_QUADS: /* from RASTERIZE(GL_QUADS) in t_dd_tritemp.h */
73 if (intel->ctx.Polygon.StippleFlag && intel->hw_stipple)
82 i915->intel.reduced_primitive = rprim;
84 if (st1 != i915->state.Stipple[I915_STPREG_ST1]) {
85 INTEL_FIREVERTICES(intel);
87 I915_STATECHANGE(i915, I915_UPLOAD_STIPPLE);
88 i915->state.Stipple[I915_STPREG_ST1] = st1;
93 /* Pull apart the vertex format registers and figure out how large a
94 * vertex is supposed to be.
97 i915_check_vertex_size(struct intel_context *intel, GLuint expected)
99 struct i915_context *i915 = i915_context(&intel->ctx);
100 int lis2 = i915->current->Ctx[I915_CTXREG_LIS2];
101 int lis4 = i915->current->Ctx[I915_CTXREG_LIS4];
104 switch (lis4 & S4_VFMT_XYZW_MASK) {
118 fprintf(stderr, "no xyzw specified\n");
122 if (lis4 & S4_VFMT_SPEC_FOG)
124 if (lis4 & S4_VFMT_COLOR)
126 if (lis4 & S4_VFMT_DEPTH_OFFSET)
128 if (lis4 & S4_VFMT_POINT_WIDTH)
130 if (lis4 & S4_VFMT_FOG_PARAM)
133 for (i = 0; i < 8; i++) {
134 switch (lis2 & S2_TEXCOORD_FMT0_MASK) {
147 case TEXCOORDFMT_2D_16:
150 case TEXCOORDFMT_4D_16:
153 case TEXCOORDFMT_NOT_PRESENT:
156 fprintf(stderr, "bad texcoord fmt %d\n", i);
159 lis2 >>= S2_TEXCOORD_FMT1_SHIFT;
163 fprintf(stderr, "vertex size mismatch %d/%d\n", sz, expected);
165 return sz == expected;
170 i915_emit_invarient_state(struct intel_context *intel)
176 OUT_BATCH(_3DSTATE_AA_CMD |
177 AA_LINE_ECAAR_WIDTH_ENABLE |
178 AA_LINE_ECAAR_WIDTH_1_0 |
179 AA_LINE_REGION_WIDTH_ENABLE | AA_LINE_REGION_WIDTH_1_0);
181 OUT_BATCH(_3DSTATE_DFLT_DIFFUSE_CMD);
184 OUT_BATCH(_3DSTATE_DFLT_SPEC_CMD);
187 OUT_BATCH(_3DSTATE_DFLT_Z_CMD);
190 /* Don't support texture crossbar yet */
191 OUT_BATCH(_3DSTATE_COORD_SET_BINDINGS |
196 CSB_TCB(4, 4) | CSB_TCB(5, 5) | CSB_TCB(6, 6) | CSB_TCB(7, 7));
198 /* Need to initialize this to zero.
200 OUT_BATCH(_3DSTATE_LOAD_STATE_IMMEDIATE_1 | I1_LOAD_S(3) | (0));
204 OUT_BATCH(_3DSTATE_SCISSOR_ENABLE_CMD | DISABLE_SCISSOR_RECT);
206 OUT_BATCH(_3DSTATE_SCISSOR_RECT_0_CMD);
210 OUT_BATCH(_3DSTATE_DEPTH_SUBRECT_DISABLE);
212 OUT_BATCH(_3DSTATE_LOAD_INDIRECT | 0); /* disable indirect state */
219 #define emit(intel, state, size ) \
220 intel_batchbuffer_data(intel->batch, state, size)
223 get_dirty(struct i915_hw_state *state)
227 /* Workaround the multitex hang - if one texture unit state is
228 * modified, emit all texture units.
230 dirty = state->active & ~state->emitted;
231 if (dirty & I915_UPLOAD_TEX_ALL)
232 state->emitted &= ~I915_UPLOAD_TEX_ALL;
233 dirty = state->active & ~state->emitted;
239 get_state_size(struct i915_hw_state *state)
241 GLuint dirty = get_dirty(state);
245 if (dirty & I915_UPLOAD_INVARIENT)
248 if (dirty & I915_UPLOAD_RASTER_RULES)
249 sz += sizeof(state->RasterRules);
251 if (dirty & I915_UPLOAD_CTX)
252 sz += sizeof(state->Ctx);
254 if (dirty & I915_UPLOAD_BUFFERS)
255 sz += sizeof(state->Buffer);
257 if (dirty & I915_UPLOAD_STIPPLE)
258 sz += sizeof(state->Stipple);
260 if (dirty & I915_UPLOAD_FOG)
261 sz += sizeof(state->Fog);
263 if (dirty & I915_UPLOAD_TEX_ALL) {
265 for (i = 0; i < I915_TEX_UNITS; i++)
266 if (dirty & I915_UPLOAD_TEX(i))
269 sz += (2 + nr * 3) * sizeof(GLuint) * 2;
272 if (dirty & I915_UPLOAD_CONSTANTS)
273 sz += state->ConstantSize * sizeof(GLuint);
275 if (dirty & I915_UPLOAD_PROGRAM)
276 sz += state->ProgramSize * sizeof(GLuint);
281 /* Push the state into the sarea and/or texture memory.
284 i915_emit_state(struct intel_context *intel)
286 struct i915_context *i915 = i915_context(&intel->ctx);
287 struct i915_hw_state *state = i915->current;
288 int i, count, aper_count;
290 dri_bo *aper_array[3 + I915_TEX_UNITS];
291 GET_CURRENT_CONTEXT(ctx);
294 /* We don't hold the lock at this point, so want to make sure that
295 * there won't be a buffer wrap between the state emits and the primitive
298 * It might be better to talk about explicit places where
299 * scheduling is allowed, rather than assume that it is whenever a
300 * batchbuffer fills up.
302 intel_batchbuffer_require_space(intel->batch,
303 get_state_size(state) + INTEL_PRIM_EMIT_SIZE);
307 dirty = get_dirty(state);
309 aper_array[aper_count++] = intel->batch->buf;
310 if (dirty & I915_UPLOAD_BUFFERS) {
311 aper_array[aper_count++] = state->draw_region->buffer;
312 if (state->depth_region)
313 aper_array[aper_count++] = state->depth_region->buffer;
316 if (dirty & I915_UPLOAD_TEX_ALL) {
317 for (i = 0; i < I915_TEX_UNITS; i++) {
318 if (dirty & I915_UPLOAD_TEX(i)) {
319 if (state->tex_buffer[i]) {
320 aper_array[aper_count++] = state->tex_buffer[i];
326 if (dri_bufmgr_check_aperture_space(aper_array, aper_count)) {
329 intel_batchbuffer_flush(intel->batch);
332 _mesa_error(ctx, GL_OUT_OF_MEMORY, "i915 emit state");
337 /* work out list of buffers to emit */
339 /* Do this here as we may have flushed the batchbuffer above,
340 * causing more state to be dirty!
342 dirty = get_dirty(state);
343 state->emitted |= dirty;
344 assert(get_dirty(state) == 0);
346 if (INTEL_DEBUG & DEBUG_STATE)
347 fprintf(stderr, "%s dirty: %x\n", __FUNCTION__, dirty);
349 if (dirty & I915_UPLOAD_INVARIENT) {
350 if (INTEL_DEBUG & DEBUG_STATE)
351 fprintf(stderr, "I915_UPLOAD_INVARIENT:\n");
352 i915_emit_invarient_state(intel);
355 if (dirty & I915_UPLOAD_RASTER_RULES) {
356 if (INTEL_DEBUG & DEBUG_STATE)
357 fprintf(stderr, "I915_UPLOAD_RASTER_RULES:\n");
358 emit(intel, state->RasterRules, sizeof(state->RasterRules));
361 if (dirty & I915_UPLOAD_CTX) {
362 if (INTEL_DEBUG & DEBUG_STATE)
363 fprintf(stderr, "I915_UPLOAD_CTX:\n");
365 emit(intel, state->Ctx, sizeof(state->Ctx));
368 if (dirty & I915_UPLOAD_BUFFERS) {
371 if (INTEL_DEBUG & DEBUG_STATE)
372 fprintf(stderr, "I915_UPLOAD_BUFFERS:\n");
374 if (state->depth_region)
378 OUT_BATCH(state->Buffer[I915_DESTREG_CBUFADDR0]);
379 OUT_BATCH(state->Buffer[I915_DESTREG_CBUFADDR1]);
380 OUT_RELOC(state->draw_region->buffer,
381 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
382 state->draw_region->draw_offset);
384 if (state->depth_region) {
385 OUT_BATCH(state->Buffer[I915_DESTREG_DBUFADDR0]);
386 OUT_BATCH(state->Buffer[I915_DESTREG_DBUFADDR1]);
387 OUT_RELOC(state->depth_region->buffer,
388 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
389 state->depth_region->draw_offset);
392 OUT_BATCH(state->Buffer[I915_DESTREG_DV0]);
393 OUT_BATCH(state->Buffer[I915_DESTREG_DV1]);
394 OUT_BATCH(state->Buffer[I915_DESTREG_SENABLE]);
395 OUT_BATCH(state->Buffer[I915_DESTREG_SR0]);
396 OUT_BATCH(state->Buffer[I915_DESTREG_SR1]);
397 OUT_BATCH(state->Buffer[I915_DESTREG_SR2]);
399 assert(state->Buffer[I915_DESTREG_DRAWRECT0] != MI_NOOP);
400 OUT_BATCH(state->Buffer[I915_DESTREG_DRAWRECT0]);
401 OUT_BATCH(state->Buffer[I915_DESTREG_DRAWRECT1]);
402 OUT_BATCH(state->Buffer[I915_DESTREG_DRAWRECT2]);
403 OUT_BATCH(state->Buffer[I915_DESTREG_DRAWRECT3]);
404 OUT_BATCH(state->Buffer[I915_DESTREG_DRAWRECT4]);
405 OUT_BATCH(state->Buffer[I915_DESTREG_DRAWRECT5]);
410 if (dirty & I915_UPLOAD_STIPPLE) {
411 if (INTEL_DEBUG & DEBUG_STATE)
412 fprintf(stderr, "I915_UPLOAD_STIPPLE:\n");
413 emit(intel, state->Stipple, sizeof(state->Stipple));
416 if (dirty & I915_UPLOAD_FOG) {
417 if (INTEL_DEBUG & DEBUG_STATE)
418 fprintf(stderr, "I915_UPLOAD_FOG:\n");
419 emit(intel, state->Fog, sizeof(state->Fog));
422 /* Combine all the dirty texture state into a single command to
423 * avoid lockups on I915 hardware.
425 if (dirty & I915_UPLOAD_TEX_ALL) {
428 for (i = 0; i < I915_TEX_UNITS; i++)
429 if (dirty & I915_UPLOAD_TEX(i))
432 BEGIN_BATCH(2 + nr * 3);
433 OUT_BATCH(_3DSTATE_MAP_STATE | (3 * nr));
434 OUT_BATCH((dirty & I915_UPLOAD_TEX_ALL) >> I915_UPLOAD_TEX_0_SHIFT);
435 for (i = 0; i < I915_TEX_UNITS; i++)
436 if (dirty & I915_UPLOAD_TEX(i)) {
438 if (state->tex_buffer[i]) {
439 OUT_RELOC(state->tex_buffer[i],
440 I915_GEM_DOMAIN_SAMPLER, 0,
441 state->tex_offset[i]);
443 else if (state == &i915->meta) {
448 OUT_BATCH(state->tex_offset[i]);
451 OUT_BATCH(state->Tex[i][I915_TEXREG_MS3]);
452 OUT_BATCH(state->Tex[i][I915_TEXREG_MS4]);
456 BEGIN_BATCH(2 + nr * 3);
457 OUT_BATCH(_3DSTATE_SAMPLER_STATE | (3 * nr));
458 OUT_BATCH((dirty & I915_UPLOAD_TEX_ALL) >> I915_UPLOAD_TEX_0_SHIFT);
459 for (i = 0; i < I915_TEX_UNITS; i++)
460 if (dirty & I915_UPLOAD_TEX(i)) {
461 OUT_BATCH(state->Tex[i][I915_TEXREG_SS2]);
462 OUT_BATCH(state->Tex[i][I915_TEXREG_SS3]);
463 OUT_BATCH(state->Tex[i][I915_TEXREG_SS4]);
468 if (dirty & I915_UPLOAD_CONSTANTS) {
469 if (INTEL_DEBUG & DEBUG_STATE)
470 fprintf(stderr, "I915_UPLOAD_CONSTANTS:\n");
471 emit(intel, state->Constant, state->ConstantSize * sizeof(GLuint));
474 if (dirty & I915_UPLOAD_PROGRAM) {
475 if (state->ProgramSize) {
476 if (INTEL_DEBUG & DEBUG_STATE)
477 fprintf(stderr, "I915_UPLOAD_PROGRAM:\n");
479 assert((state->Program[0] & 0x1ff) + 2 == state->ProgramSize);
481 emit(intel, state->Program, state->ProgramSize * sizeof(GLuint));
482 if (INTEL_DEBUG & DEBUG_STATE)
483 i915_disassemble_program(state->Program, state->ProgramSize);
487 intel->batch->dirty_state &= ~dirty;
488 assert(get_dirty(state) == 0);
489 assert((intel->batch->dirty_state & (1<<1)) == 0);
493 i915_destroy_context(struct intel_context *intel)
496 struct i915_context *i915 = i915_context(&intel->ctx);
498 intel_region_release(&i915->state.draw_region);
499 intel_region_release(&i915->state.depth_region);
500 intel_region_release(&i915->meta.draw_region);
501 intel_region_release(&i915->meta.depth_region);
502 intel_region_release(&i915->initial.draw_region);
503 intel_region_release(&i915->initial.depth_region);
505 for (i = 0; i < I915_TEX_UNITS; i++) {
506 if (i915->state.tex_buffer[i] != NULL) {
507 dri_bo_unreference(i915->state.tex_buffer[i]);
508 i915->state.tex_buffer[i] = NULL;
512 _tnl_free_vertices(&intel->ctx);
516 i915_set_buf_info_for_region(uint32_t *state, struct intel_region *region,
519 state[0] = _3DSTATE_BUF_INFO_CMD;
520 state[1] = buffer_id;
522 if (region != NULL) {
523 state[1] |= BUF_3D_PITCH(region->pitch * region->cpp);
525 if (region->tiling != I915_TILING_NONE) {
526 state[1] |= BUF_3D_TILED_SURFACE;
527 if (region->tiling == I915_TILING_Y)
528 state[1] |= BUF_3D_TILE_WALK_Y;
534 * Set the drawing regions for the color and depth/stencil buffers.
535 * This involves setting the pitch, cpp and buffer ID/location.
536 * Also set pixel format for color and Z rendering
537 * Used for setting both regular and meta state.
540 i915_state_draw_region(struct intel_context *intel,
541 struct i915_hw_state *state,
542 struct intel_region *color_region,
543 struct intel_region *depth_region)
545 struct i915_context *i915 = i915_context(&intel->ctx);
546 GLcontext *ctx = &intel->ctx;
547 struct gl_renderbuffer *rb = ctx->DrawBuffer->_ColorDrawBuffers[0];
548 struct intel_renderbuffer *irb = intel_renderbuffer(rb);
551 ASSERT(state == &i915->state || state == &i915->meta);
553 if (state->draw_region != color_region) {
554 intel_region_release(&state->draw_region);
555 intel_region_reference(&state->draw_region, color_region);
557 if (state->depth_region != depth_region) {
558 intel_region_release(&state->depth_region);
559 intel_region_reference(&state->depth_region, depth_region);
563 * Set stride/cpp values
565 i915_set_buf_info_for_region(&state->Buffer[I915_DESTREG_CBUFADDR0],
566 color_region, BUF_3D_ID_COLOR_BACK);
568 i915_set_buf_info_for_region(&state->Buffer[I915_DESTREG_DBUFADDR0],
569 depth_region, BUF_3D_ID_DEPTH);
572 * Compute/set I915_DESTREG_DV1 value
574 value = (DSTORG_HORT_BIAS(0x8) | /* .5 */
575 DSTORG_VERT_BIAS(0x8) | /* .5 */
576 LOD_PRECLAMP_OGL | TEX_DEFAULT_COLOR_OGL);
578 switch (irb->Base.Format) {
579 case MESA_FORMAT_ARGB8888:
580 case MESA_FORMAT_XRGB8888:
583 case MESA_FORMAT_RGB565:
584 value |= DV_PF_565 | DITHER_FULL_ALWAYS;
586 case MESA_FORMAT_ARGB1555:
587 value |= DV_PF_1555 | DITHER_FULL_ALWAYS;
589 case MESA_FORMAT_ARGB4444:
590 value |= DV_PF_4444 | DITHER_FULL_ALWAYS;
593 _mesa_problem(ctx, "Bad renderbuffer format: %d\n",
598 /* This isn't quite safe, thus being hidden behind an option. When changing
599 * the value of this bit, the pipeline needs to be MI_FLUSHed. And it
600 * can only be set when a depth buffer is already defined.
602 if (intel->is_945 && intel->use_early_z &&
603 depth_region->tiling != I915_TILING_NONE)
604 value |= CLASSIC_EARLY_DEPTH;
606 if (depth_region && depth_region->cpp == 4) {
607 value |= DEPTH_FRMT_24_FIXED_8_OTHER;
610 value |= DEPTH_FRMT_16_FIXED;
612 state->Buffer[I915_DESTREG_DV1] = value;
614 state->Buffer[I915_DESTREG_DRAWRECT0] = _3DSTATE_DRAWRECT_INFO;
615 state->Buffer[I915_DESTREG_DRAWRECT1] = 0;
616 state->Buffer[I915_DESTREG_DRAWRECT2] = 0; /* xmin, ymin */
617 state->Buffer[I915_DESTREG_DRAWRECT3] =
618 (ctx->DrawBuffer->Width & 0xffff) |
619 (ctx->DrawBuffer->Height << 16);
620 state->Buffer[I915_DESTREG_DRAWRECT4] = 0; /* xoff, yoff */
621 state->Buffer[I915_DESTREG_DRAWRECT5] = 0;
623 I915_STATECHANGE(i915, I915_UPLOAD_BUFFERS);
628 i915_set_draw_region(struct intel_context *intel,
629 struct intel_region *color_regions[],
630 struct intel_region *depth_region,
633 struct i915_context *i915 = i915_context(&intel->ctx);
634 i915_state_draw_region(intel, &i915->state, color_regions[0], depth_region);
640 i915_new_batch(struct intel_context *intel)
642 struct i915_context *i915 = i915_context(&intel->ctx);
644 /* Mark all state as needing to be emitted when starting a new batchbuffer.
645 * Using hardware contexts would be an alternative, but they have some
646 * difficulties associated with them (physical address requirements).
648 i915->state.emitted = 0;
652 i915_assert_not_dirty( struct intel_context *intel )
654 struct i915_context *i915 = i915_context(&intel->ctx);
655 struct i915_hw_state *state = i915->current;
656 GLuint dirty = get_dirty(state);
661 i915InitVtbl(struct i915_context *i915)
663 i915->intel.vtbl.check_vertex_size = i915_check_vertex_size;
664 i915->intel.vtbl.destroy = i915_destroy_context;
665 i915->intel.vtbl.emit_state = i915_emit_state;
666 i915->intel.vtbl.new_batch = i915_new_batch;
667 i915->intel.vtbl.reduced_primitive_state = i915_reduced_primitive_state;
668 i915->intel.vtbl.render_start = i915_render_start;
669 i915->intel.vtbl.render_prevalidate = i915_render_prevalidate;
670 i915->intel.vtbl.set_draw_region = i915_set_draw_region;
671 i915->intel.vtbl.update_texture_state = i915UpdateTextureState;
672 i915->intel.vtbl.assert_not_dirty = i915_assert_not_dirty;
673 i915->intel.vtbl.finish_batch = intel_finish_vb;