1 /**************************************************************************
3 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **************************************************************************/
30 #include "main/glheader.h"
31 #include "main/mtypes.h"
32 #include "main/imports.h"
33 #include "main/macros.h"
34 #include "main/colormac.h"
36 #include "tnl/t_context.h"
37 #include "tnl/t_vertex.h"
39 #include "intel_batchbuffer.h"
40 #include "intel_regions.h"
41 #include "intel_tris.h"
42 #include "intel_fbo.h"
45 #include "i915_context.h"
48 i915_render_prevalidate(struct intel_context *intel)
50 struct i915_context *i915 = i915_context(&intel->ctx);
52 i915ValidateFragmentProgram(i915);
56 i915_render_start(struct intel_context *intel)
62 i915_reduced_primitive_state(struct intel_context *intel, GLenum rprim)
64 struct i915_context *i915 = i915_context(&intel->ctx);
65 GLuint st1 = i915->state.Stipple[I915_STPREG_ST1];
70 case GL_QUADS: /* from RASTERIZE(GL_QUADS) in t_dd_tritemp.h */
72 if (intel->ctx.Polygon.StippleFlag && intel->hw_stipple)
81 i915->intel.reduced_primitive = rprim;
83 if (st1 != i915->state.Stipple[I915_STPREG_ST1]) {
84 INTEL_FIREVERTICES(intel);
86 I915_STATECHANGE(i915, I915_UPLOAD_STIPPLE);
87 i915->state.Stipple[I915_STPREG_ST1] = st1;
92 /* Pull apart the vertex format registers and figure out how large a
93 * vertex is supposed to be.
96 i915_check_vertex_size(struct intel_context *intel, GLuint expected)
98 struct i915_context *i915 = i915_context(&intel->ctx);
99 int lis2 = i915->state.Ctx[I915_CTXREG_LIS2];
100 int lis4 = i915->state.Ctx[I915_CTXREG_LIS4];
103 switch (lis4 & S4_VFMT_XYZW_MASK) {
117 fprintf(stderr, "no xyzw specified\n");
121 if (lis4 & S4_VFMT_SPEC_FOG)
123 if (lis4 & S4_VFMT_COLOR)
125 if (lis4 & S4_VFMT_DEPTH_OFFSET)
127 if (lis4 & S4_VFMT_POINT_WIDTH)
129 if (lis4 & S4_VFMT_FOG_PARAM)
132 for (i = 0; i < 8; i++) {
133 switch (lis2 & S2_TEXCOORD_FMT0_MASK) {
146 case TEXCOORDFMT_2D_16:
149 case TEXCOORDFMT_4D_16:
152 case TEXCOORDFMT_NOT_PRESENT:
155 fprintf(stderr, "bad texcoord fmt %d\n", i);
158 lis2 >>= S2_TEXCOORD_FMT1_SHIFT;
162 fprintf(stderr, "vertex size mismatch %d/%d\n", sz, expected);
164 return sz == expected;
169 i915_emit_invarient_state(struct intel_context *intel)
175 OUT_BATCH(_3DSTATE_AA_CMD |
176 AA_LINE_ECAAR_WIDTH_ENABLE |
177 AA_LINE_ECAAR_WIDTH_1_0 |
178 AA_LINE_REGION_WIDTH_ENABLE | AA_LINE_REGION_WIDTH_1_0);
180 OUT_BATCH(_3DSTATE_DFLT_DIFFUSE_CMD);
183 OUT_BATCH(_3DSTATE_DFLT_SPEC_CMD);
186 OUT_BATCH(_3DSTATE_DFLT_Z_CMD);
189 /* Don't support texture crossbar yet */
190 OUT_BATCH(_3DSTATE_COORD_SET_BINDINGS |
195 CSB_TCB(4, 4) | CSB_TCB(5, 5) | CSB_TCB(6, 6) | CSB_TCB(7, 7));
197 /* Need to initialize this to zero.
199 OUT_BATCH(_3DSTATE_LOAD_STATE_IMMEDIATE_1 | I1_LOAD_S(3) | (0));
203 OUT_BATCH(_3DSTATE_SCISSOR_ENABLE_CMD | DISABLE_SCISSOR_RECT);
205 OUT_BATCH(_3DSTATE_SCISSOR_RECT_0_CMD);
209 OUT_BATCH(_3DSTATE_DEPTH_SUBRECT_DISABLE);
211 OUT_BATCH(_3DSTATE_LOAD_INDIRECT | 0); /* disable indirect state */
218 #define emit(intel, state, size ) \
219 intel_batchbuffer_data(intel->batch, state, size)
222 get_dirty(struct i915_hw_state *state)
226 /* Workaround the multitex hang - if one texture unit state is
227 * modified, emit all texture units.
229 dirty = state->active & ~state->emitted;
230 if (dirty & I915_UPLOAD_TEX_ALL)
231 state->emitted &= ~I915_UPLOAD_TEX_ALL;
232 dirty = state->active & ~state->emitted;
238 get_state_size(struct i915_hw_state *state)
240 GLuint dirty = get_dirty(state);
244 if (dirty & I915_UPLOAD_INVARIENT)
247 if (dirty & I915_UPLOAD_RASTER_RULES)
248 sz += sizeof(state->RasterRules);
250 if (dirty & I915_UPLOAD_CTX)
251 sz += sizeof(state->Ctx);
253 if (dirty & I915_UPLOAD_BUFFERS)
254 sz += sizeof(state->Buffer);
256 if (dirty & I915_UPLOAD_STIPPLE)
257 sz += sizeof(state->Stipple);
259 if (dirty & I915_UPLOAD_FOG)
260 sz += sizeof(state->Fog);
262 if (dirty & I915_UPLOAD_TEX_ALL) {
264 for (i = 0; i < I915_TEX_UNITS; i++)
265 if (dirty & I915_UPLOAD_TEX(i))
268 sz += (2 + nr * 3) * sizeof(GLuint) * 2;
271 if (dirty & I915_UPLOAD_CONSTANTS)
272 sz += state->ConstantSize * sizeof(GLuint);
274 if (dirty & I915_UPLOAD_PROGRAM)
275 sz += state->ProgramSize * sizeof(GLuint);
280 /* Push the state into the sarea and/or texture memory.
283 i915_emit_state(struct intel_context *intel)
285 struct i915_context *i915 = i915_context(&intel->ctx);
286 struct i915_hw_state *state = &i915->state;
287 int i, count, aper_count;
289 dri_bo *aper_array[3 + I915_TEX_UNITS];
290 GET_CURRENT_CONTEXT(ctx);
293 /* We don't hold the lock at this point, so want to make sure that
294 * there won't be a buffer wrap between the state emits and the primitive
297 * It might be better to talk about explicit places where
298 * scheduling is allowed, rather than assume that it is whenever a
299 * batchbuffer fills up.
301 intel_batchbuffer_require_space(intel->batch,
302 get_state_size(state) + INTEL_PRIM_EMIT_SIZE);
306 dirty = get_dirty(state);
308 aper_array[aper_count++] = intel->batch->buf;
309 if (dirty & I915_UPLOAD_BUFFERS) {
310 aper_array[aper_count++] = state->draw_region->buffer;
311 if (state->depth_region)
312 aper_array[aper_count++] = state->depth_region->buffer;
315 if (dirty & I915_UPLOAD_TEX_ALL) {
316 for (i = 0; i < I915_TEX_UNITS; i++) {
317 if (dirty & I915_UPLOAD_TEX(i)) {
318 if (state->tex_buffer[i]) {
319 aper_array[aper_count++] = state->tex_buffer[i];
325 if (dri_bufmgr_check_aperture_space(aper_array, aper_count)) {
328 intel_batchbuffer_flush(intel->batch);
331 _mesa_error(ctx, GL_OUT_OF_MEMORY, "i915 emit state");
336 /* work out list of buffers to emit */
338 /* Do this here as we may have flushed the batchbuffer above,
339 * causing more state to be dirty!
341 dirty = get_dirty(state);
342 state->emitted |= dirty;
343 assert(get_dirty(state) == 0);
345 if (INTEL_DEBUG & DEBUG_STATE)
346 fprintf(stderr, "%s dirty: %x\n", __FUNCTION__, dirty);
348 if (dirty & I915_UPLOAD_INVARIENT) {
349 if (INTEL_DEBUG & DEBUG_STATE)
350 fprintf(stderr, "I915_UPLOAD_INVARIENT:\n");
351 i915_emit_invarient_state(intel);
354 if (dirty & I915_UPLOAD_RASTER_RULES) {
355 if (INTEL_DEBUG & DEBUG_STATE)
356 fprintf(stderr, "I915_UPLOAD_RASTER_RULES:\n");
357 emit(intel, state->RasterRules, sizeof(state->RasterRules));
360 if (dirty & I915_UPLOAD_CTX) {
361 if (INTEL_DEBUG & DEBUG_STATE)
362 fprintf(stderr, "I915_UPLOAD_CTX:\n");
364 emit(intel, state->Ctx, sizeof(state->Ctx));
367 if (dirty & I915_UPLOAD_BUFFERS) {
370 if (INTEL_DEBUG & DEBUG_STATE)
371 fprintf(stderr, "I915_UPLOAD_BUFFERS:\n");
373 if (state->depth_region)
377 OUT_BATCH(state->Buffer[I915_DESTREG_CBUFADDR0]);
378 OUT_BATCH(state->Buffer[I915_DESTREG_CBUFADDR1]);
379 OUT_RELOC(state->draw_region->buffer,
380 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
381 state->draw_region->draw_offset);
383 if (state->depth_region) {
384 OUT_BATCH(state->Buffer[I915_DESTREG_DBUFADDR0]);
385 OUT_BATCH(state->Buffer[I915_DESTREG_DBUFADDR1]);
386 OUT_RELOC(state->depth_region->buffer,
387 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
388 state->depth_region->draw_offset);
391 OUT_BATCH(state->Buffer[I915_DESTREG_DV0]);
392 OUT_BATCH(state->Buffer[I915_DESTREG_DV1]);
393 OUT_BATCH(state->Buffer[I915_DESTREG_SENABLE]);
394 OUT_BATCH(state->Buffer[I915_DESTREG_SR0]);
395 OUT_BATCH(state->Buffer[I915_DESTREG_SR1]);
396 OUT_BATCH(state->Buffer[I915_DESTREG_SR2]);
398 assert(state->Buffer[I915_DESTREG_DRAWRECT0] != MI_NOOP);
399 OUT_BATCH(state->Buffer[I915_DESTREG_DRAWRECT0]);
400 OUT_BATCH(state->Buffer[I915_DESTREG_DRAWRECT1]);
401 OUT_BATCH(state->Buffer[I915_DESTREG_DRAWRECT2]);
402 OUT_BATCH(state->Buffer[I915_DESTREG_DRAWRECT3]);
403 OUT_BATCH(state->Buffer[I915_DESTREG_DRAWRECT4]);
404 OUT_BATCH(state->Buffer[I915_DESTREG_DRAWRECT5]);
409 if (dirty & I915_UPLOAD_STIPPLE) {
410 if (INTEL_DEBUG & DEBUG_STATE)
411 fprintf(stderr, "I915_UPLOAD_STIPPLE:\n");
412 emit(intel, state->Stipple, sizeof(state->Stipple));
415 if (dirty & I915_UPLOAD_FOG) {
416 if (INTEL_DEBUG & DEBUG_STATE)
417 fprintf(stderr, "I915_UPLOAD_FOG:\n");
418 emit(intel, state->Fog, sizeof(state->Fog));
421 /* Combine all the dirty texture state into a single command to
422 * avoid lockups on I915 hardware.
424 if (dirty & I915_UPLOAD_TEX_ALL) {
427 for (i = 0; i < I915_TEX_UNITS; i++)
428 if (dirty & I915_UPLOAD_TEX(i))
431 BEGIN_BATCH(2 + nr * 3);
432 OUT_BATCH(_3DSTATE_MAP_STATE | (3 * nr));
433 OUT_BATCH((dirty & I915_UPLOAD_TEX_ALL) >> I915_UPLOAD_TEX_0_SHIFT);
434 for (i = 0; i < I915_TEX_UNITS; i++)
435 if (dirty & I915_UPLOAD_TEX(i)) {
437 if (state->tex_buffer[i]) {
438 OUT_RELOC(state->tex_buffer[i],
439 I915_GEM_DOMAIN_SAMPLER, 0,
440 state->tex_offset[i]);
443 OUT_BATCH(state->tex_offset[i]);
446 OUT_BATCH(state->Tex[i][I915_TEXREG_MS3]);
447 OUT_BATCH(state->Tex[i][I915_TEXREG_MS4]);
451 BEGIN_BATCH(2 + nr * 3);
452 OUT_BATCH(_3DSTATE_SAMPLER_STATE | (3 * nr));
453 OUT_BATCH((dirty & I915_UPLOAD_TEX_ALL) >> I915_UPLOAD_TEX_0_SHIFT);
454 for (i = 0; i < I915_TEX_UNITS; i++)
455 if (dirty & I915_UPLOAD_TEX(i)) {
456 OUT_BATCH(state->Tex[i][I915_TEXREG_SS2]);
457 OUT_BATCH(state->Tex[i][I915_TEXREG_SS3]);
458 OUT_BATCH(state->Tex[i][I915_TEXREG_SS4]);
463 if (dirty & I915_UPLOAD_CONSTANTS) {
464 if (INTEL_DEBUG & DEBUG_STATE)
465 fprintf(stderr, "I915_UPLOAD_CONSTANTS:\n");
466 emit(intel, state->Constant, state->ConstantSize * sizeof(GLuint));
469 if (dirty & I915_UPLOAD_PROGRAM) {
470 if (state->ProgramSize) {
471 if (INTEL_DEBUG & DEBUG_STATE)
472 fprintf(stderr, "I915_UPLOAD_PROGRAM:\n");
474 assert((state->Program[0] & 0x1ff) + 2 == state->ProgramSize);
476 emit(intel, state->Program, state->ProgramSize * sizeof(GLuint));
477 if (INTEL_DEBUG & DEBUG_STATE)
478 i915_disassemble_program(state->Program, state->ProgramSize);
482 intel->batch->dirty_state &= ~dirty;
483 assert(get_dirty(state) == 0);
484 assert((intel->batch->dirty_state & (1<<1)) == 0);
488 i915_destroy_context(struct intel_context *intel)
491 struct i915_context *i915 = i915_context(&intel->ctx);
493 intel_region_release(&i915->state.draw_region);
494 intel_region_release(&i915->state.depth_region);
496 for (i = 0; i < I915_TEX_UNITS; i++) {
497 if (i915->state.tex_buffer[i] != NULL) {
498 dri_bo_unreference(i915->state.tex_buffer[i]);
499 i915->state.tex_buffer[i] = NULL;
503 _tnl_free_vertices(&intel->ctx);
507 i915_set_buf_info_for_region(uint32_t *state, struct intel_region *region,
510 state[0] = _3DSTATE_BUF_INFO_CMD;
511 state[1] = buffer_id;
513 if (region != NULL) {
514 state[1] |= BUF_3D_PITCH(region->pitch * region->cpp);
516 if (region->tiling != I915_TILING_NONE) {
517 state[1] |= BUF_3D_TILED_SURFACE;
518 if (region->tiling == I915_TILING_Y)
519 state[1] |= BUF_3D_TILE_WALK_Y;
525 i915_set_draw_region(struct intel_context *intel,
526 struct intel_region *color_regions[],
527 struct intel_region *depth_region,
530 struct i915_context *i915 = i915_context(&intel->ctx);
531 GLcontext *ctx = &intel->ctx;
532 struct gl_renderbuffer *rb = ctx->DrawBuffer->_ColorDrawBuffers[0];
533 struct intel_renderbuffer *irb = intel_renderbuffer(rb);
535 struct i915_hw_state *state = &i915->state;
537 if (state->draw_region != color_regions[0]) {
538 intel_region_release(&state->draw_region);
539 intel_region_reference(&state->draw_region, color_regions[0]);
541 if (state->depth_region != depth_region) {
542 intel_region_release(&state->depth_region);
543 intel_region_reference(&state->depth_region, depth_region);
547 * Set stride/cpp values
549 i915_set_buf_info_for_region(&state->Buffer[I915_DESTREG_CBUFADDR0],
550 color_regions[0], BUF_3D_ID_COLOR_BACK);
552 i915_set_buf_info_for_region(&state->Buffer[I915_DESTREG_DBUFADDR0],
553 depth_region, BUF_3D_ID_DEPTH);
556 * Compute/set I915_DESTREG_DV1 value
558 value = (DSTORG_HORT_BIAS(0x8) | /* .5 */
559 DSTORG_VERT_BIAS(0x8) | /* .5 */
560 LOD_PRECLAMP_OGL | TEX_DEFAULT_COLOR_OGL);
562 switch (irb->Base.Format) {
563 case MESA_FORMAT_ARGB8888:
564 case MESA_FORMAT_XRGB8888:
567 case MESA_FORMAT_RGB565:
568 value |= DV_PF_565 | DITHER_FULL_ALWAYS;
570 case MESA_FORMAT_ARGB1555:
571 value |= DV_PF_1555 | DITHER_FULL_ALWAYS;
573 case MESA_FORMAT_ARGB4444:
574 value |= DV_PF_4444 | DITHER_FULL_ALWAYS;
577 _mesa_problem(ctx, "Bad renderbuffer format: %d\n",
582 /* This isn't quite safe, thus being hidden behind an option. When changing
583 * the value of this bit, the pipeline needs to be MI_FLUSHed. And it
584 * can only be set when a depth buffer is already defined.
586 if (intel->is_945 && intel->use_early_z &&
587 depth_region->tiling != I915_TILING_NONE)
588 value |= CLASSIC_EARLY_DEPTH;
590 if (depth_region && depth_region->cpp == 4) {
591 value |= DEPTH_FRMT_24_FIXED_8_OTHER;
594 value |= DEPTH_FRMT_16_FIXED;
596 state->Buffer[I915_DESTREG_DV1] = value;
598 state->Buffer[I915_DESTREG_DRAWRECT0] = _3DSTATE_DRAWRECT_INFO;
599 state->Buffer[I915_DESTREG_DRAWRECT1] = 0;
600 state->Buffer[I915_DESTREG_DRAWRECT2] = 0; /* xmin, ymin */
601 state->Buffer[I915_DESTREG_DRAWRECT3] =
602 (ctx->DrawBuffer->Width & 0xffff) |
603 (ctx->DrawBuffer->Height << 16);
604 state->Buffer[I915_DESTREG_DRAWRECT4] = 0; /* xoff, yoff */
605 state->Buffer[I915_DESTREG_DRAWRECT5] = 0;
607 I915_STATECHANGE(i915, I915_UPLOAD_BUFFERS);
613 i915_new_batch(struct intel_context *intel)
615 struct i915_context *i915 = i915_context(&intel->ctx);
617 /* Mark all state as needing to be emitted when starting a new batchbuffer.
618 * Using hardware contexts would be an alternative, but they have some
619 * difficulties associated with them (physical address requirements).
621 i915->state.emitted = 0;
625 i915_assert_not_dirty( struct intel_context *intel )
627 struct i915_context *i915 = i915_context(&intel->ctx);
628 GLuint dirty = get_dirty(&i915->state);
633 i915InitVtbl(struct i915_context *i915)
635 i915->intel.vtbl.check_vertex_size = i915_check_vertex_size;
636 i915->intel.vtbl.destroy = i915_destroy_context;
637 i915->intel.vtbl.emit_state = i915_emit_state;
638 i915->intel.vtbl.new_batch = i915_new_batch;
639 i915->intel.vtbl.reduced_primitive_state = i915_reduced_primitive_state;
640 i915->intel.vtbl.render_start = i915_render_start;
641 i915->intel.vtbl.render_prevalidate = i915_render_prevalidate;
642 i915->intel.vtbl.set_draw_region = i915_set_draw_region;
643 i915->intel.vtbl.update_texture_state = i915UpdateTextureState;
644 i915->intel.vtbl.assert_not_dirty = i915_assert_not_dirty;
645 i915->intel.vtbl.finish_batch = intel_finish_vb;