2 * Copyright © 2012 Intel Corporation
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5 * copy of this software and associated documentation files (the "Software"),
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9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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25 #include "intel_batchbuffer.h"
26 #include "intel_fbo.h"
28 #include "brw_blorp.h"
29 #include "brw_compiler.h"
31 #include "brw_state.h"
33 #define FILE_DEBUG_FLAG DEBUG_BLORP
36 brw_blorp_surface_info_init(struct brw_context *brw,
37 struct brw_blorp_surface_info *info,
38 struct intel_mipmap_tree *mt,
39 unsigned int level, unsigned int layer,
40 mesa_format format, bool is_render_target)
42 /* Layer is a physical layer, so if this is a 2D multisample array texture
43 * using INTEL_MSAA_LAYOUT_UMS or INTEL_MSAA_LAYOUT_CMS, then it had better
44 * be a multiple of num_samples.
46 if (mt->msaa_layout == INTEL_MSAA_LAYOUT_UMS ||
47 mt->msaa_layout == INTEL_MSAA_LAYOUT_CMS) {
48 assert(mt->num_samples <= 1 || layer % mt->num_samples == 0);
51 intel_miptree_check_level_layer(mt, level, layer);
56 info->width = minify(mt->physical_width0, level - mt->first_level);
57 info->height = minify(mt->physical_height0, level - mt->first_level);
59 intel_miptree_get_image_offset(mt, level, layer,
60 &info->x_offset, &info->y_offset);
62 info->num_samples = mt->num_samples;
63 info->array_layout = mt->array_layout;
64 info->map_stencil_as_y_tiled = false;
65 info->msaa_layout = mt->msaa_layout;
66 info->swizzle = SWIZZLE_XYZW;
68 if (format == MESA_FORMAT_NONE)
72 case MESA_FORMAT_S_UINT8:
73 /* The miptree is a W-tiled stencil buffer. Surface states can't be set
74 * up for W tiling, so we'll need to use Y tiling and have the WM
75 * program swizzle the coordinates.
77 info->map_stencil_as_y_tiled = true;
78 info->brw_surfaceformat = brw->gen >= 8 ? BRW_SURFACEFORMAT_R8_UINT :
79 BRW_SURFACEFORMAT_R8_UNORM;
81 case MESA_FORMAT_Z24_UNORM_X8_UINT:
82 /* It would make sense to use BRW_SURFACEFORMAT_R24_UNORM_X8_TYPELESS
83 * here, but unfortunately it isn't supported as a render target, which
84 * would prevent us from blitting to 24-bit depth.
86 * The miptree consists of 32 bits per pixel, arranged as 24-bit depth
87 * values interleaved with 8 "don't care" bits. Since depth values don't
88 * require any blending, it doesn't matter how we interpret the bit
89 * pattern as long as we copy the right amount of data, so just map it
92 info->brw_surfaceformat = BRW_SURFACEFORMAT_B8G8R8A8_UNORM;
94 case MESA_FORMAT_Z_FLOAT32:
95 info->brw_surfaceformat = BRW_SURFACEFORMAT_R32_FLOAT;
97 case MESA_FORMAT_Z_UNORM16:
98 info->brw_surfaceformat = BRW_SURFACEFORMAT_R16_UNORM;
101 if (is_render_target) {
102 assert(brw->format_supported_as_render_target[format]);
103 info->brw_surfaceformat = brw->render_target_format[format];
105 info->brw_surfaceformat = brw_format_for_mesa_format(format);
114 * Split x_offset and y_offset into a base offset (in bytes) and a remaining
115 * x/y offset (in pixels). Note: we can't do this by calling
116 * intel_renderbuffer_tile_offsets(), because the offsets may have been
117 * adjusted to account for Y vs. W tiling differences. So we compute it
118 * directly from the adjusted offsets.
121 brw_blorp_compute_tile_offsets(const struct brw_blorp_surface_info *info,
122 uint32_t *tile_x, uint32_t *tile_y)
124 uint32_t mask_x, mask_y;
126 intel_get_tile_masks(info->mt->tiling, info->mt->tr_mode, info->mt->cpp,
127 info->map_stencil_as_y_tiled,
130 *tile_x = info->x_offset & mask_x;
131 *tile_y = info->y_offset & mask_y;
133 return intel_miptree_get_aligned_offset(info->mt, info->x_offset & ~mask_x,
134 info->y_offset & ~mask_y,
135 info->map_stencil_as_y_tiled);
140 brw_blorp_params_init(struct brw_blorp_params *params)
142 memset(params, 0, sizeof(*params));
143 params->hiz_op = GEN6_HIZ_OP_NONE;
144 params->fast_clear_op = 0;
145 params->num_draw_buffers = 1;
146 params->num_layers = 1;
150 brw_blorp_init_wm_prog_key(struct brw_wm_prog_key *wm_key)
152 memset(wm_key, 0, sizeof(*wm_key));
153 wm_key->nr_color_regions = 1;
154 for (int i = 0; i < MAX_SAMPLERS; i++)
155 wm_key->tex.swizzles[i] = SWIZZLE_XYZW;
159 nir_uniform_type_size(const struct glsl_type *type)
161 /* Only very basic types are allowed */
162 assert(glsl_type_is_vector_or_scalar(type));
163 assert(glsl_get_bit_size(type) == 32);
165 return glsl_get_vector_elements(type) * 4;
169 brw_blorp_compile_nir_shader(struct brw_context *brw, struct nir_shader *nir,
170 const struct brw_wm_prog_key *wm_key,
172 struct brw_blorp_prog_data *prog_data,
173 unsigned *program_size)
175 const struct brw_compiler *compiler = brw->intelScreen->compiler;
177 void *mem_ctx = ralloc_context(NULL);
179 /* Calling brw_preprocess_nir and friends is destructive and, if cloning is
180 * enabled, may end up completely replacing the nir_shader. Therefore, we
181 * own it and might as well put it in our context for easy cleanup.
183 ralloc_steal(mem_ctx, nir);
185 compiler->glsl_compiler_options[MESA_SHADER_FRAGMENT].NirOptions;
187 struct brw_wm_prog_data wm_prog_data;
188 memset(&wm_prog_data, 0, sizeof(wm_prog_data));
190 wm_prog_data.base.nr_params = 0;
191 wm_prog_data.base.param = NULL;
193 /* BLORP always just uses the first two binding table entries */
194 wm_prog_data.binding_table.render_target_start = 0;
195 wm_prog_data.base.binding_table.texture_start = 1;
197 nir = brw_preprocess_nir(compiler, nir);
198 nir_remove_dead_variables(nir, nir_var_shader_in);
199 nir_shader_gather_info(nir, nir_shader_get_entrypoint(nir)->impl);
201 /* Uniforms are required to be lowered before going into compile_fs. For
202 * BLORP, we'll assume that whoever builds the shader sets the location
203 * they want so we just need to lower them and figure out how many we have
206 nir->num_uniforms = 0;
207 nir_foreach_variable(var, &nir->uniforms) {
208 var->data.driver_location = var->data.location;
209 unsigned end = var->data.location + nir_uniform_type_size(var->type);
210 nir->num_uniforms = MAX2(nir->num_uniforms, end);
212 nir_lower_io(nir, nir_var_uniform, nir_uniform_type_size);
214 const unsigned *program =
215 brw_compile_fs(compiler, brw, mem_ctx, wm_key, &wm_prog_data, nir,
216 NULL, -1, -1, false, use_repclear, program_size, NULL);
218 /* Copy the relavent bits of wm_prog_data over into the blorp prog data */
219 prog_data->dispatch_8 = wm_prog_data.dispatch_8;
220 prog_data->dispatch_16 = wm_prog_data.dispatch_16;
221 prog_data->first_curbe_grf_0 = wm_prog_data.base.dispatch_grf_start_reg;
222 prog_data->first_curbe_grf_2 = wm_prog_data.dispatch_grf_start_reg_2;
223 prog_data->ksp_offset_2 = wm_prog_data.prog_offset_2;
224 prog_data->persample_msaa_dispatch = wm_prog_data.persample_dispatch;
225 prog_data->flat_inputs = wm_prog_data.flat_inputs;
226 prog_data->num_varying_inputs = wm_prog_data.num_varying_inputs;
227 prog_data->inputs_read = nir->info.inputs_read;
229 assert(wm_prog_data.base.nr_params == 0);
235 * Perform a HiZ or depth resolve operation.
237 * For an overview of HiZ ops, see the following sections of the Sandy Bridge
238 * PRM, Volume 1, Part 2:
239 * - 7.5.3.1 Depth Buffer Clear
240 * - 7.5.3.2 Depth Buffer Resolve
241 * - 7.5.3.3 Hierarchical Depth Buffer Resolve
244 intel_hiz_exec(struct brw_context *brw, struct intel_mipmap_tree *mt,
245 unsigned int level, unsigned int layer, enum gen6_hiz_op op)
247 const char *opname = NULL;
250 case GEN6_HIZ_OP_DEPTH_RESOLVE:
251 opname = "depth resolve";
253 case GEN6_HIZ_OP_HIZ_RESOLVE:
254 opname = "hiz ambiguate";
256 case GEN6_HIZ_OP_DEPTH_CLEAR:
257 opname = "depth clear";
259 case GEN6_HIZ_OP_NONE:
264 DBG("%s %s to mt %p level %d layer %d\n",
265 __func__, opname, mt, level, layer);
268 gen8_hiz_exec(brw, mt, level, layer, op);
270 gen6_blorp_hiz_exec(brw, mt, level, layer, op);
275 brw_blorp_exec(struct brw_context *brw, const struct brw_blorp_params *params)
277 struct gl_context *ctx = &brw->ctx;
278 const uint32_t estimated_max_batch_usage = brw->gen >= 8 ? 1800 : 1500;
279 bool check_aperture_failed_once = false;
281 /* Flush the sampler and render caches. We definitely need to flush the
282 * sampler cache so that we get updated contents from the render cache for
283 * the glBlitFramebuffer() source. Also, we are sometimes warned in the
284 * docs to flush the cache between reinterpretations of the same surface
285 * data with different formats, which blorp does for stencil and depth
288 brw_emit_mi_flush(brw);
290 brw_select_pipeline(brw, BRW_RENDER_PIPELINE);
293 intel_batchbuffer_require_space(brw, estimated_max_batch_usage, RENDER_RING);
294 intel_batchbuffer_save_state(brw);
295 drm_intel_bo *saved_bo = brw->batch.bo;
296 uint32_t saved_used = USED_BATCH(brw->batch);
297 uint32_t saved_state_batch_offset = brw->batch.state_batch_offset;
301 gen6_blorp_exec(brw, params);
304 gen7_blorp_exec(brw, params);
308 gen8_blorp_exec(brw, params);
311 /* BLORP is not supported before Gen6. */
312 unreachable("not reached");
315 /* Make sure we didn't wrap the batch unintentionally, and make sure we
316 * reserved enough space that a wrap will never happen.
318 assert(brw->batch.bo == saved_bo);
319 assert((USED_BATCH(brw->batch) - saved_used) * 4 +
320 (saved_state_batch_offset - brw->batch.state_batch_offset) <
321 estimated_max_batch_usage);
322 /* Shut up compiler warnings on release build */
325 (void)saved_state_batch_offset;
327 /* Check if the blorp op we just did would make our batch likely to fail to
328 * map all the BOs into the GPU at batch exec time later. If so, flush the
329 * batch and try again with nothing else in the batch.
331 if (dri_bufmgr_check_aperture_space(&brw->batch.bo, 1)) {
332 if (!check_aperture_failed_once) {
333 check_aperture_failed_once = true;
334 intel_batchbuffer_reset_to_saved(brw);
335 intel_batchbuffer_flush(brw);
338 int ret = intel_batchbuffer_flush(brw);
339 WARN_ONCE(ret == -ENOSPC,
340 "i965: blorp emit exceeded available aperture space\n");
344 if (unlikely(brw->always_flush_batch))
345 intel_batchbuffer_flush(brw);
347 /* We've smashed all state compared to what the normal 3D pipeline
348 * rendering tracks for GL.
350 brw->ctx.NewDriverState |= BRW_NEW_BLORP;
351 brw->no_depth_or_stencil = false;
354 /* Flush the sampler cache so any texturing from the destination is
357 brw_emit_mi_flush(brw);
361 gen6_blorp_hiz_exec(struct brw_context *brw, struct intel_mipmap_tree *mt,
362 unsigned int level, unsigned int layer, enum gen6_hiz_op op)
364 struct brw_blorp_params params;
365 brw_blorp_params_init(¶ms);
369 brw_blorp_surface_info_init(brw, ¶ms.depth, mt, level, layer,
372 /* Align the rectangle primitive to 8x4 pixels.
374 * During fast depth clears, the emitted rectangle primitive must be
375 * aligned to 8x4 pixels. From the Ivybridge PRM, Vol 2 Part 1 Section
376 * 11.5.3.1 Depth Buffer Clear (and the matching section in the Sandybridge
378 * If Number of Multisamples is NUMSAMPLES_1, the rectangle must be
379 * aligned to an 8x4 pixel block relative to the upper left corner
380 * of the depth buffer [...]
382 * For hiz resolves, the rectangle must also be 8x4 aligned. Item
383 * WaHizAmbiguate8x4Aligned from the Haswell workarounds page and the
384 * Ivybridge simulator require the alignment.
386 * To be safe, let's just align the rect for all hiz operations and all
387 * hardware generations.
389 * However, for some miptree slices of a Z24 texture, emitting an 8x4
390 * aligned rectangle that covers the slice may clobber adjacent slices if
391 * we strictly adhered to the texture alignments specified in the PRM. The
392 * Ivybridge PRM, Section "Alignment Unit Size", states that
393 * SURFACE_STATE.Surface_Horizontal_Alignment should be 4 for Z24 surfaces,
394 * not 8. But commit 1f112cc increased the alignment from 4 to 8, which
395 * prevents the clobbering.
397 params.dst.num_samples = mt->num_samples;
398 if (params.dst.num_samples > 1) {
399 params.depth.width = ALIGN(mt->logical_width0, 8);
400 params.depth.height = ALIGN(mt->logical_height0, 4);
402 params.depth.width = ALIGN(params.depth.width, 8);
403 params.depth.height = ALIGN(params.depth.height, 4);
406 params.x1 = params.depth.width;
407 params.y1 = params.depth.height;
409 assert(intel_miptree_level_has_hiz(mt, level));
411 switch (mt->format) {
412 case MESA_FORMAT_Z_UNORM16:
413 params.depth_format = BRW_DEPTHFORMAT_D16_UNORM;
415 case MESA_FORMAT_Z_FLOAT32:
416 params.depth_format = BRW_DEPTHFORMAT_D32_FLOAT;
418 case MESA_FORMAT_Z24_UNORM_X8_UINT:
419 params.depth_format = BRW_DEPTHFORMAT_D24_UNORM_X8_UINT;
422 unreachable("not reached");
425 brw_blorp_exec(brw, ¶ms);