2 * Copyright © 2012 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include "main/context.h"
25 #include "main/teximage.h"
26 #include "main/blend.h"
27 #include "main/fbobject.h"
28 #include "main/renderbuffer.h"
29 #include "main/glformats.h"
31 #include "brw_blorp.h"
32 #include "brw_context.h"
33 #include "brw_defines.h"
34 #include "brw_meta_util.h"
35 #include "brw_state.h"
36 #include "intel_fbo.h"
37 #include "intel_debug.h"
39 #define FILE_DEBUG_FLAG DEBUG_BLORP
42 brw_blorp_lookup_shader(struct blorp_context *blorp,
43 const void *key, uint32_t key_size,
44 uint32_t *kernel_out, void *prog_data_out)
46 struct brw_context *brw = blorp->driver_ctx;
47 return brw_search_cache(&brw->cache, BRW_CACHE_BLORP_PROG,
48 key, key_size, kernel_out, prog_data_out);
52 brw_blorp_upload_shader(struct blorp_context *blorp,
53 const void *key, uint32_t key_size,
54 const void *kernel, uint32_t kernel_size,
55 const void *prog_data, uint32_t prog_data_size,
56 uint32_t *kernel_out, void *prog_data_out)
58 struct brw_context *brw = blorp->driver_ctx;
59 brw_upload_cache(&brw->cache, BRW_CACHE_BLORP_PROG, key, key_size,
60 kernel, kernel_size, prog_data, prog_data_size,
61 kernel_out, prog_data_out);
65 brw_blorp_init(struct brw_context *brw)
67 blorp_init(&brw->blorp, brw, &brw->isl_dev);
69 brw->blorp.compiler = brw->intelScreen->compiler;
73 brw->blorp.mocs.tex = 0;
74 brw->blorp.mocs.rb = 0;
75 brw->blorp.mocs.vb = 0;
76 brw->blorp.exec = gen6_blorp_exec;
79 brw->blorp.mocs.tex = GEN7_MOCS_L3;
80 brw->blorp.mocs.rb = GEN7_MOCS_L3;
81 brw->blorp.mocs.vb = GEN7_MOCS_L3;
82 if (brw->is_haswell) {
83 brw->blorp.exec = gen75_blorp_exec;
85 brw->blorp.exec = gen7_blorp_exec;
89 brw->blorp.mocs.tex = BDW_MOCS_WB;
90 brw->blorp.mocs.rb = BDW_MOCS_PTE;
91 brw->blorp.mocs.vb = BDW_MOCS_WB;
92 brw->blorp.exec = gen8_blorp_exec;
95 brw->blorp.mocs.tex = SKL_MOCS_WB;
96 brw->blorp.mocs.rb = SKL_MOCS_PTE;
97 brw->blorp.mocs.vb = SKL_MOCS_WB;
98 brw->blorp.exec = gen9_blorp_exec;
101 unreachable("Invalid gen");
104 brw->blorp.lookup_shader = brw_blorp_lookup_shader;
105 brw->blorp.upload_shader = brw_blorp_upload_shader;
109 apply_gen6_stencil_hiz_offset(struct isl_surf *surf,
110 struct intel_mipmap_tree *mt,
114 assert(mt->array_layout == ALL_SLICES_AT_EACH_LOD);
116 if (mt->format == MESA_FORMAT_S_UINT8) {
117 /* Note: we can't compute the stencil offset using
118 * intel_miptree_get_aligned_offset(), because the miptree
119 * claims that the region is untiled even though it's W tiled.
121 *offset = mt->level[lod].level_y * mt->pitch +
122 mt->level[lod].level_x * 64;
124 *offset = intel_miptree_get_aligned_offset(mt,
125 mt->level[lod].level_x,
126 mt->level[lod].level_y,
130 surf->logical_level0_px.width = minify(surf->logical_level0_px.width, lod);
131 surf->logical_level0_px.height = minify(surf->logical_level0_px.height, lod);
132 surf->phys_level0_sa.width = minify(surf->phys_level0_sa.width, lod);
133 surf->phys_level0_sa.height = minify(surf->phys_level0_sa.height, lod);
135 surf->array_pitch_el_rows =
136 ALIGN(surf->phys_level0_sa.height, surf->image_alignment_el.height);
140 blorp_surf_for_miptree(struct brw_context *brw,
141 struct blorp_surf *surf,
142 struct intel_mipmap_tree *mt,
143 bool is_render_target,
145 struct isl_surf tmp_surfs[2])
147 intel_miptree_get_isl_surf(brw, mt, &tmp_surfs[0]);
148 surf->surf = &tmp_surfs[0];
149 surf->addr = (struct blorp_address) {
151 .offset = mt->offset,
152 .read_domains = is_render_target ? I915_GEM_DOMAIN_RENDER :
153 I915_GEM_DOMAIN_SAMPLER,
154 .write_domain = is_render_target ? I915_GEM_DOMAIN_RENDER : 0,
157 if (brw->gen == 6 && mt->format == MESA_FORMAT_S_UINT8 &&
158 mt->array_layout == ALL_SLICES_AT_EACH_LOD) {
159 /* Sandy bridge stencil and HiZ use this ALL_SLICES_AT_EACH_LOD hack in
160 * order to allow for layered rendering. The hack makes each LOD of the
161 * stencil or HiZ buffer a single tightly packed array surface at some
162 * offset into the surface. Since ISL doesn't know how to deal with the
163 * crazy ALL_SLICES_AT_EACH_LOD layout and since we have to do a manual
164 * offset of it anyway, we might as well do the offset here and keep the
165 * hacks inside the i965 driver.
167 * See also gen6_depth_stencil_state.c
170 apply_gen6_stencil_hiz_offset(&tmp_surfs[0], mt, *level, &offset);
171 surf->addr.offset += offset;
175 struct isl_surf *aux_surf = &tmp_surfs[1];
176 intel_miptree_get_aux_isl_surf(brw, mt, aux_surf, &surf->aux_usage);
178 /* For textures that are in the RESOLVED state, we ignore the MCS */
179 if (mt->mcs_mt && !is_render_target &&
180 mt->fast_clear_state == INTEL_FAST_CLEAR_STATE_RESOLVED)
181 surf->aux_usage = ISL_AUX_USAGE_NONE;
183 if (surf->aux_usage != ISL_AUX_USAGE_NONE) {
184 /* We only really need a clear color if we also have an auxiliary
185 * surface. Without one, it does nothing.
187 surf->clear_color = intel_miptree_get_isl_clear_color(brw, mt);
189 surf->aux_surf = aux_surf;
190 surf->aux_addr = (struct blorp_address) {
191 .read_domains = is_render_target ? I915_GEM_DOMAIN_RENDER :
192 I915_GEM_DOMAIN_SAMPLER,
193 .write_domain = is_render_target ? I915_GEM_DOMAIN_RENDER : 0,
197 surf->aux_addr.buffer = mt->mcs_mt->bo;
198 surf->aux_addr.offset = mt->mcs_mt->offset;
200 assert(surf->aux_usage == ISL_AUX_USAGE_HIZ);
201 struct intel_mipmap_tree *hiz_mt = mt->hiz_buf->mt;
203 surf->aux_addr.buffer = hiz_mt->bo;
205 hiz_mt->array_layout == ALL_SLICES_AT_EACH_LOD) {
206 /* gen6 requires the HiZ buffer to be manually offset to the
207 * right location. We could fixup the surf but it doesn't
208 * matter since most of those fields don't matter.
210 apply_gen6_stencil_hiz_offset(aux_surf, hiz_mt, *level,
211 &surf->aux_addr.offset);
213 surf->aux_addr.offset = 0;
215 assert(hiz_mt->pitch == aux_surf->row_pitch);
217 surf->aux_addr.buffer = mt->hiz_buf->bo;
218 surf->aux_addr.offset = 0;
222 surf->aux_addr = (struct blorp_address) {
225 memset(&surf->clear_color, 0, sizeof(surf->clear_color));
227 assert((surf->aux_usage == ISL_AUX_USAGE_NONE) ==
228 (surf->aux_addr.buffer == NULL));
231 static enum isl_format
232 brw_blorp_to_isl_format(struct brw_context *brw, mesa_format format,
233 bool is_render_target)
236 case MESA_FORMAT_NONE:
237 return ISL_FORMAT_UNSUPPORTED;
238 case MESA_FORMAT_S_UINT8:
239 return ISL_FORMAT_R8_UINT;
240 case MESA_FORMAT_Z24_UNORM_X8_UINT:
241 return ISL_FORMAT_R24_UNORM_X8_TYPELESS;
242 case MESA_FORMAT_Z_FLOAT32:
243 return ISL_FORMAT_R32_FLOAT;
244 case MESA_FORMAT_Z_UNORM16:
245 return ISL_FORMAT_R16_UNORM;
247 if (is_render_target) {
248 assert(brw->format_supported_as_render_target[format]);
249 return brw->render_target_format[format];
251 return brw_format_for_mesa_format(format);
259 * Convert an swizzle enumeration (i.e. SWIZZLE_X) to one of the Gen7.5+
260 * "Shader Channel Select" enumerations (i.e. HSW_SCS_RED). The mappings are
262 * SWIZZLE_X, SWIZZLE_Y, SWIZZLE_Z, SWIZZLE_W, SWIZZLE_ZERO, SWIZZLE_ONE
265 * SCS_RED, SCS_GREEN, SCS_BLUE, SCS_ALPHA, SCS_ZERO, SCS_ONE
267 * which is simply adding 4 then modding by 8 (or anding with 7).
269 * We then may need to apply workarounds for textureGather hardware bugs.
271 static enum isl_channel_select
272 swizzle_to_scs(GLenum swizzle)
274 return (enum isl_channel_select)((swizzle + 4) & 7);
278 * Note: if the src (or dst) is a 2D multisample array texture on Gen7+ using
279 * INTEL_MSAA_LAYOUT_UMS or INTEL_MSAA_LAYOUT_CMS, src_layer (dst_layer) is
280 * the physical layer holding sample 0. So, for example, if
281 * src_mt->num_samples == 4, then logical layer n corresponds to src_layer ==
285 brw_blorp_blit_miptrees(struct brw_context *brw,
286 struct intel_mipmap_tree *src_mt,
287 unsigned src_level, unsigned src_layer,
288 mesa_format src_format, int src_swizzle,
289 struct intel_mipmap_tree *dst_mt,
290 unsigned dst_level, unsigned dst_layer,
291 mesa_format dst_format,
292 float src_x0, float src_y0,
293 float src_x1, float src_y1,
294 float dst_x0, float dst_y0,
295 float dst_x1, float dst_y1,
296 GLenum filter, bool mirror_x, bool mirror_y,
297 bool decode_srgb, bool encode_srgb)
299 /* Get ready to blit. This includes depth resolving the src and dst
300 * buffers if necessary. Note: it's not necessary to do a color resolve on
301 * the destination buffer because we use the standard render path to render
302 * to destination color buffers, and the standard render path is
305 intel_miptree_resolve_color(brw, src_mt, INTEL_MIPTREE_IGNORE_CCS_E);
306 intel_miptree_slice_resolve_depth(brw, src_mt, src_level, src_layer);
307 intel_miptree_slice_resolve_depth(brw, dst_mt, dst_level, dst_layer);
309 DBG("%s from %dx %s mt %p %d %d (%f,%f) (%f,%f)"
310 "to %dx %s mt %p %d %d (%f,%f) (%f,%f) (flip %d,%d)\n",
312 src_mt->num_samples, _mesa_get_format_name(src_mt->format), src_mt,
313 src_level, src_layer, src_x0, src_y0, src_x1, src_y1,
314 dst_mt->num_samples, _mesa_get_format_name(dst_mt->format), dst_mt,
315 dst_level, dst_layer, dst_x0, dst_y0, dst_x1, dst_y1,
318 if (!decode_srgb && _mesa_get_format_color_encoding(src_format) == GL_SRGB)
319 src_format = _mesa_get_srgb_format_linear(src_format);
321 if (!encode_srgb && _mesa_get_format_color_encoding(dst_format) == GL_SRGB)
322 dst_format = _mesa_get_srgb_format_linear(dst_format);
324 /* When doing a multisample resolve of a GL_LUMINANCE32F or GL_INTENSITY32F
325 * texture, the above code configures the source format for L32_FLOAT or
326 * I32_FLOAT, and the destination format for R32_FLOAT. On Sandy Bridge,
327 * the SAMPLE message appears to handle multisampled L32_FLOAT and
328 * I32_FLOAT textures incorrectly, resulting in blocky artifacts. So work
329 * around the problem by using a source format of R32_FLOAT. This
330 * shouldn't affect rendering correctness, since the destination format is
331 * R32_FLOAT, so only the contents of the red channel matters.
334 src_mt->num_samples > 1 && dst_mt->num_samples <= 1 &&
335 src_mt->format == dst_mt->format &&
336 (dst_format == MESA_FORMAT_L_FLOAT32 ||
337 dst_format == MESA_FORMAT_I_FLOAT32)) {
338 src_format = dst_format = MESA_FORMAT_R_FLOAT32;
341 intel_miptree_check_level_layer(src_mt, src_level, src_layer);
342 intel_miptree_check_level_layer(dst_mt, dst_level, dst_layer);
343 intel_miptree_used_for_rendering(dst_mt);
345 struct isl_surf tmp_surfs[4];
346 struct blorp_surf src_surf, dst_surf;
347 blorp_surf_for_miptree(brw, &src_surf, src_mt, false,
348 &src_level, &tmp_surfs[0]);
349 blorp_surf_for_miptree(brw, &dst_surf, dst_mt, true,
350 &dst_level, &tmp_surfs[2]);
352 struct isl_swizzle src_isl_swizzle = {
353 .r = swizzle_to_scs(GET_SWZ(src_swizzle, 0)),
354 .g = swizzle_to_scs(GET_SWZ(src_swizzle, 1)),
355 .b = swizzle_to_scs(GET_SWZ(src_swizzle, 2)),
356 .a = swizzle_to_scs(GET_SWZ(src_swizzle, 3)),
359 struct blorp_batch batch;
360 blorp_batch_init(&brw->blorp, &batch, brw);
361 blorp_blit(&batch, &src_surf, src_level, src_layer,
362 brw_blorp_to_isl_format(brw, src_format, false), src_isl_swizzle,
363 &dst_surf, dst_level, dst_layer,
364 brw_blorp_to_isl_format(brw, dst_format, true),
365 src_x0, src_y0, src_x1, src_y1,
366 dst_x0, dst_y0, dst_x1, dst_y1,
367 filter, mirror_x, mirror_y);
368 blorp_batch_finish(&batch);
370 intel_miptree_slice_set_needs_hiz_resolve(dst_mt, dst_level, dst_layer);
372 if (intel_miptree_is_lossless_compressed(brw, dst_mt))
373 dst_mt->fast_clear_state = INTEL_FAST_CLEAR_STATE_UNRESOLVED;
376 static struct intel_mipmap_tree *
377 find_miptree(GLbitfield buffer_bit, struct intel_renderbuffer *irb)
379 struct intel_mipmap_tree *mt = irb->mt;
380 if (buffer_bit == GL_STENCIL_BUFFER_BIT && mt->stencil_mt)
386 blorp_get_texture_swizzle(const struct intel_renderbuffer *irb)
388 return irb->Base.Base._BaseFormat == GL_RGB ?
389 MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y, SWIZZLE_Z, SWIZZLE_ONE) :
394 do_blorp_blit(struct brw_context *brw, GLbitfield buffer_bit,
395 struct intel_renderbuffer *src_irb, mesa_format src_format,
396 struct intel_renderbuffer *dst_irb, mesa_format dst_format,
397 GLfloat srcX0, GLfloat srcY0, GLfloat srcX1, GLfloat srcY1,
398 GLfloat dstX0, GLfloat dstY0, GLfloat dstX1, GLfloat dstY1,
399 GLenum filter, bool mirror_x, bool mirror_y)
401 const struct gl_context *ctx = &brw->ctx;
403 /* Find source/dst miptrees */
404 struct intel_mipmap_tree *src_mt = find_miptree(buffer_bit, src_irb);
405 struct intel_mipmap_tree *dst_mt = find_miptree(buffer_bit, dst_irb);
407 const bool do_srgb = ctx->Color.sRGBEnabled;
410 brw_blorp_blit_miptrees(brw,
411 src_mt, src_irb->mt_level, src_irb->mt_layer,
412 src_format, blorp_get_texture_swizzle(src_irb),
413 dst_mt, dst_irb->mt_level, dst_irb->mt_layer,
415 srcX0, srcY0, srcX1, srcY1,
416 dstX0, dstY0, dstX1, dstY1,
417 filter, mirror_x, mirror_y,
420 dst_irb->need_downsample = true;
424 try_blorp_blit(struct brw_context *brw,
425 const struct gl_framebuffer *read_fb,
426 const struct gl_framebuffer *draw_fb,
427 GLfloat srcX0, GLfloat srcY0, GLfloat srcX1, GLfloat srcY1,
428 GLfloat dstX0, GLfloat dstY0, GLfloat dstX1, GLfloat dstY1,
429 GLenum filter, GLbitfield buffer_bit)
431 struct gl_context *ctx = &brw->ctx;
433 /* Sync up the state of window system buffers. We need to do this before
434 * we go looking for the buffers.
436 intel_prepare_render(brw);
438 bool mirror_x, mirror_y;
439 if (brw_meta_mirror_clip_and_scissor(ctx, read_fb, draw_fb,
440 &srcX0, &srcY0, &srcX1, &srcY1,
441 &dstX0, &dstY0, &dstX1, &dstY1,
442 &mirror_x, &mirror_y))
446 struct intel_renderbuffer *src_irb;
447 struct intel_renderbuffer *dst_irb;
448 struct intel_mipmap_tree *src_mt;
449 struct intel_mipmap_tree *dst_mt;
450 switch (buffer_bit) {
451 case GL_COLOR_BUFFER_BIT:
452 src_irb = intel_renderbuffer(read_fb->_ColorReadBuffer);
453 for (unsigned i = 0; i < draw_fb->_NumColorDrawBuffers; ++i) {
454 dst_irb = intel_renderbuffer(draw_fb->_ColorDrawBuffers[i]);
456 do_blorp_blit(brw, buffer_bit,
457 src_irb, src_irb->Base.Base.Format,
458 dst_irb, dst_irb->Base.Base.Format,
459 srcX0, srcY0, srcX1, srcY1,
460 dstX0, dstY0, dstX1, dstY1,
461 filter, mirror_x, mirror_y);
464 case GL_DEPTH_BUFFER_BIT:
466 intel_renderbuffer(read_fb->Attachment[BUFFER_DEPTH].Renderbuffer);
468 intel_renderbuffer(draw_fb->Attachment[BUFFER_DEPTH].Renderbuffer);
469 src_mt = find_miptree(buffer_bit, src_irb);
470 dst_mt = find_miptree(buffer_bit, dst_irb);
472 /* We can't handle format conversions between Z24 and other formats
473 * since we have to lie about the surface format. See the comments in
474 * brw_blorp_surface_info::set().
476 if ((src_mt->format == MESA_FORMAT_Z24_UNORM_X8_UINT) !=
477 (dst_mt->format == MESA_FORMAT_Z24_UNORM_X8_UINT))
480 do_blorp_blit(brw, buffer_bit, src_irb, MESA_FORMAT_NONE,
481 dst_irb, MESA_FORMAT_NONE, srcX0, srcY0,
482 srcX1, srcY1, dstX0, dstY0, dstX1, dstY1,
483 filter, mirror_x, mirror_y);
485 case GL_STENCIL_BUFFER_BIT:
487 intel_renderbuffer(read_fb->Attachment[BUFFER_STENCIL].Renderbuffer);
489 intel_renderbuffer(draw_fb->Attachment[BUFFER_STENCIL].Renderbuffer);
490 do_blorp_blit(brw, buffer_bit, src_irb, MESA_FORMAT_NONE,
491 dst_irb, MESA_FORMAT_NONE, srcX0, srcY0,
492 srcX1, srcY1, dstX0, dstY0, dstX1, dstY1,
493 filter, mirror_x, mirror_y);
496 unreachable("not reached");
503 brw_blorp_copytexsubimage(struct brw_context *brw,
504 struct gl_renderbuffer *src_rb,
505 struct gl_texture_image *dst_image,
507 int srcX0, int srcY0,
508 int dstX0, int dstY0,
509 int width, int height)
511 struct gl_context *ctx = &brw->ctx;
512 struct intel_renderbuffer *src_irb = intel_renderbuffer(src_rb);
513 struct intel_texture_image *intel_image = intel_texture_image(dst_image);
515 /* No pixel transfer operations (zoom, bias, mapping), just a blit */
516 if (brw->ctx._ImageTransferState)
519 /* Sync up the state of window system buffers. We need to do this before
520 * we go looking at the src renderbuffer's miptree.
522 intel_prepare_render(brw);
524 struct intel_mipmap_tree *src_mt = src_irb->mt;
525 struct intel_mipmap_tree *dst_mt = intel_image->mt;
527 /* There is support for only up to eight samples. */
528 if (src_mt->num_samples > 8 || dst_mt->num_samples > 8)
531 /* BLORP is only supported from Gen6 onwards. */
535 if (_mesa_get_format_base_format(src_rb->Format) !=
536 _mesa_get_format_base_format(dst_image->TexFormat)) {
540 /* We can't handle format conversions between Z24 and other formats since
541 * we have to lie about the surface format. See the comments in
542 * brw_blorp_surface_info::set().
544 if ((src_mt->format == MESA_FORMAT_Z24_UNORM_X8_UINT) !=
545 (dst_mt->format == MESA_FORMAT_Z24_UNORM_X8_UINT)) {
549 if (!brw->format_supported_as_render_target[dst_image->TexFormat])
552 /* Source clipping shouldn't be necessary, since copytexsubimage (in
553 * src/mesa/main/teximage.c) calls _mesa_clip_copytexsubimage() which
556 * Destination clipping shouldn't be necessary since the restrictions on
557 * glCopyTexSubImage prevent the user from specifying a destination rectangle
558 * that falls outside the bounds of the destination texture.
559 * See error_check_subtexture_dimensions().
562 int srcY1 = srcY0 + height;
563 int srcX1 = srcX0 + width;
564 int dstX1 = dstX0 + width;
565 int dstY1 = dstY0 + height;
567 /* Account for the fact that in the system framebuffer, the origin is at
570 bool mirror_y = false;
571 if (_mesa_is_winsys_fbo(ctx->ReadBuffer)) {
572 GLint tmp = src_rb->Height - srcY0;
573 srcY0 = src_rb->Height - srcY1;
578 /* Account for face selection and texture view MinLayer */
579 int dst_slice = slice + dst_image->TexObject->MinLayer + dst_image->Face;
580 int dst_level = dst_image->Level + dst_image->TexObject->MinLevel;
582 brw_blorp_blit_miptrees(brw,
583 src_mt, src_irb->mt_level, src_irb->mt_layer,
584 src_rb->Format, blorp_get_texture_swizzle(src_irb),
585 dst_mt, dst_level, dst_slice,
586 dst_image->TexFormat,
587 srcX0, srcY0, srcX1, srcY1,
588 dstX0, dstY0, dstX1, dstY1,
589 GL_NEAREST, false, mirror_y,
592 /* If we're copying to a packed depth stencil texture and the source
593 * framebuffer has separate stencil, we need to also copy the stencil data
596 src_rb = ctx->ReadBuffer->Attachment[BUFFER_STENCIL].Renderbuffer;
597 if (_mesa_get_format_bits(dst_image->TexFormat, GL_STENCIL_BITS) > 0 &&
599 src_irb = intel_renderbuffer(src_rb);
600 src_mt = src_irb->mt;
602 if (src_mt->stencil_mt)
603 src_mt = src_mt->stencil_mt;
604 if (dst_mt->stencil_mt)
605 dst_mt = dst_mt->stencil_mt;
607 if (src_mt != dst_mt) {
608 brw_blorp_blit_miptrees(brw,
609 src_mt, src_irb->mt_level, src_irb->mt_layer,
611 blorp_get_texture_swizzle(src_irb),
612 dst_mt, dst_level, dst_slice,
614 srcX0, srcY0, srcX1, srcY1,
615 dstX0, dstY0, dstX1, dstY1,
616 GL_NEAREST, false, mirror_y,
626 brw_blorp_framebuffer(struct brw_context *brw,
627 struct gl_framebuffer *readFb,
628 struct gl_framebuffer *drawFb,
629 GLint srcX0, GLint srcY0, GLint srcX1, GLint srcY1,
630 GLint dstX0, GLint dstY0, GLint dstX1, GLint dstY1,
631 GLbitfield mask, GLenum filter)
633 /* BLORP is not supported before Gen6. */
637 static GLbitfield buffer_bits[] = {
640 GL_STENCIL_BUFFER_BIT,
643 for (unsigned int i = 0; i < ARRAY_SIZE(buffer_bits); ++i) {
644 if ((mask & buffer_bits[i]) &&
645 try_blorp_blit(brw, readFb, drawFb,
646 srcX0, srcY0, srcX1, srcY1,
647 dstX0, dstY0, dstX1, dstY1,
648 filter, buffer_bits[i])) {
649 mask &= ~buffer_bits[i];
657 set_write_disables(const struct intel_renderbuffer *irb,
658 const GLubyte *color_mask, bool *color_write_disable)
660 /* Format information in the renderbuffer represents the requirements
661 * given by the client. There are cases where the backing miptree uses,
662 * for example, RGBA to represent RGBX. Since the client is only expecting
663 * RGB we can treat alpha as not used and write whatever we like into it.
665 const GLenum base_format = irb->Base.Base._BaseFormat;
666 const int components = _mesa_base_format_component_count(base_format);
667 bool disables = false;
669 assert(components > 0);
671 for (int i = 0; i < components; i++) {
672 color_write_disable[i] = !color_mask[i];
673 disables = disables || !color_mask[i];
680 do_single_blorp_clear(struct brw_context *brw, struct gl_framebuffer *fb,
681 struct gl_renderbuffer *rb, unsigned buf,
682 bool partial_clear, bool encode_srgb)
684 struct gl_context *ctx = &brw->ctx;
685 struct intel_renderbuffer *irb = intel_renderbuffer(rb);
686 mesa_format format = irb->mt->format;
687 uint32_t x0, x1, y0, y1;
689 if (!encode_srgb && _mesa_get_format_color_encoding(format) == GL_SRGB)
690 format = _mesa_get_srgb_format_linear(format);
698 y0 = rb->Height - fb->_Ymax;
699 y1 = rb->Height - fb->_Ymin;
702 /* If the clear region is empty, just return. */
703 if (x0 == x1 || y0 == y1)
706 bool can_fast_clear = !partial_clear;
708 bool color_write_disable[4] = { false, false, false, false };
709 if (set_write_disables(irb, ctx->Color.ColorMask[buf], color_write_disable))
710 can_fast_clear = false;
712 if (irb->mt->fast_clear_state == INTEL_FAST_CLEAR_STATE_NO_MCS ||
713 !brw_is_color_fast_clear_compatible(brw, irb->mt, &ctx->Color.ClearColor))
714 can_fast_clear = false;
716 const bool is_lossless_compressed = intel_miptree_is_lossless_compressed(
719 if (can_fast_clear) {
720 /* Record the clear color in the miptree so that it will be
721 * programmed in SURFACE_STATE by later rendering and resolve
724 const bool color_updated = brw_meta_set_fast_clear_color(
725 brw, irb->mt, &ctx->Color.ClearColor);
727 /* If the buffer is already in INTEL_FAST_CLEAR_STATE_CLEAR, the clear
728 * is redundant and can be skipped.
730 if (!color_updated &&
731 irb->mt->fast_clear_state == INTEL_FAST_CLEAR_STATE_CLEAR)
734 /* If the MCS buffer hasn't been allocated yet, we need to allocate
737 if (!irb->mt->mcs_mt) {
738 assert(!is_lossless_compressed);
739 if (!intel_miptree_alloc_non_msrt_mcs(brw, irb->mt, false)) {
740 /* MCS allocation failed--probably this will only happen in
741 * out-of-memory conditions. But in any case, try to recover
742 * by falling back to a non-blorp clear technique.
749 intel_miptree_used_for_rendering(irb->mt);
751 /* We can't setup the blorp_surf until we've allocated the MCS above */
752 struct isl_surf isl_tmp[2];
753 struct blorp_surf surf;
754 unsigned level = irb->mt_level;
755 blorp_surf_for_miptree(brw, &surf, irb->mt, true, &level, isl_tmp);
756 const unsigned num_layers = fb->MaxNumLayers ? irb->layer_count : 1;
758 if (can_fast_clear) {
759 DBG("%s (fast) to mt %p level %d layers %d+%d\n", __FUNCTION__,
760 irb->mt, irb->mt_level, irb->mt_layer, num_layers);
762 struct blorp_batch batch;
763 blorp_batch_init(&brw->blorp, &batch, brw);
764 blorp_fast_clear(&batch, &surf,
765 (enum isl_format)brw->render_target_format[format],
766 level, irb->mt_layer, num_layers, x0, y0, x1, y1);
767 blorp_batch_finish(&batch);
769 /* Now that the fast clear has occurred, put the buffer in
770 * INTEL_FAST_CLEAR_STATE_CLEAR so that we won't waste time doing
773 irb->mt->fast_clear_state = INTEL_FAST_CLEAR_STATE_CLEAR;
775 DBG("%s (slow) to mt %p level %d layer %d+%d\n", __FUNCTION__,
776 irb->mt, irb->mt_level, irb->mt_layer, num_layers);
778 union isl_color_value clear_color;
779 memcpy(clear_color.f32, ctx->Color.ClearColor.f, sizeof(float) * 4);
781 struct blorp_batch batch;
782 blorp_batch_init(&brw->blorp, &batch, brw);
783 blorp_clear(&batch, &surf, level, irb->mt_layer, num_layers,
785 (enum isl_format)brw->render_target_format[format],
786 clear_color, color_write_disable);
787 blorp_batch_finish(&batch);
789 if (is_lossless_compressed) {
790 /* Compressed buffers can be cleared also using normal rep-clear. In
791 * such case they behave such as if they were drawn using normal 3D
792 * render pipeline, and we simply mark the mcs as dirty.
794 irb->mt->fast_clear_state = INTEL_FAST_CLEAR_STATE_UNRESOLVED;
802 brw_blorp_clear_color(struct brw_context *brw, struct gl_framebuffer *fb,
803 GLbitfield mask, bool partial_clear, bool encode_srgb)
805 for (unsigned buf = 0; buf < fb->_NumColorDrawBuffers; buf++) {
806 struct gl_renderbuffer *rb = fb->_ColorDrawBuffers[buf];
807 struct intel_renderbuffer *irb = intel_renderbuffer(rb);
809 /* Only clear the buffers present in the provided mask */
810 if (((1 << fb->_ColorDrawBufferIndexes[buf]) & mask) == 0)
813 /* If this is an ES2 context or GL_ARB_ES2_compatibility is supported,
814 * the framebuffer can be complete with some attachments missing. In
815 * this case the _ColorDrawBuffers pointer will be NULL.
820 const unsigned num_layers = fb->MaxNumLayers ? irb->layer_count : 1;
821 for (unsigned layer = 0; layer < num_layers; layer++) {
822 intel_miptree_check_level_layer(irb->mt, irb->mt_level, layer);
825 if (!do_single_blorp_clear(brw, fb, rb, buf, partial_clear,
830 irb->need_downsample = true;
837 brw_blorp_resolve_color(struct brw_context *brw, struct intel_mipmap_tree *mt)
839 DBG("%s to mt %p\n", __FUNCTION__, mt);
841 const mesa_format format = _mesa_get_srgb_format_linear(mt->format);
843 intel_miptree_check_level_layer(mt, 0 /* level */, 0 /* layer */);
844 intel_miptree_used_for_rendering(mt);
846 struct isl_surf isl_tmp[2];
847 struct blorp_surf surf;
849 blorp_surf_for_miptree(brw, &surf, mt, true, &level, isl_tmp);
851 struct blorp_batch batch;
852 blorp_batch_init(&brw->blorp, &batch, brw);
853 blorp_ccs_resolve(&batch, &surf,
854 brw_blorp_to_isl_format(brw, format, true));
855 blorp_batch_finish(&batch);
857 mt->fast_clear_state = INTEL_FAST_CLEAR_STATE_RESOLVED;
861 gen6_blorp_hiz_exec(struct brw_context *brw, struct intel_mipmap_tree *mt,
862 unsigned int level, unsigned int layer, enum blorp_hiz_op op)
864 intel_miptree_check_level_layer(mt, level, layer);
865 intel_miptree_used_for_rendering(mt);
867 assert(intel_miptree_level_has_hiz(mt, level));
869 struct isl_surf isl_tmp[2];
870 struct blorp_surf surf;
871 blorp_surf_for_miptree(brw, &surf, mt, true, &level, isl_tmp);
873 struct blorp_batch batch;
874 blorp_batch_init(&brw->blorp, &batch, brw);
875 blorp_gen6_hiz_op(&batch, &surf, level, layer, op);
876 blorp_batch_finish(&batch);
880 * Perform a HiZ or depth resolve operation.
882 * For an overview of HiZ ops, see the following sections of the Sandy Bridge
883 * PRM, Volume 1, Part 2:
884 * - 7.5.3.1 Depth Buffer Clear
885 * - 7.5.3.2 Depth Buffer Resolve
886 * - 7.5.3.3 Hierarchical Depth Buffer Resolve
889 intel_hiz_exec(struct brw_context *brw, struct intel_mipmap_tree *mt,
890 unsigned int level, unsigned int layer, enum blorp_hiz_op op)
892 const char *opname = NULL;
895 case BLORP_HIZ_OP_DEPTH_RESOLVE:
896 opname = "depth resolve";
898 case BLORP_HIZ_OP_HIZ_RESOLVE:
899 opname = "hiz ambiguate";
901 case BLORP_HIZ_OP_DEPTH_CLEAR:
902 opname = "depth clear";
904 case BLORP_HIZ_OP_NONE:
909 DBG("%s %s to mt %p level %d layer %d\n",
910 __func__, opname, mt, level, layer);
913 gen8_hiz_exec(brw, mt, level, layer, op);
915 gen6_blorp_hiz_exec(brw, mt, level, layer, op);