2 * Copyright © 2012 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include "main/context.h"
25 #include "main/teximage.h"
26 #include "main/blend.h"
27 #include "main/fbobject.h"
28 #include "main/renderbuffer.h"
29 #include "main/glformats.h"
31 #include "brw_blorp.h"
32 #include "brw_context.h"
33 #include "brw_defines.h"
34 #include "brw_meta_util.h"
35 #include "brw_state.h"
36 #include "intel_fbo.h"
37 #include "intel_debug.h"
39 #define FILE_DEBUG_FLAG DEBUG_BLORP
42 brw_blorp_lookup_shader(struct blorp_context *blorp,
43 const void *key, uint32_t key_size,
44 uint32_t *kernel_out, void *prog_data_out)
46 struct brw_context *brw = blorp->driver_ctx;
47 return brw_search_cache(&brw->cache, BRW_CACHE_BLORP_PROG,
48 key, key_size, kernel_out, prog_data_out);
52 brw_blorp_upload_shader(struct blorp_context *blorp,
53 const void *key, uint32_t key_size,
54 const void *kernel, uint32_t kernel_size,
55 const void *prog_data, uint32_t prog_data_size,
56 uint32_t *kernel_out, void *prog_data_out)
58 struct brw_context *brw = blorp->driver_ctx;
59 brw_upload_cache(&brw->cache, BRW_CACHE_BLORP_PROG, key, key_size,
60 kernel, kernel_size, prog_data, prog_data_size,
61 kernel_out, prog_data_out);
65 brw_blorp_init(struct brw_context *brw)
67 blorp_init(&brw->blorp, brw, &brw->isl_dev);
71 brw->blorp.mocs.tex = 0;
72 brw->blorp.mocs.rb = 0;
73 brw->blorp.mocs.vb = 0;
76 brw->blorp.mocs.tex = GEN7_MOCS_L3;
77 brw->blorp.mocs.rb = GEN7_MOCS_L3;
78 brw->blorp.mocs.vb = GEN7_MOCS_L3;
81 brw->blorp.mocs.tex = BDW_MOCS_WB;
82 brw->blorp.mocs.rb = BDW_MOCS_PTE;
83 brw->blorp.mocs.vb = BDW_MOCS_WB;
86 brw->blorp.mocs.tex = SKL_MOCS_WB;
87 brw->blorp.mocs.rb = SKL_MOCS_PTE;
88 brw->blorp.mocs.vb = SKL_MOCS_WB;
91 unreachable("Invalid gen");
94 brw->blorp.lookup_shader = brw_blorp_lookup_shader;
95 brw->blorp.upload_shader = brw_blorp_upload_shader;
99 apply_gen6_stencil_hiz_offset(struct isl_surf *surf,
100 struct intel_mipmap_tree *mt,
104 assert(mt->array_layout == ALL_SLICES_AT_EACH_LOD);
106 if (mt->format == MESA_FORMAT_S_UINT8) {
107 /* Note: we can't compute the stencil offset using
108 * intel_miptree_get_aligned_offset(), because the miptree
109 * claims that the region is untiled even though it's W tiled.
111 *offset = mt->level[lod].level_y * mt->pitch +
112 mt->level[lod].level_x * 64;
114 *offset = intel_miptree_get_aligned_offset(mt,
115 mt->level[lod].level_x,
116 mt->level[lod].level_y,
120 surf->logical_level0_px.width = minify(surf->logical_level0_px.width, lod);
121 surf->logical_level0_px.height = minify(surf->logical_level0_px.height, lod);
122 surf->phys_level0_sa.width = minify(surf->phys_level0_sa.width, lod);
123 surf->phys_level0_sa.height = minify(surf->phys_level0_sa.height, lod);
125 surf->array_pitch_el_rows =
126 ALIGN(surf->phys_level0_sa.height, surf->image_alignment_el.height);
130 brw_blorp_surf_for_miptree(struct brw_context *brw,
131 struct brw_blorp_surf *surf,
132 struct intel_mipmap_tree *mt,
133 bool is_render_target,
135 struct isl_surf tmp_surfs[2])
137 intel_miptree_get_isl_surf(brw, mt, &tmp_surfs[0]);
138 surf->surf = &tmp_surfs[0];
139 surf->addr = (struct blorp_address) {
141 .offset = mt->offset,
142 .read_domains = is_render_target ? I915_GEM_DOMAIN_RENDER :
143 I915_GEM_DOMAIN_SAMPLER,
144 .write_domain = is_render_target ? I915_GEM_DOMAIN_RENDER : 0,
147 if (brw->gen == 6 && mt->format == MESA_FORMAT_S_UINT8 &&
148 mt->array_layout == ALL_SLICES_AT_EACH_LOD) {
149 /* Sandy bridge stencil and HiZ use this ALL_SLICES_AT_EACH_LOD hack in
150 * order to allow for layered rendering. The hack makes each LOD of the
151 * stencil or HiZ buffer a single tightly packed array surface at some
152 * offset into the surface. Since ISL doesn't know how to deal with the
153 * crazy ALL_SLICES_AT_EACH_LOD layout and since we have to do a manual
154 * offset of it anyway, we might as well do the offset here and keep the
155 * hacks inside the i965 driver.
157 * See also gen6_depth_stencil_state.c
160 apply_gen6_stencil_hiz_offset(&tmp_surfs[0], mt, *level, &offset);
161 surf->addr.offset += offset;
165 struct isl_surf *aux_surf = &tmp_surfs[1];
166 intel_miptree_get_aux_isl_surf(brw, mt, aux_surf, &surf->aux_usage);
168 /* For textures that are in the RESOLVED state, we ignore the MCS */
169 if (mt->mcs_mt && !is_render_target &&
170 mt->fast_clear_state == INTEL_FAST_CLEAR_STATE_RESOLVED)
171 surf->aux_usage = ISL_AUX_USAGE_NONE;
173 if (surf->aux_usage != ISL_AUX_USAGE_NONE) {
174 /* We only really need a clear color if we also have an auxiliary
175 * surface. Without one, it does nothing.
177 surf->clear_color = intel_miptree_get_isl_clear_color(brw, mt);
179 surf->aux_surf = aux_surf;
180 surf->aux_addr = (struct blorp_address) {
181 .read_domains = is_render_target ? I915_GEM_DOMAIN_RENDER :
182 I915_GEM_DOMAIN_SAMPLER,
183 .write_domain = is_render_target ? I915_GEM_DOMAIN_RENDER : 0,
187 surf->aux_addr.buffer = mt->mcs_mt->bo;
188 surf->aux_addr.offset = mt->mcs_mt->offset;
190 assert(surf->aux_usage == ISL_AUX_USAGE_HIZ);
191 struct intel_mipmap_tree *hiz_mt = mt->hiz_buf->mt;
193 surf->aux_addr.buffer = hiz_mt->bo;
195 hiz_mt->array_layout == ALL_SLICES_AT_EACH_LOD) {
196 /* gen6 requires the HiZ buffer to be manually offset to the
197 * right location. We could fixup the surf but it doesn't
198 * matter since most of those fields don't matter.
200 apply_gen6_stencil_hiz_offset(aux_surf, hiz_mt, *level,
201 &surf->aux_addr.offset);
203 surf->aux_addr.offset = 0;
205 assert(hiz_mt->pitch == aux_surf->row_pitch);
207 surf->aux_addr.buffer = mt->hiz_buf->bo;
208 surf->aux_addr.offset = 0;
212 surf->aux_addr = (struct blorp_address) {
215 memset(&surf->clear_color, 0, sizeof(surf->clear_color));
217 assert((surf->aux_usage == ISL_AUX_USAGE_NONE) ==
218 (surf->aux_addr.buffer == NULL));
221 static enum isl_format
222 brw_blorp_to_isl_format(struct brw_context *brw, mesa_format format,
223 bool is_render_target)
226 case MESA_FORMAT_NONE:
227 return ISL_FORMAT_UNSUPPORTED;
228 case MESA_FORMAT_S_UINT8:
229 return ISL_FORMAT_R8_UINT;
230 case MESA_FORMAT_Z24_UNORM_X8_UINT:
231 return ISL_FORMAT_R24_UNORM_X8_TYPELESS;
232 case MESA_FORMAT_Z_FLOAT32:
233 return ISL_FORMAT_R32_FLOAT;
234 case MESA_FORMAT_Z_UNORM16:
235 return ISL_FORMAT_R16_UNORM;
237 if (is_render_target) {
238 assert(brw->format_supported_as_render_target[format]);
239 return brw->render_target_format[format];
241 return brw_format_for_mesa_format(format);
249 * Note: if the src (or dst) is a 2D multisample array texture on Gen7+ using
250 * INTEL_MSAA_LAYOUT_UMS or INTEL_MSAA_LAYOUT_CMS, src_layer (dst_layer) is
251 * the physical layer holding sample 0. So, for example, if
252 * src_mt->num_samples == 4, then logical layer n corresponds to src_layer ==
256 brw_blorp_blit_miptrees(struct brw_context *brw,
257 struct intel_mipmap_tree *src_mt,
258 unsigned src_level, unsigned src_layer,
259 mesa_format src_format, int src_swizzle,
260 struct intel_mipmap_tree *dst_mt,
261 unsigned dst_level, unsigned dst_layer,
262 mesa_format dst_format,
263 float src_x0, float src_y0,
264 float src_x1, float src_y1,
265 float dst_x0, float dst_y0,
266 float dst_x1, float dst_y1,
267 GLenum filter, bool mirror_x, bool mirror_y,
268 bool decode_srgb, bool encode_srgb)
270 /* Get ready to blit. This includes depth resolving the src and dst
271 * buffers if necessary. Note: it's not necessary to do a color resolve on
272 * the destination buffer because we use the standard render path to render
273 * to destination color buffers, and the standard render path is
276 intel_miptree_resolve_color(brw, src_mt, INTEL_MIPTREE_IGNORE_CCS_E);
277 intel_miptree_slice_resolve_depth(brw, src_mt, src_level, src_layer);
278 intel_miptree_slice_resolve_depth(brw, dst_mt, dst_level, dst_layer);
280 intel_miptree_prepare_mcs(brw, dst_mt);
282 DBG("%s from %dx %s mt %p %d %d (%f,%f) (%f,%f)"
283 "to %dx %s mt %p %d %d (%f,%f) (%f,%f) (flip %d,%d)\n",
285 src_mt->num_samples, _mesa_get_format_name(src_mt->format), src_mt,
286 src_level, src_layer, src_x0, src_y0, src_x1, src_y1,
287 dst_mt->num_samples, _mesa_get_format_name(dst_mt->format), dst_mt,
288 dst_level, dst_layer, dst_x0, dst_y0, dst_x1, dst_y1,
291 if (!decode_srgb && _mesa_get_format_color_encoding(src_format) == GL_SRGB)
292 src_format = _mesa_get_srgb_format_linear(src_format);
294 if (!encode_srgb && _mesa_get_format_color_encoding(dst_format) == GL_SRGB)
295 dst_format = _mesa_get_srgb_format_linear(dst_format);
297 /* When doing a multisample resolve of a GL_LUMINANCE32F or GL_INTENSITY32F
298 * texture, the above code configures the source format for L32_FLOAT or
299 * I32_FLOAT, and the destination format for R32_FLOAT. On Sandy Bridge,
300 * the SAMPLE message appears to handle multisampled L32_FLOAT and
301 * I32_FLOAT textures incorrectly, resulting in blocky artifacts. So work
302 * around the problem by using a source format of R32_FLOAT. This
303 * shouldn't affect rendering correctness, since the destination format is
304 * R32_FLOAT, so only the contents of the red channel matters.
307 src_mt->num_samples > 1 && dst_mt->num_samples <= 1 &&
308 src_mt->format == dst_mt->format &&
309 (dst_format == MESA_FORMAT_L_FLOAT32 ||
310 dst_format == MESA_FORMAT_I_FLOAT32)) {
311 src_format = dst_format = MESA_FORMAT_R_FLOAT32;
314 intel_miptree_check_level_layer(src_mt, src_level, src_layer);
315 intel_miptree_check_level_layer(dst_mt, dst_level, dst_layer);
316 intel_miptree_used_for_rendering(dst_mt);
318 struct isl_surf tmp_surfs[4];
319 struct brw_blorp_surf src_surf, dst_surf;
320 brw_blorp_surf_for_miptree(brw, &src_surf, src_mt, false,
321 &src_level, &tmp_surfs[0]);
322 brw_blorp_surf_for_miptree(brw, &dst_surf, dst_mt, true,
323 &dst_level, &tmp_surfs[2]);
325 brw_blorp_blit(brw, &src_surf, src_level, src_layer,
326 brw_blorp_to_isl_format(brw, src_format, false), src_swizzle,
327 &dst_surf, dst_level, dst_layer,
328 brw_blorp_to_isl_format(brw, dst_format, true),
329 src_x0, src_y0, src_x1, src_y1,
330 dst_x0, dst_y0, dst_x1, dst_y1,
331 filter, mirror_x, mirror_y);
333 intel_miptree_slice_set_needs_hiz_resolve(dst_mt, dst_level, dst_layer);
335 if (intel_miptree_is_lossless_compressed(brw, dst_mt))
336 dst_mt->fast_clear_state = INTEL_FAST_CLEAR_STATE_UNRESOLVED;
339 static struct intel_mipmap_tree *
340 find_miptree(GLbitfield buffer_bit, struct intel_renderbuffer *irb)
342 struct intel_mipmap_tree *mt = irb->mt;
343 if (buffer_bit == GL_STENCIL_BUFFER_BIT && mt->stencil_mt)
349 blorp_get_texture_swizzle(const struct intel_renderbuffer *irb)
351 return irb->Base.Base._BaseFormat == GL_RGB ?
352 MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y, SWIZZLE_Z, SWIZZLE_ONE) :
357 do_blorp_blit(struct brw_context *brw, GLbitfield buffer_bit,
358 struct intel_renderbuffer *src_irb, mesa_format src_format,
359 struct intel_renderbuffer *dst_irb, mesa_format dst_format,
360 GLfloat srcX0, GLfloat srcY0, GLfloat srcX1, GLfloat srcY1,
361 GLfloat dstX0, GLfloat dstY0, GLfloat dstX1, GLfloat dstY1,
362 GLenum filter, bool mirror_x, bool mirror_y)
364 const struct gl_context *ctx = &brw->ctx;
366 /* Find source/dst miptrees */
367 struct intel_mipmap_tree *src_mt = find_miptree(buffer_bit, src_irb);
368 struct intel_mipmap_tree *dst_mt = find_miptree(buffer_bit, dst_irb);
370 const bool do_srgb = ctx->Color.sRGBEnabled;
373 brw_blorp_blit_miptrees(brw,
374 src_mt, src_irb->mt_level, src_irb->mt_layer,
375 src_format, blorp_get_texture_swizzle(src_irb),
376 dst_mt, dst_irb->mt_level, dst_irb->mt_layer,
378 srcX0, srcY0, srcX1, srcY1,
379 dstX0, dstY0, dstX1, dstY1,
380 filter, mirror_x, mirror_y,
383 dst_irb->need_downsample = true;
387 try_blorp_blit(struct brw_context *brw,
388 const struct gl_framebuffer *read_fb,
389 const struct gl_framebuffer *draw_fb,
390 GLfloat srcX0, GLfloat srcY0, GLfloat srcX1, GLfloat srcY1,
391 GLfloat dstX0, GLfloat dstY0, GLfloat dstX1, GLfloat dstY1,
392 GLenum filter, GLbitfield buffer_bit)
394 struct gl_context *ctx = &brw->ctx;
396 /* Sync up the state of window system buffers. We need to do this before
397 * we go looking for the buffers.
399 intel_prepare_render(brw);
401 bool mirror_x, mirror_y;
402 if (brw_meta_mirror_clip_and_scissor(ctx, read_fb, draw_fb,
403 &srcX0, &srcY0, &srcX1, &srcY1,
404 &dstX0, &dstY0, &dstX1, &dstY1,
405 &mirror_x, &mirror_y))
409 struct intel_renderbuffer *src_irb;
410 struct intel_renderbuffer *dst_irb;
411 struct intel_mipmap_tree *src_mt;
412 struct intel_mipmap_tree *dst_mt;
413 switch (buffer_bit) {
414 case GL_COLOR_BUFFER_BIT:
415 src_irb = intel_renderbuffer(read_fb->_ColorReadBuffer);
416 for (unsigned i = 0; i < draw_fb->_NumColorDrawBuffers; ++i) {
417 dst_irb = intel_renderbuffer(draw_fb->_ColorDrawBuffers[i]);
419 do_blorp_blit(brw, buffer_bit,
420 src_irb, src_irb->Base.Base.Format,
421 dst_irb, dst_irb->Base.Base.Format,
422 srcX0, srcY0, srcX1, srcY1,
423 dstX0, dstY0, dstX1, dstY1,
424 filter, mirror_x, mirror_y);
427 case GL_DEPTH_BUFFER_BIT:
429 intel_renderbuffer(read_fb->Attachment[BUFFER_DEPTH].Renderbuffer);
431 intel_renderbuffer(draw_fb->Attachment[BUFFER_DEPTH].Renderbuffer);
432 src_mt = find_miptree(buffer_bit, src_irb);
433 dst_mt = find_miptree(buffer_bit, dst_irb);
435 /* We can't handle format conversions between Z24 and other formats
436 * since we have to lie about the surface format. See the comments in
437 * brw_blorp_surface_info::set().
439 if ((src_mt->format == MESA_FORMAT_Z24_UNORM_X8_UINT) !=
440 (dst_mt->format == MESA_FORMAT_Z24_UNORM_X8_UINT))
443 do_blorp_blit(brw, buffer_bit, src_irb, MESA_FORMAT_NONE,
444 dst_irb, MESA_FORMAT_NONE, srcX0, srcY0,
445 srcX1, srcY1, dstX0, dstY0, dstX1, dstY1,
446 filter, mirror_x, mirror_y);
448 case GL_STENCIL_BUFFER_BIT:
450 intel_renderbuffer(read_fb->Attachment[BUFFER_STENCIL].Renderbuffer);
452 intel_renderbuffer(draw_fb->Attachment[BUFFER_STENCIL].Renderbuffer);
453 do_blorp_blit(brw, buffer_bit, src_irb, MESA_FORMAT_NONE,
454 dst_irb, MESA_FORMAT_NONE, srcX0, srcY0,
455 srcX1, srcY1, dstX0, dstY0, dstX1, dstY1,
456 filter, mirror_x, mirror_y);
459 unreachable("not reached");
466 brw_blorp_copytexsubimage(struct brw_context *brw,
467 struct gl_renderbuffer *src_rb,
468 struct gl_texture_image *dst_image,
470 int srcX0, int srcY0,
471 int dstX0, int dstY0,
472 int width, int height)
474 struct gl_context *ctx = &brw->ctx;
475 struct intel_renderbuffer *src_irb = intel_renderbuffer(src_rb);
476 struct intel_texture_image *intel_image = intel_texture_image(dst_image);
478 /* No pixel transfer operations (zoom, bias, mapping), just a blit */
479 if (brw->ctx._ImageTransferState)
482 /* Sync up the state of window system buffers. We need to do this before
483 * we go looking at the src renderbuffer's miptree.
485 intel_prepare_render(brw);
487 struct intel_mipmap_tree *src_mt = src_irb->mt;
488 struct intel_mipmap_tree *dst_mt = intel_image->mt;
490 /* There is support for only up to eight samples. */
491 if (src_mt->num_samples > 8 || dst_mt->num_samples > 8)
494 /* BLORP is only supported from Gen6 onwards. */
498 if (_mesa_get_format_base_format(src_rb->Format) !=
499 _mesa_get_format_base_format(dst_image->TexFormat)) {
503 /* We can't handle format conversions between Z24 and other formats since
504 * we have to lie about the surface format. See the comments in
505 * brw_blorp_surface_info::set().
507 if ((src_mt->format == MESA_FORMAT_Z24_UNORM_X8_UINT) !=
508 (dst_mt->format == MESA_FORMAT_Z24_UNORM_X8_UINT)) {
512 if (!brw->format_supported_as_render_target[dst_image->TexFormat])
515 /* Source clipping shouldn't be necessary, since copytexsubimage (in
516 * src/mesa/main/teximage.c) calls _mesa_clip_copytexsubimage() which
519 * Destination clipping shouldn't be necessary since the restrictions on
520 * glCopyTexSubImage prevent the user from specifying a destination rectangle
521 * that falls outside the bounds of the destination texture.
522 * See error_check_subtexture_dimensions().
525 int srcY1 = srcY0 + height;
526 int srcX1 = srcX0 + width;
527 int dstX1 = dstX0 + width;
528 int dstY1 = dstY0 + height;
530 /* Account for the fact that in the system framebuffer, the origin is at
533 bool mirror_y = false;
534 if (_mesa_is_winsys_fbo(ctx->ReadBuffer)) {
535 GLint tmp = src_rb->Height - srcY0;
536 srcY0 = src_rb->Height - srcY1;
541 /* Account for face selection and texture view MinLayer */
542 int dst_slice = slice + dst_image->TexObject->MinLayer + dst_image->Face;
543 int dst_level = dst_image->Level + dst_image->TexObject->MinLevel;
545 brw_blorp_blit_miptrees(brw,
546 src_mt, src_irb->mt_level, src_irb->mt_layer,
547 src_rb->Format, blorp_get_texture_swizzle(src_irb),
548 dst_mt, dst_level, dst_slice,
549 dst_image->TexFormat,
550 srcX0, srcY0, srcX1, srcY1,
551 dstX0, dstY0, dstX1, dstY1,
552 GL_NEAREST, false, mirror_y,
555 /* If we're copying to a packed depth stencil texture and the source
556 * framebuffer has separate stencil, we need to also copy the stencil data
559 src_rb = ctx->ReadBuffer->Attachment[BUFFER_STENCIL].Renderbuffer;
560 if (_mesa_get_format_bits(dst_image->TexFormat, GL_STENCIL_BITS) > 0 &&
562 src_irb = intel_renderbuffer(src_rb);
563 src_mt = src_irb->mt;
565 if (src_mt->stencil_mt)
566 src_mt = src_mt->stencil_mt;
567 if (dst_mt->stencil_mt)
568 dst_mt = dst_mt->stencil_mt;
570 if (src_mt != dst_mt) {
571 brw_blorp_blit_miptrees(brw,
572 src_mt, src_irb->mt_level, src_irb->mt_layer,
574 blorp_get_texture_swizzle(src_irb),
575 dst_mt, dst_level, dst_slice,
577 srcX0, srcY0, srcX1, srcY1,
578 dstX0, dstY0, dstX1, dstY1,
579 GL_NEAREST, false, mirror_y,
589 brw_blorp_framebuffer(struct brw_context *brw,
590 struct gl_framebuffer *readFb,
591 struct gl_framebuffer *drawFb,
592 GLint srcX0, GLint srcY0, GLint srcX1, GLint srcY1,
593 GLint dstX0, GLint dstY0, GLint dstX1, GLint dstY1,
594 GLbitfield mask, GLenum filter)
596 /* BLORP is not supported before Gen6. */
600 static GLbitfield buffer_bits[] = {
603 GL_STENCIL_BUFFER_BIT,
606 for (unsigned int i = 0; i < ARRAY_SIZE(buffer_bits); ++i) {
607 if ((mask & buffer_bits[i]) &&
608 try_blorp_blit(brw, readFb, drawFb,
609 srcX0, srcY0, srcX1, srcY1,
610 dstX0, dstY0, dstX1, dstY1,
611 filter, buffer_bits[i])) {
612 mask &= ~buffer_bits[i];
620 set_write_disables(const struct intel_renderbuffer *irb,
621 const GLubyte *color_mask, bool *color_write_disable)
623 /* Format information in the renderbuffer represents the requirements
624 * given by the client. There are cases where the backing miptree uses,
625 * for example, RGBA to represent RGBX. Since the client is only expecting
626 * RGB we can treat alpha as not used and write whatever we like into it.
628 const GLenum base_format = irb->Base.Base._BaseFormat;
629 const int components = _mesa_base_format_component_count(base_format);
630 bool disables = false;
632 assert(components > 0);
634 for (int i = 0; i < components; i++) {
635 color_write_disable[i] = !color_mask[i];
636 disables = disables || !color_mask[i];
643 do_single_blorp_clear(struct brw_context *brw, struct gl_framebuffer *fb,
644 struct gl_renderbuffer *rb, unsigned buf,
645 bool partial_clear, bool encode_srgb, unsigned layer)
647 struct gl_context *ctx = &brw->ctx;
648 struct intel_renderbuffer *irb = intel_renderbuffer(rb);
649 mesa_format format = irb->mt->format;
650 uint32_t x0, x1, y0, y1;
652 if (!encode_srgb && _mesa_get_format_color_encoding(format) == GL_SRGB)
653 format = _mesa_get_srgb_format_linear(format);
661 y0 = rb->Height - fb->_Ymax;
662 y1 = rb->Height - fb->_Ymin;
665 /* If the clear region is empty, just return. */
666 if (x0 == x1 || y0 == y1)
669 bool can_fast_clear = !partial_clear;
671 bool color_write_disable[4] = { false, false, false, false };
672 if (set_write_disables(irb, ctx->Color.ColorMask[buf], color_write_disable))
673 can_fast_clear = false;
675 if (irb->mt->fast_clear_state == INTEL_FAST_CLEAR_STATE_NO_MCS ||
676 !brw_is_color_fast_clear_compatible(brw, irb->mt, &ctx->Color.ClearColor))
677 can_fast_clear = false;
679 if (can_fast_clear) {
680 /* Record the clear color in the miptree so that it will be
681 * programmed in SURFACE_STATE by later rendering and resolve
684 const bool color_updated = brw_meta_set_fast_clear_color(
685 brw, irb->mt, &ctx->Color.ClearColor);
687 /* If the buffer is already in INTEL_FAST_CLEAR_STATE_CLEAR, the clear
688 * is redundant and can be skipped.
690 if (!color_updated &&
691 irb->mt->fast_clear_state == INTEL_FAST_CLEAR_STATE_CLEAR)
694 /* If the MCS buffer hasn't been allocated yet, we need to allocate
697 if (!irb->mt->mcs_mt) {
698 if (!intel_miptree_alloc_non_msrt_mcs(brw, irb->mt)) {
699 /* MCS allocation failed--probably this will only happen in
700 * out-of-memory conditions. But in any case, try to recover
701 * by falling back to a non-blorp clear technique.
708 intel_miptree_check_level_layer(irb->mt, irb->mt_level, layer);
709 intel_miptree_used_for_rendering(irb->mt);
711 /* We can't setup the blorp_surf until we've allocated the MCS above */
712 struct isl_surf isl_tmp[2];
713 struct brw_blorp_surf surf;
714 unsigned level = irb->mt_level;
715 brw_blorp_surf_for_miptree(brw, &surf, irb->mt, true, &level, isl_tmp);
717 if (can_fast_clear) {
718 DBG("%s (fast) to mt %p level %d layer %d\n", __FUNCTION__,
719 irb->mt, irb->mt_level, irb->mt_layer);
721 blorp_fast_clear(brw, &surf, level, layer, x0, y0, x1, y1);
723 /* Now that the fast clear has occurred, put the buffer in
724 * INTEL_FAST_CLEAR_STATE_CLEAR so that we won't waste time doing
727 irb->mt->fast_clear_state = INTEL_FAST_CLEAR_STATE_CLEAR;
729 DBG("%s (slow) to mt %p level %d layer %d\n", __FUNCTION__,
730 irb->mt, irb->mt_level, irb->mt_layer);
732 union isl_color_value clear_color;
733 memcpy(clear_color.f32, ctx->Color.ClearColor.f, sizeof(float) * 4);
735 blorp_clear(brw, &surf, level, layer, x0, y0, x1, y1,
736 (enum isl_format)brw->render_target_format[format],
737 clear_color, color_write_disable);
739 if (intel_miptree_is_lossless_compressed(brw, irb->mt)) {
740 /* Compressed buffers can be cleared also using normal rep-clear. In
741 * such case they bahave such as if they were drawn using normal 3D
742 * render pipeline, and we simply mark the mcs as dirty.
744 assert(partial_clear);
745 irb->mt->fast_clear_state = INTEL_FAST_CLEAR_STATE_UNRESOLVED;
753 brw_blorp_clear_color(struct brw_context *brw, struct gl_framebuffer *fb,
754 GLbitfield mask, bool partial_clear, bool encode_srgb)
756 for (unsigned buf = 0; buf < fb->_NumColorDrawBuffers; buf++) {
757 struct gl_renderbuffer *rb = fb->_ColorDrawBuffers[buf];
758 struct intel_renderbuffer *irb = intel_renderbuffer(rb);
760 /* Only clear the buffers present in the provided mask */
761 if (((1 << fb->_ColorDrawBufferIndexes[buf]) & mask) == 0)
764 /* If this is an ES2 context or GL_ARB_ES2_compatibility is supported,
765 * the framebuffer can be complete with some attachments missing. In
766 * this case the _ColorDrawBuffers pointer will be NULL.
771 if (fb->MaxNumLayers > 0) {
772 unsigned layer_multiplier =
773 (irb->mt->msaa_layout == INTEL_MSAA_LAYOUT_UMS ||
774 irb->mt->msaa_layout == INTEL_MSAA_LAYOUT_CMS) ?
775 irb->mt->num_samples : 1;
776 unsigned num_layers = irb->layer_count;
777 for (unsigned layer = 0; layer < num_layers; layer++) {
778 if (!do_single_blorp_clear(
779 brw, fb, rb, buf, partial_clear, encode_srgb,
780 irb->mt_layer + layer * layer_multiplier)) {
785 unsigned layer = irb->mt_layer;
786 if (!do_single_blorp_clear(brw, fb, rb, buf, partial_clear,
791 irb->need_downsample = true;
798 brw_blorp_resolve_color(struct brw_context *brw, struct intel_mipmap_tree *mt)
800 DBG("%s to mt %p\n", __FUNCTION__, mt);
802 const mesa_format format = _mesa_get_srgb_format_linear(mt->format);
804 intel_miptree_check_level_layer(mt, 0 /* level */, 0 /* layer */);
805 intel_miptree_used_for_rendering(mt);
807 struct isl_surf isl_tmp[2];
808 struct brw_blorp_surf surf;
810 brw_blorp_surf_for_miptree(brw, &surf, mt, true, &level, isl_tmp);
812 brw_blorp_ccs_resolve(brw, &surf, brw_blorp_to_isl_format(brw, format, true));
814 mt->fast_clear_state = INTEL_FAST_CLEAR_STATE_RESOLVED;
818 gen6_blorp_hiz_exec(struct brw_context *brw, struct intel_mipmap_tree *mt,
819 unsigned int level, unsigned int layer, enum gen6_hiz_op op)
821 intel_miptree_check_level_layer(mt, level, layer);
822 intel_miptree_used_for_rendering(mt);
824 assert(intel_miptree_level_has_hiz(mt, level));
826 struct isl_surf isl_tmp[2];
827 struct brw_blorp_surf surf;
828 brw_blorp_surf_for_miptree(brw, &surf, mt, true, &level, isl_tmp);
830 blorp_gen6_hiz_op(brw, &surf, level, layer, op);
834 * Perform a HiZ or depth resolve operation.
836 * For an overview of HiZ ops, see the following sections of the Sandy Bridge
837 * PRM, Volume 1, Part 2:
838 * - 7.5.3.1 Depth Buffer Clear
839 * - 7.5.3.2 Depth Buffer Resolve
840 * - 7.5.3.3 Hierarchical Depth Buffer Resolve
843 intel_hiz_exec(struct brw_context *brw, struct intel_mipmap_tree *mt,
844 unsigned int level, unsigned int layer, enum gen6_hiz_op op)
846 const char *opname = NULL;
849 case GEN6_HIZ_OP_DEPTH_RESOLVE:
850 opname = "depth resolve";
852 case GEN6_HIZ_OP_HIZ_RESOLVE:
853 opname = "hiz ambiguate";
855 case GEN6_HIZ_OP_DEPTH_CLEAR:
856 opname = "depth clear";
858 case GEN6_HIZ_OP_NONE:
863 DBG("%s %s to mt %p level %d layer %d\n",
864 __func__, opname, mt, level, layer);
867 gen8_hiz_exec(brw, mt, level, layer, op);
869 gen6_blorp_hiz_exec(brw, mt, level, layer, op);