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11 * The above copyright notice and this permission notice (including the next
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25 #include "intel_batchbuffer.h"
26 #include "intel_fbo.h"
28 #include "brw_blorp.h"
29 #include "brw_state.h"
31 #define FILE_DEBUG_FLAG DEBUG_BLORP
33 brw_blorp_mip_info::brw_blorp_mip_info()
44 brw_blorp_surface_info::brw_blorp_surface_info()
45 : map_stencil_as_y_tiled(false),
51 brw_blorp_mip_info::set(struct intel_mipmap_tree *mt,
52 unsigned int level, unsigned int layer)
54 /* Layer is a physical layer, so if this is a 2D multisample array texture
55 * using INTEL_MSAA_LAYOUT_UMS or INTEL_MSAA_LAYOUT_CMS, then it had better
56 * be a multiple of num_samples.
58 if (mt->msaa_layout == INTEL_MSAA_LAYOUT_UMS ||
59 mt->msaa_layout == INTEL_MSAA_LAYOUT_CMS) {
60 assert(layer % mt->num_samples == 0);
63 intel_miptree_check_level_layer(mt, level, layer);
68 this->width = minify(mt->physical_width0, level - mt->first_level);
69 this->height = minify(mt->physical_height0, level - mt->first_level);
71 intel_miptree_get_image_offset(mt, level, layer, &x_offset, &y_offset);
75 brw_blorp_surface_info::set(struct brw_context *brw,
76 struct intel_mipmap_tree *mt,
77 unsigned int level, unsigned int layer,
78 mesa_format format, bool is_render_target)
80 brw_blorp_mip_info::set(mt, level, layer);
81 this->num_samples = mt->num_samples;
82 this->array_layout = mt->array_layout;
83 this->map_stencil_as_y_tiled = false;
84 this->msaa_layout = mt->msaa_layout;
86 if (format == MESA_FORMAT_NONE)
90 case MESA_FORMAT_S_UINT8:
91 /* The miptree is a W-tiled stencil buffer. Surface states can't be set
92 * up for W tiling, so we'll need to use Y tiling and have the WM
93 * program swizzle the coordinates.
95 this->map_stencil_as_y_tiled = true;
96 this->brw_surfaceformat = BRW_SURFACEFORMAT_R8_UNORM;
98 case MESA_FORMAT_Z24_UNORM_X8_UINT:
99 /* It would make sense to use BRW_SURFACEFORMAT_R24_UNORM_X8_TYPELESS
100 * here, but unfortunately it isn't supported as a render target, which
101 * would prevent us from blitting to 24-bit depth.
103 * The miptree consists of 32 bits per pixel, arranged as 24-bit depth
104 * values interleaved with 8 "don't care" bits. Since depth values don't
105 * require any blending, it doesn't matter how we interpret the bit
106 * pattern as long as we copy the right amount of data, so just map it
109 this->brw_surfaceformat = BRW_SURFACEFORMAT_B8G8R8A8_UNORM;
111 case MESA_FORMAT_Z_FLOAT32:
112 this->brw_surfaceformat = BRW_SURFACEFORMAT_R32_FLOAT;
114 case MESA_FORMAT_Z_UNORM16:
115 this->brw_surfaceformat = BRW_SURFACEFORMAT_R16_UNORM;
118 mesa_format linear_format = _mesa_get_srgb_format_linear(format);
119 if (is_render_target) {
120 assert(brw->format_supported_as_render_target[linear_format]);
121 this->brw_surfaceformat = brw->render_target_format[linear_format];
123 this->brw_surfaceformat = brw_format_for_mesa_format(linear_format);
132 * Split x_offset and y_offset into a base offset (in bytes) and a remaining
133 * x/y offset (in pixels). Note: we can't do this by calling
134 * intel_renderbuffer_tile_offsets(), because the offsets may have been
135 * adjusted to account for Y vs. W tiling differences. So we compute it
136 * directly from the adjusted offsets.
139 brw_blorp_surface_info::compute_tile_offsets(uint32_t *tile_x,
140 uint32_t *tile_y) const
142 uint32_t mask_x, mask_y;
144 intel_get_tile_masks(mt->tiling, mt->tr_mode, mt->cpp,
145 map_stencil_as_y_tiled,
148 *tile_x = x_offset & mask_x;
149 *tile_y = y_offset & mask_y;
151 return intel_miptree_get_aligned_offset(mt, x_offset & ~mask_x,
153 map_stencil_as_y_tiled);
157 brw_blorp_params::brw_blorp_params(unsigned num_varyings,
158 unsigned num_draw_buffers,
165 hiz_op(GEN6_HIZ_OP_NONE),
167 num_varyings(num_varyings),
168 num_draw_buffers(num_draw_buffers),
169 num_layers(num_layers)
175 intel_hiz_exec(struct brw_context *brw, struct intel_mipmap_tree *mt,
176 unsigned int level, unsigned int layer, gen6_hiz_op op)
178 const char *opname = NULL;
181 case GEN6_HIZ_OP_DEPTH_RESOLVE:
182 opname = "depth resolve";
184 case GEN6_HIZ_OP_HIZ_RESOLVE:
185 opname = "hiz ambiguate";
187 case GEN6_HIZ_OP_DEPTH_CLEAR:
188 opname = "depth clear";
190 case GEN6_HIZ_OP_NONE:
195 DBG("%s %s to mt %p level %d layer %d\n",
196 __func__, opname, mt, level, layer);
199 gen8_hiz_exec(brw, mt, level, layer, op);
201 brw_hiz_op_params params(mt, level, layer, op);
202 brw_blorp_exec(brw, ¶ms);
209 brw_blorp_exec(struct brw_context *brw, const brw_blorp_params *params)
211 struct gl_context *ctx = &brw->ctx;
212 uint32_t estimated_max_batch_usage = 1500;
213 bool check_aperture_failed_once = false;
215 /* Flush the sampler and render caches. We definitely need to flush the
216 * sampler cache so that we get updated contents from the render cache for
217 * the glBlitFramebuffer() source. Also, we are sometimes warned in the
218 * docs to flush the cache between reinterpretations of the same surface
219 * data with different formats, which blorp does for stencil and depth
222 brw_emit_mi_flush(brw);
225 intel_batchbuffer_require_space(brw, estimated_max_batch_usage, RENDER_RING);
226 intel_batchbuffer_save_state(brw);
227 drm_intel_bo *saved_bo = brw->batch.bo;
228 uint32_t saved_used = USED_BATCH(brw->batch);
229 uint32_t saved_state_batch_offset = brw->batch.state_batch_offset;
233 gen6_blorp_exec(brw, params);
236 gen7_blorp_exec(brw, params);
239 /* BLORP is not supported before Gen6. */
240 unreachable("not reached");
243 /* Make sure we didn't wrap the batch unintentionally, and make sure we
244 * reserved enough space that a wrap will never happen.
246 assert(brw->batch.bo == saved_bo);
247 assert((USED_BATCH(brw->batch) - saved_used) * 4 +
248 (saved_state_batch_offset - brw->batch.state_batch_offset) <
249 estimated_max_batch_usage);
250 /* Shut up compiler warnings on release build */
253 (void)saved_state_batch_offset;
255 /* Check if the blorp op we just did would make our batch likely to fail to
256 * map all the BOs into the GPU at batch exec time later. If so, flush the
257 * batch and try again with nothing else in the batch.
259 if (dri_bufmgr_check_aperture_space(&brw->batch.bo, 1)) {
260 if (!check_aperture_failed_once) {
261 check_aperture_failed_once = true;
262 intel_batchbuffer_reset_to_saved(brw);
263 intel_batchbuffer_flush(brw);
266 int ret = intel_batchbuffer_flush(brw);
267 WARN_ONCE(ret == -ENOSPC,
268 "i965: blorp emit exceeded available aperture space\n");
272 if (unlikely(brw->always_flush_batch))
273 intel_batchbuffer_flush(brw);
275 /* We've smashed all state compared to what the normal 3D pipeline
276 * rendering tracks for GL.
278 brw->ctx.NewDriverState = ~0ull;
279 brw->no_depth_or_stencil = false;
282 /* Flush the sampler cache so any texturing from the destination is
285 brw_emit_mi_flush(brw);
288 brw_hiz_op_params::brw_hiz_op_params(struct intel_mipmap_tree *mt,
295 depth.set(mt, level, layer);
297 /* Align the rectangle primitive to 8x4 pixels.
299 * During fast depth clears, the emitted rectangle primitive must be
300 * aligned to 8x4 pixels. From the Ivybridge PRM, Vol 2 Part 1 Section
301 * 11.5.3.1 Depth Buffer Clear (and the matching section in the Sandybridge
303 * If Number of Multisamples is NUMSAMPLES_1, the rectangle must be
304 * aligned to an 8x4 pixel block relative to the upper left corner
305 * of the depth buffer [...]
307 * For hiz resolves, the rectangle must also be 8x4 aligned. Item
308 * WaHizAmbiguate8x4Aligned from the Haswell workarounds page and the
309 * Ivybridge simulator require the alignment.
311 * To be safe, let's just align the rect for all hiz operations and all
312 * hardware generations.
314 * However, for some miptree slices of a Z24 texture, emitting an 8x4
315 * aligned rectangle that covers the slice may clobber adjacent slices if
316 * we strictly adhered to the texture alignments specified in the PRM. The
317 * Ivybridge PRM, Section "Alignment Unit Size", states that
318 * SURFACE_STATE.Surface_Horizontal_Alignment should be 4 for Z24 surfaces,
319 * not 8. But commit 1f112cc increased the alignment from 4 to 8, which
320 * prevents the clobbering.
322 dst.num_samples = mt->num_samples;
323 if (dst.num_samples > 1) {
324 depth.width = ALIGN(mt->logical_width0, 8);
325 depth.height = ALIGN(mt->logical_height0, 4);
327 depth.width = ALIGN(depth.width, 8);
328 depth.height = ALIGN(depth.height, 4);
334 assert(intel_miptree_level_has_hiz(mt, level));
336 switch (mt->format) {
337 case MESA_FORMAT_Z_UNORM16: depth_format = BRW_DEPTHFORMAT_D16_UNORM; break;
338 case MESA_FORMAT_Z_FLOAT32: depth_format = BRW_DEPTHFORMAT_D32_FLOAT; break;
339 case MESA_FORMAT_Z24_UNORM_X8_UINT: depth_format = BRW_DEPTHFORMAT_D24_UNORM_X8_UINT; break;
340 default: unreachable("not reached");
345 brw_hiz_op_params::get_wm_prog(struct brw_context *brw,
346 brw_blorp_prog_data **prog_data) const