src/mesa/drivers/dri/i965/brw_compiler.c

   1 /*
   2  * Copyright © 2015-2016 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include "brw_compiler.h"
  25 #include "brw_context.h"
  26 #include "compiler/nir/nir.h"
  27 #include "main/errors.h"
  28 #include "util/debug.h"
  29
  30 static void
  31 shader_debug_log_mesa(void *data, const char *fmt, ...)
  32 {
  33    struct brw_context *brw = (struct brw_context *)data;
  34    va_list args;
  35
  36    va_start(args, fmt);
  37    GLuint msg_id = 0;
  38    _mesa_gl_vdebug(&brw->ctx, &msg_id,
  39                    MESA_DEBUG_SOURCE_SHADER_COMPILER,
  40                    MESA_DEBUG_TYPE_OTHER,
  41                    MESA_DEBUG_SEVERITY_NOTIFICATION, fmt, args);
  42    va_end(args);
  43 }
  44
  45 static void
  46 shader_perf_log_mesa(void *data, const char *fmt, ...)
  47 {
  48    struct brw_context *brw = (struct brw_context *)data;
  49
  50    va_list args;
  51    va_start(args, fmt);
  52
  53    if (unlikely(INTEL_DEBUG & DEBUG_PERF)) {
  54       va_list args_copy;
  55       va_copy(args_copy, args);
  56       vfprintf(stderr, fmt, args_copy);
  57       va_end(args_copy);
  58    }
  59
  60    if (brw->perf_debug) {
  61       GLuint msg_id = 0;
  62       _mesa_gl_vdebug(&brw->ctx, &msg_id,
  63                       MESA_DEBUG_SOURCE_SHADER_COMPILER,
  64                       MESA_DEBUG_TYPE_PERFORMANCE,
  65                       MESA_DEBUG_SEVERITY_MEDIUM, fmt, args);
  66    }
  67    va_end(args);
  68 }
  69
  70 #define COMMON_OPTIONS                                                        \
  71    /* In order to help allow for better CSE at the NIR level we tell NIR to   \
  72     * split all ffma instructions during opt_algebraic and we then re-combine \
  73     * them as a later step.                                                   \
  74     */                                                                        \
  75    .lower_ffma = true,                                                        \
  76    .lower_sub = true,                                                         \
  77    .lower_fdiv = true,                                                        \
  78    .lower_scmp = true,                                                        \
  79    .lower_fmod = true,                                                        \
  80    .lower_bitfield_extract = true,                                            \
  81    .lower_bitfield_insert = true,                                             \
  82    .lower_uadd_carry = true,                                                  \
  83    .lower_usub_borrow = true,                                                 \
  84    .lower_fdiv = true,                                                        \
  85    .native_integers = true,                                                   \
  86    .vertex_id_zero_based = true
  87
  88 static const struct nir_shader_compiler_options scalar_nir_options = {
  89    COMMON_OPTIONS,
  90    .lower_pack_half_2x16 = true,
  91    .lower_pack_snorm_2x16 = true,
  92    .lower_pack_snorm_4x8 = true,
  93    .lower_pack_unorm_2x16 = true,
  94    .lower_pack_unorm_4x8 = true,
  95    .lower_unpack_half_2x16 = true,
  96    .lower_unpack_snorm_2x16 = true,
  97    .lower_unpack_snorm_4x8 = true,
  98    .lower_unpack_unorm_2x16 = true,
  99    .lower_unpack_unorm_4x8 = true,
 100 };
 101
 102 static const struct nir_shader_compiler_options vector_nir_options = {
 103    COMMON_OPTIONS,
 104
 105    /* In the vec4 backend, our dpN instruction replicates its result to all the
 106     * components of a vec4.  We would like NIR to give us replicated fdot
 107     * instructions because it can optimize better for us.
 108     */
 109    .fdot_replicates = true,
 110
 111    /* Prior to Gen6, there are no three source operations for SIMD4x2. */
 112    .lower_flrp = true,
 113
 114    .lower_pack_snorm_2x16 = true,
 115    .lower_pack_unorm_2x16 = true,
 116    .lower_unpack_snorm_2x16 = true,
 117    .lower_unpack_unorm_2x16 = true,
 118    .lower_extract_byte = true,
 119    .lower_extract_word = true,
 120 };
 121
 122 static const struct nir_shader_compiler_options vector_nir_options_gen6 = {
 123    COMMON_OPTIONS,
 124
 125    /* In the vec4 backend, our dpN instruction replicates its result to all the
 126     * components of a vec4.  We would like NIR to give us replicated fdot
 127     * instructions because it can optimize better for us.
 128     */
 129    .fdot_replicates = true,
 130
 131    .lower_pack_snorm_2x16 = true,
 132    .lower_pack_unorm_2x16 = true,
 133    .lower_unpack_snorm_2x16 = true,
 134    .lower_unpack_unorm_2x16 = true,
 135    .lower_extract_byte = true,
 136    .lower_extract_word = true,
 137 };
 138
 139 struct brw_compiler *
 140 brw_compiler_create(void *mem_ctx, const struct brw_device_info *devinfo)
 141 {
 142    struct brw_compiler *compiler = rzalloc(mem_ctx, struct brw_compiler);
 143
 144    compiler->devinfo = devinfo;
 145    compiler->shader_debug_log = shader_debug_log_mesa;
 146    compiler->shader_perf_log = shader_perf_log_mesa;
 147
 148    brw_fs_alloc_reg_sets(compiler);
 149    brw_vec4_alloc_reg_set(compiler);
 150
 151    compiler->precise_trig = env_var_as_boolean("INTEL_PRECISE_TRIG", false);
 152
 153    compiler->scalar_stage[MESA_SHADER_VERTEX] =
 154       devinfo->gen >= 8 && !(INTEL_DEBUG & DEBUG_VEC4VS);
 155    compiler->scalar_stage[MESA_SHADER_TESS_CTRL] = false;
 156    compiler->scalar_stage[MESA_SHADER_TESS_EVAL] =
 157       devinfo->gen >= 8 && env_var_as_boolean("INTEL_SCALAR_TES", true);
 158    compiler->scalar_stage[MESA_SHADER_GEOMETRY] =
 159       devinfo->gen >= 8 && env_var_as_boolean("INTEL_SCALAR_GS", true);
 160    compiler->scalar_stage[MESA_SHADER_FRAGMENT] = true;
 161    compiler->scalar_stage[MESA_SHADER_COMPUTE] = true;
 162
 163    /* We want the GLSL compiler to emit code that uses condition codes */
 164    for (int i = 0; i < MESA_SHADER_STAGES; i++) {
 165       compiler->glsl_compiler_options[i].MaxUnrollIterations = 32;
 166       compiler->glsl_compiler_options[i].MaxIfDepth =
 167          devinfo->gen < 6 ? 16 : UINT_MAX;
 168
 169       compiler->glsl_compiler_options[i].EmitNoNoise = true;
 170       compiler->glsl_compiler_options[i].EmitNoMainReturn = true;
 171       compiler->glsl_compiler_options[i].EmitNoIndirectInput = true;
 172       compiler->glsl_compiler_options[i].EmitNoIndirectUniform = false;
 173       compiler->glsl_compiler_options[i].LowerClipDistance = true;
 174
 175       bool is_scalar = compiler->scalar_stage[i];
 176
 177       compiler->glsl_compiler_options[i].EmitNoIndirectOutput = is_scalar;
 178       compiler->glsl_compiler_options[i].EmitNoIndirectTemp = is_scalar;
 179       compiler->glsl_compiler_options[i].OptimizeForAOS = !is_scalar;
 180
 181       /* !ARB_gpu_shader5 */
 182       if (devinfo->gen < 7)
 183          compiler->glsl_compiler_options[i].EmitNoIndirectSampler = true;
 184
 185       if (is_scalar) {
 186          compiler->glsl_compiler_options[i].NirOptions = &scalar_nir_options;
 187       } else {
 188          compiler->glsl_compiler_options[i].NirOptions =
 189             devinfo->gen < 6 ? &vector_nir_options : &vector_nir_options_gen6;
 190       }
 191
 192       compiler->glsl_compiler_options[i].LowerBufferInterfaceBlocks = true;
 193    }
 194
 195    compiler->glsl_compiler_options[MESA_SHADER_TESS_CTRL].EmitNoIndirectInput = false;
 196    compiler->glsl_compiler_options[MESA_SHADER_TESS_EVAL].EmitNoIndirectInput = false;
 197
 198    if (compiler->scalar_stage[MESA_SHADER_GEOMETRY])
 199       compiler->glsl_compiler_options[MESA_SHADER_GEOMETRY].EmitNoIndirectInput = false;
 200
 201    compiler->glsl_compiler_options[MESA_SHADER_COMPUTE]
 202       .LowerShaderSharedVariables = true;
 203
 204    return compiler;
 205 }