2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics to
4 develop this 3D driver.
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **********************************************************************/
29 * Keith Whitwell <keithw@vmware.com>
33 #ifndef BRWCONTEXT_INC
34 #define BRWCONTEXT_INC
38 #include "main/imports.h"
39 #include "main/macros.h"
41 #include "main/mtypes.h"
42 #include "brw_structs.h"
43 #include "intel_aub.h"
44 #include "program/prog_parameter.h"
48 /* Evil hack for using libdrm in a c++ compiler. */
53 #include <intel_bufmgr.h>
63 #include "intel_debug.h"
64 #include "intel_screen.h"
65 #include "intel_tex_obj.h"
66 #include "intel_resolve_map.h"
70 * URB - uniform resource buffer. A mid-sized buffer which is
71 * partitioned between the fixed function units and used for passing
72 * values (vertices, primitives, constants) between them.
74 * CURBE - constant URB entry. An urb region (entry) used to hold
75 * constant values which the fixed function units can be instructed to
76 * preload into the GRF when spawning a thread.
78 * VUE - vertex URB entry. An urb entry holding a vertex and usually
79 * a vertex header. The header contains control information and
80 * things like primitive type, Begin/end flags and clip codes.
82 * PUE - primitive URB entry. An urb entry produced by the setup (SF)
83 * unit holding rasterization and interpolation parameters.
85 * GRF - general register file. One of several register files
86 * addressable by programmed threads. The inputs (r0, payload, curbe,
87 * urb) of the thread are preloaded to this area before the thread is
88 * spawned. The registers are individually 8 dwords wide and suitable
89 * for general usage. Registers holding thread input values are not
90 * special and may be overwritten.
92 * MRF - message register file. Threads communicate (and terminate)
93 * by sending messages. Message parameters are placed in contiguous
94 * MRF registers. All program output is via these messages. URB
95 * entries are populated by sending a message to the shared URB
96 * function containing the new data, together with a control word,
97 * often an unmodified copy of R0.
99 * R0 - GRF register 0. Typically holds control information used when
100 * sending messages to other threads.
102 * EU or GEN4 EU: The name of the programmable subsystem of the
103 * i965 hardware. Threads are executed by the EU, the registers
104 * described above are part of the EU architecture.
106 * Fixed function units:
108 * CS - Command streamer. Notional first unit, little software
109 * interaction. Holds the URB entries used for constant data, ie the
112 * VF/VS - Vertex Fetch / Vertex Shader. The fixed function part of
113 * this unit is responsible for pulling vertices out of vertex buffers
114 * in vram and injecting them into the processing pipe as VUEs. If
115 * enabled, it first passes them to a VS thread which is a good place
116 * for the driver to implement any active vertex shader.
118 * GS - Geometry Shader. This corresponds to a new DX10 concept. If
119 * enabled, incoming strips etc are passed to GS threads in individual
120 * line/triangle/point units. The GS thread may perform arbitary
121 * computation and emit whatever primtives with whatever vertices it
122 * chooses. This makes GS an excellent place to implement GL's
123 * unfilled polygon modes, though of course it is capable of much
124 * more. Additionally, GS is used to translate away primitives not
125 * handled by latter units, including Quads and Lineloops.
127 * CS - Clipper. Mesa's clipping algorithms are imported to run on
128 * this unit. The fixed function part performs cliptesting against
129 * the 6 fixed clipplanes and makes descisions on whether or not the
130 * incoming primitive needs to be passed to a thread for clipping.
131 * User clip planes are handled via cooperation with the VS thread.
133 * SF - Strips Fans or Setup: Triangles are prepared for
134 * rasterization. Interpolation coefficients are calculated.
135 * Flatshading and two-side lighting usually performed here.
137 * WM - Windower. Interpolation of vertex attributes performed here.
138 * Fragment shader implemented here. SIMD aspects of EU taken full
139 * advantage of, as pixels are processed in blocks of 16.
141 * CC - Color Calculator. No EU threads associated with this unit.
142 * Handles blending and (presumably) depth and stencil testing.
147 struct brw_vs_prog_key;
148 struct brw_vue_prog_key;
149 struct brw_wm_prog_key;
150 struct brw_wm_prog_data;
151 struct brw_cs_prog_key;
152 struct brw_cs_prog_data;
156 BRW_COMPUTE_PIPELINE,
163 BRW_CACHE_BLORP_BLIT_PROG,
166 BRW_CACHE_FF_GS_PROG,
175 /* brw_cache_ids must come first - see brw_state_cache.c */
176 BRW_STATE_URB_FENCE = BRW_MAX_CACHE,
177 BRW_STATE_FRAGMENT_PROGRAM,
178 BRW_STATE_GEOMETRY_PROGRAM,
179 BRW_STATE_VERTEX_PROGRAM,
180 BRW_STATE_CURBE_OFFSETS,
181 BRW_STATE_REDUCED_PRIMITIVE,
186 BRW_STATE_VS_BINDING_TABLE,
187 BRW_STATE_GS_BINDING_TABLE,
188 BRW_STATE_PS_BINDING_TABLE,
192 BRW_STATE_INDEX_BUFFER,
193 BRW_STATE_VS_CONSTBUF,
194 BRW_STATE_GS_CONSTBUF,
195 BRW_STATE_PROGRAM_CACHE,
196 BRW_STATE_STATE_BASE_ADDRESS,
197 BRW_STATE_VUE_MAP_GEOM_OUT,
198 BRW_STATE_TRANSFORM_FEEDBACK,
199 BRW_STATE_RASTERIZER_DISCARD,
201 BRW_STATE_UNIFORM_BUFFER,
202 BRW_STATE_ATOMIC_BUFFER,
203 BRW_STATE_IMAGE_UNITS,
204 BRW_STATE_META_IN_PROGRESS,
205 BRW_STATE_INTERPOLATION_MAP,
206 BRW_STATE_PUSH_CONSTANT_ALLOCATION,
207 BRW_STATE_NUM_SAMPLES,
208 BRW_STATE_TEXTURE_BUFFER,
209 BRW_STATE_GEN4_UNIT_STATE,
213 BRW_STATE_SAMPLER_STATE_TABLE,
214 BRW_STATE_VS_ATTRIB_WORKAROUNDS,
215 BRW_STATE_COMPUTE_PROGRAM,
216 BRW_STATE_CS_WORK_GROUPS,
221 * BRW_NEW_*_PROG_DATA and BRW_NEW_*_PROGRAM are similar, but distinct.
223 * BRW_NEW_*_PROGRAM relates to the gl_shader_program/gl_program structures.
224 * When the currently bound shader program differs from the previous draw
225 * call, these will be flagged. They cover brw->{stage}_program and
226 * ctx->{Stage}Program->_Current.
228 * BRW_NEW_*_PROG_DATA is flagged when the effective shaders change, from a
229 * driver perspective. Even if the same shader is bound at the API level,
230 * we may need to switch between multiple versions of that shader to handle
231 * changes in non-orthagonal state.
233 * Additionally, multiple shader programs may have identical vertex shaders
234 * (for example), or compile down to the same code in the backend. We combine
235 * those into a single program cache entry.
237 * BRW_NEW_*_PROG_DATA occurs when switching program cache entries, which
238 * covers the brw_*_prog_data structures, and brw->*.prog_offset.
240 #define BRW_NEW_FS_PROG_DATA (1ull << BRW_CACHE_FS_PROG)
241 /* XXX: The BRW_NEW_BLORP_BLIT_PROG_DATA dirty bit is unused (as BLORP doesn't
242 * use the normal state upload paths), but the cache is still used. To avoid
243 * polluting the brw_state_cache code with special cases, we retain the dirty
244 * bit for now. It should eventually be removed.
246 #define BRW_NEW_BLORP_BLIT_PROG_DATA (1ull << BRW_CACHE_BLORP_BLIT_PROG)
247 #define BRW_NEW_SF_PROG_DATA (1ull << BRW_CACHE_SF_PROG)
248 #define BRW_NEW_VS_PROG_DATA (1ull << BRW_CACHE_VS_PROG)
249 #define BRW_NEW_FF_GS_PROG_DATA (1ull << BRW_CACHE_FF_GS_PROG)
250 #define BRW_NEW_GS_PROG_DATA (1ull << BRW_CACHE_GS_PROG)
251 #define BRW_NEW_CLIP_PROG_DATA (1ull << BRW_CACHE_CLIP_PROG)
252 #define BRW_NEW_CS_PROG_DATA (1ull << BRW_CACHE_CS_PROG)
253 #define BRW_NEW_URB_FENCE (1ull << BRW_STATE_URB_FENCE)
254 #define BRW_NEW_FRAGMENT_PROGRAM (1ull << BRW_STATE_FRAGMENT_PROGRAM)
255 #define BRW_NEW_GEOMETRY_PROGRAM (1ull << BRW_STATE_GEOMETRY_PROGRAM)
256 #define BRW_NEW_VERTEX_PROGRAM (1ull << BRW_STATE_VERTEX_PROGRAM)
257 #define BRW_NEW_CURBE_OFFSETS (1ull << BRW_STATE_CURBE_OFFSETS)
258 #define BRW_NEW_REDUCED_PRIMITIVE (1ull << BRW_STATE_REDUCED_PRIMITIVE)
259 #define BRW_NEW_PRIMITIVE (1ull << BRW_STATE_PRIMITIVE)
260 #define BRW_NEW_CONTEXT (1ull << BRW_STATE_CONTEXT)
261 #define BRW_NEW_PSP (1ull << BRW_STATE_PSP)
262 #define BRW_NEW_SURFACES (1ull << BRW_STATE_SURFACES)
263 #define BRW_NEW_VS_BINDING_TABLE (1ull << BRW_STATE_VS_BINDING_TABLE)
264 #define BRW_NEW_GS_BINDING_TABLE (1ull << BRW_STATE_GS_BINDING_TABLE)
265 #define BRW_NEW_PS_BINDING_TABLE (1ull << BRW_STATE_PS_BINDING_TABLE)
266 #define BRW_NEW_INDICES (1ull << BRW_STATE_INDICES)
267 #define BRW_NEW_VERTICES (1ull << BRW_STATE_VERTICES)
269 * Used for any batch entry with a relocated pointer that will be used
270 * by any 3D rendering.
272 #define BRW_NEW_BATCH (1ull << BRW_STATE_BATCH)
273 /** \see brw.state.depth_region */
274 #define BRW_NEW_INDEX_BUFFER (1ull << BRW_STATE_INDEX_BUFFER)
275 #define BRW_NEW_VS_CONSTBUF (1ull << BRW_STATE_VS_CONSTBUF)
276 #define BRW_NEW_GS_CONSTBUF (1ull << BRW_STATE_GS_CONSTBUF)
277 #define BRW_NEW_PROGRAM_CACHE (1ull << BRW_STATE_PROGRAM_CACHE)
278 #define BRW_NEW_STATE_BASE_ADDRESS (1ull << BRW_STATE_STATE_BASE_ADDRESS)
279 #define BRW_NEW_VUE_MAP_GEOM_OUT (1ull << BRW_STATE_VUE_MAP_GEOM_OUT)
280 #define BRW_NEW_TRANSFORM_FEEDBACK (1ull << BRW_STATE_TRANSFORM_FEEDBACK)
281 #define BRW_NEW_RASTERIZER_DISCARD (1ull << BRW_STATE_RASTERIZER_DISCARD)
282 #define BRW_NEW_STATS_WM (1ull << BRW_STATE_STATS_WM)
283 #define BRW_NEW_UNIFORM_BUFFER (1ull << BRW_STATE_UNIFORM_BUFFER)
284 #define BRW_NEW_ATOMIC_BUFFER (1ull << BRW_STATE_ATOMIC_BUFFER)
285 #define BRW_NEW_IMAGE_UNITS (1ull << BRW_STATE_IMAGE_UNITS)
286 #define BRW_NEW_META_IN_PROGRESS (1ull << BRW_STATE_META_IN_PROGRESS)
287 #define BRW_NEW_INTERPOLATION_MAP (1ull << BRW_STATE_INTERPOLATION_MAP)
288 #define BRW_NEW_PUSH_CONSTANT_ALLOCATION (1ull << BRW_STATE_PUSH_CONSTANT_ALLOCATION)
289 #define BRW_NEW_NUM_SAMPLES (1ull << BRW_STATE_NUM_SAMPLES)
290 #define BRW_NEW_TEXTURE_BUFFER (1ull << BRW_STATE_TEXTURE_BUFFER)
291 #define BRW_NEW_GEN4_UNIT_STATE (1ull << BRW_STATE_GEN4_UNIT_STATE)
292 #define BRW_NEW_CC_VP (1ull << BRW_STATE_CC_VP)
293 #define BRW_NEW_SF_VP (1ull << BRW_STATE_SF_VP)
294 #define BRW_NEW_CLIP_VP (1ull << BRW_STATE_CLIP_VP)
295 #define BRW_NEW_SAMPLER_STATE_TABLE (1ull << BRW_STATE_SAMPLER_STATE_TABLE)
296 #define BRW_NEW_VS_ATTRIB_WORKAROUNDS (1ull << BRW_STATE_VS_ATTRIB_WORKAROUNDS)
297 #define BRW_NEW_COMPUTE_PROGRAM (1ull << BRW_STATE_COMPUTE_PROGRAM)
298 #define BRW_NEW_CS_WORK_GROUPS (1ull << BRW_STATE_CS_WORK_GROUPS)
300 struct brw_state_flags {
301 /** State update flags signalled by mesa internals */
304 * State update flags signalled as the result of brw_tracked_state updates
309 /** Subclass of Mesa vertex program */
310 struct brw_vertex_program {
311 struct gl_vertex_program program;
316 /** Subclass of Mesa geometry program */
317 struct brw_geometry_program {
318 struct gl_geometry_program program;
319 unsigned id; /**< serial no. to identify geom progs, never re-used */
323 /** Subclass of Mesa fragment program */
324 struct brw_fragment_program {
325 struct gl_fragment_program program;
326 GLuint id; /**< serial no. to identify frag progs, never re-used */
330 /** Subclass of Mesa compute program */
331 struct brw_compute_program {
332 struct gl_compute_program program;
333 unsigned id; /**< serial no. to identify compute progs, never re-used */
338 struct gl_shader base;
343 /* Note: If adding fields that need anything besides a normal memcmp() for
344 * comparing them, be sure to go fix brw_stage_prog_data_compare().
346 struct brw_stage_prog_data {
348 /** size of our binding table. */
352 * surface indices for the various groups of surfaces
354 uint32_t pull_constants_start;
355 uint32_t texture_start;
356 uint32_t gather_texture_start;
359 uint32_t image_start;
360 uint32_t shader_time_start;
364 GLuint nr_params; /**< number of float params/constants */
365 GLuint nr_pull_params;
366 unsigned nr_image_params;
368 unsigned curb_read_length;
369 unsigned total_scratch;
372 * Register where the thread expects to find input data from the URB
373 * (typically uniforms, followed by vertex or fragment attributes).
375 unsigned dispatch_grf_start_reg;
377 bool use_alt_mode; /**< Use ALT floating point mode? Otherwise, IEEE. */
379 /* Pointers to tracked values (only valid once
380 * _mesa_load_state_parameters has been called at runtime).
382 * These must be the last fields of the struct (see
383 * brw_stage_prog_data_compare()).
385 const gl_constant_value **param;
386 const gl_constant_value **pull_param;
389 * Image metadata passed to the shader as uniforms. This is deliberately
390 * ignored by brw_stage_prog_data_compare() because its contents don't have
391 * any influence on program compilation.
393 struct brw_image_param *image_param;
397 * Image metadata structure as laid out in the shader parameter
398 * buffer. Entries have to be 16B-aligned for the vec4 back-end to be
399 * able to use them. That's okay because the padding and any unused
400 * entries [most of them except when we're doing untyped surface
401 * access] will be removed by the uniform packing pass.
403 #define BRW_IMAGE_PARAM_SURFACE_IDX_OFFSET 0
404 #define BRW_IMAGE_PARAM_OFFSET_OFFSET 4
405 #define BRW_IMAGE_PARAM_SIZE_OFFSET 8
406 #define BRW_IMAGE_PARAM_STRIDE_OFFSET 12
407 #define BRW_IMAGE_PARAM_TILING_OFFSET 16
408 #define BRW_IMAGE_PARAM_SWIZZLING_OFFSET 20
409 #define BRW_IMAGE_PARAM_SIZE 24
411 struct brw_image_param {
412 /** Surface binding table index. */
413 uint32_t surface_idx;
415 /** Offset applied to the X and Y surface coordinates. */
418 /** Surface X, Y and Z dimensions. */
421 /** X-stride in bytes, Y-stride in pixels, horizontal slice stride in
422 * pixels, vertical slice stride in pixels.
426 /** Log2 of the tiling modulus in the X, Y and Z dimension. */
430 * Right shift to apply for bit 6 address swizzling. Two different
431 * swizzles can be specified and will be applied one after the other. The
432 * resulting address will be:
434 * addr' = addr ^ ((1 << 6) & ((addr >> swizzling[0]) ^
435 * (addr >> swizzling[1])))
437 * Use \c 0xff if any of the swizzles is not required.
439 uint32_t swizzling[2];
442 /* Data about a particular attempt to compile a program. Note that
443 * there can be many of these, each in a different GL state
444 * corresponding to a different brw_wm_prog_key struct, with different
447 * Note: brw_wm_prog_data_compare() must be updated when adding fields to this
450 struct brw_wm_prog_data {
451 struct brw_stage_prog_data base;
453 GLuint num_varying_inputs;
455 GLuint dispatch_grf_start_reg_16;
457 GLuint reg_blocks_16;
461 * surface indices the WM-specific surfaces
463 uint32_t render_target_start;
467 uint8_t computed_depth_mode;
469 bool early_fragment_tests;
472 bool uses_pos_offset;
476 uint32_t prog_offset_16;
479 * Mask of which interpolation modes are required by the fragment shader.
480 * Used in hardware setup on gen6+.
482 uint32_t barycentric_interp_modes;
485 * Map from gl_varying_slot to the position within the FS setup data
486 * payload where the varying's attribute vertex deltas should be delivered.
487 * For varying slots that are not used by the FS, the value is -1.
489 int urb_setup[VARYING_SLOT_MAX];
492 /* Note: brw_cs_prog_data_compare() must be updated when adding fields to this
495 struct brw_cs_prog_data {
496 struct brw_stage_prog_data base;
498 GLuint dispatch_grf_start_reg_16;
499 unsigned local_size[3];
502 bool uses_num_work_groups;
506 * surface indices the CS-specific surfaces
508 uint32_t work_groups_start;
514 * Enum representing the i965-specific vertex results that don't correspond
515 * exactly to any element of gl_varying_slot. The values of this enum are
516 * assigned such that they don't conflict with gl_varying_slot.
520 BRW_VARYING_SLOT_NDC = VARYING_SLOT_MAX,
521 BRW_VARYING_SLOT_PAD,
523 * Technically this is not a varying but just a placeholder that
524 * compile_sf_prog() inserts into its VUE map to cause the gl_PointCoord
525 * builtin variable to be compiled correctly. see compile_sf_prog() for
528 BRW_VARYING_SLOT_PNTC,
529 BRW_VARYING_SLOT_COUNT
534 * Data structure recording the relationship between the gl_varying_slot enum
535 * and "slots" within the vertex URB entry (VUE). A "slot" is defined as a
536 * single octaword within the VUE (128 bits).
538 * Note that each BRW register contains 256 bits (2 octawords), so when
539 * accessing the VUE in URB_NOSWIZZLE mode, each register corresponds to two
540 * consecutive VUE slots. When accessing the VUE in URB_INTERLEAVED mode (as
541 * in a vertex shader), each register corresponds to a single VUE slot, since
542 * it contains data for two separate vertices.
546 * Bitfield representing all varying slots that are (a) stored in this VUE
547 * map, and (b) actually written by the shader. Does not include any of
548 * the additional varying slots defined in brw_varying_slot.
550 GLbitfield64 slots_valid;
553 * Is this VUE map for a separate shader pipeline?
555 * Separable programs (GL_ARB_separate_shader_objects) can be mixed and matched
556 * without the linker having a chance to dead code eliminate unused varyings.
558 * This means that we have to use a fixed slot layout, based on the output's
559 * location field, rather than assigning slots in a compact contiguous block.
564 * Map from gl_varying_slot value to VUE slot. For gl_varying_slots that are
565 * not stored in a slot (because they are not written, or because
566 * additional processing is applied before storing them in the VUE), the
569 signed char varying_to_slot[BRW_VARYING_SLOT_COUNT];
572 * Map from VUE slot to gl_varying_slot value. For slots that do not
573 * directly correspond to a gl_varying_slot, the value comes from
576 * For slots that are not in use, the value is BRW_VARYING_SLOT_COUNT (this
577 * simplifies code that uses the value stored in slot_to_varying to
578 * create a bit mask).
580 signed char slot_to_varying[BRW_VARYING_SLOT_COUNT];
583 * Total number of VUE slots in use
589 * Convert a VUE slot number into a byte offset within the VUE.
591 static inline GLuint brw_vue_slot_to_offset(GLuint slot)
597 * Convert a vertex output (brw_varying_slot) into a byte offset within the
600 static inline GLuint brw_varying_to_offset(struct brw_vue_map *vue_map,
603 return brw_vue_slot_to_offset(vue_map->varying_to_slot[varying]);
606 void brw_compute_vue_map(const struct brw_device_info *devinfo,
607 struct brw_vue_map *vue_map,
608 GLbitfield64 slots_valid,
609 bool separate_shader);
613 * Bitmask indicating which fragment shader inputs represent varyings (and
614 * hence have to be delivered to the fragment shader by the SF/SBE stage).
616 #define BRW_FS_VARYING_INPUT_MASK \
617 (BITFIELD64_RANGE(0, VARYING_SLOT_MAX) & \
618 ~VARYING_BIT_POS & ~VARYING_BIT_FACE)
622 * Mapping of VUE map slots to interpolation modes.
624 struct interpolation_mode_map {
625 unsigned char mode[BRW_VARYING_SLOT_COUNT];
628 static inline bool brw_any_flat_varyings(struct interpolation_mode_map *map)
630 for (int i = 0; i < BRW_VARYING_SLOT_COUNT; i++)
631 if (map->mode[i] == INTERP_QUALIFIER_FLAT)
637 static inline bool brw_any_noperspective_varyings(struct interpolation_mode_map *map)
639 for (int i = 0; i < BRW_VARYING_SLOT_COUNT; i++)
640 if (map->mode[i] == INTERP_QUALIFIER_NOPERSPECTIVE)
647 struct brw_sf_prog_data {
648 GLuint urb_read_length;
651 /* Each vertex may have upto 12 attributes, 4 components each,
652 * except WPOS which requires only 2. (11*4 + 2) == 44 ==> 11
655 * Actually we use 4 for each, so call it 12 rows.
657 GLuint urb_entry_size;
662 * We always program SF to start reading at an offset of 1 (2 varying slots)
663 * from the start of the vertex URB entry. This causes it to skip:
664 * - VARYING_SLOT_PSIZ and BRW_VARYING_SLOT_NDC on gen4-5
665 * - VARYING_SLOT_PSIZ and VARYING_SLOT_POS on gen6+
667 #define BRW_SF_URB_ENTRY_READ_OFFSET 1
670 struct brw_clip_prog_data {
671 GLuint curb_read_length; /* user planes? */
673 GLuint urb_read_length;
677 struct brw_ff_gs_prog_data {
678 GLuint urb_read_length;
682 * Gen6 transform feedback: Amount by which the streaming vertex buffer
683 * indices should be incremented each time the GS is invoked.
685 unsigned svbi_postincrement_value;
688 enum shader_dispatch_mode {
689 DISPATCH_MODE_4X1_SINGLE = 0,
690 DISPATCH_MODE_4X2_DUAL_INSTANCE = 1,
691 DISPATCH_MODE_4X2_DUAL_OBJECT = 2,
692 DISPATCH_MODE_SIMD8 = 3,
695 /* Note: brw_vue_prog_data_compare() must be updated when adding fields to
698 struct brw_vue_prog_data {
699 struct brw_stage_prog_data base;
700 struct brw_vue_map vue_map;
702 GLuint urb_read_length;
705 /* Used for calculating urb partitions. In the VS, this is the size of the
706 * URB entry used for both input and output to the thread. In the GS, this
707 * is the size of the URB entry used for output.
709 GLuint urb_entry_size;
711 enum shader_dispatch_mode dispatch_mode;
715 /* Note: brw_vs_prog_data_compare() must be updated when adding fields to this
718 struct brw_vs_prog_data {
719 struct brw_vue_prog_data base;
721 GLbitfield64 inputs_read;
724 bool uses_instanceid;
727 /** Number of texture sampler units */
728 #define BRW_MAX_TEX_UNIT 32
730 /** Max number of render targets in a shader */
731 #define BRW_MAX_DRAW_BUFFERS 8
733 /** Max number of atomic counter buffer objects in a shader */
734 #define BRW_MAX_ABO 16
736 /** Max number of image uniforms in a shader */
737 #define BRW_MAX_IMAGES 32
740 * Max number of binding table entries used for stream output.
742 * From the OpenGL 3.0 spec, table 6.44 (Transform Feedback State), the
743 * minimum value of MAX_TRANSFORM_FEEDBACK_INTERLEAVED_COMPONENTS is 64.
745 * On Gen6, the size of transform feedback data is limited not by the number
746 * of components but by the number of binding table entries we set aside. We
747 * use one binding table entry for a float, one entry for a vector, and one
748 * entry per matrix column. Since the only way we can communicate our
749 * transform feedback capabilities to the client is via
750 * MAX_TRANSFORM_FEEDBACK_INTERLEAVED_COMPONENTS, we need to plan for the
751 * worst case, in which all the varyings are floats, so we use up one binding
752 * table entry per component. Therefore we need to set aside at least 64
753 * binding table entries for use by transform feedback.
755 * Note: since we don't currently pack varyings, it is currently impossible
756 * for the client to actually use up all of these binding table entries--if
757 * all of their varyings were floats, they would run out of varying slots and
758 * fail to link. But that's a bug, so it seems prudent to go ahead and
759 * allocate the number of binding table entries we will need once the bug is
762 #define BRW_MAX_SOL_BINDINGS 64
764 /** Maximum number of actual buffers used for stream output */
765 #define BRW_MAX_SOL_BUFFERS 4
767 #define BRW_MAX_SURFACES (BRW_MAX_DRAW_BUFFERS + \
768 BRW_MAX_TEX_UNIT * 2 + /* normal, gather */ \
772 2 + /* shader time, pull constants */ \
773 1 /* cs num work groups */)
775 #define SURF_INDEX_GEN6_SOL_BINDING(t) (t)
777 /* Note: brw_gs_prog_data_compare() must be updated when adding fields to
780 struct brw_gs_prog_data
782 struct brw_vue_prog_data base;
785 * Size of an output vertex, measured in HWORDS (32 bytes).
787 unsigned output_vertex_size_hwords;
789 unsigned output_topology;
792 * Size of the control data (cut bits or StreamID bits), in hwords (32
793 * bytes). 0 if there is no control data.
795 unsigned control_data_header_size_hwords;
798 * Format of the control data (either GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_SID
799 * if the control data is StreamID bits, or
800 * GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_CUT if the control data is cut bits).
801 * Ignored if control_data_header_size is 0.
803 unsigned control_data_format;
805 bool include_primitive_id;
808 * The number of vertices emitted, if constant - otherwise -1.
810 int static_vertex_count;
815 * Gen6 transform feedback enabled flag.
817 bool gen6_xfb_enabled;
820 * Gen6: Provoking vertex convention for odd-numbered triangles
826 * Gen6: Number of varyings that are output to transform feedback.
828 GLuint num_transform_feedback_bindings:7; /* 0-BRW_MAX_SOL_BINDINGS */
831 * Gen6: Map from the index of a transform feedback binding table entry to the
832 * gl_varying_slot that should be streamed out through that binding table
835 unsigned char transform_feedback_bindings[BRW_MAX_SOL_BINDINGS];
838 * Gen6: Map from the index of a transform feedback binding table entry to the
839 * swizzles that should be used when streaming out data through that
840 * binding table entry.
842 unsigned char transform_feedback_swizzles[BRW_MAX_SOL_BINDINGS];
846 * Stride in bytes between shader_time entries.
848 * We separate entries by a cacheline to reduce traffic between EUs writing to
851 #define SHADER_TIME_STRIDE 64
853 struct brw_cache_item {
855 * Effectively part of the key, cache_id identifies what kind of state
856 * buffer is involved, and also which dirty flag should set.
858 enum brw_cache_id cache_id;
859 /** 32-bit hash of the key data */
861 GLuint key_size; /* for variable-sized keys */
868 struct brw_cache_item *next;
872 typedef bool (*cache_aux_compare_func)(const void *a, const void *b);
873 typedef void (*cache_aux_free_func)(const void *aux);
876 struct brw_context *brw;
878 struct brw_cache_item **items;
880 GLuint size, n_items;
882 uint32_t next_offset;
886 * Optional functions used in determining whether the prog_data for a new
887 * cache item matches an existing cache item (in case there's relevant data
888 * outside of the prog_data). If NULL, a plain memcmp is done.
890 cache_aux_compare_func aux_compare[BRW_MAX_CACHE];
891 /** Optional functions for freeing other pointers attached to a prog_data. */
892 cache_aux_free_func aux_free[BRW_MAX_CACHE];
896 /* Considered adding a member to this struct to document which flags
897 * an update might raise so that ordering of the state atoms can be
898 * checked or derived at runtime. Dropped the idea in favor of having
899 * a debug mode where the state is monitored for flags which are
900 * raised that have already been tested against.
902 struct brw_tracked_state {
903 struct brw_state_flags dirty;
904 void (*emit)( struct brw_context *brw );
907 enum shader_time_shader_type {
916 struct brw_vertex_buffer {
917 /** Buffer object containing the uploaded vertex data */
920 /** Byte stride between elements in the uploaded array */
924 struct brw_vertex_element {
925 const struct gl_client_array *glarray;
929 /** Offset of the first element within the buffer object */
933 struct brw_query_object {
934 struct gl_query_object Base;
936 /** Last query BO associated with this query. */
939 /** Last index in bo with query data for this object. */
942 /** True if we know the batch has been flushed since we ended the query. */
952 struct intel_batchbuffer {
953 /** Current batchbuffer being queued up. */
955 /** Last BO submitted to the hardware. Used for glFinish(). */
956 drm_intel_bo *last_bo;
959 uint16_t emit, total;
961 uint16_t reserved_space;
965 #define BATCH_SZ (8192*sizeof(uint32_t))
967 uint32_t state_batch_offset;
968 enum brw_gpu_ring ring;
969 bool needs_sol_reset;
977 #define BRW_MAX_XFB_STREAMS 4
979 struct brw_transform_feedback_object {
980 struct gl_transform_feedback_object base;
982 /** A buffer to hold SO_WRITE_OFFSET(n) values while paused. */
983 drm_intel_bo *offset_bo;
985 /** If true, SO_WRITE_OFFSET(n) should be reset to zero at next use. */
988 /** The most recent primitive mode (GL_TRIANGLES/GL_POINTS/GL_LINES). */
989 GLenum primitive_mode;
992 * Count of primitives generated during this transform feedback operation.
995 uint64_t prims_generated[BRW_MAX_XFB_STREAMS];
996 drm_intel_bo *prim_count_bo;
997 unsigned prim_count_buffer_index; /**< in number of uint64_t units */
1001 * Number of vertices written between last Begin/EndTransformFeedback().
1003 * Used to implement DrawTransformFeedback().
1005 uint64_t vertices_written[BRW_MAX_XFB_STREAMS];
1006 bool vertices_written_valid;
1010 * Data shared between each programmable stage in the pipeline (vs, gs, and
1013 struct brw_stage_state
1015 gl_shader_stage stage;
1016 struct brw_stage_prog_data *prog_data;
1019 * Optional scratch buffer used to store spilled register values and
1020 * variably-indexed GRF arrays.
1022 drm_intel_bo *scratch_bo;
1024 /** Offset in the program cache to the program */
1025 uint32_t prog_offset;
1027 /** Offset in the batchbuffer to Gen4-5 pipelined state (VS/WM/GS_STATE). */
1028 uint32_t state_offset;
1030 uint32_t push_const_offset; /* Offset in the batchbuffer */
1031 int push_const_size; /* in 256-bit register increments */
1033 /* Binding table: pointers to SURFACE_STATE entries. */
1034 uint32_t bind_bo_offset;
1035 uint32_t surf_offset[BRW_MAX_SURFACES];
1037 /** SAMPLER_STATE count and table offset */
1038 uint32_t sampler_count;
1039 uint32_t sampler_offset;
1042 enum brw_predicate_state {
1043 /* The first two states are used if we can determine whether to draw
1044 * without having to look at the values in the query object buffer. This
1045 * will happen if there is no conditional render in progress, if the query
1046 * object is already completed or if something else has already added
1047 * samples to the preliminary result such as via a BLT command.
1049 BRW_PREDICATE_STATE_RENDER,
1050 BRW_PREDICATE_STATE_DONT_RENDER,
1051 /* In this case whether to draw or not depends on the result of an
1052 * MI_PREDICATE command so the predicate enable bit needs to be checked.
1054 BRW_PREDICATE_STATE_USE_BIT
1057 struct shader_times;
1060 * brw_context is derived from gl_context.
1064 struct gl_context ctx; /**< base class, must be first field */
1068 void (*update_texture_surface)(struct gl_context *ctx,
1070 uint32_t *surf_offset,
1072 uint32_t (*update_renderbuffer_surface)(struct brw_context *brw,
1073 struct gl_renderbuffer *rb,
1074 bool layered, unsigned unit,
1075 uint32_t surf_index);
1077 void (*emit_texture_surface_state)(struct brw_context *brw,
1078 struct intel_mipmap_tree *mt,
1086 uint32_t *surf_offset,
1087 bool rw, bool for_gather);
1088 void (*emit_buffer_surface_state)(struct brw_context *brw,
1089 uint32_t *out_offset,
1091 unsigned buffer_offset,
1092 unsigned surface_format,
1093 unsigned buffer_size,
1096 void (*emit_null_surface_state)(struct brw_context *brw,
1100 uint32_t *out_offset);
1103 * Send the appropriate state packets to configure depth, stencil, and
1104 * HiZ buffers (i965+ only)
1106 void (*emit_depth_stencil_hiz)(struct brw_context *brw,
1107 struct intel_mipmap_tree *depth_mt,
1108 uint32_t depth_offset,
1109 uint32_t depthbuffer_format,
1110 uint32_t depth_surface_type,
1111 struct intel_mipmap_tree *stencil_mt,
1112 bool hiz, bool separate_stencil,
1113 uint32_t width, uint32_t height,
1114 uint32_t tile_x, uint32_t tile_y);
1120 drm_intel_context *hw_ctx;
1122 /** BO for post-sync nonzero writes for gen6 workaround. */
1123 drm_intel_bo *workaround_bo;
1124 uint8_t pipe_controls_since_last_cs_stall;
1127 * Set of drm_intel_bo * that have been rendered to within this batchbuffer
1128 * and would need flushing before being used from another cache domain that
1129 * isn't coherent with it (i.e. the sampler).
1131 struct set *render_cache;
1134 * Number of resets observed in the system at context creation.
1136 * This is tracked in the context so that we can determine that another
1137 * reset has occurred.
1139 uint32_t reset_count;
1141 struct intel_batchbuffer batch;
1146 uint32_t next_offset;
1150 * Set if rendering has occurred to the drawable's front buffer.
1152 * This is used in the DRI2 case to detect that glFlush should also copy
1153 * the contents of the fake front buffer to the real front buffer.
1155 bool front_buffer_dirty;
1157 /** Framerate throttling: @{ */
1158 drm_intel_bo *throttle_batch[2];
1160 /* Limit the number of outstanding SwapBuffers by waiting for an earlier
1161 * frame of rendering to complete. This gives a very precise cap to the
1162 * latency between input and output such that rendering never gets more
1163 * than a frame behind the user. (With the caveat that we technically are
1164 * not using the SwapBuffers itself as a barrier but the first batch
1165 * submitted afterwards, which may be immediately prior to the next
1168 bool need_swap_throttle;
1170 /** General throttling, not caught by throttling between SwapBuffers */
1171 bool need_flush_throttle;
1181 bool always_flush_batch;
1182 bool always_flush_cache;
1183 bool disable_throttling;
1186 driOptionCache optionCache;
1189 GLuint primitive; /**< Hardware primitive, such as _3DPRIM_TRILIST. */
1191 GLenum reduced_primitive;
1194 * Set if we're either a debug context or the INTEL_DEBUG=perf environment
1195 * variable is set, this is the flag indicating to do expensive work that
1196 * might lead to a perf_debug() call.
1200 uint32_t max_gtt_map_object_size;
1212 bool has_separate_stencil;
1213 bool must_use_separate_stencil;
1216 bool has_surface_tile_offset;
1218 bool has_negative_rhw_bug;
1222 bool use_resource_streamer;
1225 * Some versions of Gen hardware don't do centroid interpolation correctly
1226 * on unlit pixels, causing incorrect values for derivatives near triangle
1227 * edges. Enabling this flag causes the fragment shader to use
1228 * non-centroid interpolation for unlit pixels, at the expense of two extra
1229 * fragment shader instructions.
1231 bool needs_unlit_centroid_workaround;
1235 struct brw_state_flags pipelines[BRW_NUM_PIPELINES];
1238 enum brw_pipeline last_pipeline;
1240 struct brw_cache cache;
1242 /** IDs for meta stencil blit shader programs. */
1243 unsigned meta_stencil_blit_programs[2];
1245 /* Whether a meta-operation is in progress. */
1246 bool meta_in_progress;
1248 /* Whether the last depth/stencil packets were both NULL. */
1249 bool no_depth_or_stencil;
1251 /* The last PMA stall bits programmed. */
1252 uint32_t pma_stall_bits;
1255 /** The value of gl_BaseVertex for the current _mesa_prim. */
1259 * Buffer and offset used for GL_ARB_shader_draw_parameters
1260 * (for now, only gl_BaseVertex).
1262 drm_intel_bo *draw_params_bo;
1263 uint32_t draw_params_offset;
1268 * For gl_NumWorkGroups: If num_work_groups_bo is non NULL, then it is
1269 * an indirect call, and num_work_groups_offset is valid. Otherwise,
1270 * num_work_groups is set based on glDispatchCompute.
1272 drm_intel_bo *num_work_groups_bo;
1273 GLintptr num_work_groups_offset;
1274 const GLuint *num_work_groups;
1278 struct brw_vertex_element inputs[VERT_ATTRIB_MAX];
1279 struct brw_vertex_buffer buffers[VERT_ATTRIB_MAX];
1281 struct brw_vertex_element *enabled[VERT_ATTRIB_MAX];
1285 /* Summary of size and varying of active arrays, so we can check
1286 * for changes to this state:
1288 unsigned int min_index, max_index;
1290 /* Offset from start of vertex buffer so we can avoid redefining
1291 * the same VB packed over and over again.
1293 unsigned int start_vertex_bias;
1296 * Certain vertex attribute formats aren't natively handled by the
1297 * hardware and require special VS code to fix up their values.
1299 * These bitfields indicate which workarounds are needed.
1301 uint8_t attrib_wa_flags[VERT_ATTRIB_MAX];
1306 * Index buffer for this draw_prims call.
1308 * Updates are signaled by BRW_NEW_INDICES.
1310 const struct _mesa_index_buffer *ib;
1312 /* Updates are signaled by BRW_NEW_INDEX_BUFFER. */
1316 /* Offset to index buffer index to use in CMD_3D_PRIM so that we can
1317 * avoid re-uploading the IB packet over and over if we're actually
1318 * referencing the same index buffer.
1320 unsigned int start_vertex_offset;
1323 /* Active vertex program:
1325 const struct gl_vertex_program *vertex_program;
1326 const struct gl_geometry_program *geometry_program;
1327 const struct gl_fragment_program *fragment_program;
1328 const struct gl_compute_program *compute_program;
1331 * Number of samples in ctx->DrawBuffer, updated by BRW_NEW_NUM_SAMPLES so
1332 * that we don't have to reemit that state every time we change FBOs.
1337 * Platform specific constants containing the maximum number of threads
1338 * for each pipeline stage.
1340 unsigned max_vs_threads;
1341 unsigned max_hs_threads;
1342 unsigned max_ds_threads;
1343 unsigned max_gs_threads;
1344 unsigned max_wm_threads;
1345 unsigned max_cs_threads;
1347 /* BRW_NEW_URB_ALLOCATIONS:
1350 GLuint vsize; /* vertex size plus header in urb registers */
1351 GLuint gsize; /* GS output size in urb registers */
1352 GLuint csize; /* constant buffer size in urb registers */
1353 GLuint sfsize; /* setup data size in urb registers */
1357 GLuint min_vs_entries; /* Minimum number of VS entries */
1358 GLuint max_vs_entries; /* Maximum number of VS entries */
1359 GLuint max_hs_entries; /* Maximum number of HS entries */
1360 GLuint max_ds_entries; /* Maximum number of DS entries */
1361 GLuint max_gs_entries; /* Maximum number of GS entries */
1363 GLuint nr_vs_entries;
1364 GLuint nr_gs_entries;
1365 GLuint nr_clip_entries;
1366 GLuint nr_sf_entries;
1367 GLuint nr_cs_entries;
1374 GLuint size; /* Hardware URB size, in KB. */
1376 /* True if the most recently sent _3DSTATE_URB message allocated
1377 * URB space for the GS.
1383 /* BRW_NEW_CURBE_OFFSETS:
1386 GLuint wm_start; /**< pos of first wm const in CURBE buffer */
1387 GLuint wm_size; /**< number of float[4] consts, multiple of 16 */
1395 * Pointer to the (intel_upload.c-generated) BO containing the uniforms
1396 * for upload to the CURBE.
1398 drm_intel_bo *curbe_bo;
1399 /** Offset within curbe_bo of space for current curbe entry */
1400 GLuint curbe_offset;
1404 * Layout of vertex data exiting the geometry portion of the pipleine.
1405 * This comes from the last enabled shader stage (GS, DS, or VS).
1407 * BRW_NEW_VUE_MAP_GEOM_OUT is flagged when the VUE map changes.
1409 struct brw_vue_map vue_map_geom_out;
1412 struct brw_stage_state base;
1413 struct brw_vs_prog_data *prog_data;
1417 struct brw_stage_state base;
1418 struct brw_gs_prog_data *prog_data;
1421 * True if the 3DSTATE_GS command most recently emitted to the 3D
1422 * pipeline enabled the GS; false otherwise.
1428 struct brw_ff_gs_prog_data *prog_data;
1431 /** Offset in the program cache to the CLIP program pre-gen6 */
1432 uint32_t prog_offset;
1433 uint32_t state_offset;
1435 uint32_t bind_bo_offset;
1437 * Surface offsets for the binding table. We only need surfaces to
1438 * implement transform feedback so BRW_MAX_SOL_BINDINGS is all that we
1439 * need in this case.
1441 uint32_t surf_offset[BRW_MAX_SOL_BINDINGS];
1445 struct brw_clip_prog_data *prog_data;
1447 /** Offset in the program cache to the CLIP program pre-gen6 */
1448 uint32_t prog_offset;
1450 /* Offset in the batch to the CLIP state on pre-gen6. */
1451 uint32_t state_offset;
1453 /* As of gen6, this is the offset in the batch to the CLIP VP,
1461 struct brw_sf_prog_data *prog_data;
1463 /** Offset in the program cache to the CLIP program pre-gen6 */
1464 uint32_t prog_offset;
1465 uint32_t state_offset;
1467 bool viewport_transform_enable;
1471 struct brw_stage_state base;
1472 struct brw_wm_prog_data *prog_data;
1477 * Buffer object used in place of multisampled null render targets on
1478 * Gen6. See brw_emit_null_surface_state().
1480 drm_intel_bo *multisampled_null_render_target_bo;
1481 uint32_t fast_clear_op;
1485 struct brw_stage_state base;
1486 struct brw_cs_prog_data *prog_data;
1489 /* RS hardware binding table */
1492 uint32_t next_offset;
1496 uint32_t state_offset;
1497 uint32_t blend_state_offset;
1498 uint32_t depth_stencil_state_offset;
1503 struct brw_query_object *obj;
1508 enum brw_predicate_state state;
1513 /** A map from pipeline statistics counter IDs to MMIO addresses. */
1514 const int *statistics_registers;
1516 /** The number of active monitors using OA counters. */
1520 * A buffer object storing OA counter snapshots taken at the start and
1521 * end of each batch (creating "bookends" around the batch).
1523 drm_intel_bo *bookend_bo;
1525 /** The number of snapshots written to bookend_bo. */
1526 int bookend_snapshots;
1529 * An array of monitors whose results haven't yet been assembled based on
1530 * the data in buffer objects.
1532 * These may be active, or have already ended. However, the results
1533 * have not been requested.
1535 struct brw_perf_monitor_object **unresolved;
1536 int unresolved_elements;
1537 int unresolved_array_size;
1540 * Mapping from a uint32_t offset within an OA snapshot to the ID of
1541 * the counter which MI_REPORT_PERF_COUNT stores there.
1543 const int *oa_snapshot_layout;
1545 /** Number of 32-bit entries in a hardware counter snapshot. */
1546 int entries_per_oa_snapshot;
1549 int num_atoms[BRW_NUM_PIPELINES];
1550 const struct brw_tracked_state render_atoms[60];
1551 const struct brw_tracked_state compute_atoms[7];
1553 /* If (INTEL_DEBUG & DEBUG_BATCH) */
1557 enum aub_state_struct_type type;
1559 } *state_batch_list;
1560 int state_batch_count;
1562 uint32_t render_target_format[MESA_FORMAT_COUNT];
1563 bool format_supported_as_render_target[MESA_FORMAT_COUNT];
1565 /* Interpolation modes, one byte per vue slot.
1566 * Used Gen4/5 by the clip|sf|wm stages. Ignored on Gen6+.
1568 struct interpolation_mode_map interpolation_mode;
1570 /* PrimitiveRestart */
1573 bool enable_cut_index;
1576 /** Computed depth/stencil/hiz state from the current attached
1577 * renderbuffers, valid only during the drawing state upload loop after
1578 * brw_workaround_depthstencil_alignment().
1581 struct intel_mipmap_tree *depth_mt;
1582 struct intel_mipmap_tree *stencil_mt;
1584 /* Inter-tile (page-aligned) byte offsets. */
1585 uint32_t depth_offset, hiz_offset, stencil_offset;
1586 /* Intra-tile x,y offsets for drawing to depth/stencil/hiz */
1587 uint32_t tile_x, tile_y;
1590 uint32_t num_instances;
1597 enum shader_time_shader_type *types;
1598 struct shader_times *cumulative;
1604 struct brw_fast_clear_state *fast_clear_state;
1606 __DRIcontext *driContext;
1607 struct intel_screen *intelScreen;
1610 /*======================================================================
1613 void brwInitVtbl( struct brw_context *brw );
1616 extern void intelInitClearFuncs(struct dd_function_table *functions);
1618 /*======================================================================
1621 extern const char *const brw_vendor_string;
1623 extern const char *brw_get_renderer_string(unsigned deviceID);
1626 DRI_CONF_BO_REUSE_DISABLED,
1627 DRI_CONF_BO_REUSE_ALL
1630 void intel_update_renderbuffers(__DRIcontext *context,
1631 __DRIdrawable *drawable);
1632 void intel_prepare_render(struct brw_context *brw);
1634 void intel_resolve_for_dri2_flush(struct brw_context *brw,
1635 __DRIdrawable *drawable);
1637 GLboolean brwCreateContext(gl_api api,
1638 const struct gl_config *mesaVis,
1639 __DRIcontext *driContextPriv,
1640 unsigned major_version,
1641 unsigned minor_version,
1645 void *sharedContextPrivate);
1647 /*======================================================================
1650 GLuint brw_get_rb_for_slice(struct brw_context *brw,
1651 struct intel_mipmap_tree *mt,
1652 unsigned level, unsigned layer, bool flat);
1654 void brw_meta_updownsample(struct brw_context *brw,
1655 struct intel_mipmap_tree *src,
1656 struct intel_mipmap_tree *dst);
1658 void brw_meta_fbo_stencil_blit(struct brw_context *brw,
1659 struct gl_framebuffer *read_fb,
1660 struct gl_framebuffer *draw_fb,
1661 GLfloat srcX0, GLfloat srcY0,
1662 GLfloat srcX1, GLfloat srcY1,
1663 GLfloat dstX0, GLfloat dstY0,
1664 GLfloat dstX1, GLfloat dstY1);
1666 void brw_meta_stencil_updownsample(struct brw_context *brw,
1667 struct intel_mipmap_tree *src,
1668 struct intel_mipmap_tree *dst);
1670 bool brw_meta_fast_clear(struct brw_context *brw,
1671 struct gl_framebuffer *fb,
1673 bool partial_clear);
1676 brw_meta_resolve_color(struct brw_context *brw,
1677 struct intel_mipmap_tree *mt);
1679 brw_meta_fast_clear_free(struct brw_context *brw);
1682 /*======================================================================
1685 void brw_get_depthstencil_tile_masks(struct intel_mipmap_tree *depth_mt,
1686 uint32_t depth_level,
1687 uint32_t depth_layer,
1688 struct intel_mipmap_tree *stencil_mt,
1689 uint32_t *out_tile_mask_x,
1690 uint32_t *out_tile_mask_y);
1691 void brw_workaround_depthstencil_alignment(struct brw_context *brw,
1692 GLbitfield clear_mask);
1694 /* brw_object_purgeable.c */
1695 void brw_init_object_purgeable_functions(struct dd_function_table *functions);
1697 /*======================================================================
1700 void brw_init_common_queryobj_functions(struct dd_function_table *functions);
1701 void gen4_init_queryobj_functions(struct dd_function_table *functions);
1702 void brw_emit_query_begin(struct brw_context *brw);
1703 void brw_emit_query_end(struct brw_context *brw);
1705 /** gen6_queryobj.c */
1706 void gen6_init_queryobj_functions(struct dd_function_table *functions);
1707 void brw_write_timestamp(struct brw_context *brw, drm_intel_bo *bo, int idx);
1708 void brw_write_depth_count(struct brw_context *brw, drm_intel_bo *bo, int idx);
1709 void brw_store_register_mem64(struct brw_context *brw,
1710 drm_intel_bo *bo, uint32_t reg, int idx);
1712 /** brw_conditional_render.c */
1713 void brw_init_conditional_render_functions(struct dd_function_table *functions);
1714 bool brw_check_conditional_render(struct brw_context *brw);
1716 /** intel_batchbuffer.c */
1717 void brw_load_register_mem(struct brw_context *brw,
1720 uint32_t read_domains, uint32_t write_domain,
1722 void brw_load_register_mem64(struct brw_context *brw,
1725 uint32_t read_domains, uint32_t write_domain,
1728 /*======================================================================
1731 void brw_debug_batch(struct brw_context *brw);
1732 void brw_annotate_aub(struct brw_context *brw);
1734 /*======================================================================
1737 void brw_validate_textures( struct brw_context *brw );
1740 /*======================================================================
1743 void brwInitFragProgFuncs( struct dd_function_table *functions );
1745 int brw_get_scratch_size(int size);
1746 void brw_get_scratch_bo(struct brw_context *brw,
1747 drm_intel_bo **scratch_bo, int size);
1748 void brw_init_shader_time(struct brw_context *brw);
1749 int brw_get_shader_time_index(struct brw_context *brw,
1750 struct gl_shader_program *shader_prog,
1751 struct gl_program *prog,
1752 enum shader_time_shader_type type);
1753 void brw_collect_and_report_shader_time(struct brw_context *brw);
1754 void brw_destroy_shader_time(struct brw_context *brw);
1758 void brw_upload_urb_fence(struct brw_context *brw);
1762 void brw_upload_cs_urb_state(struct brw_context *brw);
1764 /* brw_fs_reg_allocate.cpp
1766 void brw_fs_alloc_reg_sets(struct brw_compiler *compiler);
1768 /* brw_vec4_reg_allocate.cpp */
1769 void brw_vec4_alloc_reg_set(struct brw_compiler *compiler);
1772 int brw_disassemble_inst(FILE *file, const struct brw_device_info *devinfo,
1773 struct brw_inst *inst, bool is_compacted);
1776 gl_clip_plane *brw_select_clip_planes(struct gl_context *ctx);
1778 /* brw_draw_upload.c */
1779 unsigned brw_get_vertex_surface_type(struct brw_context *brw,
1780 const struct gl_client_array *glarray);
1782 static inline unsigned
1783 brw_get_index_type(GLenum type)
1785 assert((type == GL_UNSIGNED_BYTE)
1786 || (type == GL_UNSIGNED_SHORT)
1787 || (type == GL_UNSIGNED_INT));
1789 /* The possible values for type are GL_UNSIGNED_BYTE (0x1401),
1790 * GL_UNSIGNED_SHORT (0x1403), and GL_UNSIGNED_INT (0x1405) which we want
1791 * to map to scale factors of 0, 1, and 2, respectively. These scale
1792 * factors are then left-shfited by 8 to be in the correct position in the
1793 * CMD_INDEX_BUFFER packet.
1795 * Subtracting 0x1401 gives 0, 2, and 4. Shifting left by 7 afterwards
1796 * gives 0x00000000, 0x00000100, and 0x00000200. These just happen to be
1797 * the values the need to be written in the CMD_INDEX_BUFFER packet.
1799 return (type - 0x1401) << 7;
1802 void brw_prepare_vertices(struct brw_context *brw);
1804 /* brw_wm_surface_state.c */
1805 void brw_init_surface_formats(struct brw_context *brw);
1806 void brw_create_constant_surface(struct brw_context *brw,
1810 uint32_t *out_offset,
1812 void brw_create_buffer_surface(struct brw_context *brw,
1816 uint32_t *out_offset,
1818 void brw_update_buffer_texture_surface(struct gl_context *ctx,
1820 uint32_t *surf_offset);
1822 brw_update_sol_surface(struct brw_context *brw,
1823 struct gl_buffer_object *buffer_obj,
1824 uint32_t *out_offset, unsigned num_vector_components,
1825 unsigned stride_dwords, unsigned offset_dwords);
1826 void brw_upload_ubo_surfaces(struct brw_context *brw,
1827 struct gl_shader *shader,
1828 struct brw_stage_state *stage_state,
1829 struct brw_stage_prog_data *prog_data,
1831 void brw_upload_abo_surfaces(struct brw_context *brw,
1832 struct gl_shader_program *prog,
1833 struct brw_stage_state *stage_state,
1834 struct brw_stage_prog_data *prog_data);
1835 void brw_upload_image_surfaces(struct brw_context *brw,
1836 struct gl_shader *shader,
1837 struct brw_stage_state *stage_state,
1838 struct brw_stage_prog_data *prog_data);
1840 /* brw_surface_formats.c */
1841 bool brw_render_target_supported(struct brw_context *brw,
1842 struct gl_renderbuffer *rb);
1843 uint32_t brw_depth_format(struct brw_context *brw, mesa_format format);
1844 mesa_format brw_lower_mesa_image_format(const struct brw_device_info *devinfo,
1845 mesa_format format);
1847 /* brw_performance_monitor.c */
1848 void brw_init_performance_monitors(struct brw_context *brw);
1849 void brw_dump_perf_monitors(struct brw_context *brw);
1850 void brw_perf_monitor_new_batch(struct brw_context *brw);
1851 void brw_perf_monitor_finish_batch(struct brw_context *brw);
1853 /* intel_buffer_objects.c */
1854 int brw_bo_map(struct brw_context *brw, drm_intel_bo *bo, int write_enable,
1855 const char *bo_name);
1856 int brw_bo_map_gtt(struct brw_context *brw, drm_intel_bo *bo,
1857 const char *bo_name);
1859 /* intel_extensions.c */
1860 extern void intelInitExtensions(struct gl_context *ctx);
1863 extern int intel_translate_shadow_compare_func(GLenum func);
1864 extern int intel_translate_compare_func(GLenum func);
1865 extern int intel_translate_stencil_op(GLenum op);
1866 extern int intel_translate_logic_op(GLenum opcode);
1868 /* intel_syncobj.c */
1869 void intel_init_syncobj_functions(struct dd_function_table *functions);
1872 struct gl_transform_feedback_object *
1873 brw_new_transform_feedback(struct gl_context *ctx, GLuint name);
1875 brw_delete_transform_feedback(struct gl_context *ctx,
1876 struct gl_transform_feedback_object *obj);
1878 brw_begin_transform_feedback(struct gl_context *ctx, GLenum mode,
1879 struct gl_transform_feedback_object *obj);
1881 brw_end_transform_feedback(struct gl_context *ctx,
1882 struct gl_transform_feedback_object *obj);
1884 brw_get_transform_feedback_vertex_count(struct gl_context *ctx,
1885 struct gl_transform_feedback_object *obj,
1888 /* gen7_sol_state.c */
1890 gen7_begin_transform_feedback(struct gl_context *ctx, GLenum mode,
1891 struct gl_transform_feedback_object *obj);
1893 gen7_end_transform_feedback(struct gl_context *ctx,
1894 struct gl_transform_feedback_object *obj);
1896 gen7_pause_transform_feedback(struct gl_context *ctx,
1897 struct gl_transform_feedback_object *obj);
1899 gen7_resume_transform_feedback(struct gl_context *ctx,
1900 struct gl_transform_feedback_object *obj);
1902 /* brw_blorp_blit.cpp */
1904 brw_blorp_framebuffer(struct brw_context *brw,
1905 struct gl_framebuffer *readFb,
1906 struct gl_framebuffer *drawFb,
1907 GLint srcX0, GLint srcY0, GLint srcX1, GLint srcY1,
1908 GLint dstX0, GLint dstY0, GLint dstX1, GLint dstY1,
1909 GLbitfield mask, GLenum filter);
1912 brw_blorp_copytexsubimage(struct brw_context *brw,
1913 struct gl_renderbuffer *src_rb,
1914 struct gl_texture_image *dst_image,
1916 int srcX0, int srcY0,
1917 int dstX0, int dstY0,
1918 int width, int height);
1920 /* gen6_multisample_state.c */
1922 gen6_determine_sample_mask(struct brw_context *brw);
1925 gen6_emit_3dstate_multisample(struct brw_context *brw,
1926 unsigned num_samples);
1928 gen6_emit_3dstate_sample_mask(struct brw_context *brw, unsigned mask);
1930 gen6_get_sample_position(struct gl_context *ctx,
1931 struct gl_framebuffer *fb,
1935 gen6_set_sample_maps(struct gl_context *ctx);
1937 /* gen8_multisample_state.c */
1938 void gen8_emit_3dstate_multisample(struct brw_context *brw, unsigned num_samp);
1939 void gen8_emit_3dstate_sample_pattern(struct brw_context *brw);
1943 gen7_emit_push_constant_state(struct brw_context *brw, unsigned vs_size,
1944 unsigned gs_size, unsigned fs_size);
1947 gen7_emit_urb_state(struct brw_context *brw,
1948 unsigned nr_vs_entries, unsigned vs_size,
1949 unsigned vs_start, unsigned nr_gs_entries,
1950 unsigned gs_size, unsigned gs_start);
1955 brw_get_graphics_reset_status(struct gl_context *ctx);
1959 brw_init_compute_functions(struct dd_function_table *functions);
1961 /*======================================================================
1962 * Inline conversion functions. These are better-typed than the
1963 * macros used previously:
1965 static inline struct brw_context *
1966 brw_context( struct gl_context *ctx )
1968 return (struct brw_context *)ctx;
1971 static inline struct brw_vertex_program *
1972 brw_vertex_program(struct gl_vertex_program *p)
1974 return (struct brw_vertex_program *) p;
1977 static inline const struct brw_vertex_program *
1978 brw_vertex_program_const(const struct gl_vertex_program *p)
1980 return (const struct brw_vertex_program *) p;
1983 static inline struct brw_geometry_program *
1984 brw_geometry_program(struct gl_geometry_program *p)
1986 return (struct brw_geometry_program *) p;
1989 static inline struct brw_fragment_program *
1990 brw_fragment_program(struct gl_fragment_program *p)
1992 return (struct brw_fragment_program *) p;
1995 static inline const struct brw_fragment_program *
1996 brw_fragment_program_const(const struct gl_fragment_program *p)
1998 return (const struct brw_fragment_program *) p;
2001 static inline struct brw_compute_program *
2002 brw_compute_program(struct gl_compute_program *p)
2004 return (struct brw_compute_program *) p;
2008 * Pre-gen6, the register file of the EUs was shared between threads,
2009 * and each thread used some subset allocated on a 16-register block
2010 * granularity. The unit states wanted these block counts.
2013 brw_register_blocks(int reg_count)
2015 return ALIGN(reg_count, 16) / 16 - 1;
2018 static inline uint32_t
2019 brw_program_reloc(struct brw_context *brw, uint32_t state_offset,
2020 uint32_t prog_offset)
2022 if (brw->gen >= 5) {
2023 /* Using state base address. */
2027 drm_intel_bo_emit_reloc(brw->batch.bo,
2031 I915_GEM_DOMAIN_INSTRUCTION, 0);
2033 return brw->cache.bo->offset64 + prog_offset;
2036 bool brw_do_cubemap_normalize(struct exec_list *instructions);
2037 bool brw_lower_texture_gradients(struct brw_context *brw,
2038 struct exec_list *instructions);
2039 bool brw_do_lower_unnormalized_offset(struct exec_list *instructions);
2041 struct opcode_desc {
2047 extern const struct opcode_desc opcode_descs[128];
2048 extern const char * const conditional_modifier[16];
2051 brw_emit_depthbuffer(struct brw_context *brw);
2054 brw_emit_depth_stencil_hiz(struct brw_context *brw,
2055 struct intel_mipmap_tree *depth_mt,
2056 uint32_t depth_offset, uint32_t depthbuffer_format,
2057 uint32_t depth_surface_type,
2058 struct intel_mipmap_tree *stencil_mt,
2059 bool hiz, bool separate_stencil,
2060 uint32_t width, uint32_t height,
2061 uint32_t tile_x, uint32_t tile_y);
2064 gen6_emit_depth_stencil_hiz(struct brw_context *brw,
2065 struct intel_mipmap_tree *depth_mt,
2066 uint32_t depth_offset, uint32_t depthbuffer_format,
2067 uint32_t depth_surface_type,
2068 struct intel_mipmap_tree *stencil_mt,
2069 bool hiz, bool separate_stencil,
2070 uint32_t width, uint32_t height,
2071 uint32_t tile_x, uint32_t tile_y);
2074 gen7_emit_depth_stencil_hiz(struct brw_context *brw,
2075 struct intel_mipmap_tree *depth_mt,
2076 uint32_t depth_offset, uint32_t depthbuffer_format,
2077 uint32_t depth_surface_type,
2078 struct intel_mipmap_tree *stencil_mt,
2079 bool hiz, bool separate_stencil,
2080 uint32_t width, uint32_t height,
2081 uint32_t tile_x, uint32_t tile_y);
2083 gen8_emit_depth_stencil_hiz(struct brw_context *brw,
2084 struct intel_mipmap_tree *depth_mt,
2085 uint32_t depth_offset, uint32_t depthbuffer_format,
2086 uint32_t depth_surface_type,
2087 struct intel_mipmap_tree *stencil_mt,
2088 bool hiz, bool separate_stencil,
2089 uint32_t width, uint32_t height,
2090 uint32_t tile_x, uint32_t tile_y);
2092 void gen8_hiz_exec(struct brw_context *brw, struct intel_mipmap_tree *mt,
2093 unsigned int level, unsigned int layer, enum gen6_hiz_op op);
2095 uint32_t get_hw_prim_for_gl_prim(int mode);
2098 gen6_upload_push_constants(struct brw_context *brw,
2099 const struct gl_program *prog,
2100 const struct brw_stage_prog_data *prog_data,
2101 struct brw_stage_state *stage_state,
2102 enum aub_state_struct_type type);
2105 gen9_use_linear_1d_layout(const struct brw_context *brw,
2106 const struct intel_mipmap_tree *mt);
2108 /* brw_pipe_control.c */
2109 int brw_init_pipe_control(struct brw_context *brw,
2110 const struct brw_device_info *info);
2111 void brw_fini_pipe_control(struct brw_context *brw);
2113 void brw_emit_pipe_control_flush(struct brw_context *brw, uint32_t flags);
2114 void brw_emit_pipe_control_write(struct brw_context *brw, uint32_t flags,
2115 drm_intel_bo *bo, uint32_t offset,
2116 uint32_t imm_lower, uint32_t imm_upper);
2117 void brw_emit_mi_flush(struct brw_context *brw);
2118 void brw_emit_post_sync_nonzero_flush(struct brw_context *brw);
2119 void brw_emit_depth_stall_flushes(struct brw_context *brw);
2120 void gen7_emit_vs_workaround_flush(struct brw_context *brw);
2121 void gen7_emit_cs_stall_flush(struct brw_context *brw);