2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
4 develop this 3D driver.
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **********************************************************************/
29 * Keith Whitwell <keith@tungstengraphics.com>
33 #ifndef BRWCONTEXT_INC
34 #define BRWCONTEXT_INC
36 #include "intel_context.h"
37 #include "brw_structs.h"
38 #include "main/imports.h"
39 #include "main/macros.h"
47 * URB - uniform resource buffer. A mid-sized buffer which is
48 * partitioned between the fixed function units and used for passing
49 * values (vertices, primitives, constants) between them.
51 * CURBE - constant URB entry. An urb region (entry) used to hold
52 * constant values which the fixed function units can be instructed to
53 * preload into the GRF when spawning a thread.
55 * VUE - vertex URB entry. An urb entry holding a vertex and usually
56 * a vertex header. The header contains control information and
57 * things like primitive type, Begin/end flags and clip codes.
59 * PUE - primitive URB entry. An urb entry produced by the setup (SF)
60 * unit holding rasterization and interpolation parameters.
62 * GRF - general register file. One of several register files
63 * addressable by programmed threads. The inputs (r0, payload, curbe,
64 * urb) of the thread are preloaded to this area before the thread is
65 * spawned. The registers are individually 8 dwords wide and suitable
66 * for general usage. Registers holding thread input values are not
67 * special and may be overwritten.
69 * MRF - message register file. Threads communicate (and terminate)
70 * by sending messages. Message parameters are placed in contiguous
71 * MRF registers. All program output is via these messages. URB
72 * entries are populated by sending a message to the shared URB
73 * function containing the new data, together with a control word,
74 * often an unmodified copy of R0.
76 * R0 - GRF register 0. Typically holds control information used when
77 * sending messages to other threads.
79 * EU or GEN4 EU: The name of the programmable subsystem of the
80 * i965 hardware. Threads are executed by the EU, the registers
81 * described above are part of the EU architecture.
83 * Fixed function units:
85 * CS - Command streamer. Notional first unit, little software
86 * interaction. Holds the URB entries used for constant data, ie the
89 * VF/VS - Vertex Fetch / Vertex Shader. The fixed function part of
90 * this unit is responsible for pulling vertices out of vertex buffers
91 * in vram and injecting them into the processing pipe as VUEs. If
92 * enabled, it first passes them to a VS thread which is a good place
93 * for the driver to implement any active vertex shader.
95 * GS - Geometry Shader. This corresponds to a new DX10 concept. If
96 * enabled, incoming strips etc are passed to GS threads in individual
97 * line/triangle/point units. The GS thread may perform arbitary
98 * computation and emit whatever primtives with whatever vertices it
99 * chooses. This makes GS an excellent place to implement GL's
100 * unfilled polygon modes, though of course it is capable of much
101 * more. Additionally, GS is used to translate away primitives not
102 * handled by latter units, including Quads and Lineloops.
104 * CS - Clipper. Mesa's clipping algorithms are imported to run on
105 * this unit. The fixed function part performs cliptesting against
106 * the 6 fixed clipplanes and makes descisions on whether or not the
107 * incoming primitive needs to be passed to a thread for clipping.
108 * User clip planes are handled via cooperation with the VS thread.
110 * SF - Strips Fans or Setup: Triangles are prepared for
111 * rasterization. Interpolation coefficients are calculated.
112 * Flatshading and two-side lighting usually performed here.
114 * WM - Windower. Interpolation of vertex attributes performed here.
115 * Fragment shader implemented here. SIMD aspects of EU taken full
116 * advantage of, as pixels are processed in blocks of 16.
118 * CC - Color Calculator. No EU threads associated with this unit.
119 * Handles blending and (presumably) depth and stencil testing.
123 #define BRW_MAX_CURBE (32*16)
126 struct brw_instruction;
127 struct brw_vs_prog_key;
128 struct brw_wm_prog_key;
129 struct brw_wm_prog_data;
133 BRW_STATE_FRAGMENT_PROGRAM,
134 BRW_STATE_VERTEX_PROGRAM,
135 BRW_STATE_INPUT_DIMENSIONS,
136 BRW_STATE_CURBE_OFFSETS,
137 BRW_STATE_REDUCED_PRIMITIVE,
140 BRW_STATE_WM_INPUT_DIMENSIONS,
143 BRW_STATE_VS_BINDING_TABLE,
144 BRW_STATE_GS_BINDING_TABLE,
145 BRW_STATE_PS_BINDING_TABLE,
149 BRW_STATE_NR_WM_SURFACES,
150 BRW_STATE_NR_VS_SURFACES,
151 BRW_STATE_INDEX_BUFFER,
152 BRW_STATE_VS_CONSTBUF,
153 BRW_STATE_PROGRAM_CACHE,
154 BRW_STATE_STATE_BASE_ADDRESS,
155 BRW_STATE_SOL_INDICES,
158 #define BRW_NEW_URB_FENCE (1 << BRW_STATE_URB_FENCE)
159 #define BRW_NEW_FRAGMENT_PROGRAM (1 << BRW_STATE_FRAGMENT_PROGRAM)
160 #define BRW_NEW_VERTEX_PROGRAM (1 << BRW_STATE_VERTEX_PROGRAM)
161 #define BRW_NEW_INPUT_DIMENSIONS (1 << BRW_STATE_INPUT_DIMENSIONS)
162 #define BRW_NEW_CURBE_OFFSETS (1 << BRW_STATE_CURBE_OFFSETS)
163 #define BRW_NEW_REDUCED_PRIMITIVE (1 << BRW_STATE_REDUCED_PRIMITIVE)
164 #define BRW_NEW_PRIMITIVE (1 << BRW_STATE_PRIMITIVE)
165 #define BRW_NEW_CONTEXT (1 << BRW_STATE_CONTEXT)
166 #define BRW_NEW_WM_INPUT_DIMENSIONS (1 << BRW_STATE_WM_INPUT_DIMENSIONS)
167 #define BRW_NEW_PSP (1 << BRW_STATE_PSP)
168 #define BRW_NEW_SURFACES (1 << BRW_STATE_SURFACES)
169 #define BRW_NEW_VS_BINDING_TABLE (1 << BRW_STATE_VS_BINDING_TABLE)
170 #define BRW_NEW_GS_BINDING_TABLE (1 << BRW_STATE_GS_BINDING_TABLE)
171 #define BRW_NEW_PS_BINDING_TABLE (1 << BRW_STATE_PS_BINDING_TABLE)
172 #define BRW_NEW_INDICES (1 << BRW_STATE_INDICES)
173 #define BRW_NEW_VERTICES (1 << BRW_STATE_VERTICES)
175 * Used for any batch entry with a relocated pointer that will be used
176 * by any 3D rendering.
178 #define BRW_NEW_BATCH (1 << BRW_STATE_BATCH)
179 /** \see brw.state.depth_region */
180 #define BRW_NEW_INDEX_BUFFER (1 << BRW_STATE_INDEX_BUFFER)
181 #define BRW_NEW_VS_CONSTBUF (1 << BRW_STATE_VS_CONSTBUF)
182 #define BRW_NEW_PROGRAM_CACHE (1 << BRW_STATE_PROGRAM_CACHE)
183 #define BRW_NEW_STATE_BASE_ADDRESS (1 << BRW_STATE_STATE_BASE_ADDRESS)
184 #define BRW_NEW_SOL_INDICES (1 << BRW_STATE_SOL_INDICES)
186 struct brw_state_flags {
187 /** State update flags signalled by mesa internals */
190 * State update flags signalled as the result of brw_tracked_state updates
193 /** State update flags signalled by brw_state_cache.c searches */
197 #define AUB_TRACE_TYPE_MASK 0x0000ff00
198 #define AUB_TRACE_TYPE_NOTYPE (0 << 8)
199 #define AUB_TRACE_TYPE_BATCH (1 << 8)
200 #define AUB_TRACE_TYPE_VERTEX_BUFFER (5 << 8)
201 #define AUB_TRACE_TYPE_2D_MAP (6 << 8)
202 #define AUB_TRACE_TYPE_CUBE_MAP (7 << 8)
203 #define AUB_TRACE_TYPE_VOLUME_MAP (9 << 8)
204 #define AUB_TRACE_TYPE_1D_MAP (10 << 8)
205 #define AUB_TRACE_TYPE_CONSTANT_BUFFER (11 << 8)
206 #define AUB_TRACE_TYPE_CONSTANT_URB (12 << 8)
207 #define AUB_TRACE_TYPE_INDEX_BUFFER (13 << 8)
208 #define AUB_TRACE_TYPE_GENERAL (14 << 8)
209 #define AUB_TRACE_TYPE_SURFACE (15 << 8)
212 * state_struct_type enum values are encoded with the top 16 bits representing
213 * the type to be delivered to the .aub file, and the bottom 16 bits
214 * representing the subtype. This macro performs the encoding.
216 #define ENCODE_SS_TYPE(type, subtype) (((type) << 16) | (subtype))
218 enum state_struct_type {
219 AUB_TRACE_VS_STATE = ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL, 1),
220 AUB_TRACE_GS_STATE = ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL, 2),
221 AUB_TRACE_CLIP_STATE = ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL, 3),
222 AUB_TRACE_SF_STATE = ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL, 4),
223 AUB_TRACE_WM_STATE = ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL, 5),
224 AUB_TRACE_CC_STATE = ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL, 6),
225 AUB_TRACE_CLIP_VP_STATE = ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL, 7),
226 AUB_TRACE_SF_VP_STATE = ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL, 8),
227 AUB_TRACE_CC_VP_STATE = ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL, 0x9),
228 AUB_TRACE_SAMPLER_STATE = ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL, 0xa),
229 AUB_TRACE_KERNEL_INSTRUCTIONS = ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL, 0xb),
230 AUB_TRACE_SCRATCH_SPACE = ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL, 0xc),
231 AUB_TRACE_SAMPLER_DEFAULT_COLOR = ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL, 0xd),
233 AUB_TRACE_SCISSOR_STATE = ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL, 0x15),
234 AUB_TRACE_BLEND_STATE = ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL, 0x16),
235 AUB_TRACE_DEPTH_STENCIL_STATE = ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL, 0x17),
237 AUB_TRACE_VERTEX_BUFFER = ENCODE_SS_TYPE(AUB_TRACE_TYPE_VERTEX_BUFFER, 0),
238 AUB_TRACE_BINDING_TABLE = ENCODE_SS_TYPE(AUB_TRACE_TYPE_SURFACE, 0x100),
239 AUB_TRACE_SURFACE_STATE = ENCODE_SS_TYPE(AUB_TRACE_TYPE_SURFACE, 0x200),
240 AUB_TRACE_VS_CONSTANTS = ENCODE_SS_TYPE(AUB_TRACE_TYPE_CONSTANT_BUFFER, 0),
241 AUB_TRACE_WM_CONSTANTS = ENCODE_SS_TYPE(AUB_TRACE_TYPE_CONSTANT_BUFFER, 1),
245 * Decode a state_struct_type value to determine the type that should be
246 * stored in the .aub file.
248 static inline uint32_t AUB_TRACE_TYPE(enum state_struct_type ss_type)
250 return (ss_type & 0xFFFF0000) >> 16;
254 * Decode a state_struct_type value to determine the subtype that should be
255 * stored in the .aub file.
257 static inline uint32_t AUB_TRACE_SUBTYPE(enum state_struct_type ss_type)
259 return ss_type & 0xFFFF;
262 /** Subclass of Mesa vertex program */
263 struct brw_vertex_program {
264 struct gl_vertex_program program;
269 /** Subclass of Mesa fragment program */
270 struct brw_fragment_program {
271 struct gl_fragment_program program;
272 GLuint id; /**< serial no. to identify frag progs, never re-used */
276 struct gl_shader base;
280 /** Shader IR transformed for native compile, at link time. */
281 struct exec_list *ir;
284 /* Data about a particular attempt to compile a program. Note that
285 * there can be many of these, each in a different GL state
286 * corresponding to a different brw_wm_prog_key struct, with different
289 * Note: brw_wm_prog_data_compare() must be updated when adding fields to this
292 struct brw_wm_prog_data {
293 GLuint curb_read_length;
294 GLuint urb_read_length;
296 GLuint first_curbe_grf;
297 GLuint first_curbe_grf_16;
299 GLuint reg_blocks_16;
300 GLuint total_scratch;
302 GLuint nr_params; /**< number of float params/constants */
303 GLuint nr_pull_params;
306 uint32_t prog_offset_16;
309 * Mask of which interpolation modes are required by the fragment shader.
310 * Used in hardware setup on gen6+.
312 uint32_t barycentric_interp_modes;
314 /* Pointers to tracked values (only valid once
315 * _mesa_load_state_parameters has been called at runtime).
317 * These must be the last fields of the struct (see
318 * brw_wm_prog_data_compare()).
321 const float **pull_param;
325 * Enum representing the i965-specific vertex results that don't correspond
326 * exactly to any element of gl_vert_result. The values of this enum are
327 * assigned such that they don't conflict with gl_vert_result.
331 BRW_VERT_RESULT_NDC = VERT_RESULT_MAX,
332 BRW_VERT_RESULT_HPOS_DUPLICATE,
335 * It's actually not a vert_result but just a _mark_ to let sf aware that
336 * he need do something special to handle gl_PointCoord builtin variable
337 * correctly. see compile_sf_prog() for more info.
339 BRW_VERT_RESULT_PNTC,
345 * Data structure recording the relationship between the gl_vert_result enum
346 * and "slots" within the vertex URB entry (VUE). A "slot" is defined as a
347 * single octaword within the VUE (128 bits).
349 * Note that each BRW register contains 256 bits (2 octawords), so when
350 * accessing the VUE in URB_NOSWIZZLE mode, each register corresponds to two
351 * consecutive VUE slots. When accessing the VUE in URB_INTERLEAVED mode (as
352 * in a vertex shader), each register corresponds to a single VUE slot, since
353 * it contains data for two separate vertices.
357 * Map from gl_vert_result value to VUE slot. For gl_vert_results that are
358 * not stored in a slot (because they are not written, or because
359 * additional processing is applied before storing them in the VUE), the
362 int vert_result_to_slot[BRW_VERT_RESULT_MAX];
365 * Map from VUE slot to gl_vert_result value. For slots that do not
366 * directly correspond to a gl_vert_result, the value comes from
369 * For slots that are not in use, the value is BRW_VERT_RESULT_MAX (this
370 * simplifies code that uses the value stored in slot_to_vert_result to
371 * create a bit mask).
373 int slot_to_vert_result[BRW_VERT_RESULT_MAX];
376 * Total number of VUE slots in use
382 * Convert a VUE slot number into a byte offset within the VUE.
384 static inline GLuint brw_vue_slot_to_offset(GLuint slot)
390 * Convert a vert_result into a byte offset within the VUE.
392 static inline GLuint brw_vert_result_to_offset(struct brw_vue_map *vue_map,
395 return brw_vue_slot_to_offset(vue_map->vert_result_to_slot[vert_result]);
399 struct brw_sf_prog_data {
400 GLuint urb_read_length;
403 /* Each vertex may have upto 12 attributes, 4 components each,
404 * except WPOS which requires only 2. (11*4 + 2) == 44 ==> 11
407 * Actually we use 4 for each, so call it 12 rows.
409 GLuint urb_entry_size;
412 struct brw_clip_prog_data {
413 GLuint curb_read_length; /* user planes? */
415 GLuint urb_read_length;
419 struct brw_gs_prog_data {
420 GLuint urb_read_length;
424 * Gen6 transform feedback: Amount by which the streaming vertex buffer
425 * indices should be incremented each time the GS is invoked.
427 unsigned svbi_postincrement_value;
430 /* Note: brw_vs_prog_data_compare() must be updated when adding fields to this
433 struct brw_vs_prog_data {
434 struct brw_vue_map vue_map;
436 GLuint curb_read_length;
437 GLuint urb_read_length;
439 GLbitfield64 outputs_written;
440 GLuint nr_params; /**< number of float params/constants */
441 GLuint nr_pull_params; /**< number of dwords referenced by pull_param[] */
442 GLuint total_scratch;
444 GLbitfield64 inputs_read;
446 /* Used for calculating urb partitions:
448 GLuint urb_entry_size;
454 /* These pointers must appear last. See brw_vs_prog_data_compare(). */
456 const float **pull_param;
459 /** Number of texture sampler units */
460 #define BRW_MAX_TEX_UNIT 16
462 /** Max number of render targets in a shader */
463 #define BRW_MAX_DRAW_BUFFERS 8
466 * Max number of binding table entries used for stream output.
468 * From the OpenGL 3.0 spec, table 6.44 (Transform Feedback State), the
469 * minimum value of MAX_TRANSFORM_FEEDBACK_INTERLEAVED_COMPONENTS is 64.
471 * On Gen6, the size of transform feedback data is limited not by the number
472 * of components but by the number of binding table entries we set aside. We
473 * use one binding table entry for a float, one entry for a vector, and one
474 * entry per matrix column. Since the only way we can communicate our
475 * transform feedback capabilities to the client is via
476 * MAX_TRANSFORM_FEEDBACK_INTERLEAVED_COMPONENTS, we need to plan for the
477 * worst case, in which all the varyings are floats, so we use up one binding
478 * table entry per component. Therefore we need to set aside at least 64
479 * binding table entries for use by transform feedback.
481 * Note: since we don't currently pack varyings, it is currently impossible
482 * for the client to actually use up all of these binding table entries--if
483 * all of their varyings were floats, they would run out of varying slots and
484 * fail to link. But that's a bug, so it seems prudent to go ahead and
485 * allocate the number of binding table entries we will need once the bug is
488 #define BRW_MAX_SOL_BINDINGS 64
490 /** Maximum number of actual buffers used for stream output */
491 #define BRW_MAX_SOL_BUFFERS 4
493 #define BRW_MAX_WM_UBOS 12
494 #define BRW_MAX_VS_UBOS 12
497 * Helpers to create Surface Binding Table indexes for draw buffers,
498 * textures, and constant buffers.
500 * Shader threads access surfaces via numeric handles, rather than directly
501 * using pointers. The binding table maps these numeric handles to the
502 * address of the actual buffer.
504 * For example, a shader might ask to sample from "surface 7." In this case,
505 * bind[7] would contain a pointer to a texture.
507 * Currently, our WM binding tables are (arbitrarily) programmed as follows:
509 * +-------------------------------+
510 * | 0 | Draw buffer 0 |
513 * | 7 | Draw buffer 7 |
514 * |-----|-------------------------|
515 * | 8 | WM Pull Constant Buffer |
516 * |-----|-------------------------|
520 * | 24 | Texture 15 |
521 * |-----|-------------------------|
526 * +-------------------------------+
528 * Our VS binding tables are programmed as follows:
530 * +-----+-------------------------+
531 * | 0 | VS Pull Constant Buffer |
532 * +-----+-------------------------+
536 * | 16 | Texture 15 |
537 * +-----+-------------------------+
542 * +-------------------------------+
544 * Our (gen6) GS binding tables are programmed as follows:
546 * +-----+-------------------------+
547 * | 0 | SOL Binding 0 |
550 * | 63 | SOL Binding 63 |
551 * +-----+-------------------------+
553 * Note that nothing actually uses the SURF_INDEX_DRAW macro, so it has to be
554 * the identity function or things will break. We do want to keep draw buffers
555 * first so we can use headerless render target writes for RT 0.
557 #define SURF_INDEX_DRAW(d) (d)
558 #define SURF_INDEX_FRAG_CONST_BUFFER (BRW_MAX_DRAW_BUFFERS + 1)
559 #define SURF_INDEX_TEXTURE(t) (BRW_MAX_DRAW_BUFFERS + 2 + (t))
560 #define SURF_INDEX_WM_UBO(u) (SURF_INDEX_TEXTURE(BRW_MAX_TEX_UNIT) + u)
561 #define SURF_INDEX_WM_SHADER_TIME (SURF_INDEX_WM_UBO(12))
562 /** Maximum size of the binding table. */
563 #define BRW_MAX_WM_SURFACES (SURF_INDEX_WM_SHADER_TIME + 1)
565 #define SURF_INDEX_VERT_CONST_BUFFER (0)
566 #define SURF_INDEX_VS_TEXTURE(t) (SURF_INDEX_VERT_CONST_BUFFER + 1 + (t))
567 #define SURF_INDEX_VS_UBO(u) (SURF_INDEX_VS_TEXTURE(BRW_MAX_TEX_UNIT) + u)
568 #define SURF_INDEX_VS_SHADER_TIME (SURF_INDEX_VS_UBO(12))
569 #define BRW_MAX_VS_SURFACES (SURF_INDEX_VS_SHADER_TIME + 1)
571 #define SURF_INDEX_SOL_BINDING(t) ((t))
572 #define BRW_MAX_GS_SURFACES SURF_INDEX_SOL_BINDING(BRW_MAX_SOL_BINDINGS)
576 BRW_DEPTH_STENCIL_STATE,
577 BRW_COLOR_CALC_STATE,
586 BRW_SF_UNIT, /* scissor state on gen6 */
598 struct brw_cache_item {
600 * Effectively part of the key, cache_id identifies what kind of state
601 * buffer is involved, and also which brw->state.dirty.cache flag should
602 * be set when this cache item is chosen.
604 enum brw_cache_id cache_id;
605 /** 32-bit hash of the key data */
607 GLuint key_size; /* for variable-sized keys */
614 struct brw_cache_item *next;
618 typedef bool (*cache_aux_compare_func)(const void *a, const void *b,
619 int aux_size, const void *key);
620 typedef void (*cache_aux_free_func)(const void *aux);
623 struct brw_context *brw;
625 struct brw_cache_item **items;
627 GLuint size, n_items;
629 uint32_t next_offset;
633 * Optional functions used in determining whether the prog_data for a new
634 * cache item matches an existing cache item (in case there's relevant data
635 * outside of the prog_data). If NULL, a plain memcmp is done.
637 cache_aux_compare_func aux_compare[BRW_MAX_CACHE];
638 /** Optional functions for freeing other pointers attached to a prog_data. */
639 cache_aux_free_func aux_free[BRW_MAX_CACHE];
643 /* Considered adding a member to this struct to document which flags
644 * an update might raise so that ordering of the state atoms can be
645 * checked or derived at runtime. Dropped the idea in favor of having
646 * a debug mode where the state is monitored for flags which are
647 * raised that have already been tested against.
649 struct brw_tracked_state {
650 struct brw_state_flags dirty;
651 void (*emit)( struct brw_context *brw );
654 enum shader_time_shader_type {
667 /* Flags for brw->state.cache.
669 #define CACHE_NEW_BLEND_STATE (1<<BRW_BLEND_STATE)
670 #define CACHE_NEW_DEPTH_STENCIL_STATE (1<<BRW_DEPTH_STENCIL_STATE)
671 #define CACHE_NEW_COLOR_CALC_STATE (1<<BRW_COLOR_CALC_STATE)
672 #define CACHE_NEW_CC_VP (1<<BRW_CC_VP)
673 #define CACHE_NEW_CC_UNIT (1<<BRW_CC_UNIT)
674 #define CACHE_NEW_WM_PROG (1<<BRW_WM_PROG)
675 #define CACHE_NEW_SAMPLER (1<<BRW_SAMPLER)
676 #define CACHE_NEW_WM_UNIT (1<<BRW_WM_UNIT)
677 #define CACHE_NEW_SF_PROG (1<<BRW_SF_PROG)
678 #define CACHE_NEW_SF_VP (1<<BRW_SF_VP)
679 #define CACHE_NEW_SF_UNIT (1<<BRW_SF_UNIT)
680 #define CACHE_NEW_VS_UNIT (1<<BRW_VS_UNIT)
681 #define CACHE_NEW_VS_PROG (1<<BRW_VS_PROG)
682 #define CACHE_NEW_GS_UNIT (1<<BRW_GS_UNIT)
683 #define CACHE_NEW_GS_PROG (1<<BRW_GS_PROG)
684 #define CACHE_NEW_CLIP_VP (1<<BRW_CLIP_VP)
685 #define CACHE_NEW_CLIP_UNIT (1<<BRW_CLIP_UNIT)
686 #define CACHE_NEW_CLIP_PROG (1<<BRW_CLIP_PROG)
688 struct brw_cached_batch_item {
689 struct header *header;
691 struct brw_cached_batch_item *next;
696 /* Protect against a future where VERT_ATTRIB_MAX > 32. Wouldn't life
697 * be easier if C allowed arrays of packed elements?
699 #define ATTRIB_BIT_DWORDS ((VERT_ATTRIB_MAX+31)/32)
701 struct brw_vertex_buffer {
702 /** Buffer object containing the uploaded vertex data */
705 /** Byte stride between elements in the uploaded array */
709 struct brw_vertex_element {
710 const struct gl_client_array *glarray;
714 /** The corresponding Mesa vertex attribute */
715 gl_vert_attrib attrib;
716 /** Offset of the first element within the buffer object */
722 struct brw_vertex_info {
723 GLuint sizes[ATTRIB_BIT_DWORDS * 2]; /* sizes:2[VERT_ATTRIB_MAX] */
726 struct brw_query_object {
727 struct gl_query_object Base;
729 /** Last query BO associated with this query. */
732 /** Last index in bo with query data for this object. */
738 * brw_context is derived from intel_context.
742 struct intel_context intel; /**< base class, must be first field */
743 GLuint primitive; /**< Hardware primitive, such as _3DPRIM_TRILIST. */
745 bool emit_state_always;
746 bool has_surface_tile_offset;
748 bool has_negative_rhw_bug;
749 bool has_aa_line_parameters;
754 * Some versions of Gen hardware don't do centroid interpolation correctly
755 * on unlit pixels, causing incorrect values for derivatives near triangle
756 * edges. Enabling this flag causes the fragment shader to use
757 * non-centroid interpolation for unlit pixels, at the expense of two extra
758 * fragment shader instructions.
760 bool needs_unlit_centroid_workaround;
763 struct brw_state_flags dirty;
766 struct brw_cache cache;
767 struct brw_cached_batch_item *cached_batch_items;
770 struct brw_vertex_element inputs[VERT_ATTRIB_MAX];
771 struct brw_vertex_buffer buffers[VERT_ATTRIB_MAX];
773 struct brw_vertex_element *enabled[VERT_ATTRIB_MAX];
777 /* Summary of size and varying of active arrays, so we can check
778 * for changes to this state:
780 struct brw_vertex_info info;
781 unsigned int min_index, max_index;
783 /* Offset from start of vertex buffer so we can avoid redefining
784 * the same VB packed over and over again.
786 unsigned int start_vertex_bias;
791 * Index buffer for this draw_prims call.
793 * Updates are signaled by BRW_NEW_INDICES.
795 const struct _mesa_index_buffer *ib;
797 /* Updates are signaled by BRW_NEW_INDEX_BUFFER. */
801 /* Offset to index buffer index to use in CMD_3D_PRIM so that we can
802 * avoid re-uploading the IB packet over and over if we're actually
803 * referencing the same index buffer.
805 unsigned int start_vertex_offset;
808 /* Active vertex program:
810 const struct gl_vertex_program *vertex_program;
811 const struct gl_fragment_program *fragment_program;
813 /* hw-dependent 3DSTATE_VF_STATISTICS opcode */
814 uint32_t CMD_VF_STATISTICS;
815 /* hw-dependent 3DSTATE_PIPELINE_SELECT opcode */
816 uint32_t CMD_PIPELINE_SELECT;
819 * Platform specific constants containing the maximum number of threads
820 * for each pipeline stage.
826 /* BRW_NEW_URB_ALLOCATIONS:
829 GLuint vsize; /* vertex size plus header in urb registers */
830 GLuint csize; /* constant buffer size in urb registers */
831 GLuint sfsize; /* setup data size in urb registers */
835 GLuint max_vs_entries; /* Maximum number of VS entries */
836 GLuint max_gs_entries; /* Maximum number of GS entries */
838 GLuint nr_vs_entries;
839 GLuint nr_gs_entries;
840 GLuint nr_clip_entries;
841 GLuint nr_sf_entries;
842 GLuint nr_cs_entries;
845 * The length of each URB entry owned by the VS (or GS), as
846 * a number of 1024-bit (128-byte) rows. Should be >= 1.
848 * gen7: Same meaning, but in 512-bit (64-byte) rows.
858 GLuint size; /* Hardware URB size, in KB. */
860 /* gen6: True if the most recently sent _3DSTATE_URB message allocated
861 * URB space for the GS.
863 bool gen6_gs_previously_active;
867 /* BRW_NEW_CURBE_OFFSETS:
870 GLuint wm_start; /**< pos of first wm const in CURBE buffer */
871 GLuint wm_size; /**< number of float[4] consts, multiple of 16 */
878 drm_intel_bo *curbe_bo;
879 /** Offset within curbe_bo of space for current curbe entry */
881 /** Offset within curbe_bo of space for next curbe entry */
882 GLuint curbe_next_offset;
885 * Copy of the last set of CURBEs uploaded. Frequently we'll end up
886 * in brw_curbe.c with the same set of constant data to be uploaded,
887 * so we'd rather not upload new constants in that case (it can cause
888 * a pipeline bubble since only up to 4 can be pipelined at a time).
892 * Allocation for where to calculate the next set of CURBEs.
893 * It's a hot enough path that malloc/free of that data matters.
899 /** SAMPLER_STATE count and offset */
906 struct brw_vs_prog_data *prog_data;
908 drm_intel_bo *scratch_bo;
909 drm_intel_bo *const_bo;
910 /** Offset in the program cache to the VS program */
911 uint32_t prog_offset;
912 uint32_t state_offset;
914 uint32_t push_const_offset; /* Offset in the batchbuffer */
915 int push_const_size; /* in 256-bit register increments */
917 /** @{ register allocator */
919 struct ra_regs *regs;
922 * Array of the ra classes for the unaligned contiguous register
928 * Mapping for register-allocated objects in *regs to the first
929 * GRF for that object.
931 uint8_t *ra_reg_to_grf;
934 uint32_t bind_bo_offset;
935 uint32_t surf_offset[BRW_MAX_VS_SURFACES];
939 struct brw_gs_prog_data *prog_data;
942 /** Offset in the program cache to the CLIP program pre-gen6 */
943 uint32_t prog_offset;
944 uint32_t state_offset;
946 uint32_t bind_bo_offset;
947 uint32_t surf_offset[BRW_MAX_GS_SURFACES];
951 struct brw_clip_prog_data *prog_data;
953 /** Offset in the program cache to the CLIP program pre-gen6 */
954 uint32_t prog_offset;
956 /* Offset in the batch to the CLIP state on pre-gen6. */
957 uint32_t state_offset;
959 /* As of gen6, this is the offset in the batch to the CLIP VP,
967 struct brw_sf_prog_data *prog_data;
969 /** Offset in the program cache to the CLIP program pre-gen6 */
970 uint32_t prog_offset;
971 uint32_t state_offset;
976 struct brw_wm_prog_data *prog_data;
978 /** Input sizes, calculated from active vertex program.
979 * One bit per fragment program input attribute.
981 GLbitfield input_size_masks[4];
983 /** offsets in the batch to sampler default colors (texture border color)
985 uint32_t sdc_offset[BRW_MAX_TEX_UNIT];
989 drm_intel_bo *scratch_bo;
992 * Buffer object used in place of multisampled null render targets on
993 * Gen6. See brw_update_null_renderbuffer_surface().
995 drm_intel_bo *multisampled_null_render_target_bo;
997 /** Offset in the program cache to the WM program */
998 uint32_t prog_offset;
1000 uint32_t state_offset; /* offset in batchbuffer to pre-gen6 WM state */
1002 drm_intel_bo *const_bo; /* pull constant buffer. */
1004 * This is offset in the batch to the push constants on gen6.
1006 * Pre-gen6, push constants live in the CURBE.
1008 uint32_t push_const_offset;
1010 /** Binding table of pointers to surf_bo entries */
1011 uint32_t bind_bo_offset;
1012 uint32_t surf_offset[BRW_MAX_WM_SURFACES];
1015 struct ra_regs *regs;
1017 /** Array of the ra classes for the unaligned contiguous
1018 * register block sizes used.
1023 * Mapping for register-allocated objects in *regs to the first
1024 * GRF for that object.
1026 uint8_t *ra_reg_to_grf;
1029 * ra class for the aligned pairs we use for PLN, which doesn't
1030 * appear in *classes.
1032 int aligned_pairs_class;
1038 uint32_t state_offset;
1039 uint32_t blend_state_offset;
1040 uint32_t depth_stencil_state_offset;
1045 struct brw_query_object *obj;
1050 const struct brw_tracked_state **atoms;
1052 /* If (INTEL_DEBUG & DEBUG_BATCH) */
1056 enum state_struct_type type;
1057 } *state_batch_list;
1058 int state_batch_count;
1060 struct brw_sol_state {
1061 uint32_t svbi_0_starting_index;
1062 uint32_t svbi_0_max_index;
1063 uint32_t offset_0_batch_start;
1064 uint32_t primitives_generated;
1065 uint32_t primitives_written;
1066 bool counting_primitives_generated;
1067 bool counting_primitives_written;
1070 uint32_t render_target_format[MESA_FORMAT_COUNT];
1071 bool format_supported_as_render_target[MESA_FORMAT_COUNT];
1073 /* PrimitiveRestart */
1076 bool enable_cut_index;
1079 /** Computed depth/stencil/hiz state from the current attached
1080 * renderbuffers, valid only during the drawing state upload loop after
1081 * brw_workaround_depthstencil_alignment().
1084 struct intel_mipmap_tree *depth_mt;
1085 struct intel_mipmap_tree *stencil_mt;
1086 struct intel_mipmap_tree *hiz_mt;
1088 /* Inter-tile (page-aligned) byte offsets. */
1089 uint32_t depth_offset, hiz_offset, stencil_offset;
1090 /* Intra-tile x,y offsets for drawing to depth/stencil/hiz */
1091 uint32_t tile_x, tile_y;
1094 uint32_t num_instances;
1099 struct gl_shader_program **programs;
1100 enum shader_time_shader_type *types;
1101 uint64_t *cumulative;
1108 /*======================================================================
1111 void brwInitVtbl( struct brw_context *brw );
1113 /*======================================================================
1116 bool brwCreateContext(int api,
1117 const struct gl_config *mesaVis,
1118 __DRIcontext *driContextPriv,
1119 unsigned major_version,
1120 unsigned minor_version,
1123 void *sharedContextPrivate);
1125 /*======================================================================
1128 void brw_get_depthstencil_tile_masks(struct intel_mipmap_tree *depth_mt,
1129 struct intel_mipmap_tree *stencil_mt,
1130 uint32_t *out_tile_mask_x,
1131 uint32_t *out_tile_mask_y);
1132 void brw_workaround_depthstencil_alignment(struct brw_context *brw);
1134 /*======================================================================
1137 void brw_init_queryobj_functions(struct dd_function_table *functions);
1138 void brw_emit_query_begin(struct brw_context *brw);
1139 void brw_emit_query_end(struct brw_context *brw);
1141 /*======================================================================
1144 void brw_debug_batch(struct intel_context *intel);
1145 void brw_annotate_aub(struct intel_context *intel);
1147 /*======================================================================
1150 void brw_validate_textures( struct brw_context *brw );
1153 /*======================================================================
1156 void brwInitFragProgFuncs( struct dd_function_table *functions );
1158 int brw_get_scratch_size(int size);
1159 void brw_get_scratch_bo(struct intel_context *intel,
1160 drm_intel_bo **scratch_bo, int size);
1161 void brw_init_shader_time(struct brw_context *brw);
1162 void brw_collect_and_report_shader_time(struct brw_context *brw);
1163 void brw_destroy_shader_time(struct brw_context *brw);
1167 void brw_upload_urb_fence(struct brw_context *brw);
1171 void brw_upload_cs_urb_state(struct brw_context *brw);
1173 /* brw_fs_reg_allocate.cpp
1175 void brw_fs_alloc_reg_sets(struct brw_context *brw);
1178 int brw_disasm (FILE *file, struct brw_instruction *inst, int gen);
1181 gl_clip_plane *brw_select_clip_planes(struct gl_context *ctx);
1183 /* brw_wm_surface_state.c */
1184 void brw_init_surface_formats(struct brw_context *brw);
1186 brw_update_sol_surface(struct brw_context *brw,
1187 struct gl_buffer_object *buffer_obj,
1188 uint32_t *out_offset, unsigned num_vector_components,
1189 unsigned stride_dwords, unsigned offset_dwords);
1190 void brw_upload_ubo_surfaces(struct brw_context *brw,
1191 struct gl_shader *shader,
1192 uint32_t *surf_offsets);
1196 brw_begin_transform_feedback(struct gl_context *ctx, GLenum mode,
1197 struct gl_transform_feedback_object *obj);
1199 brw_end_transform_feedback(struct gl_context *ctx,
1200 struct gl_transform_feedback_object *obj);
1202 /* gen7_sol_state.c */
1204 gen7_end_transform_feedback(struct gl_context *ctx,
1205 struct gl_transform_feedback_object *obj);
1207 /* brw_blorp_blit.cpp */
1209 brw_blorp_framebuffer(struct intel_context *intel,
1210 GLint srcX0, GLint srcY0, GLint srcX1, GLint srcY1,
1211 GLint dstX0, GLint dstY0, GLint dstX1, GLint dstY1,
1212 GLbitfield mask, GLenum filter);
1215 brw_blorp_copytexsubimage(struct intel_context *intel,
1216 struct gl_renderbuffer *src_rb,
1217 struct gl_texture_image *dst_image,
1218 int srcX0, int srcY0,
1219 int dstX0, int dstY0,
1220 int width, int height);
1222 /* gen6_multisample_state.c */
1224 gen6_emit_3dstate_multisample(struct brw_context *brw,
1225 unsigned num_samples);
1227 gen6_emit_3dstate_sample_mask(struct brw_context *brw,
1228 unsigned num_samples, float coverage,
1229 bool coverage_invert, unsigned sample_mask);
1231 gen6_get_sample_position(struct gl_context *ctx,
1232 struct gl_framebuffer *fb,
1238 gen7_allocate_push_constants(struct brw_context *brw);
1241 gen7_emit_urb_state(struct brw_context *brw, GLuint nr_vs_entries,
1242 GLuint vs_size, GLuint vs_start);
1246 /*======================================================================
1247 * Inline conversion functions. These are better-typed than the
1248 * macros used previously:
1250 static INLINE struct brw_context *
1251 brw_context( struct gl_context *ctx )
1253 return (struct brw_context *)ctx;
1256 static INLINE struct brw_vertex_program *
1257 brw_vertex_program(struct gl_vertex_program *p)
1259 return (struct brw_vertex_program *) p;
1262 static INLINE const struct brw_vertex_program *
1263 brw_vertex_program_const(const struct gl_vertex_program *p)
1265 return (const struct brw_vertex_program *) p;
1268 static INLINE struct brw_fragment_program *
1269 brw_fragment_program(struct gl_fragment_program *p)
1271 return (struct brw_fragment_program *) p;
1274 static INLINE const struct brw_fragment_program *
1275 brw_fragment_program_const(const struct gl_fragment_program *p)
1277 return (const struct brw_fragment_program *) p;
1281 * Pre-gen6, the register file of the EUs was shared between threads,
1282 * and each thread used some subset allocated on a 16-register block
1283 * granularity. The unit states wanted these block counts.
1286 brw_register_blocks(int reg_count)
1288 return ALIGN(reg_count, 16) / 16 - 1;
1291 static inline uint32_t
1292 brw_program_reloc(struct brw_context *brw, uint32_t state_offset,
1293 uint32_t prog_offset)
1295 struct intel_context *intel = &brw->intel;
1297 if (intel->gen >= 5) {
1298 /* Using state base address. */
1302 drm_intel_bo_emit_reloc(intel->batch.bo,
1306 I915_GEM_DOMAIN_INSTRUCTION, 0);
1308 return brw->cache.bo->offset + prog_offset;
1311 bool brw_do_cubemap_normalize(struct exec_list *instructions);
1312 bool brw_lower_texture_gradients(struct exec_list *instructions);
1314 struct opcode_desc {
1320 extern const struct opcode_desc opcode_descs[128];