2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 * This file drives the GLSL IR -> LIR translation, contains the
27 * optimizations on the LIR, and drives the generation of native code
33 #include <sys/types.h>
35 #include "main/macros.h"
36 #include "main/shaderobj.h"
37 #include "main/uniforms.h"
38 #include "main/fbobject.h"
39 #include "program/prog_parameter.h"
40 #include "program/prog_print.h"
41 #include "program/register_allocate.h"
42 #include "program/sampler.h"
43 #include "program/hash_table.h"
44 #include "brw_context.h"
49 #include "glsl/glsl_types.h"
50 #include "glsl/ir_print_visitor.h"
55 memset(this, 0, sizeof(*this));
56 this->opcode = BRW_OPCODE_NOP;
57 this->conditional_mod = BRW_CONDITIONAL_NONE;
59 this->dst = reg_undef;
60 this->src[0] = reg_undef;
61 this->src[1] = reg_undef;
62 this->src[2] = reg_undef;
70 fs_inst::fs_inst(enum opcode opcode)
73 this->opcode = opcode;
76 fs_inst::fs_inst(enum opcode opcode, fs_reg dst)
79 this->opcode = opcode;
83 assert(dst.reg_offset >= 0);
86 fs_inst::fs_inst(enum opcode opcode, fs_reg dst, fs_reg src0)
89 this->opcode = opcode;
94 assert(dst.reg_offset >= 0);
95 if (src[0].file == GRF)
96 assert(src[0].reg_offset >= 0);
99 fs_inst::fs_inst(enum opcode opcode, fs_reg dst, fs_reg src0, fs_reg src1)
102 this->opcode = opcode;
108 assert(dst.reg_offset >= 0);
109 if (src[0].file == GRF)
110 assert(src[0].reg_offset >= 0);
111 if (src[1].file == GRF)
112 assert(src[1].reg_offset >= 0);
115 fs_inst::fs_inst(enum opcode opcode, fs_reg dst,
116 fs_reg src0, fs_reg src1, fs_reg src2)
119 this->opcode = opcode;
126 assert(dst.reg_offset >= 0);
127 if (src[0].file == GRF)
128 assert(src[0].reg_offset >= 0);
129 if (src[1].file == GRF)
130 assert(src[1].reg_offset >= 0);
131 if (src[2].file == GRF)
132 assert(src[2].reg_offset >= 0);
137 fs_visitor::op(fs_reg dst, fs_reg src0) \
139 return new(mem_ctx) fs_inst(BRW_OPCODE_##op, dst, src0); \
144 fs_visitor::op(fs_reg dst, fs_reg src0, fs_reg src1) \
146 return new(mem_ctx) fs_inst(BRW_OPCODE_##op, dst, src0, src1); \
151 fs_visitor::op(fs_reg dst, fs_reg src0, fs_reg src1, fs_reg src2) \
153 return new(mem_ctx) fs_inst(BRW_OPCODE_##op, dst, src0, src1, src2);\
173 /** Gen4 predicated IF. */
175 fs_visitor::IF(uint32_t predicate)
177 fs_inst *inst = new(mem_ctx) fs_inst(BRW_OPCODE_IF);
178 inst->predicate = predicate;
182 /** Gen6+ IF with embedded comparison. */
184 fs_visitor::IF(fs_reg src0, fs_reg src1, uint32_t condition)
186 assert(intel->gen >= 6);
187 fs_inst *inst = new(mem_ctx) fs_inst(BRW_OPCODE_IF,
188 reg_null_d, src0, src1);
189 inst->conditional_mod = condition;
194 * CMP: Sets the low bit of the destination channels with the result
195 * of the comparison, while the upper bits are undefined, and updates
196 * the flag register with the packed 16 bits of the result.
199 fs_visitor::CMP(fs_reg dst, fs_reg src0, fs_reg src1, uint32_t condition)
203 /* Take the instruction:
205 * CMP null<d> src0<f> src1<f>
207 * Original gen4 does type conversion to the destination type before
208 * comparison, producing garbage results for floating point comparisons.
209 * gen5 does the comparison on the execution type (resolved source types),
210 * so dst type doesn't matter. gen6 does comparison and then uses the
211 * result as if it was the dst type with no conversion, which happens to
212 * mostly work out for float-interpreted-as-int since our comparisons are
215 if (intel->gen == 4) {
216 dst.type = src0.type;
217 if (dst.file == FIXED_HW_REG)
218 dst.fixed_hw_reg.type = dst.type;
221 resolve_ud_negate(&src0);
222 resolve_ud_negate(&src1);
224 inst = new(mem_ctx) fs_inst(BRW_OPCODE_CMP, dst, src0, src1);
225 inst->conditional_mod = condition;
231 fs_visitor::VARYING_PULL_CONSTANT_LOAD(fs_reg dst, fs_reg surf_index,
234 exec_list instructions;
237 if (intel->gen >= 7) {
238 inst = new(mem_ctx) fs_inst(FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7,
239 dst, surf_index, offset);
240 instructions.push_tail(inst);
243 bool header_present = true;
245 fs_reg mrf = fs_reg(MRF, base_mrf + header_present);
246 mrf.type = BRW_REGISTER_TYPE_D;
248 /* On gen6+ we want the dword offset passed in, but on gen4/5 we need a
249 * dword-aligned byte offset.
251 if (intel->gen == 6) {
252 instructions.push_tail(MOV(mrf, offset));
254 instructions.push_tail(MUL(mrf, offset, fs_reg(4)));
256 inst = MOV(mrf, offset);
257 inst = new(mem_ctx) fs_inst(FS_OPCODE_VARYING_PULL_CONSTANT_LOAD,
259 inst->header_present = header_present;
260 inst->base_mrf = base_mrf;
261 inst->mlen = header_present + dispatch_width / 8;
263 instructions.push_tail(inst);
270 * A helper for MOV generation for fixing up broken hardware SEND dependency
274 fs_visitor::DEP_RESOLVE_MOV(int grf)
276 fs_inst *inst = MOV(brw_null_reg(), fs_reg(GRF, grf, BRW_REGISTER_TYPE_F));
279 inst->annotation = "send dependency resolve";
281 /* The caller always wants uncompressed to emit the minimal extra
282 * dependencies, and to avoid having to deal with aligning its regs to 2.
284 inst->force_uncompressed = true;
290 fs_inst::equals(fs_inst *inst)
292 return (opcode == inst->opcode &&
293 dst.equals(inst->dst) &&
294 src[0].equals(inst->src[0]) &&
295 src[1].equals(inst->src[1]) &&
296 src[2].equals(inst->src[2]) &&
297 saturate == inst->saturate &&
298 predicate == inst->predicate &&
299 conditional_mod == inst->conditional_mod &&
300 mlen == inst->mlen &&
301 base_mrf == inst->base_mrf &&
302 sampler == inst->sampler &&
303 target == inst->target &&
305 header_present == inst->header_present &&
306 shadow_compare == inst->shadow_compare &&
307 offset == inst->offset);
311 fs_inst::regs_written()
316 /* The SINCOS and INT_DIV_QUOTIENT_AND_REMAINDER math functions return 2,
317 * but we don't currently use them...nor do we have an opcode for them.
324 fs_inst::overwrites_reg(const fs_reg ®)
326 return (reg.file == dst.file &&
327 reg.reg == dst.reg &&
328 reg.reg_offset >= dst.reg_offset &&
329 reg.reg_offset < dst.reg_offset + regs_written());
335 return (opcode == SHADER_OPCODE_TEX ||
336 opcode == FS_OPCODE_TXB ||
337 opcode == SHADER_OPCODE_TXD ||
338 opcode == SHADER_OPCODE_TXF ||
339 opcode == SHADER_OPCODE_TXL ||
340 opcode == SHADER_OPCODE_TXS);
346 return (opcode == SHADER_OPCODE_RCP ||
347 opcode == SHADER_OPCODE_RSQ ||
348 opcode == SHADER_OPCODE_SQRT ||
349 opcode == SHADER_OPCODE_EXP2 ||
350 opcode == SHADER_OPCODE_LOG2 ||
351 opcode == SHADER_OPCODE_SIN ||
352 opcode == SHADER_OPCODE_COS ||
353 opcode == SHADER_OPCODE_INT_QUOTIENT ||
354 opcode == SHADER_OPCODE_INT_REMAINDER ||
355 opcode == SHADER_OPCODE_POW);
359 fs_inst::is_control_flow()
363 case BRW_OPCODE_WHILE:
365 case BRW_OPCODE_ELSE:
366 case BRW_OPCODE_ENDIF:
367 case BRW_OPCODE_BREAK:
368 case BRW_OPCODE_CONTINUE:
376 fs_inst::is_send_from_grf()
378 return (opcode == FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7 ||
379 (opcode == FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD &&
380 src[1].file == GRF));
384 fs_visitor::can_do_source_mods(fs_inst *inst)
386 if (intel->gen == 6 && inst->is_math())
389 if (inst->is_send_from_grf())
398 memset(this, 0, sizeof(*this));
402 /** Generic unset register constructor. */
406 this->file = BAD_FILE;
409 /** Immediate value constructor. */
410 fs_reg::fs_reg(float f)
414 this->type = BRW_REGISTER_TYPE_F;
418 /** Immediate value constructor. */
419 fs_reg::fs_reg(int32_t i)
423 this->type = BRW_REGISTER_TYPE_D;
427 /** Immediate value constructor. */
428 fs_reg::fs_reg(uint32_t u)
432 this->type = BRW_REGISTER_TYPE_UD;
436 /** Fixed brw_reg Immediate value constructor. */
437 fs_reg::fs_reg(struct brw_reg fixed_hw_reg)
440 this->file = FIXED_HW_REG;
441 this->fixed_hw_reg = fixed_hw_reg;
442 this->type = fixed_hw_reg.type;
446 fs_reg::equals(const fs_reg &r) const
448 return (file == r.file &&
450 reg_offset == r.reg_offset &&
452 negate == r.negate &&
454 !reladdr && !r.reladdr &&
455 memcmp(&fixed_hw_reg, &r.fixed_hw_reg,
456 sizeof(fixed_hw_reg)) == 0 &&
462 fs_reg::is_zero() const
467 return type == BRW_REGISTER_TYPE_F ? imm.f == 0.0 : imm.i == 0;
471 fs_reg::is_one() const
476 return type == BRW_REGISTER_TYPE_F ? imm.f == 1.0 : imm.i == 1;
480 fs_visitor::type_size(const struct glsl_type *type)
482 unsigned int size, i;
484 switch (type->base_type) {
487 case GLSL_TYPE_FLOAT:
489 return type->components();
490 case GLSL_TYPE_ARRAY:
491 return type_size(type->fields.array) * type->length;
492 case GLSL_TYPE_STRUCT:
494 for (i = 0; i < type->length; i++) {
495 size += type_size(type->fields.structure[i].type);
498 case GLSL_TYPE_SAMPLER:
499 /* Samplers take up no register space, since they're baked in at
504 case GLSL_TYPE_ERROR:
505 case GLSL_TYPE_INTERFACE:
506 assert(!"not reached");
514 fs_visitor::get_timestamp()
516 assert(intel->gen >= 7);
518 fs_reg ts = fs_reg(retype(brw_vec1_reg(BRW_ARCHITECTURE_REGISTER_FILE,
521 BRW_REGISTER_TYPE_UD));
523 fs_reg dst = fs_reg(this, glsl_type::uint_type);
525 fs_inst *mov = emit(MOV(dst, ts));
526 /* We want to read the 3 fields we care about (mostly field 0, but also 2)
527 * even if it's not enabled in the dispatch.
529 mov->force_writemask_all = true;
530 mov->force_uncompressed = true;
532 /* The caller wants the low 32 bits of the timestamp. Since it's running
533 * at the GPU clock rate of ~1.2ghz, it will roll over every ~3 seconds,
534 * which is plenty of time for our purposes. It is identical across the
535 * EUs, but since it's tracking GPU core speed it will increment at a
536 * varying rate as render P-states change.
538 * The caller could also check if render P-states have changed (or anything
539 * else that might disrupt timing) by setting smear to 2 and checking if
540 * that field is != 0.
548 fs_visitor::emit_shader_time_begin()
550 current_annotation = "shader time start";
551 shader_start_time = get_timestamp();
555 fs_visitor::emit_shader_time_end()
557 current_annotation = "shader time end";
559 enum shader_time_shader_type type, written_type, reset_type;
560 if (dispatch_width == 8) {
562 written_type = ST_FS8_WRITTEN;
563 reset_type = ST_FS8_RESET;
565 assert(dispatch_width == 16);
567 written_type = ST_FS16_WRITTEN;
568 reset_type = ST_FS16_RESET;
571 fs_reg shader_end_time = get_timestamp();
573 /* Check that there weren't any timestamp reset events (assuming these
574 * were the only two timestamp reads that happened).
576 fs_reg reset = shader_end_time;
578 fs_inst *test = emit(AND(reg_null_d, reset, fs_reg(1u)));
579 test->conditional_mod = BRW_CONDITIONAL_Z;
580 emit(IF(BRW_PREDICATE_NORMAL));
582 push_force_uncompressed();
583 fs_reg start = shader_start_time;
585 fs_reg diff = fs_reg(this, glsl_type::uint_type);
586 emit(ADD(diff, start, shader_end_time));
588 /* If there were no instructions between the two timestamp gets, the diff
589 * is 2 cycles. Remove that overhead, so I can forget about that when
590 * trying to determine the time taken for single instructions.
592 emit(ADD(diff, diff, fs_reg(-2u)));
594 emit_shader_time_write(type, diff);
595 emit_shader_time_write(written_type, fs_reg(1u));
596 emit(BRW_OPCODE_ELSE);
597 emit_shader_time_write(reset_type, fs_reg(1u));
598 emit(BRW_OPCODE_ENDIF);
600 pop_force_uncompressed();
604 fs_visitor::emit_shader_time_write(enum shader_time_shader_type type,
607 /* Choose an index in the buffer and set up tracking information for our
610 int shader_time_index = brw->shader_time.num_entries++;
611 assert(shader_time_index <= brw->shader_time.max_entries);
612 brw->shader_time.types[shader_time_index] = type;
614 _mesa_reference_shader_program(ctx,
615 &brw->shader_time.programs[shader_time_index],
621 fs_reg offset_mrf = fs_reg(MRF, base_mrf);
622 offset_mrf.type = BRW_REGISTER_TYPE_UD;
623 emit(MOV(offset_mrf, fs_reg(shader_time_index * 4)));
625 fs_reg time_mrf = fs_reg(MRF, base_mrf + 1);
626 time_mrf.type = BRW_REGISTER_TYPE_UD;
627 emit(MOV(time_mrf, value));
629 fs_inst *inst = emit(fs_inst(SHADER_OPCODE_SHADER_TIME_ADD));
630 inst->base_mrf = base_mrf;
635 fs_visitor::fail(const char *format, ...)
645 va_start(va, format);
646 msg = ralloc_vasprintf(mem_ctx, format, va);
648 msg = ralloc_asprintf(mem_ctx, "FS compile failed: %s\n", msg);
650 this->fail_msg = msg;
652 if (INTEL_DEBUG & DEBUG_WM) {
653 fprintf(stderr, "%s", msg);
658 fs_visitor::emit(enum opcode opcode)
660 return emit(fs_inst(opcode));
664 fs_visitor::emit(enum opcode opcode, fs_reg dst)
666 return emit(fs_inst(opcode, dst));
670 fs_visitor::emit(enum opcode opcode, fs_reg dst, fs_reg src0)
672 return emit(fs_inst(opcode, dst, src0));
676 fs_visitor::emit(enum opcode opcode, fs_reg dst, fs_reg src0, fs_reg src1)
678 return emit(fs_inst(opcode, dst, src0, src1));
682 fs_visitor::emit(enum opcode opcode, fs_reg dst,
683 fs_reg src0, fs_reg src1, fs_reg src2)
685 return emit(fs_inst(opcode, dst, src0, src1, src2));
689 fs_visitor::push_force_uncompressed()
691 force_uncompressed_stack++;
695 fs_visitor::pop_force_uncompressed()
697 force_uncompressed_stack--;
698 assert(force_uncompressed_stack >= 0);
702 fs_visitor::push_force_sechalf()
704 force_sechalf_stack++;
708 fs_visitor::pop_force_sechalf()
710 force_sechalf_stack--;
711 assert(force_sechalf_stack >= 0);
715 * Returns how many MRFs an FS opcode will write over.
717 * Note that this is not the 0 or 1 implied writes in an actual gen
718 * instruction -- the FS opcodes often generate MOVs in addition.
721 fs_visitor::implied_mrf_writes(fs_inst *inst)
726 switch (inst->opcode) {
727 case SHADER_OPCODE_RCP:
728 case SHADER_OPCODE_RSQ:
729 case SHADER_OPCODE_SQRT:
730 case SHADER_OPCODE_EXP2:
731 case SHADER_OPCODE_LOG2:
732 case SHADER_OPCODE_SIN:
733 case SHADER_OPCODE_COS:
734 return 1 * dispatch_width / 8;
735 case SHADER_OPCODE_POW:
736 case SHADER_OPCODE_INT_QUOTIENT:
737 case SHADER_OPCODE_INT_REMAINDER:
738 return 2 * dispatch_width / 8;
739 case SHADER_OPCODE_TEX:
741 case SHADER_OPCODE_TXD:
742 case SHADER_OPCODE_TXF:
743 case SHADER_OPCODE_TXL:
744 case SHADER_OPCODE_TXS:
746 case SHADER_OPCODE_SHADER_TIME_ADD:
748 case FS_OPCODE_FB_WRITE:
750 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD:
751 case FS_OPCODE_UNSPILL:
753 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD:
754 return inst->header_present;
755 case FS_OPCODE_SPILL:
758 assert(!"not reached");
764 fs_visitor::virtual_grf_alloc(int size)
766 if (virtual_grf_array_size <= virtual_grf_count) {
767 if (virtual_grf_array_size == 0)
768 virtual_grf_array_size = 16;
770 virtual_grf_array_size *= 2;
771 virtual_grf_sizes = reralloc(mem_ctx, virtual_grf_sizes, int,
772 virtual_grf_array_size);
774 virtual_grf_sizes[virtual_grf_count] = size;
775 return virtual_grf_count++;
778 /** Fixed HW reg constructor. */
779 fs_reg::fs_reg(enum register_file file, int reg)
784 this->type = BRW_REGISTER_TYPE_F;
787 /** Fixed HW reg constructor. */
788 fs_reg::fs_reg(enum register_file file, int reg, uint32_t type)
796 /** Automatic reg constructor. */
797 fs_reg::fs_reg(class fs_visitor *v, const struct glsl_type *type)
802 this->reg = v->virtual_grf_alloc(v->type_size(type));
803 this->reg_offset = 0;
804 this->type = brw_type_for_base_type(type);
808 fs_visitor::variable_storage(ir_variable *var)
810 return (fs_reg *)hash_table_find(this->variable_ht, var);
814 import_uniforms_callback(const void *key,
818 struct hash_table *dst_ht = (struct hash_table *)closure;
819 const fs_reg *reg = (const fs_reg *)data;
821 if (reg->file != UNIFORM)
824 hash_table_insert(dst_ht, data, key);
827 /* For 16-wide, we need to follow from the uniform setup of 8-wide dispatch.
828 * This brings in those uniform definitions
831 fs_visitor::import_uniforms(fs_visitor *v)
833 hash_table_call_foreach(v->variable_ht,
834 import_uniforms_callback,
836 this->params_remap = v->params_remap;
839 /* Our support for uniforms is piggy-backed on the struct
840 * gl_fragment_program, because that's where the values actually
841 * get stored, rather than in some global gl_shader_program uniform
845 fs_visitor::setup_uniform_values(ir_variable *ir)
847 int namelen = strlen(ir->name);
849 /* The data for our (non-builtin) uniforms is stored in a series of
850 * gl_uniform_driver_storage structs for each subcomponent that
851 * glGetUniformLocation() could name. We know it's been set up in the same
852 * order we'd walk the type, so walk the list of storage and find anything
853 * with our name, or the prefix of a component that starts with our name.
855 unsigned params_before = c->prog_data.nr_params;
856 for (unsigned u = 0; u < prog->NumUserUniformStorage; u++) {
857 struct gl_uniform_storage *storage = &prog->UniformStorage[u];
859 if (strncmp(ir->name, storage->name, namelen) != 0 ||
860 (storage->name[namelen] != 0 &&
861 storage->name[namelen] != '.' &&
862 storage->name[namelen] != '[')) {
866 unsigned slots = storage->type->component_slots();
867 if (storage->array_elements)
868 slots *= storage->array_elements;
870 for (unsigned i = 0; i < slots; i++) {
871 c->prog_data.param[c->prog_data.nr_params++] =
872 &storage->storage[i].f;
876 /* Make sure we actually initialized the right amount of stuff here. */
877 assert(params_before + ir->type->component_slots() ==
878 c->prog_data.nr_params);
882 /* Our support for builtin uniforms is even scarier than non-builtin.
883 * It sits on top of the PROG_STATE_VAR parameters that are
884 * automatically updated from GL context state.
887 fs_visitor::setup_builtin_uniform_values(ir_variable *ir)
889 const ir_state_slot *const slots = ir->state_slots;
890 assert(ir->state_slots != NULL);
892 for (unsigned int i = 0; i < ir->num_state_slots; i++) {
893 /* This state reference has already been setup by ir_to_mesa, but we'll
894 * get the same index back here.
896 int index = _mesa_add_state_reference(this->fp->Base.Parameters,
897 (gl_state_index *)slots[i].tokens);
899 /* Add each of the unique swizzles of the element as a parameter.
900 * This'll end up matching the expected layout of the
901 * array/matrix/structure we're trying to fill in.
904 for (unsigned int j = 0; j < 4; j++) {
905 int swiz = GET_SWZ(slots[i].swizzle, j);
906 if (swiz == last_swiz)
910 c->prog_data.param[c->prog_data.nr_params++] =
911 &fp->Base.Parameters->ParameterValues[index][swiz].f;
917 fs_visitor::emit_fragcoord_interpolation(ir_variable *ir)
919 fs_reg *reg = new(this->mem_ctx) fs_reg(this, ir->type);
921 bool flip = !ir->origin_upper_left ^ c->key.render_to_fbo;
924 if (ir->pixel_center_integer) {
925 emit(MOV(wpos, this->pixel_x));
927 emit(ADD(wpos, this->pixel_x, fs_reg(0.5f)));
932 if (!flip && ir->pixel_center_integer) {
933 emit(MOV(wpos, this->pixel_y));
935 fs_reg pixel_y = this->pixel_y;
936 float offset = (ir->pixel_center_integer ? 0.0 : 0.5);
939 pixel_y.negate = true;
940 offset += c->key.drawable_height - 1.0;
943 emit(ADD(wpos, pixel_y, fs_reg(offset)));
948 if (intel->gen >= 6) {
949 emit(MOV(wpos, fs_reg(brw_vec8_grf(c->source_depth_reg, 0))));
951 emit(FS_OPCODE_LINTERP, wpos,
952 this->delta_x[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC],
953 this->delta_y[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC],
954 interp_reg(FRAG_ATTRIB_WPOS, 2));
958 /* gl_FragCoord.w: Already set up in emit_interpolation */
959 emit(BRW_OPCODE_MOV, wpos, this->wpos_w);
965 fs_visitor::emit_linterp(const fs_reg &attr, const fs_reg &interp,
966 glsl_interp_qualifier interpolation_mode,
969 brw_wm_barycentric_interp_mode barycoord_mode;
971 if (interpolation_mode == INTERP_QUALIFIER_SMOOTH)
972 barycoord_mode = BRW_WM_PERSPECTIVE_CENTROID_BARYCENTRIC;
974 barycoord_mode = BRW_WM_NONPERSPECTIVE_CENTROID_BARYCENTRIC;
976 if (interpolation_mode == INTERP_QUALIFIER_SMOOTH)
977 barycoord_mode = BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC;
979 barycoord_mode = BRW_WM_NONPERSPECTIVE_PIXEL_BARYCENTRIC;
981 return emit(FS_OPCODE_LINTERP, attr,
982 this->delta_x[barycoord_mode],
983 this->delta_y[barycoord_mode], interp);
987 fs_visitor::emit_general_interpolation(ir_variable *ir)
989 fs_reg *reg = new(this->mem_ctx) fs_reg(this, ir->type);
990 reg->type = brw_type_for_base_type(ir->type->get_scalar_type());
993 unsigned int array_elements;
994 const glsl_type *type;
996 if (ir->type->is_array()) {
997 array_elements = ir->type->length;
998 if (array_elements == 0) {
999 fail("dereferenced array '%s' has length 0\n", ir->name);
1001 type = ir->type->fields.array;
1007 glsl_interp_qualifier interpolation_mode =
1008 ir->determine_interpolation_mode(c->key.flat_shade);
1010 int location = ir->location;
1011 for (unsigned int i = 0; i < array_elements; i++) {
1012 for (unsigned int j = 0; j < type->matrix_columns; j++) {
1013 if (urb_setup[location] == -1) {
1014 /* If there's no incoming setup data for this slot, don't
1015 * emit interpolation for it.
1017 attr.reg_offset += type->vector_elements;
1022 if (interpolation_mode == INTERP_QUALIFIER_FLAT) {
1023 /* Constant interpolation (flat shading) case. The SF has
1024 * handed us defined values in only the constant offset
1025 * field of the setup reg.
1027 for (unsigned int k = 0; k < type->vector_elements; k++) {
1028 struct brw_reg interp = interp_reg(location, k);
1029 interp = suboffset(interp, 3);
1030 interp.type = reg->type;
1031 emit(FS_OPCODE_CINTERP, attr, fs_reg(interp));
1035 /* Smooth/noperspective interpolation case. */
1036 for (unsigned int k = 0; k < type->vector_elements; k++) {
1037 /* FINISHME: At some point we probably want to push
1038 * this farther by giving similar treatment to the
1039 * other potentially constant components of the
1040 * attribute, as well as making brw_vs_constval.c
1041 * handle varyings other than gl_TexCoord.
1043 if (location >= FRAG_ATTRIB_TEX0 &&
1044 location <= FRAG_ATTRIB_TEX7 &&
1045 k == 3 && !(c->key.proj_attrib_mask & (1 << location))) {
1046 emit(BRW_OPCODE_MOV, attr, fs_reg(1.0f));
1048 struct brw_reg interp = interp_reg(location, k);
1049 emit_linterp(attr, fs_reg(interp), interpolation_mode,
1051 if (brw->needs_unlit_centroid_workaround && ir->centroid) {
1052 /* Get the pixel/sample mask into f0 so that we know
1053 * which pixels are lit. Then, for each channel that is
1054 * unlit, replace the centroid data with non-centroid
1057 emit(FS_OPCODE_MOV_DISPATCH_TO_FLAGS, attr);
1058 fs_inst *inst = emit_linterp(attr, fs_reg(interp),
1059 interpolation_mode, false);
1060 inst->predicate = BRW_PREDICATE_NORMAL;
1061 inst->predicate_inverse = true;
1063 if (intel->gen < 6) {
1064 emit(BRW_OPCODE_MUL, attr, attr, this->pixel_w);
1079 fs_visitor::emit_frontfacing_interpolation(ir_variable *ir)
1081 fs_reg *reg = new(this->mem_ctx) fs_reg(this, ir->type);
1083 /* The frontfacing comes in as a bit in the thread payload. */
1084 if (intel->gen >= 6) {
1085 emit(BRW_OPCODE_ASR, *reg,
1086 fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_D)),
1088 emit(BRW_OPCODE_NOT, *reg, *reg);
1089 emit(BRW_OPCODE_AND, *reg, *reg, fs_reg(1));
1091 struct brw_reg r1_6ud = retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_UD);
1092 /* bit 31 is "primitive is back face", so checking < (1 << 31) gives
1095 emit(CMP(*reg, fs_reg(r1_6ud), fs_reg(1u << 31), BRW_CONDITIONAL_L));
1096 emit(BRW_OPCODE_AND, *reg, *reg, fs_reg(1u));
1103 fs_visitor::fix_math_operand(fs_reg src)
1105 /* Can't do hstride == 0 args on gen6 math, so expand it out. We
1106 * might be able to do better by doing execsize = 1 math and then
1107 * expanding that result out, but we would need to be careful with
1110 * The hardware ignores source modifiers (negate and abs) on math
1111 * instructions, so we also move to a temp to set those up.
1113 if (intel->gen == 6 && src.file != UNIFORM && src.file != IMM &&
1114 !src.abs && !src.negate)
1117 /* Gen7 relaxes most of the above restrictions, but still can't use IMM
1120 if (intel->gen >= 7 && src.file != IMM)
1123 fs_reg expanded = fs_reg(this, glsl_type::float_type);
1124 expanded.type = src.type;
1125 emit(BRW_OPCODE_MOV, expanded, src);
1130 fs_visitor::emit_math(enum opcode opcode, fs_reg dst, fs_reg src)
1133 case SHADER_OPCODE_RCP:
1134 case SHADER_OPCODE_RSQ:
1135 case SHADER_OPCODE_SQRT:
1136 case SHADER_OPCODE_EXP2:
1137 case SHADER_OPCODE_LOG2:
1138 case SHADER_OPCODE_SIN:
1139 case SHADER_OPCODE_COS:
1142 assert(!"not reached: bad math opcode");
1146 /* Can't do hstride == 0 args to gen6 math, so expand it out. We
1147 * might be able to do better by doing execsize = 1 math and then
1148 * expanding that result out, but we would need to be careful with
1151 * Gen 6 hardware ignores source modifiers (negate and abs) on math
1152 * instructions, so we also move to a temp to set those up.
1154 if (intel->gen >= 6)
1155 src = fix_math_operand(src);
1157 fs_inst *inst = emit(opcode, dst, src);
1159 if (intel->gen < 6) {
1161 inst->mlen = dispatch_width / 8;
1168 fs_visitor::emit_math(enum opcode opcode, fs_reg dst, fs_reg src0, fs_reg src1)
1174 case SHADER_OPCODE_INT_QUOTIENT:
1175 case SHADER_OPCODE_INT_REMAINDER:
1176 if (intel->gen >= 7 && dispatch_width == 16)
1177 fail("16-wide INTDIV unsupported\n");
1179 case SHADER_OPCODE_POW:
1182 assert(!"not reached: unsupported binary math opcode.");
1186 if (intel->gen >= 6) {
1187 src0 = fix_math_operand(src0);
1188 src1 = fix_math_operand(src1);
1190 inst = emit(opcode, dst, src0, src1);
1192 /* From the Ironlake PRM, Volume 4, Part 1, Section 6.1.13
1193 * "Message Payload":
1195 * "Operand0[7]. For the INT DIV functions, this operand is the
1198 * "Operand1[7]. For the INT DIV functions, this operand is the
1201 bool is_int_div = opcode != SHADER_OPCODE_POW;
1202 fs_reg &op0 = is_int_div ? src1 : src0;
1203 fs_reg &op1 = is_int_div ? src0 : src1;
1205 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + 1, op1.type), op1);
1206 inst = emit(opcode, dst, op0, reg_null_f);
1208 inst->base_mrf = base_mrf;
1209 inst->mlen = 2 * dispatch_width / 8;
1215 fs_visitor::assign_curb_setup()
1217 c->prog_data.curb_read_length = ALIGN(c->prog_data.nr_params, 8) / 8;
1218 if (dispatch_width == 8) {
1219 c->prog_data.first_curbe_grf = c->nr_payload_regs;
1221 c->prog_data.first_curbe_grf_16 = c->nr_payload_regs;
1224 /* Map the offsets in the UNIFORM file to fixed HW regs. */
1225 foreach_list(node, &this->instructions) {
1226 fs_inst *inst = (fs_inst *)node;
1228 for (unsigned int i = 0; i < 3; i++) {
1229 if (inst->src[i].file == UNIFORM) {
1230 int constant_nr = inst->src[i].reg + inst->src[i].reg_offset;
1231 struct brw_reg brw_reg = brw_vec1_grf(c->nr_payload_regs +
1235 inst->src[i].file = FIXED_HW_REG;
1236 inst->src[i].fixed_hw_reg = retype(brw_reg, inst->src[i].type);
1243 fs_visitor::calculate_urb_setup()
1245 for (unsigned int i = 0; i < FRAG_ATTRIB_MAX; i++) {
1250 /* Figure out where each of the incoming setup attributes lands. */
1251 if (intel->gen >= 6) {
1252 for (unsigned int i = 0; i < FRAG_ATTRIB_MAX; i++) {
1253 if (fp->Base.InputsRead & BITFIELD64_BIT(i)) {
1254 urb_setup[i] = urb_next++;
1258 /* FINISHME: The sf doesn't map VS->FS inputs for us very well. */
1259 for (unsigned int i = 0; i < VERT_RESULT_MAX; i++) {
1260 /* Point size is packed into the header, not as a general attribute */
1261 if (i == VERT_RESULT_PSIZ)
1264 if (c->key.vp_outputs_written & BITFIELD64_BIT(i)) {
1265 int fp_index = _mesa_vert_result_to_frag_attrib((gl_vert_result) i);
1267 /* The back color slot is skipped when the front color is
1268 * also written to. In addition, some slots can be
1269 * written in the vertex shader and not read in the
1270 * fragment shader. So the register number must always be
1271 * incremented, mapped or not.
1274 urb_setup[fp_index] = urb_next;
1280 * It's a FS only attribute, and we did interpolation for this attribute
1281 * in SF thread. So, count it here, too.
1283 * See compile_sf_prog() for more info.
1285 if (fp->Base.InputsRead & BITFIELD64_BIT(FRAG_ATTRIB_PNTC))
1286 urb_setup[FRAG_ATTRIB_PNTC] = urb_next++;
1289 /* Each attribute is 4 setup channels, each of which is half a reg. */
1290 c->prog_data.urb_read_length = urb_next * 2;
1294 fs_visitor::assign_urb_setup()
1296 int urb_start = c->nr_payload_regs + c->prog_data.curb_read_length;
1298 /* Offset all the urb_setup[] index by the actual position of the
1299 * setup regs, now that the location of the constants has been chosen.
1301 foreach_list(node, &this->instructions) {
1302 fs_inst *inst = (fs_inst *)node;
1304 if (inst->opcode == FS_OPCODE_LINTERP) {
1305 assert(inst->src[2].file == FIXED_HW_REG);
1306 inst->src[2].fixed_hw_reg.nr += urb_start;
1309 if (inst->opcode == FS_OPCODE_CINTERP) {
1310 assert(inst->src[0].file == FIXED_HW_REG);
1311 inst->src[0].fixed_hw_reg.nr += urb_start;
1315 this->first_non_payload_grf = urb_start + c->prog_data.urb_read_length;
1319 * Split large virtual GRFs into separate components if we can.
1321 * This is mostly duplicated with what brw_fs_vector_splitting does,
1322 * but that's really conservative because it's afraid of doing
1323 * splitting that doesn't result in real progress after the rest of
1324 * the optimization phases, which would cause infinite looping in
1325 * optimization. We can do it once here, safely. This also has the
1326 * opportunity to split interpolated values, or maybe even uniforms,
1327 * which we don't have at the IR level.
1329 * We want to split, because virtual GRFs are what we register
1330 * allocate and spill (due to contiguousness requirements for some
1331 * instructions), and they're what we naturally generate in the
1332 * codegen process, but most virtual GRFs don't actually need to be
1333 * contiguous sets of GRFs. If we split, we'll end up with reduced
1334 * live intervals and better dead code elimination and coalescing.
1337 fs_visitor::split_virtual_grfs()
1339 int num_vars = this->virtual_grf_count;
1340 bool split_grf[num_vars];
1341 int new_virtual_grf[num_vars];
1343 /* Try to split anything > 0 sized. */
1344 for (int i = 0; i < num_vars; i++) {
1345 if (this->virtual_grf_sizes[i] != 1)
1346 split_grf[i] = true;
1348 split_grf[i] = false;
1352 this->delta_x[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC].file == GRF) {
1353 /* PLN opcodes rely on the delta_xy being contiguous. We only have to
1354 * check this for BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC, because prior to
1355 * Gen6, that was the only supported interpolation mode, and since Gen6,
1356 * delta_x and delta_y are in fixed hardware registers.
1358 split_grf[this->delta_x[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC].reg] =
1362 foreach_list(node, &this->instructions) {
1363 fs_inst *inst = (fs_inst *)node;
1365 /* If there's a SEND message that requires contiguous destination
1366 * registers, no splitting is allowed.
1368 if (inst->regs_written() > 1) {
1369 split_grf[inst->dst.reg] = false;
1373 /* Allocate new space for split regs. Note that the virtual
1374 * numbers will be contiguous.
1376 for (int i = 0; i < num_vars; i++) {
1378 new_virtual_grf[i] = virtual_grf_alloc(1);
1379 for (int j = 2; j < this->virtual_grf_sizes[i]; j++) {
1380 int reg = virtual_grf_alloc(1);
1381 assert(reg == new_virtual_grf[i] + j - 1);
1384 this->virtual_grf_sizes[i] = 1;
1388 foreach_list(node, &this->instructions) {
1389 fs_inst *inst = (fs_inst *)node;
1391 if (inst->dst.file == GRF &&
1392 split_grf[inst->dst.reg] &&
1393 inst->dst.reg_offset != 0) {
1394 inst->dst.reg = (new_virtual_grf[inst->dst.reg] +
1395 inst->dst.reg_offset - 1);
1396 inst->dst.reg_offset = 0;
1398 for (int i = 0; i < 3; i++) {
1399 if (inst->src[i].file == GRF &&
1400 split_grf[inst->src[i].reg] &&
1401 inst->src[i].reg_offset != 0) {
1402 inst->src[i].reg = (new_virtual_grf[inst->src[i].reg] +
1403 inst->src[i].reg_offset - 1);
1404 inst->src[i].reg_offset = 0;
1408 this->live_intervals_valid = false;
1412 * Remove unused virtual GRFs and compact the virtual_grf_* arrays.
1414 * During code generation, we create tons of temporary variables, many of
1415 * which get immediately killed and are never used again. Yet, in later
1416 * optimization and analysis passes, such as compute_live_intervals, we need
1417 * to loop over all the virtual GRFs. Compacting them can save a lot of
1421 fs_visitor::compact_virtual_grfs()
1423 /* Mark which virtual GRFs are used, and count how many. */
1424 int remap_table[this->virtual_grf_count];
1425 memset(remap_table, -1, sizeof(remap_table));
1427 foreach_list(node, &this->instructions) {
1428 const fs_inst *inst = (const fs_inst *) node;
1430 if (inst->dst.file == GRF)
1431 remap_table[inst->dst.reg] = 0;
1433 for (int i = 0; i < 3; i++) {
1434 if (inst->src[i].file == GRF)
1435 remap_table[inst->src[i].reg] = 0;
1439 /* In addition to registers used in instructions, fs_visitor keeps
1440 * direct references to certain special values which must be patched:
1442 fs_reg *special[] = {
1443 &frag_depth, &pixel_x, &pixel_y, &pixel_w, &wpos_w, &dual_src_output,
1444 &outputs[0], &outputs[1], &outputs[2], &outputs[3],
1445 &outputs[4], &outputs[5], &outputs[6], &outputs[7],
1446 &delta_x[0], &delta_x[1], &delta_x[2],
1447 &delta_x[3], &delta_x[4], &delta_x[5],
1448 &delta_y[0], &delta_y[1], &delta_y[2],
1449 &delta_y[3], &delta_y[4], &delta_y[5],
1451 STATIC_ASSERT(BRW_WM_BARYCENTRIC_INTERP_MODE_COUNT == 6);
1452 STATIC_ASSERT(BRW_MAX_DRAW_BUFFERS == 8);
1454 /* Treat all special values as used, to be conservative */
1455 for (unsigned i = 0; i < ARRAY_SIZE(special); i++) {
1456 if (special[i]->file == GRF)
1457 remap_table[special[i]->reg] = 0;
1460 /* Compact the GRF arrays. */
1462 for (int i = 0; i < this->virtual_grf_count; i++) {
1463 if (remap_table[i] != -1) {
1464 remap_table[i] = new_index;
1465 virtual_grf_sizes[new_index] = virtual_grf_sizes[i];
1466 if (live_intervals_valid) {
1467 virtual_grf_use[new_index] = virtual_grf_use[i];
1468 virtual_grf_def[new_index] = virtual_grf_def[i];
1474 this->virtual_grf_count = new_index;
1476 /* Patch all the instructions to use the newly renumbered registers */
1477 foreach_list(node, &this->instructions) {
1478 fs_inst *inst = (fs_inst *) node;
1480 if (inst->dst.file == GRF)
1481 inst->dst.reg = remap_table[inst->dst.reg];
1483 for (int i = 0; i < 3; i++) {
1484 if (inst->src[i].file == GRF)
1485 inst->src[i].reg = remap_table[inst->src[i].reg];
1489 /* Patch all the references to special values */
1490 for (unsigned i = 0; i < ARRAY_SIZE(special); i++) {
1491 if (special[i]->file == GRF && remap_table[special[i]->reg] != -1)
1492 special[i]->reg = remap_table[special[i]->reg];
1497 fs_visitor::remove_dead_constants()
1499 if (dispatch_width == 8) {
1500 this->params_remap = ralloc_array(mem_ctx, int, c->prog_data.nr_params);
1502 for (unsigned int i = 0; i < c->prog_data.nr_params; i++)
1503 this->params_remap[i] = -1;
1505 /* Find which params are still in use. */
1506 foreach_list(node, &this->instructions) {
1507 fs_inst *inst = (fs_inst *)node;
1509 for (int i = 0; i < 3; i++) {
1510 int constant_nr = inst->src[i].reg + inst->src[i].reg_offset;
1512 if (inst->src[i].file != UNIFORM)
1515 assert(constant_nr < (int)c->prog_data.nr_params);
1517 /* For now, set this to non-negative. We'll give it the
1518 * actual new number in a moment, in order to keep the
1519 * register numbers nicely ordered.
1521 this->params_remap[constant_nr] = 0;
1525 /* Figure out what the new numbers for the params will be. At some
1526 * point when we're doing uniform array access, we're going to want
1527 * to keep the distinction between .reg and .reg_offset, but for
1528 * now we don't care.
1530 unsigned int new_nr_params = 0;
1531 for (unsigned int i = 0; i < c->prog_data.nr_params; i++) {
1532 if (this->params_remap[i] != -1) {
1533 this->params_remap[i] = new_nr_params++;
1537 /* Update the list of params to be uploaded to match our new numbering. */
1538 for (unsigned int i = 0; i < c->prog_data.nr_params; i++) {
1539 int remapped = this->params_remap[i];
1544 c->prog_data.param[remapped] = c->prog_data.param[i];
1547 c->prog_data.nr_params = new_nr_params;
1549 /* This should have been generated in the 8-wide pass already. */
1550 assert(this->params_remap);
1553 /* Now do the renumbering of the shader to remove unused params. */
1554 foreach_list(node, &this->instructions) {
1555 fs_inst *inst = (fs_inst *)node;
1557 for (int i = 0; i < 3; i++) {
1558 int constant_nr = inst->src[i].reg + inst->src[i].reg_offset;
1560 if (inst->src[i].file != UNIFORM)
1563 assert(this->params_remap[constant_nr] != -1);
1564 inst->src[i].reg = this->params_remap[constant_nr];
1565 inst->src[i].reg_offset = 0;
1573 * Implements array access of uniforms by inserting a
1574 * PULL_CONSTANT_LOAD instruction.
1576 * Unlike temporary GRF array access (where we don't support it due to
1577 * the difficulty of doing relative addressing on instruction
1578 * destinations), we could potentially do array access of uniforms
1579 * that were loaded in GRF space as push constants. In real-world
1580 * usage we've seen, though, the arrays being used are always larger
1581 * than we could load as push constants, so just always move all
1582 * uniform array access out to a pull constant buffer.
1585 fs_visitor::move_uniform_array_access_to_pull_constants()
1587 int pull_constant_loc[c->prog_data.nr_params];
1589 for (unsigned int i = 0; i < c->prog_data.nr_params; i++) {
1590 pull_constant_loc[i] = -1;
1593 /* Walk through and find array access of uniforms. Put a copy of that
1594 * uniform in the pull constant buffer.
1596 * Note that we don't move constant-indexed accesses to arrays. No
1597 * testing has been done of the performance impact of this choice.
1599 foreach_list_safe(node, &this->instructions) {
1600 fs_inst *inst = (fs_inst *)node;
1602 for (int i = 0 ; i < 3; i++) {
1603 if (inst->src[i].file != UNIFORM || !inst->src[i].reladdr)
1606 int uniform = inst->src[i].reg;
1608 /* If this array isn't already present in the pull constant buffer,
1611 if (pull_constant_loc[uniform] == -1) {
1612 const float **values = &c->prog_data.param[uniform];
1614 pull_constant_loc[uniform] = c->prog_data.nr_pull_params;
1616 assert(param_size[uniform]);
1618 for (int j = 0; j < param_size[uniform]; j++) {
1619 c->prog_data.pull_param[c->prog_data.nr_pull_params++] =
1624 /* Set up the annotation tracking for new generated instructions. */
1626 current_annotation = inst->annotation;
1628 fs_reg offset = fs_reg(this, glsl_type::int_type);
1629 inst->insert_before(ADD(offset, *inst->src[i].reladdr,
1630 fs_reg(pull_constant_loc[uniform] +
1631 inst->src[i].reg_offset)));
1633 fs_reg surf_index = fs_reg((unsigned)SURF_INDEX_FRAG_CONST_BUFFER);
1634 fs_reg temp = fs_reg(this, glsl_type::float_type);
1635 exec_list list = VARYING_PULL_CONSTANT_LOAD(temp,
1636 surf_index, offset);
1637 inst->insert_before(&list);
1639 inst->src[i].file = temp.file;
1640 inst->src[i].reg = temp.reg;
1641 inst->src[i].reg_offset = temp.reg_offset;
1642 inst->src[i].reladdr = NULL;
1648 * Choose accesses from the UNIFORM file to demote to using the pull
1651 * We allow a fragment shader to have more than the specified minimum
1652 * maximum number of fragment shader uniform components (64). If
1653 * there are too many of these, they'd fill up all of register space.
1654 * So, this will push some of them out to the pull constant buffer and
1655 * update the program to load them.
1658 fs_visitor::setup_pull_constants()
1660 /* Only allow 16 registers (128 uniform components) as push constants. */
1661 unsigned int max_uniform_components = 16 * 8;
1662 if (c->prog_data.nr_params <= max_uniform_components)
1665 if (dispatch_width == 16) {
1666 fail("Pull constants not supported in 16-wide\n");
1670 /* Just demote the end of the list. We could probably do better
1671 * here, demoting things that are rarely used in the program first.
1673 unsigned int pull_uniform_base = max_uniform_components;
1675 int pull_constant_loc[c->prog_data.nr_params];
1676 for (unsigned int i = 0; i < c->prog_data.nr_params; i++) {
1677 if (i < pull_uniform_base) {
1678 pull_constant_loc[i] = -1;
1680 pull_constant_loc[i] = -1;
1681 /* If our constant is already being uploaded for reladdr purposes,
1684 for (unsigned int j = 0; j < c->prog_data.nr_pull_params; j++) {
1685 if (c->prog_data.pull_param[j] == c->prog_data.param[i]) {
1686 pull_constant_loc[i] = j;
1690 if (pull_constant_loc[i] == -1) {
1691 int pull_index = c->prog_data.nr_pull_params++;
1692 c->prog_data.pull_param[pull_index] = c->prog_data.param[i];
1693 pull_constant_loc[i] = pull_index;;
1697 c->prog_data.nr_params = pull_uniform_base;
1699 foreach_list(node, &this->instructions) {
1700 fs_inst *inst = (fs_inst *)node;
1702 for (int i = 0; i < 3; i++) {
1703 if (inst->src[i].file != UNIFORM)
1706 int pull_index = pull_constant_loc[inst->src[i].reg +
1707 inst->src[i].reg_offset];
1708 if (pull_index == -1)
1711 assert(!inst->src[i].reladdr);
1713 fs_reg dst = fs_reg(this, glsl_type::float_type);
1714 fs_reg index = fs_reg((unsigned)SURF_INDEX_FRAG_CONST_BUFFER);
1715 fs_reg offset = fs_reg((unsigned)(pull_index * 4) & ~15);
1717 new(mem_ctx) fs_inst(FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD,
1718 dst, index, offset);
1719 pull->ir = inst->ir;
1720 pull->annotation = inst->annotation;
1722 inst->insert_before(pull);
1724 inst->src[i].file = GRF;
1725 inst->src[i].reg = dst.reg;
1726 inst->src[i].reg_offset = 0;
1727 inst->src[i].smear = pull_index & 3;
1733 fs_visitor::opt_algebraic()
1735 bool progress = false;
1737 foreach_list(node, &this->instructions) {
1738 fs_inst *inst = (fs_inst *)node;
1740 switch (inst->opcode) {
1741 case BRW_OPCODE_MUL:
1742 if (inst->src[1].file != IMM)
1746 if (inst->src[1].is_one()) {
1747 inst->opcode = BRW_OPCODE_MOV;
1748 inst->src[1] = reg_undef;
1754 if (inst->src[1].is_zero()) {
1755 inst->opcode = BRW_OPCODE_MOV;
1756 inst->src[0] = inst->src[1];
1757 inst->src[1] = reg_undef;
1763 case BRW_OPCODE_ADD:
1764 if (inst->src[1].file != IMM)
1768 if (inst->src[1].is_zero()) {
1769 inst->opcode = BRW_OPCODE_MOV;
1770 inst->src[1] = reg_undef;
1784 * Must be called after calculate_live_intervales() to remove unused
1785 * writes to registers -- register allocation will fail otherwise
1786 * because something deffed but not used won't be considered to
1787 * interfere with other regs.
1790 fs_visitor::dead_code_eliminate()
1792 bool progress = false;
1795 calculate_live_intervals();
1797 foreach_list_safe(node, &this->instructions) {
1798 fs_inst *inst = (fs_inst *)node;
1800 if (inst->dst.file == GRF && this->virtual_grf_use[inst->dst.reg] <= pc) {
1809 live_intervals_valid = false;
1815 * Implements a second type of register coalescing: This one checks if
1816 * the two regs involved in a raw move don't interfere, in which case
1817 * they can both by stored in the same place and the MOV removed.
1820 fs_visitor::register_coalesce_2()
1822 bool progress = false;
1824 calculate_live_intervals();
1826 foreach_list_safe(node, &this->instructions) {
1827 fs_inst *inst = (fs_inst *)node;
1829 if (inst->opcode != BRW_OPCODE_MOV ||
1832 inst->src[0].file != GRF ||
1833 inst->src[0].negate ||
1835 inst->src[0].smear != -1 ||
1836 inst->dst.file != GRF ||
1837 inst->dst.type != inst->src[0].type ||
1838 virtual_grf_sizes[inst->src[0].reg] != 1 ||
1839 virtual_grf_interferes(inst->dst.reg, inst->src[0].reg)) {
1843 int reg_from = inst->src[0].reg;
1844 assert(inst->src[0].reg_offset == 0);
1845 int reg_to = inst->dst.reg;
1846 int reg_to_offset = inst->dst.reg_offset;
1848 foreach_list(node, &this->instructions) {
1849 fs_inst *scan_inst = (fs_inst *)node;
1851 if (scan_inst->dst.file == GRF &&
1852 scan_inst->dst.reg == reg_from) {
1853 scan_inst->dst.reg = reg_to;
1854 scan_inst->dst.reg_offset = reg_to_offset;
1856 for (int i = 0; i < 3; i++) {
1857 if (scan_inst->src[i].file == GRF &&
1858 scan_inst->src[i].reg == reg_from) {
1859 scan_inst->src[i].reg = reg_to;
1860 scan_inst->src[i].reg_offset = reg_to_offset;
1867 /* We don't need to recalculate live intervals inside the loop despite
1868 * flagging live_intervals_valid because we only use live intervals for
1869 * the interferes test, and we must have had a situation where the
1880 * Some register R that might get coalesced with one of these two could
1881 * only be referencing "to", otherwise "from"'s range would have been
1882 * longer. R's range could also only start at the end of "to" or later,
1883 * otherwise it will conflict with "to" when we try to coalesce "to"
1886 live_intervals_valid = false;
1896 fs_visitor::register_coalesce()
1898 bool progress = false;
1902 foreach_list_safe(node, &this->instructions) {
1903 fs_inst *inst = (fs_inst *)node;
1905 /* Make sure that we dominate the instructions we're going to
1906 * scan for interfering with our coalescing, or we won't have
1907 * scanned enough to see if anything interferes with our
1908 * coalescing. We don't dominate the following instructions if
1909 * we're in a loop or an if block.
1911 switch (inst->opcode) {
1915 case BRW_OPCODE_WHILE:
1921 case BRW_OPCODE_ENDIF:
1927 if (loop_depth || if_depth)
1930 if (inst->opcode != BRW_OPCODE_MOV ||
1933 inst->dst.file != GRF || (inst->src[0].file != GRF &&
1934 inst->src[0].file != UNIFORM)||
1935 inst->dst.type != inst->src[0].type)
1938 bool has_source_modifiers = (inst->src[0].abs ||
1939 inst->src[0].negate ||
1940 inst->src[0].smear != -1 ||
1941 inst->src[0].file == UNIFORM);
1943 /* Found a move of a GRF to a GRF. Let's see if we can coalesce
1944 * them: check for no writes to either one until the exit of the
1947 bool interfered = false;
1949 for (fs_inst *scan_inst = (fs_inst *)inst->next;
1950 !scan_inst->is_tail_sentinel();
1951 scan_inst = (fs_inst *)scan_inst->next) {
1952 if (scan_inst->dst.file == GRF) {
1953 if (scan_inst->overwrites_reg(inst->dst) ||
1954 scan_inst->overwrites_reg(inst->src[0])) {
1960 /* The gen6 MATH instruction can't handle source modifiers or
1961 * unusual register regions, so avoid coalescing those for
1962 * now. We should do something more specific.
1964 if (has_source_modifiers && !can_do_source_mods(scan_inst)) {
1969 /* The accumulator result appears to get used for the
1970 * conditional modifier generation. When negating a UD
1971 * value, there is a 33rd bit generated for the sign in the
1972 * accumulator value, so now you can't check, for example,
1973 * equality with a 32-bit value. See piglit fs-op-neg-uint.
1975 if (scan_inst->conditional_mod &&
1976 inst->src[0].negate &&
1977 inst->src[0].type == BRW_REGISTER_TYPE_UD) {
1986 /* Rewrite the later usage to point at the source of the move to
1989 for (fs_inst *scan_inst = inst;
1990 !scan_inst->is_tail_sentinel();
1991 scan_inst = (fs_inst *)scan_inst->next) {
1992 for (int i = 0; i < 3; i++) {
1993 if (scan_inst->src[i].file == GRF &&
1994 scan_inst->src[i].reg == inst->dst.reg &&
1995 scan_inst->src[i].reg_offset == inst->dst.reg_offset) {
1996 fs_reg new_src = inst->src[0];
1997 if (scan_inst->src[i].abs) {
2001 new_src.negate ^= scan_inst->src[i].negate;
2002 scan_inst->src[i] = new_src;
2012 live_intervals_valid = false;
2019 fs_visitor::compute_to_mrf()
2021 bool progress = false;
2024 calculate_live_intervals();
2026 foreach_list_safe(node, &this->instructions) {
2027 fs_inst *inst = (fs_inst *)node;
2032 if (inst->opcode != BRW_OPCODE_MOV ||
2034 inst->dst.file != MRF || inst->src[0].file != GRF ||
2035 inst->dst.type != inst->src[0].type ||
2036 inst->src[0].abs || inst->src[0].negate || inst->src[0].smear != -1)
2039 /* Work out which hardware MRF registers are written by this
2042 int mrf_low = inst->dst.reg & ~BRW_MRF_COMPR4;
2044 if (inst->dst.reg & BRW_MRF_COMPR4) {
2045 mrf_high = mrf_low + 4;
2046 } else if (dispatch_width == 16 &&
2047 (!inst->force_uncompressed && !inst->force_sechalf)) {
2048 mrf_high = mrf_low + 1;
2053 /* Can't compute-to-MRF this GRF if someone else was going to
2056 if (this->virtual_grf_use[inst->src[0].reg] > ip)
2059 /* Found a move of a GRF to a MRF. Let's see if we can go
2060 * rewrite the thing that made this GRF to write into the MRF.
2063 for (scan_inst = (fs_inst *)inst->prev;
2064 scan_inst->prev != NULL;
2065 scan_inst = (fs_inst *)scan_inst->prev) {
2066 if (scan_inst->dst.file == GRF &&
2067 scan_inst->dst.reg == inst->src[0].reg) {
2068 /* Found the last thing to write our reg we want to turn
2069 * into a compute-to-MRF.
2072 /* If it's predicated, it (probably) didn't populate all
2073 * the channels. We might be able to rewrite everything
2074 * that writes that reg, but it would require smarter
2075 * tracking to delay the rewriting until complete success.
2077 if (scan_inst->predicate)
2080 /* If it's half of register setup and not the same half as
2081 * our MOV we're trying to remove, bail for now.
2083 if (scan_inst->force_uncompressed != inst->force_uncompressed ||
2084 scan_inst->force_sechalf != inst->force_sechalf) {
2088 /* SEND instructions can't have MRF as a destination. */
2089 if (scan_inst->mlen)
2092 if (intel->gen == 6) {
2093 /* gen6 math instructions must have the destination be
2094 * GRF, so no compute-to-MRF for them.
2096 if (scan_inst->is_math()) {
2101 if (scan_inst->dst.reg_offset == inst->src[0].reg_offset) {
2102 /* Found the creator of our MRF's source value. */
2103 scan_inst->dst.file = MRF;
2104 scan_inst->dst.reg = inst->dst.reg;
2105 scan_inst->saturate |= inst->saturate;
2112 /* We don't handle control flow here. Most computation of
2113 * values that end up in MRFs are shortly before the MRF
2116 if (scan_inst->is_control_flow() && scan_inst->opcode != BRW_OPCODE_IF)
2119 /* You can't read from an MRF, so if someone else reads our
2120 * MRF's source GRF that we wanted to rewrite, that stops us.
2122 bool interfered = false;
2123 for (int i = 0; i < 3; i++) {
2124 if (scan_inst->src[i].file == GRF &&
2125 scan_inst->src[i].reg == inst->src[0].reg &&
2126 scan_inst->src[i].reg_offset == inst->src[0].reg_offset) {
2133 if (scan_inst->dst.file == MRF) {
2134 /* If somebody else writes our MRF here, we can't
2135 * compute-to-MRF before that.
2137 int scan_mrf_low = scan_inst->dst.reg & ~BRW_MRF_COMPR4;
2140 if (scan_inst->dst.reg & BRW_MRF_COMPR4) {
2141 scan_mrf_high = scan_mrf_low + 4;
2142 } else if (dispatch_width == 16 &&
2143 (!scan_inst->force_uncompressed &&
2144 !scan_inst->force_sechalf)) {
2145 scan_mrf_high = scan_mrf_low + 1;
2147 scan_mrf_high = scan_mrf_low;
2150 if (mrf_low == scan_mrf_low ||
2151 mrf_low == scan_mrf_high ||
2152 mrf_high == scan_mrf_low ||
2153 mrf_high == scan_mrf_high) {
2158 if (scan_inst->mlen > 0) {
2159 /* Found a SEND instruction, which means that there are
2160 * live values in MRFs from base_mrf to base_mrf +
2161 * scan_inst->mlen - 1. Don't go pushing our MRF write up
2164 if (mrf_low >= scan_inst->base_mrf &&
2165 mrf_low < scan_inst->base_mrf + scan_inst->mlen) {
2168 if (mrf_high >= scan_inst->base_mrf &&
2169 mrf_high < scan_inst->base_mrf + scan_inst->mlen) {
2177 live_intervals_valid = false;
2183 * Walks through basic blocks, looking for repeated MRF writes and
2184 * removing the later ones.
2187 fs_visitor::remove_duplicate_mrf_writes()
2189 fs_inst *last_mrf_move[16];
2190 bool progress = false;
2192 /* Need to update the MRF tracking for compressed instructions. */
2193 if (dispatch_width == 16)
2196 memset(last_mrf_move, 0, sizeof(last_mrf_move));
2198 foreach_list_safe(node, &this->instructions) {
2199 fs_inst *inst = (fs_inst *)node;
2201 if (inst->is_control_flow()) {
2202 memset(last_mrf_move, 0, sizeof(last_mrf_move));
2205 if (inst->opcode == BRW_OPCODE_MOV &&
2206 inst->dst.file == MRF) {
2207 fs_inst *prev_inst = last_mrf_move[inst->dst.reg];
2208 if (prev_inst && inst->equals(prev_inst)) {
2215 /* Clear out the last-write records for MRFs that were overwritten. */
2216 if (inst->dst.file == MRF) {
2217 last_mrf_move[inst->dst.reg] = NULL;
2220 if (inst->mlen > 0) {
2221 /* Found a SEND instruction, which will include two or fewer
2222 * implied MRF writes. We could do better here.
2224 for (int i = 0; i < implied_mrf_writes(inst); i++) {
2225 last_mrf_move[inst->base_mrf + i] = NULL;
2229 /* Clear out any MRF move records whose sources got overwritten. */
2230 if (inst->dst.file == GRF) {
2231 for (unsigned int i = 0; i < Elements(last_mrf_move); i++) {
2232 if (last_mrf_move[i] &&
2233 last_mrf_move[i]->src[0].reg == inst->dst.reg) {
2234 last_mrf_move[i] = NULL;
2239 if (inst->opcode == BRW_OPCODE_MOV &&
2240 inst->dst.file == MRF &&
2241 inst->src[0].file == GRF &&
2243 last_mrf_move[inst->dst.reg] = inst;
2248 live_intervals_valid = false;
2254 clear_deps_for_inst_src(fs_inst *inst, int dispatch_width, bool *deps,
2255 int first_grf, int grf_len)
2257 bool inst_16wide = (dispatch_width > 8 &&
2258 !inst->force_uncompressed &&
2259 !inst->force_sechalf);
2261 /* Clear the flag for registers that actually got read (as expected). */
2262 for (int i = 0; i < 3; i++) {
2264 if (inst->src[i].file == GRF) {
2265 grf = inst->src[i].reg;
2266 } else if (inst->src[i].file == FIXED_HW_REG &&
2267 inst->src[i].fixed_hw_reg.file == BRW_GENERAL_REGISTER_FILE) {
2268 grf = inst->src[i].fixed_hw_reg.nr;
2273 if (grf >= first_grf &&
2274 grf < first_grf + grf_len) {
2275 deps[grf - first_grf] = false;
2277 deps[grf - first_grf + 1] = false;
2283 * Implements this workaround for the original 965:
2285 * "[DevBW, DevCL] Implementation Restrictions: As the hardware does not
2286 * check for post destination dependencies on this instruction, software
2287 * must ensure that there is no destination hazard for the case of ‘write
2288 * followed by a posted write’ shown in the following example.
2291 * 2. send r3.xy <rest of send instruction>
2294 * Due to no post-destination dependency check on the ‘send’, the above
2295 * code sequence could have two instructions (1 and 2) in flight at the
2296 * same time that both consider ‘r3’ as the target of their final writes.
2299 fs_visitor::insert_gen4_pre_send_dependency_workarounds(fs_inst *inst)
2301 int write_len = inst->regs_written() * dispatch_width / 8;
2302 int first_write_grf = inst->dst.reg;
2303 bool needs_dep[BRW_MAX_MRF];
2304 assert(write_len < (int)sizeof(needs_dep) - 1);
2306 memset(needs_dep, false, sizeof(needs_dep));
2307 memset(needs_dep, true, write_len);
2309 clear_deps_for_inst_src(inst, dispatch_width,
2310 needs_dep, first_write_grf, write_len);
2312 /* Walk backwards looking for writes to registers we're writing which
2313 * aren't read since being written. If we hit the start of the program,
2314 * we assume that there are no outstanding dependencies on entry to the
2317 for (fs_inst *scan_inst = (fs_inst *)inst->prev;
2319 scan_inst = (fs_inst *)scan_inst->prev) {
2321 /* If we hit control flow, assume that there *are* outstanding
2322 * dependencies, and force their cleanup before our instruction.
2324 if (scan_inst->is_control_flow()) {
2325 for (int i = 0; i < write_len; i++) {
2327 inst->insert_before(DEP_RESOLVE_MOV(first_write_grf + i));
2332 bool scan_inst_16wide = (dispatch_width > 8 &&
2333 !scan_inst->force_uncompressed &&
2334 !scan_inst->force_sechalf);
2336 /* We insert our reads as late as possible on the assumption that any
2337 * instruction but a MOV that might have left us an outstanding
2338 * dependency has more latency than a MOV.
2340 if (scan_inst->dst.file == GRF &&
2341 scan_inst->dst.reg >= first_write_grf &&
2342 scan_inst->dst.reg < first_write_grf + write_len &&
2343 needs_dep[scan_inst->dst.reg - first_write_grf]) {
2344 inst->insert_before(DEP_RESOLVE_MOV(scan_inst->dst.reg));
2345 needs_dep[scan_inst->dst.reg - first_write_grf] = false;
2346 if (scan_inst_16wide)
2347 needs_dep[scan_inst->dst.reg - first_write_grf + 1] = false;
2350 /* Clear the flag for registers that actually got read (as expected). */
2351 clear_deps_for_inst_src(scan_inst, dispatch_width,
2352 needs_dep, first_write_grf, write_len);
2354 /* Continue the loop only if we haven't resolved all the dependencies */
2356 for (i = 0; i < write_len; i++) {
2366 * Implements this workaround for the original 965:
2368 * "[DevBW, DevCL] Errata: A destination register from a send can not be
2369 * used as a destination register until after it has been sourced by an
2370 * instruction with a different destination register.
2373 fs_visitor::insert_gen4_post_send_dependency_workarounds(fs_inst *inst)
2375 int write_len = inst->regs_written() * dispatch_width / 8;
2376 int first_write_grf = inst->dst.reg;
2377 bool needs_dep[BRW_MAX_MRF];
2378 assert(write_len < (int)sizeof(needs_dep) - 1);
2380 memset(needs_dep, false, sizeof(needs_dep));
2381 memset(needs_dep, true, write_len);
2382 /* Walk forwards looking for writes to registers we're writing which aren't
2383 * read before being written.
2385 for (fs_inst *scan_inst = (fs_inst *)inst->next;
2386 !scan_inst->is_tail_sentinel();
2387 scan_inst = (fs_inst *)scan_inst->next) {
2388 /* If we hit control flow, force resolve all remaining dependencies. */
2389 if (scan_inst->is_control_flow()) {
2390 for (int i = 0; i < write_len; i++) {
2392 scan_inst->insert_before(DEP_RESOLVE_MOV(first_write_grf + i));
2396 /* Clear the flag for registers that actually got read (as expected). */
2397 clear_deps_for_inst_src(scan_inst, dispatch_width,
2398 needs_dep, first_write_grf, write_len);
2400 /* We insert our reads as late as possible since they're reading the
2401 * result of a SEND, which has massive latency.
2403 if (scan_inst->dst.file == GRF &&
2404 scan_inst->dst.reg >= first_write_grf &&
2405 scan_inst->dst.reg < first_write_grf + write_len &&
2406 needs_dep[scan_inst->dst.reg - first_write_grf]) {
2407 scan_inst->insert_before(DEP_RESOLVE_MOV(scan_inst->dst.reg));
2408 needs_dep[scan_inst->dst.reg - first_write_grf] = false;
2411 /* Continue the loop only if we haven't resolved all the dependencies */
2413 for (i = 0; i < write_len; i++) {
2421 /* If we hit the end of the program, resolve all remaining dependencies out
2424 fs_inst *last_inst = (fs_inst *)this->instructions.get_tail();
2425 assert(last_inst->eot);
2426 for (int i = 0; i < write_len; i++) {
2428 last_inst->insert_before(DEP_RESOLVE_MOV(first_write_grf + i));
2433 fs_visitor::insert_gen4_send_dependency_workarounds()
2435 if (intel->gen != 4 || intel->is_g4x)
2438 /* Note that we're done with register allocation, so GRF fs_regs always
2439 * have a .reg_offset of 0.
2442 foreach_list_safe(node, &this->instructions) {
2443 fs_inst *inst = (fs_inst *)node;
2445 if (inst->mlen != 0 && inst->dst.file == GRF) {
2446 insert_gen4_pre_send_dependency_workarounds(inst);
2447 insert_gen4_post_send_dependency_workarounds(inst);
2453 * Turns the generic expression-style uniform pull constant load instruction
2454 * into a hardware-specific series of instructions for loading a pull
2457 * The expression style allows the CSE pass before this to optimize out
2458 * repeated loads from the same offset, and gives the pre-register-allocation
2459 * scheduling full flexibility, while the conversion to native instructions
2460 * allows the post-register-allocation scheduler the best information
2464 fs_visitor::lower_uniform_pull_constant_loads()
2466 foreach_list(node, &this->instructions) {
2467 fs_inst *inst = (fs_inst *)node;
2469 if (inst->opcode != FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD)
2472 if (intel->gen >= 7) {
2473 fs_reg const_offset_reg = inst->src[1];
2474 assert(const_offset_reg.file == IMM &&
2475 const_offset_reg.type == BRW_REGISTER_TYPE_UD);
2476 const_offset_reg.imm.u /= 16;
2477 fs_reg payload = fs_reg(this, glsl_type::uint_type);
2478 struct brw_reg g0 = retype(brw_vec8_grf(0, 0),
2479 BRW_REGISTER_TYPE_UD);
2481 fs_inst *setup1 = MOV(payload, fs_reg(g0));
2482 setup1->force_writemask_all = true;
2483 /* We don't need the second half of this vgrf to be filled with g1
2484 * in the 16-wide case, but if we use force_uncompressed then live
2485 * variable analysis won't consider this a def!
2488 fs_inst *setup2 = new(mem_ctx) fs_inst(FS_OPCODE_SET_GLOBAL_OFFSET,
2492 setup1->ir = inst->ir;
2493 setup1->annotation = inst->annotation;
2494 inst->insert_before(setup1);
2495 setup2->ir = inst->ir;
2496 setup2->annotation = inst->annotation;
2497 inst->insert_before(setup2);
2498 inst->opcode = FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7;
2499 inst->src[1] = payload;
2501 /* Before register allocation, we didn't tell the scheduler about the
2502 * MRF we use. We know it's safe to use this MRF because nothing
2503 * else does except for register spill/unspill, which generates and
2504 * uses its MRF within a single IR instruction.
2506 inst->base_mrf = 14;
2513 fs_visitor::dump_instruction(fs_inst *inst)
2515 if (inst->predicate) {
2516 printf("(%cf0.%d) ",
2517 inst->predicate_inverse ? '-' : '+',
2521 if (inst->opcode < ARRAY_SIZE(opcode_descs) &&
2522 opcode_descs[inst->opcode].name) {
2523 printf("%s", opcode_descs[inst->opcode].name);
2525 switch (inst->opcode) {
2526 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD:
2527 printf("uniform_pull_const");
2529 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7:
2530 printf("uniform_pull_const_gen7");
2532 case FS_OPCODE_SET_GLOBAL_OFFSET:
2533 printf("set_global_offset");
2536 printf("op%d", inst->opcode);
2542 if (inst->conditional_mod) {
2544 if (!inst->predicate &&
2545 (intel->gen < 5 || (inst->opcode != BRW_OPCODE_SEL &&
2546 inst->opcode != BRW_OPCODE_IF &&
2547 inst->opcode != BRW_OPCODE_WHILE))) {
2548 printf(".f0.%d\n", inst->flag_subreg);
2554 switch (inst->dst.file) {
2556 printf("vgrf%d", inst->dst.reg);
2557 if (inst->dst.reg_offset)
2558 printf("+%d", inst->dst.reg_offset);
2561 printf("m%d", inst->dst.reg);
2567 printf("***u%d***", inst->dst.reg);
2575 for (int i = 0; i < 3; i++) {
2576 if (inst->src[i].negate)
2578 if (inst->src[i].abs)
2580 switch (inst->src[i].file) {
2582 printf("vgrf%d", inst->src[i].reg);
2583 if (inst->src[i].reg_offset)
2584 printf("+%d", inst->src[i].reg_offset);
2587 printf("***m%d***", inst->src[i].reg);
2590 printf("u%d", inst->src[i].reg);
2591 if (inst->src[i].reg_offset)
2592 printf(".%d", inst->src[i].reg_offset);
2598 switch (inst->src[i].type) {
2599 case BRW_REGISTER_TYPE_F:
2600 printf("%ff", inst->src[i].imm.f);
2602 case BRW_REGISTER_TYPE_D:
2603 printf("%dd", inst->src[i].imm.i);
2605 case BRW_REGISTER_TYPE_UD:
2606 printf("%uu", inst->src[i].imm.u);
2617 if (inst->src[i].abs)
2626 if (inst->force_uncompressed)
2629 if (inst->force_sechalf)
2636 fs_visitor::dump_instructions()
2639 foreach_list(node, &this->instructions) {
2640 fs_inst *inst = (fs_inst *)node;
2641 printf("%d: ", ip++);
2642 dump_instruction(inst);
2647 * Possibly returns an instruction that set up @param reg.
2649 * Sometimes we want to take the result of some expression/variable
2650 * dereference tree and rewrite the instruction generating the result
2651 * of the tree. When processing the tree, we know that the
2652 * instructions generated are all writing temporaries that are dead
2653 * outside of this tree. So, if we have some instructions that write
2654 * a temporary, we're free to point that temp write somewhere else.
2656 * Note that this doesn't guarantee that the instruction generated
2657 * only reg -- it might be the size=4 destination of a texture instruction.
2660 fs_visitor::get_instruction_generating_reg(fs_inst *start,
2666 end->force_uncompressed ||
2667 end->force_sechalf ||
2669 !reg.equals(end->dst)) {
2677 fs_visitor::setup_payload_gen6()
2679 struct intel_context *intel = &brw->intel;
2681 (fp->Base.InputsRead & (1 << FRAG_ATTRIB_WPOS)) != 0;
2682 unsigned barycentric_interp_modes = c->prog_data.barycentric_interp_modes;
2684 assert(intel->gen >= 6);
2686 /* R0-1: masks, pixel X/Y coordinates. */
2687 c->nr_payload_regs = 2;
2688 /* R2: only for 32-pixel dispatch.*/
2690 /* R3-26: barycentric interpolation coordinates. These appear in the
2691 * same order that they appear in the brw_wm_barycentric_interp_mode
2692 * enum. Each set of coordinates occupies 2 registers if dispatch width
2693 * == 8 and 4 registers if dispatch width == 16. Coordinates only
2694 * appear if they were enabled using the "Barycentric Interpolation
2695 * Mode" bits in WM_STATE.
2697 for (int i = 0; i < BRW_WM_BARYCENTRIC_INTERP_MODE_COUNT; ++i) {
2698 if (barycentric_interp_modes & (1 << i)) {
2699 c->barycentric_coord_reg[i] = c->nr_payload_regs;
2700 c->nr_payload_regs += 2;
2701 if (dispatch_width == 16) {
2702 c->nr_payload_regs += 2;
2707 /* R27: interpolated depth if uses source depth */
2709 c->source_depth_reg = c->nr_payload_regs;
2710 c->nr_payload_regs++;
2711 if (dispatch_width == 16) {
2712 /* R28: interpolated depth if not 8-wide. */
2713 c->nr_payload_regs++;
2716 /* R29: interpolated W set if GEN6_WM_USES_SOURCE_W. */
2718 c->source_w_reg = c->nr_payload_regs;
2719 c->nr_payload_regs++;
2720 if (dispatch_width == 16) {
2721 /* R30: interpolated W if not 8-wide. */
2722 c->nr_payload_regs++;
2725 /* R31: MSAA position offsets. */
2726 /* R32-: bary for 32-pixel. */
2727 /* R58-59: interp W for 32-pixel. */
2729 if (fp->Base.OutputsWritten & BITFIELD64_BIT(FRAG_RESULT_DEPTH)) {
2730 c->source_depth_to_render_target = true;
2737 sanity_param_count = fp->Base.Parameters->NumParameters;
2738 uint32_t orig_nr_params = c->prog_data.nr_params;
2740 if (intel->gen >= 6)
2741 setup_payload_gen6();
2743 setup_payload_gen4();
2748 if (INTEL_DEBUG & DEBUG_SHADER_TIME)
2749 emit_shader_time_begin();
2751 calculate_urb_setup();
2753 emit_interpolation_setup_gen4();
2755 emit_interpolation_setup_gen6();
2757 /* We handle discards by keeping track of the still-live pixels in f0.1.
2758 * Initialize it with the dispatched pixels.
2761 fs_inst *discard_init = emit(FS_OPCODE_MOV_DISPATCH_TO_FLAGS);
2762 discard_init->flag_subreg = 1;
2765 /* Generate FS IR for main(). (the visitor only descends into
2766 * functions called "main").
2769 foreach_list(node, &*shader->ir) {
2770 ir_instruction *ir = (ir_instruction *)node;
2772 this->result = reg_undef;
2776 emit_fragment_program_code();
2782 if (INTEL_DEBUG & DEBUG_SHADER_TIME)
2783 emit_shader_time_end();
2787 split_virtual_grfs();
2789 move_uniform_array_access_to_pull_constants();
2790 setup_pull_constants();
2796 compact_virtual_grfs();
2798 progress = remove_duplicate_mrf_writes() || progress;
2800 progress = opt_algebraic() || progress;
2801 progress = opt_cse() || progress;
2802 progress = opt_copy_propagate() || progress;
2803 progress = dead_code_eliminate() || progress;
2804 progress = register_coalesce() || progress;
2805 progress = register_coalesce_2() || progress;
2806 progress = compute_to_mrf() || progress;
2809 remove_dead_constants();
2811 schedule_instructions(false);
2813 lower_uniform_pull_constant_loads();
2815 assign_curb_setup();
2819 /* Debug of register spilling: Go spill everything. */
2820 for (int i = 0; i < virtual_grf_count; i++) {
2826 assign_regs_trivial();
2828 while (!assign_regs()) {
2834 assert(force_uncompressed_stack == 0);
2835 assert(force_sechalf_stack == 0);
2837 /* This must come after all optimization and register allocation, since
2838 * it inserts dead code that happens to have side effects, and it does
2839 * so based on the actual physical registers in use.
2841 insert_gen4_send_dependency_workarounds();
2846 schedule_instructions(true);
2848 if (dispatch_width == 8) {
2849 c->prog_data.reg_blocks = brw_register_blocks(grf_used);
2851 c->prog_data.reg_blocks_16 = brw_register_blocks(grf_used);
2853 /* Make sure we didn't try to sneak in an extra uniform */
2854 assert(orig_nr_params == c->prog_data.nr_params);
2855 (void) orig_nr_params;
2858 /* If any state parameters were appended, then ParameterValues could have
2859 * been realloced, in which case the driver uniform storage set up by
2860 * _mesa_associate_uniform_storage() would point to freed memory. Make
2861 * sure that didn't happen.
2863 assert(sanity_param_count == fp->Base.Parameters->NumParameters);
2869 brw_wm_fs_emit(struct brw_context *brw, struct brw_wm_compile *c,
2870 struct gl_fragment_program *fp,
2871 struct gl_shader_program *prog,
2872 unsigned *final_assembly_size)
2874 struct intel_context *intel = &brw->intel;
2875 bool start_busy = false;
2876 float start_time = 0;
2878 if (unlikely(INTEL_DEBUG & DEBUG_PERF)) {
2879 start_busy = (intel->batch.last_bo &&
2880 drm_intel_bo_busy(intel->batch.last_bo));
2881 start_time = get_time();
2884 struct brw_shader *shader = NULL;
2886 shader = (brw_shader *) prog->_LinkedShaders[MESA_SHADER_FRAGMENT];
2888 if (unlikely(INTEL_DEBUG & DEBUG_WM)) {
2890 printf("GLSL IR for native fragment shader %d:\n", prog->Name);
2891 _mesa_print_ir(shader->ir, NULL);
2894 printf("ARB_fragment_program %d ir for native fragment shader\n",
2896 _mesa_print_program(&fp->Base);
2900 /* Now the main event: Visit the shader IR and generate our FS IR for it.
2902 fs_visitor v(brw, c, prog, fp, 8);
2904 prog->LinkStatus = false;
2905 ralloc_strcat(&prog->InfoLog, v.fail_msg);
2907 _mesa_problem(NULL, "Failed to compile fragment shader: %s\n",
2913 exec_list *simd16_instructions = NULL;
2914 fs_visitor v2(brw, c, prog, fp, 16);
2915 bool no16 = INTEL_DEBUG & DEBUG_NO16;
2916 if (intel->gen >= 5 && c->prog_data.nr_pull_params == 0 && likely(!no16)) {
2917 v2.import_uniforms(&v);
2919 perf_debug("16-wide shader failed to compile, falling back to "
2920 "8-wide at a 10-20%% performance cost: %s", v2.fail_msg);
2922 simd16_instructions = &v2.instructions;
2926 c->prog_data.dispatch_width = 8;
2928 fs_generator g(brw, c, prog, fp, v.dual_src_output.file != BAD_FILE);
2929 const unsigned *generated = g.generate_assembly(&v.instructions,
2930 simd16_instructions,
2931 final_assembly_size);
2933 if (unlikely(INTEL_DEBUG & DEBUG_PERF) && shader) {
2934 if (shader->compiled_once)
2935 brw_wm_debug_recompile(brw, prog, &c->key);
2936 shader->compiled_once = true;
2938 if (start_busy && !drm_intel_bo_busy(intel->batch.last_bo)) {
2939 perf_debug("FS compile took %.03f ms and stalled the GPU\n",
2940 (get_time() - start_time) * 1000);
2948 brw_fs_precompile(struct gl_context *ctx, struct gl_shader_program *prog)
2950 struct brw_context *brw = brw_context(ctx);
2951 struct intel_context *intel = &brw->intel;
2952 struct brw_wm_prog_key key;
2954 if (!prog->_LinkedShaders[MESA_SHADER_FRAGMENT])
2957 struct gl_fragment_program *fp = (struct gl_fragment_program *)
2958 prog->_LinkedShaders[MESA_SHADER_FRAGMENT]->Program;
2959 struct brw_fragment_program *bfp = brw_fragment_program(fp);
2960 bool program_uses_dfdy = fp->UsesDFdy;
2962 memset(&key, 0, sizeof(key));
2964 if (intel->gen < 6) {
2966 key.iz_lookup |= IZ_PS_KILL_ALPHATEST_BIT;
2968 if (fp->Base.OutputsWritten & BITFIELD64_BIT(FRAG_RESULT_DEPTH))
2969 key.iz_lookup |= IZ_PS_COMPUTES_DEPTH_BIT;
2971 /* Just assume depth testing. */
2972 key.iz_lookup |= IZ_DEPTH_TEST_ENABLE_BIT;
2973 key.iz_lookup |= IZ_DEPTH_WRITE_ENABLE_BIT;
2976 if (prog->Name != 0)
2977 key.proj_attrib_mask = 0xffffffff;
2980 key.vp_outputs_written |= BITFIELD64_BIT(FRAG_ATTRIB_WPOS);
2982 for (int i = 0; i < FRAG_ATTRIB_MAX; i++) {
2983 if (!(fp->Base.InputsRead & BITFIELD64_BIT(i)))
2986 if (prog->Name == 0)
2987 key.proj_attrib_mask |= 1 << i;
2989 if (intel->gen < 6) {
2990 int vp_index = _mesa_vert_result_to_frag_attrib((gl_vert_result) i);
2993 key.vp_outputs_written |= BITFIELD64_BIT(vp_index);
2997 key.clamp_fragment_color = true;
2999 for (int i = 0; i < MAX_SAMPLERS; i++) {
3000 if (fp->Base.ShadowSamplers & (1 << i)) {
3001 /* Assume DEPTH_TEXTURE_MODE is the default: X, X, X, 1 */
3002 key.tex.swizzles[i] =
3003 MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_X, SWIZZLE_X, SWIZZLE_ONE);
3005 /* Color sampler: assume no swizzling. */
3006 key.tex.swizzles[i] = SWIZZLE_XYZW;
3010 if (fp->Base.InputsRead & FRAG_BIT_WPOS) {
3011 key.drawable_height = ctx->DrawBuffer->Height;
3014 if ((fp->Base.InputsRead & FRAG_BIT_WPOS) || program_uses_dfdy) {
3015 key.render_to_fbo = _mesa_is_user_fbo(ctx->DrawBuffer);
3018 key.nr_color_regions = 1;
3020 key.program_string_id = bfp->id;
3022 uint32_t old_prog_offset = brw->wm.prog_offset;
3023 struct brw_wm_prog_data *old_prog_data = brw->wm.prog_data;
3025 bool success = do_wm_prog(brw, prog, bfp, &key);
3027 brw->wm.prog_offset = old_prog_offset;
3028 brw->wm.prog_data = old_prog_data;